takashi kadono
Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_mpu.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| kadonotakashi | 0:8fdf9a60065b | 1 | /* |
| kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| kadonotakashi | 0:8fdf9a60065b | 3 | * All rights reserved. |
| kadonotakashi | 0:8fdf9a60065b | 4 | * |
| kadonotakashi | 0:8fdf9a60065b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| kadonotakashi | 0:8fdf9a60065b | 6 | * are permitted provided that the following conditions are met: |
| kadonotakashi | 0:8fdf9a60065b | 7 | * |
| kadonotakashi | 0:8fdf9a60065b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| kadonotakashi | 0:8fdf9a60065b | 9 | * of conditions and the following disclaimer. |
| kadonotakashi | 0:8fdf9a60065b | 10 | * |
| kadonotakashi | 0:8fdf9a60065b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| kadonotakashi | 0:8fdf9a60065b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| kadonotakashi | 0:8fdf9a60065b | 13 | * other materials provided with the distribution. |
| kadonotakashi | 0:8fdf9a60065b | 14 | * |
| kadonotakashi | 0:8fdf9a60065b | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| kadonotakashi | 0:8fdf9a60065b | 16 | * contributors may be used to endorse or promote products derived from this |
| kadonotakashi | 0:8fdf9a60065b | 17 | * software without specific prior written permission. |
| kadonotakashi | 0:8fdf9a60065b | 18 | * |
| kadonotakashi | 0:8fdf9a60065b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| kadonotakashi | 0:8fdf9a60065b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| kadonotakashi | 0:8fdf9a60065b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| kadonotakashi | 0:8fdf9a60065b | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| kadonotakashi | 0:8fdf9a60065b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| kadonotakashi | 0:8fdf9a60065b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| kadonotakashi | 0:8fdf9a60065b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| kadonotakashi | 0:8fdf9a60065b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| kadonotakashi | 0:8fdf9a60065b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| kadonotakashi | 0:8fdf9a60065b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| kadonotakashi | 0:8fdf9a60065b | 29 | */ |
| kadonotakashi | 0:8fdf9a60065b | 30 | #ifndef _FSL_MPU_H_ |
| kadonotakashi | 0:8fdf9a60065b | 31 | #define _FSL_MPU_H_ |
| kadonotakashi | 0:8fdf9a60065b | 32 | |
| kadonotakashi | 0:8fdf9a60065b | 33 | #include "fsl_common.h" |
| kadonotakashi | 0:8fdf9a60065b | 34 | |
| kadonotakashi | 0:8fdf9a60065b | 35 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 36 | * @addtogroup mpu |
| kadonotakashi | 0:8fdf9a60065b | 37 | * @{ |
| kadonotakashi | 0:8fdf9a60065b | 38 | */ |
| kadonotakashi | 0:8fdf9a60065b | 39 | |
| kadonotakashi | 0:8fdf9a60065b | 40 | |
| kadonotakashi | 0:8fdf9a60065b | 41 | /******************************************************************************* |
| kadonotakashi | 0:8fdf9a60065b | 42 | * Definitions |
| kadonotakashi | 0:8fdf9a60065b | 43 | ******************************************************************************/ |
| kadonotakashi | 0:8fdf9a60065b | 44 | |
| kadonotakashi | 0:8fdf9a60065b | 45 | /*! @name Driver version */ |
| kadonotakashi | 0:8fdf9a60065b | 46 | /*@{*/ |
| kadonotakashi | 0:8fdf9a60065b | 47 | /*! @brief MPU driver version 2.1.0. */ |
| kadonotakashi | 0:8fdf9a60065b | 48 | #define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) |
| kadonotakashi | 0:8fdf9a60065b | 49 | /*@}*/ |
| kadonotakashi | 0:8fdf9a60065b | 50 | |
| kadonotakashi | 0:8fdf9a60065b | 51 | /*! @brief MPU the bit shift for masters with privilege rights: read write and execute. */ |
| kadonotakashi | 0:8fdf9a60065b | 52 | #define MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6) |
| kadonotakashi | 0:8fdf9a60065b | 53 | |
| kadonotakashi | 0:8fdf9a60065b | 54 | /*! @brief MPU masters with read, write and execute rights bit mask. */ |
| kadonotakashi | 0:8fdf9a60065b | 55 | #define MPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n)) |
| kadonotakashi | 0:8fdf9a60065b | 56 | |
| kadonotakashi | 0:8fdf9a60065b | 57 | /*! @brief MPU masters with read, write and execute rights bit width. */ |
| kadonotakashi | 0:8fdf9a60065b | 58 | #define MPU_REGION_RWXRIGHTS_MASTER_WIDTH 5 |
| kadonotakashi | 0:8fdf9a60065b | 59 | |
| kadonotakashi | 0:8fdf9a60065b | 60 | /*! @brief MPU masters with read, write and execute rights priority setting. */ |
| kadonotakashi | 0:8fdf9a60065b | 61 | #define MPU_REGION_RWXRIGHTS_MASTER(n, x) \ |
| kadonotakashi | 0:8fdf9a60065b | 62 | (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_MASK(n)) |
| kadonotakashi | 0:8fdf9a60065b | 63 | |
| kadonotakashi | 0:8fdf9a60065b | 64 | /*! @brief MPU masters with read, write and execute rights process enable bit shift. */ |
| kadonotakashi | 0:8fdf9a60065b | 65 | #define MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + MPU_REGION_RWXRIGHTS_MASTER_WIDTH) |
| kadonotakashi | 0:8fdf9a60065b | 66 | |
| kadonotakashi | 0:8fdf9a60065b | 67 | /*! @brief MPU masters with read, write and execute rights process enable bit mask. */ |
| kadonotakashi | 0:8fdf9a60065b | 68 | #define MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n)) |
| kadonotakashi | 0:8fdf9a60065b | 69 | |
| kadonotakashi | 0:8fdf9a60065b | 70 | /*! @brief MPU masters with read, write and execute rights process enable setting. */ |
| kadonotakashi | 0:8fdf9a60065b | 71 | #define MPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \ |
| kadonotakashi | 0:8fdf9a60065b | 72 | (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n)) |
| kadonotakashi | 0:8fdf9a60065b | 73 | |
| kadonotakashi | 0:8fdf9a60065b | 74 | /*! @brief MPU masters with normal read write permission bit shift. */ |
| kadonotakashi | 0:8fdf9a60065b | 75 | #define MPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT) * 2 + 24) |
| kadonotakashi | 0:8fdf9a60065b | 76 | |
| kadonotakashi | 0:8fdf9a60065b | 77 | /*! @brief MPU masters with normal read write rights bit mask. */ |
| kadonotakashi | 0:8fdf9a60065b | 78 | #define MPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n)) |
| kadonotakashi | 0:8fdf9a60065b | 79 | |
| kadonotakashi | 0:8fdf9a60065b | 80 | /*! @brief MPU masters with normal read write rights priority setting. */ |
| kadonotakashi | 0:8fdf9a60065b | 81 | #define MPU_REGION_RWRIGHTS_MASTER(n, x) \ |
| kadonotakashi | 0:8fdf9a60065b | 82 | (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWRIGHTS_MASTER_MASK(n)) |
| kadonotakashi | 0:8fdf9a60065b | 83 | |
| kadonotakashi | 0:8fdf9a60065b | 84 | /*! @brief the Slave port numbers. */ |
| kadonotakashi | 0:8fdf9a60065b | 85 | #define MPU_SLAVE_PORT_NUM (4u) |
| kadonotakashi | 0:8fdf9a60065b | 86 | /*! @brief define the maximum index of master with privileged rights. */ |
| kadonotakashi | 0:8fdf9a60065b | 87 | #define MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX (3) |
| kadonotakashi | 0:8fdf9a60065b | 88 | |
| kadonotakashi | 0:8fdf9a60065b | 89 | /*! @brief Describes the number of MPU regions. */ |
| kadonotakashi | 0:8fdf9a60065b | 90 | typedef enum _mpu_region_total_num |
| kadonotakashi | 0:8fdf9a60065b | 91 | { |
| kadonotakashi | 0:8fdf9a60065b | 92 | kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */ |
| kadonotakashi | 0:8fdf9a60065b | 93 | kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */ |
| kadonotakashi | 0:8fdf9a60065b | 94 | kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */ |
| kadonotakashi | 0:8fdf9a60065b | 95 | } mpu_region_total_num_t; |
| kadonotakashi | 0:8fdf9a60065b | 96 | |
| kadonotakashi | 0:8fdf9a60065b | 97 | /*! @brief MPU slave port number. */ |
| kadonotakashi | 0:8fdf9a60065b | 98 | typedef enum _mpu_slave |
| kadonotakashi | 0:8fdf9a60065b | 99 | { |
| kadonotakashi | 0:8fdf9a60065b | 100 | kMPU_Slave0 = 0U, /*!< MPU slave port 0. */ |
| kadonotakashi | 0:8fdf9a60065b | 101 | kMPU_Slave1 = 1U, /*!< MPU slave port 1. */ |
| kadonotakashi | 0:8fdf9a60065b | 102 | kMPU_Slave2 = 2U, /*!< MPU slave port 2. */ |
| kadonotakashi | 0:8fdf9a60065b | 103 | kMPU_Slave3 = 3U, /*!< MPU slave port 3. */ |
| kadonotakashi | 0:8fdf9a60065b | 104 | kMPU_Slave4 = 4U /*!< MPU slave port 4. */ |
| kadonotakashi | 0:8fdf9a60065b | 105 | } mpu_slave_t; |
| kadonotakashi | 0:8fdf9a60065b | 106 | |
| kadonotakashi | 0:8fdf9a60065b | 107 | /*! @brief MPU error access control detail. */ |
| kadonotakashi | 0:8fdf9a60065b | 108 | typedef enum _mpu_err_access_control |
| kadonotakashi | 0:8fdf9a60065b | 109 | { |
| kadonotakashi | 0:8fdf9a60065b | 110 | kMPU_NoRegionHit = 0U, /*!< No region hit error. */ |
| kadonotakashi | 0:8fdf9a60065b | 111 | kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */ |
| kadonotakashi | 0:8fdf9a60065b | 112 | kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */ |
| kadonotakashi | 0:8fdf9a60065b | 113 | } mpu_err_access_control_t; |
| kadonotakashi | 0:8fdf9a60065b | 114 | |
| kadonotakashi | 0:8fdf9a60065b | 115 | /*! @brief MPU error access type. */ |
| kadonotakashi | 0:8fdf9a60065b | 116 | typedef enum _mpu_err_access_type |
| kadonotakashi | 0:8fdf9a60065b | 117 | { |
| kadonotakashi | 0:8fdf9a60065b | 118 | kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */ |
| kadonotakashi | 0:8fdf9a60065b | 119 | kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */ |
| kadonotakashi | 0:8fdf9a60065b | 120 | } mpu_err_access_type_t; |
| kadonotakashi | 0:8fdf9a60065b | 121 | |
| kadonotakashi | 0:8fdf9a60065b | 122 | /*! @brief MPU access error attributes.*/ |
| kadonotakashi | 0:8fdf9a60065b | 123 | typedef enum _mpu_err_attributes |
| kadonotakashi | 0:8fdf9a60065b | 124 | { |
| kadonotakashi | 0:8fdf9a60065b | 125 | kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 126 | kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 127 | kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 128 | kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 129 | } mpu_err_attributes_t; |
| kadonotakashi | 0:8fdf9a60065b | 130 | |
| kadonotakashi | 0:8fdf9a60065b | 131 | /*! @brief MPU access rights in supervisor mode for bus master 0 ~ 3. */ |
| kadonotakashi | 0:8fdf9a60065b | 132 | typedef enum _mpu_supervisor_access_rights |
| kadonotakashi | 0:8fdf9a60065b | 133 | { |
| kadonotakashi | 0:8fdf9a60065b | 134 | kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 135 | kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 136 | kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 137 | kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 138 | } mpu_supervisor_access_rights_t; |
| kadonotakashi | 0:8fdf9a60065b | 139 | |
| kadonotakashi | 0:8fdf9a60065b | 140 | /*! @brief MPU access rights in user mode for bus master 0 ~ 3. */ |
| kadonotakashi | 0:8fdf9a60065b | 141 | typedef enum _mpu_user_access_rights |
| kadonotakashi | 0:8fdf9a60065b | 142 | { |
| kadonotakashi | 0:8fdf9a60065b | 143 | kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 144 | kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 145 | kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 146 | kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 147 | kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 148 | kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 149 | kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 150 | kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 151 | } mpu_user_access_rights_t; |
| kadonotakashi | 0:8fdf9a60065b | 152 | |
| kadonotakashi | 0:8fdf9a60065b | 153 | /*! @brief MPU hardware basic information. */ |
| kadonotakashi | 0:8fdf9a60065b | 154 | typedef struct _mpu_hardware_info |
| kadonotakashi | 0:8fdf9a60065b | 155 | { |
| kadonotakashi | 0:8fdf9a60065b | 156 | uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */ |
| kadonotakashi | 0:8fdf9a60065b | 157 | uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */ |
| kadonotakashi | 0:8fdf9a60065b | 158 | mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */ |
| kadonotakashi | 0:8fdf9a60065b | 159 | } mpu_hardware_info_t; |
| kadonotakashi | 0:8fdf9a60065b | 160 | |
| kadonotakashi | 0:8fdf9a60065b | 161 | /*! @brief MPU detail error access information. */ |
| kadonotakashi | 0:8fdf9a60065b | 162 | typedef struct _mpu_access_err_info |
| kadonotakashi | 0:8fdf9a60065b | 163 | { |
| kadonotakashi | 0:8fdf9a60065b | 164 | uint32_t master; /*!< Access error master. */ |
| kadonotakashi | 0:8fdf9a60065b | 165 | mpu_err_attributes_t attributes; /*!< Access error attributes. */ |
| kadonotakashi | 0:8fdf9a60065b | 166 | mpu_err_access_type_t accessType; /*!< Access error type. */ |
| kadonotakashi | 0:8fdf9a60065b | 167 | mpu_err_access_control_t accessControl; /*!< Access error control. */ |
| kadonotakashi | 0:8fdf9a60065b | 168 | uint32_t address; /*!< Access error address. */ |
| kadonotakashi | 0:8fdf9a60065b | 169 | #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER |
| kadonotakashi | 0:8fdf9a60065b | 170 | uint8_t processorIdentification; /*!< Access error processor identification. */ |
| kadonotakashi | 0:8fdf9a60065b | 171 | #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ |
| kadonotakashi | 0:8fdf9a60065b | 172 | } mpu_access_err_info_t; |
| kadonotakashi | 0:8fdf9a60065b | 173 | |
| kadonotakashi | 0:8fdf9a60065b | 174 | /*! @brief MPU read/write/execute rights control for bus master 0 ~ 3. */ |
| kadonotakashi | 0:8fdf9a60065b | 175 | typedef struct _mpu_rwxrights_master_access_control |
| kadonotakashi | 0:8fdf9a60065b | 176 | { |
| kadonotakashi | 0:8fdf9a60065b | 177 | mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 178 | mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */ |
| kadonotakashi | 0:8fdf9a60065b | 179 | #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER |
| kadonotakashi | 0:8fdf9a60065b | 180 | bool processIdentifierEnable; /*!< Enables or disables process identifier. */ |
| kadonotakashi | 0:8fdf9a60065b | 181 | #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ |
| kadonotakashi | 0:8fdf9a60065b | 182 | } mpu_rwxrights_master_access_control_t; |
| kadonotakashi | 0:8fdf9a60065b | 183 | |
| kadonotakashi | 0:8fdf9a60065b | 184 | /*! @brief MPU read/write access control for bus master 4 ~ 7. */ |
| kadonotakashi | 0:8fdf9a60065b | 185 | typedef struct _mpu_rwrights_master_access_control |
| kadonotakashi | 0:8fdf9a60065b | 186 | { |
| kadonotakashi | 0:8fdf9a60065b | 187 | bool writeEnable; /*!< Enables or disables write permission. */ |
| kadonotakashi | 0:8fdf9a60065b | 188 | bool readEnable; /*!< Enables or disables read permission. */ |
| kadonotakashi | 0:8fdf9a60065b | 189 | } mpu_rwrights_master_access_control_t; |
| kadonotakashi | 0:8fdf9a60065b | 190 | |
| kadonotakashi | 0:8fdf9a60065b | 191 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 192 | * @brief MPU region configuration structure. |
| kadonotakashi | 0:8fdf9a60065b | 193 | * |
| kadonotakashi | 0:8fdf9a60065b | 194 | * This structure is used to configure the regionNum region. |
| kadonotakashi | 0:8fdf9a60065b | 195 | * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master |
| kadonotakashi | 0:8fdf9a60065b | 196 | * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3] |
| kadonotakashi | 0:8fdf9a60065b | 197 | * are used to configure the high master 4 ~ 7 with the normal read write permission. |
| kadonotakashi | 0:8fdf9a60065b | 198 | * The master port assignment is the chip configuration. Normally, the core is the |
| kadonotakashi | 0:8fdf9a60065b | 199 | * master 0, debugger is the master 1. |
| kadonotakashi | 0:8fdf9a60065b | 200 | * Note that the MPU assigns a priority scheme where the debugger is treated as the highest |
| kadonotakashi | 0:8fdf9a60065b | 201 | * priority master followed by the core and then all the remaining masters. |
| kadonotakashi | 0:8fdf9a60065b | 202 | * MPU protection does not allow writes from the core to affect the "regionNum 0" start |
| kadonotakashi | 0:8fdf9a60065b | 203 | * and end address nor the permissions associated with the debugger. It can only write |
| kadonotakashi | 0:8fdf9a60065b | 204 | * the permission fields associated with the other masters. This protection guarantees that |
| kadonotakashi | 0:8fdf9a60065b | 205 | * the debugger always has access to the entire address space and those rights can't |
| kadonotakashi | 0:8fdf9a60065b | 206 | * be changed by the core or any other bus master. Prepare |
| kadonotakashi | 0:8fdf9a60065b | 207 | * the region configuration when regionNum is 0. |
| kadonotakashi | 0:8fdf9a60065b | 208 | */ |
| kadonotakashi | 0:8fdf9a60065b | 209 | typedef struct _mpu_region_config |
| kadonotakashi | 0:8fdf9a60065b | 210 | { |
| kadonotakashi | 0:8fdf9a60065b | 211 | uint32_t regionNum; /*!< MPU region number, range form 0 ~ FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. */ |
| kadonotakashi | 0:8fdf9a60065b | 212 | uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual |
| kadonotakashi | 0:8fdf9a60065b | 213 | start address is 0-modulo-32 byte address. */ |
| kadonotakashi | 0:8fdf9a60065b | 214 | uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end |
| kadonotakashi | 0:8fdf9a60065b | 215 | address is 31-modulo-32 byte address. */ |
| kadonotakashi | 0:8fdf9a60065b | 216 | mpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */ |
| kadonotakashi | 0:8fdf9a60065b | 217 | mpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */ |
| kadonotakashi | 0:8fdf9a60065b | 218 | #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER |
| kadonotakashi | 0:8fdf9a60065b | 219 | uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */ |
| kadonotakashi | 0:8fdf9a60065b | 220 | uint8_t |
| kadonotakashi | 0:8fdf9a60065b | 221 | processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */ |
| kadonotakashi | 0:8fdf9a60065b | 222 | #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ |
| kadonotakashi | 0:8fdf9a60065b | 223 | } mpu_region_config_t; |
| kadonotakashi | 0:8fdf9a60065b | 224 | |
| kadonotakashi | 0:8fdf9a60065b | 225 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 226 | * @brief The configuration structure for the MPU initialization. |
| kadonotakashi | 0:8fdf9a60065b | 227 | * |
| kadonotakashi | 0:8fdf9a60065b | 228 | * This structure is used when calling the MPU_Init function. |
| kadonotakashi | 0:8fdf9a60065b | 229 | */ |
| kadonotakashi | 0:8fdf9a60065b | 230 | typedef struct _mpu_config |
| kadonotakashi | 0:8fdf9a60065b | 231 | { |
| kadonotakashi | 0:8fdf9a60065b | 232 | mpu_region_config_t regionConfig; /*!< Region access permission. */ |
| kadonotakashi | 0:8fdf9a60065b | 233 | struct _mpu_config *next; /*!< Pointer to the next structure. */ |
| kadonotakashi | 0:8fdf9a60065b | 234 | } mpu_config_t; |
| kadonotakashi | 0:8fdf9a60065b | 235 | |
| kadonotakashi | 0:8fdf9a60065b | 236 | /******************************************************************************* |
| kadonotakashi | 0:8fdf9a60065b | 237 | * API |
| kadonotakashi | 0:8fdf9a60065b | 238 | ******************************************************************************/ |
| kadonotakashi | 0:8fdf9a60065b | 239 | |
| kadonotakashi | 0:8fdf9a60065b | 240 | #if defined(__cplusplus) |
| kadonotakashi | 0:8fdf9a60065b | 241 | extern "C" { |
| kadonotakashi | 0:8fdf9a60065b | 242 | #endif /* _cplusplus */ |
| kadonotakashi | 0:8fdf9a60065b | 243 | |
| kadonotakashi | 0:8fdf9a60065b | 244 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 245 | * @name Initialization and deinitialization |
| kadonotakashi | 0:8fdf9a60065b | 246 | * @{ |
| kadonotakashi | 0:8fdf9a60065b | 247 | */ |
| kadonotakashi | 0:8fdf9a60065b | 248 | |
| kadonotakashi | 0:8fdf9a60065b | 249 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 250 | * @brief Initializes the MPU with the user configuration structure. |
| kadonotakashi | 0:8fdf9a60065b | 251 | * |
| kadonotakashi | 0:8fdf9a60065b | 252 | * This function configures the MPU module with the user-defined configuration. |
| kadonotakashi | 0:8fdf9a60065b | 253 | * |
| kadonotakashi | 0:8fdf9a60065b | 254 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 255 | * @param config The pointer to the configuration structure. |
| kadonotakashi | 0:8fdf9a60065b | 256 | */ |
| kadonotakashi | 0:8fdf9a60065b | 257 | void MPU_Init(MPU_Type *base, const mpu_config_t *config); |
| kadonotakashi | 0:8fdf9a60065b | 258 | |
| kadonotakashi | 0:8fdf9a60065b | 259 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 260 | * @brief Deinitializes the MPU regions. |
| kadonotakashi | 0:8fdf9a60065b | 261 | * |
| kadonotakashi | 0:8fdf9a60065b | 262 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 263 | */ |
| kadonotakashi | 0:8fdf9a60065b | 264 | void MPU_Deinit(MPU_Type *base); |
| kadonotakashi | 0:8fdf9a60065b | 265 | |
| kadonotakashi | 0:8fdf9a60065b | 266 | /* @}*/ |
| kadonotakashi | 0:8fdf9a60065b | 267 | |
| kadonotakashi | 0:8fdf9a60065b | 268 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 269 | * @name Basic Control Operations |
| kadonotakashi | 0:8fdf9a60065b | 270 | * @{ |
| kadonotakashi | 0:8fdf9a60065b | 271 | */ |
| kadonotakashi | 0:8fdf9a60065b | 272 | |
| kadonotakashi | 0:8fdf9a60065b | 273 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 274 | * @brief Enables/disables the MPU globally. |
| kadonotakashi | 0:8fdf9a60065b | 275 | * |
| kadonotakashi | 0:8fdf9a60065b | 276 | * Call this API to enable or disable the MPU module. |
| kadonotakashi | 0:8fdf9a60065b | 277 | * |
| kadonotakashi | 0:8fdf9a60065b | 278 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 279 | * @param enable True enable MPU, false disable MPU. |
| kadonotakashi | 0:8fdf9a60065b | 280 | */ |
| kadonotakashi | 0:8fdf9a60065b | 281 | static inline void MPU_Enable(MPU_Type *base, bool enable) |
| kadonotakashi | 0:8fdf9a60065b | 282 | { |
| kadonotakashi | 0:8fdf9a60065b | 283 | if (enable) |
| kadonotakashi | 0:8fdf9a60065b | 284 | { |
| kadonotakashi | 0:8fdf9a60065b | 285 | /* Enable the MPU globally. */ |
| kadonotakashi | 0:8fdf9a60065b | 286 | base->CESR |= MPU_CESR_VLD_MASK; |
| kadonotakashi | 0:8fdf9a60065b | 287 | } |
| kadonotakashi | 0:8fdf9a60065b | 288 | else |
| kadonotakashi | 0:8fdf9a60065b | 289 | { /* Disable the MPU globally. */ |
| kadonotakashi | 0:8fdf9a60065b | 290 | base->CESR &= ~MPU_CESR_VLD_MASK; |
| kadonotakashi | 0:8fdf9a60065b | 291 | } |
| kadonotakashi | 0:8fdf9a60065b | 292 | } |
| kadonotakashi | 0:8fdf9a60065b | 293 | |
| kadonotakashi | 0:8fdf9a60065b | 294 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 295 | * @brief Enables/disables the MPU for a special region. |
| kadonotakashi | 0:8fdf9a60065b | 296 | * |
| kadonotakashi | 0:8fdf9a60065b | 297 | * When MPU is enabled, call this API to disable an unused region |
| kadonotakashi | 0:8fdf9a60065b | 298 | * of an enabled MPU. Call this API to minimize the power dissipation. |
| kadonotakashi | 0:8fdf9a60065b | 299 | * |
| kadonotakashi | 0:8fdf9a60065b | 300 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 301 | * @param number MPU region number. |
| kadonotakashi | 0:8fdf9a60065b | 302 | * @param enable True enable the special region MPU, false disable the special region MPU. |
| kadonotakashi | 0:8fdf9a60065b | 303 | */ |
| kadonotakashi | 0:8fdf9a60065b | 304 | static inline void MPU_RegionEnable(MPU_Type *base, uint32_t number, bool enable) |
| kadonotakashi | 0:8fdf9a60065b | 305 | { |
| kadonotakashi | 0:8fdf9a60065b | 306 | if (enable) |
| kadonotakashi | 0:8fdf9a60065b | 307 | { |
| kadonotakashi | 0:8fdf9a60065b | 308 | /* Enable the #number region MPU. */ |
| kadonotakashi | 0:8fdf9a60065b | 309 | base->WORD[number][3] |= MPU_WORD_VLD_MASK; |
| kadonotakashi | 0:8fdf9a60065b | 310 | } |
| kadonotakashi | 0:8fdf9a60065b | 311 | else |
| kadonotakashi | 0:8fdf9a60065b | 312 | { /* Disable the #number region MPU. */ |
| kadonotakashi | 0:8fdf9a60065b | 313 | base->WORD[number][3] &= ~MPU_WORD_VLD_MASK; |
| kadonotakashi | 0:8fdf9a60065b | 314 | } |
| kadonotakashi | 0:8fdf9a60065b | 315 | } |
| kadonotakashi | 0:8fdf9a60065b | 316 | |
| kadonotakashi | 0:8fdf9a60065b | 317 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 318 | * @brief Gets the MPU basic hardware information. |
| kadonotakashi | 0:8fdf9a60065b | 319 | * |
| kadonotakashi | 0:8fdf9a60065b | 320 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 321 | * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t". |
| kadonotakashi | 0:8fdf9a60065b | 322 | */ |
| kadonotakashi | 0:8fdf9a60065b | 323 | void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform); |
| kadonotakashi | 0:8fdf9a60065b | 324 | |
| kadonotakashi | 0:8fdf9a60065b | 325 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 326 | * @brief Sets the MPU region. |
| kadonotakashi | 0:8fdf9a60065b | 327 | * |
| kadonotakashi | 0:8fdf9a60065b | 328 | * Note: Due to the MPU protection, the region number 0 does not allow writes from |
| kadonotakashi | 0:8fdf9a60065b | 329 | * core to affect the start and end address nor the permissions associated with |
| kadonotakashi | 0:8fdf9a60065b | 330 | * the debugger. It can only write the permission fields associated |
| kadonotakashi | 0:8fdf9a60065b | 331 | * with the other masters. |
| kadonotakashi | 0:8fdf9a60065b | 332 | * |
| kadonotakashi | 0:8fdf9a60065b | 333 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 334 | * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t". |
| kadonotakashi | 0:8fdf9a60065b | 335 | */ |
| kadonotakashi | 0:8fdf9a60065b | 336 | void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig); |
| kadonotakashi | 0:8fdf9a60065b | 337 | |
| kadonotakashi | 0:8fdf9a60065b | 338 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 339 | * @brief Sets the region start and end address. |
| kadonotakashi | 0:8fdf9a60065b | 340 | * |
| kadonotakashi | 0:8fdf9a60065b | 341 | * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU. |
| kadonotakashi | 0:8fdf9a60065b | 342 | * The actual start address by MPU is 0-modulo-32 byte address. |
| kadonotakashi | 0:8fdf9a60065b | 343 | * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. |
| kadonotakashi | 0:8fdf9a60065b | 344 | * The end address used by the MPU is 31-modulo-32 byte address. |
| kadonotakashi | 0:8fdf9a60065b | 345 | * Note: Due to the MPU protection, the startAddr and endAddr can't be |
| kadonotakashi | 0:8fdf9a60065b | 346 | * changed by the core when regionNum is 0. |
| kadonotakashi | 0:8fdf9a60065b | 347 | * |
| kadonotakashi | 0:8fdf9a60065b | 348 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 349 | * @param regionNum MPU region number. The range is from 0 to |
| kadonotakashi | 0:8fdf9a60065b | 350 | * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. |
| kadonotakashi | 0:8fdf9a60065b | 351 | * @param startAddr Region start address. |
| kadonotakashi | 0:8fdf9a60065b | 352 | * @param endAddr Region end address. |
| kadonotakashi | 0:8fdf9a60065b | 353 | */ |
| kadonotakashi | 0:8fdf9a60065b | 354 | void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr); |
| kadonotakashi | 0:8fdf9a60065b | 355 | |
| kadonotakashi | 0:8fdf9a60065b | 356 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 357 | * @brief Sets the MPU region access rights for masters with read, write, and execute rights. |
| kadonotakashi | 0:8fdf9a60065b | 358 | * The MPU access rights depend on two board classifications of bus masters. |
| kadonotakashi | 0:8fdf9a60065b | 359 | * The privilege rights masters and the normal rights masters. |
| kadonotakashi | 0:8fdf9a60065b | 360 | * The privilege rights masters have the read, write, and execute access rights. |
| kadonotakashi | 0:8fdf9a60065b | 361 | * Except the normal read and write rights, the execute rights are also |
| kadonotakashi | 0:8fdf9a60065b | 362 | * allowed for these masters. The privilege rights masters normally range from |
| kadonotakashi | 0:8fdf9a60065b | 363 | * bus masters 0 - 3. However, the maximum master number is device-specific. |
| kadonotakashi | 0:8fdf9a60065b | 364 | * See the "MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX". |
| kadonotakashi | 0:8fdf9a60065b | 365 | * The normal rights masters access rights control see |
| kadonotakashi | 0:8fdf9a60065b | 366 | * "MPU_SetRegionRwMasterAccessRights()". |
| kadonotakashi | 0:8fdf9a60065b | 367 | * |
| kadonotakashi | 0:8fdf9a60065b | 368 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 369 | * @param regionNum MPU region number. Should range from 0 to |
| kadonotakashi | 0:8fdf9a60065b | 370 | * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. |
| kadonotakashi | 0:8fdf9a60065b | 371 | * @param masterNum MPU bus master number. Should range from 0 to |
| kadonotakashi | 0:8fdf9a60065b | 372 | * MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX. |
| kadonotakashi | 0:8fdf9a60065b | 373 | * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwxrights_master_access_control_t". |
| kadonotakashi | 0:8fdf9a60065b | 374 | */ |
| kadonotakashi | 0:8fdf9a60065b | 375 | void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base, |
| kadonotakashi | 0:8fdf9a60065b | 376 | uint32_t regionNum, |
| kadonotakashi | 0:8fdf9a60065b | 377 | uint32_t masterNum, |
| kadonotakashi | 0:8fdf9a60065b | 378 | const mpu_rwxrights_master_access_control_t *accessRights); |
| kadonotakashi | 0:8fdf9a60065b | 379 | #if FSL_FEATURE_MPU_HAS_MASTER_4_7 |
| kadonotakashi | 0:8fdf9a60065b | 380 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 381 | * @brief Sets the MPU region access rights for masters with read and write rights. |
| kadonotakashi | 0:8fdf9a60065b | 382 | * The MPU access rights depend on two board classifications of bus masters. |
| kadonotakashi | 0:8fdf9a60065b | 383 | * The privilege rights masters and the normal rights masters. |
| kadonotakashi | 0:8fdf9a60065b | 384 | * The normal rights masters only have the read and write access permissions. |
| kadonotakashi | 0:8fdf9a60065b | 385 | * The privilege rights access control see "MPU_SetRegionRwxMasterAccessRights". |
| kadonotakashi | 0:8fdf9a60065b | 386 | * |
| kadonotakashi | 0:8fdf9a60065b | 387 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 388 | * @param regionNum MPU region number. The range is from 0 to |
| kadonotakashi | 0:8fdf9a60065b | 389 | * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. |
| kadonotakashi | 0:8fdf9a60065b | 390 | * @param masterNum MPU bus master number. Should range from FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT |
| kadonotakashi | 0:8fdf9a60065b | 391 | * to ~ FSL_FEATURE_MPU_MASTER_MAX_INDEX. |
| kadonotakashi | 0:8fdf9a60065b | 392 | * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwrights_master_access_control_t". |
| kadonotakashi | 0:8fdf9a60065b | 393 | */ |
| kadonotakashi | 0:8fdf9a60065b | 394 | void MPU_SetRegionRwMasterAccessRights(MPU_Type *base, |
| kadonotakashi | 0:8fdf9a60065b | 395 | uint32_t regionNum, |
| kadonotakashi | 0:8fdf9a60065b | 396 | uint32_t masterNum, |
| kadonotakashi | 0:8fdf9a60065b | 397 | const mpu_rwrights_master_access_control_t *accessRights); |
| kadonotakashi | 0:8fdf9a60065b | 398 | #endif /* FSL_FEATURE_MPU_HAS_MASTER_4_7 */ |
| kadonotakashi | 0:8fdf9a60065b | 399 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 400 | * @brief Gets the numbers of slave ports where errors occur. |
| kadonotakashi | 0:8fdf9a60065b | 401 | * |
| kadonotakashi | 0:8fdf9a60065b | 402 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 403 | * @param slaveNum MPU slave port number. |
| kadonotakashi | 0:8fdf9a60065b | 404 | * @return The slave ports error status. |
| kadonotakashi | 0:8fdf9a60065b | 405 | * true - error happens in this slave port. |
| kadonotakashi | 0:8fdf9a60065b | 406 | * false - error didn't happen in this slave port. |
| kadonotakashi | 0:8fdf9a60065b | 407 | */ |
| kadonotakashi | 0:8fdf9a60065b | 408 | bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum); |
| kadonotakashi | 0:8fdf9a60065b | 409 | |
| kadonotakashi | 0:8fdf9a60065b | 410 | /*! |
| kadonotakashi | 0:8fdf9a60065b | 411 | * @brief Gets the MPU detailed error access information. |
| kadonotakashi | 0:8fdf9a60065b | 412 | * |
| kadonotakashi | 0:8fdf9a60065b | 413 | * @param base MPU peripheral base address. |
| kadonotakashi | 0:8fdf9a60065b | 414 | * @param slaveNum MPU slave port number. |
| kadonotakashi | 0:8fdf9a60065b | 415 | * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t". |
| kadonotakashi | 0:8fdf9a60065b | 416 | */ |
| kadonotakashi | 0:8fdf9a60065b | 417 | void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform); |
| kadonotakashi | 0:8fdf9a60065b | 418 | |
| kadonotakashi | 0:8fdf9a60065b | 419 | /* @} */ |
| kadonotakashi | 0:8fdf9a60065b | 420 | |
| kadonotakashi | 0:8fdf9a60065b | 421 | #if defined(__cplusplus) |
| kadonotakashi | 0:8fdf9a60065b | 422 | } |
| kadonotakashi | 0:8fdf9a60065b | 423 | #endif |
| kadonotakashi | 0:8fdf9a60065b | 424 | |
| kadonotakashi | 0:8fdf9a60065b | 425 | /*! @}*/ |
| kadonotakashi | 0:8fdf9a60065b | 426 | |
| kadonotakashi | 0:8fdf9a60065b | 427 | #endif /* _FSL_MPU_H_ */ |