takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_ftm.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

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kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30 #ifndef _FSL_FTM_H_
kadonotakashi 0:8fdf9a60065b 31 #define _FSL_FTM_H_
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #include "fsl_common.h"
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 /*!
kadonotakashi 0:8fdf9a60065b 36 * @addtogroup ftm
kadonotakashi 0:8fdf9a60065b 37 * @{
kadonotakashi 0:8fdf9a60065b 38 */
kadonotakashi 0:8fdf9a60065b 39
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 42 * Definitions
kadonotakashi 0:8fdf9a60065b 43 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 44
kadonotakashi 0:8fdf9a60065b 45 /*! @name Driver version */
kadonotakashi 0:8fdf9a60065b 46 /*@{*/
kadonotakashi 0:8fdf9a60065b 47 #define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
kadonotakashi 0:8fdf9a60065b 48 /*@}*/
kadonotakashi 0:8fdf9a60065b 49
kadonotakashi 0:8fdf9a60065b 50 /*!
kadonotakashi 0:8fdf9a60065b 51 * @brief List of FTM channels
kadonotakashi 0:8fdf9a60065b 52 * @note Actual number of available channels is SoC dependent
kadonotakashi 0:8fdf9a60065b 53 */
kadonotakashi 0:8fdf9a60065b 54 typedef enum _ftm_chnl
kadonotakashi 0:8fdf9a60065b 55 {
kadonotakashi 0:8fdf9a60065b 56 kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/
kadonotakashi 0:8fdf9a60065b 57 kFTM_Chnl_1, /*!< FTM channel number 1 */
kadonotakashi 0:8fdf9a60065b 58 kFTM_Chnl_2, /*!< FTM channel number 2 */
kadonotakashi 0:8fdf9a60065b 59 kFTM_Chnl_3, /*!< FTM channel number 3 */
kadonotakashi 0:8fdf9a60065b 60 kFTM_Chnl_4, /*!< FTM channel number 4 */
kadonotakashi 0:8fdf9a60065b 61 kFTM_Chnl_5, /*!< FTM channel number 5 */
kadonotakashi 0:8fdf9a60065b 62 kFTM_Chnl_6, /*!< FTM channel number 6 */
kadonotakashi 0:8fdf9a60065b 63 kFTM_Chnl_7 /*!< FTM channel number 7 */
kadonotakashi 0:8fdf9a60065b 64 } ftm_chnl_t;
kadonotakashi 0:8fdf9a60065b 65
kadonotakashi 0:8fdf9a60065b 66 /*! @brief List of FTM faults */
kadonotakashi 0:8fdf9a60065b 67 typedef enum _ftm_fault_input
kadonotakashi 0:8fdf9a60065b 68 {
kadonotakashi 0:8fdf9a60065b 69 kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */
kadonotakashi 0:8fdf9a60065b 70 kFTM_Fault_1, /*!< FTM fault 1 input pin */
kadonotakashi 0:8fdf9a60065b 71 kFTM_Fault_2, /*!< FTM fault 2 input pin */
kadonotakashi 0:8fdf9a60065b 72 kFTM_Fault_3 /*!< FTM fault 3 input pin */
kadonotakashi 0:8fdf9a60065b 73 } ftm_fault_input_t;
kadonotakashi 0:8fdf9a60065b 74
kadonotakashi 0:8fdf9a60065b 75 /*! @brief FTM PWM operation modes */
kadonotakashi 0:8fdf9a60065b 76 typedef enum _ftm_pwm_mode
kadonotakashi 0:8fdf9a60065b 77 {
kadonotakashi 0:8fdf9a60065b 78 kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
kadonotakashi 0:8fdf9a60065b 79 kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */
kadonotakashi 0:8fdf9a60065b 80 kFTM_CombinedPwm /*!< Combined PWM */
kadonotakashi 0:8fdf9a60065b 81 } ftm_pwm_mode_t;
kadonotakashi 0:8fdf9a60065b 82
kadonotakashi 0:8fdf9a60065b 83 /*! @brief FTM PWM output pulse mode: high-true, low-true or no output */
kadonotakashi 0:8fdf9a60065b 84 typedef enum _ftm_pwm_level_select
kadonotakashi 0:8fdf9a60065b 85 {
kadonotakashi 0:8fdf9a60065b 86 kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */
kadonotakashi 0:8fdf9a60065b 87 kFTM_LowTrue, /*!< Low true pulses */
kadonotakashi 0:8fdf9a60065b 88 kFTM_HighTrue /*!< High true pulses */
kadonotakashi 0:8fdf9a60065b 89 } ftm_pwm_level_select_t;
kadonotakashi 0:8fdf9a60065b 90
kadonotakashi 0:8fdf9a60065b 91 /*! @brief Options to configure a FTM channel's PWM signal */
kadonotakashi 0:8fdf9a60065b 92 typedef struct _ftm_chnl_pwm_signal_param
kadonotakashi 0:8fdf9a60065b 93 {
kadonotakashi 0:8fdf9a60065b 94 ftm_chnl_t chnlNumber; /*!< The channel/channel pair number.
kadonotakashi 0:8fdf9a60065b 95 In combined mode, this represents the channel pair number. */
kadonotakashi 0:8fdf9a60065b 96 ftm_pwm_level_select_t level; /*!< PWM output active level select. */
kadonotakashi 0:8fdf9a60065b 97 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
kadonotakashi 0:8fdf9a60065b 98 0 = inactive signal(0% duty cycle)...
kadonotakashi 0:8fdf9a60065b 99 100 = always active signal (100% duty cycle).*/
kadonotakashi 0:8fdf9a60065b 100 uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate an asymmetrical PWM.
kadonotakashi 0:8fdf9a60065b 101 Specifies the delay to the first edge in a PWM period.
kadonotakashi 0:8fdf9a60065b 102 If unsure leave as 0; Should be specified as a
kadonotakashi 0:8fdf9a60065b 103 percentage of the PWM period */
kadonotakashi 0:8fdf9a60065b 104 } ftm_chnl_pwm_signal_param_t;
kadonotakashi 0:8fdf9a60065b 105
kadonotakashi 0:8fdf9a60065b 106 /*! @brief FlexTimer output compare mode */
kadonotakashi 0:8fdf9a60065b 107 typedef enum _ftm_output_compare_mode
kadonotakashi 0:8fdf9a60065b 108 {
kadonotakashi 0:8fdf9a60065b 109 kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
kadonotakashi 0:8fdf9a60065b 110 kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
kadonotakashi 0:8fdf9a60065b 111 kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */
kadonotakashi 0:8fdf9a60065b 112 kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */
kadonotakashi 0:8fdf9a60065b 113 } ftm_output_compare_mode_t;
kadonotakashi 0:8fdf9a60065b 114
kadonotakashi 0:8fdf9a60065b 115 /*! @brief FlexTimer input capture edge */
kadonotakashi 0:8fdf9a60065b 116 typedef enum _ftm_input_capture_edge
kadonotakashi 0:8fdf9a60065b 117 {
kadonotakashi 0:8fdf9a60065b 118 kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/
kadonotakashi 0:8fdf9a60065b 119 kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/
kadonotakashi 0:8fdf9a60065b 120 kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
kadonotakashi 0:8fdf9a60065b 121 } ftm_input_capture_edge_t;
kadonotakashi 0:8fdf9a60065b 122
kadonotakashi 0:8fdf9a60065b 123 /*! @brief FlexTimer dual edge capture modes */
kadonotakashi 0:8fdf9a60065b 124 typedef enum _ftm_dual_edge_capture_mode
kadonotakashi 0:8fdf9a60065b 125 {
kadonotakashi 0:8fdf9a60065b 126 kFTM_OneShot = 0U, /*!< One-shot capture mode */
kadonotakashi 0:8fdf9a60065b 127 kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */
kadonotakashi 0:8fdf9a60065b 128 } ftm_dual_edge_capture_mode_t;
kadonotakashi 0:8fdf9a60065b 129
kadonotakashi 0:8fdf9a60065b 130 /*! @brief FlexTimer dual edge capture parameters */
kadonotakashi 0:8fdf9a60065b 131 typedef struct _ftm_dual_edge_capture_param
kadonotakashi 0:8fdf9a60065b 132 {
kadonotakashi 0:8fdf9a60065b 133 ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */
kadonotakashi 0:8fdf9a60065b 134 ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
kadonotakashi 0:8fdf9a60065b 135 ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
kadonotakashi 0:8fdf9a60065b 136 } ftm_dual_edge_capture_param_t;
kadonotakashi 0:8fdf9a60065b 137
kadonotakashi 0:8fdf9a60065b 138 /*! @brief FlexTimer quadrature decode modes */
kadonotakashi 0:8fdf9a60065b 139 typedef enum _ftm_quad_decode_mode
kadonotakashi 0:8fdf9a60065b 140 {
kadonotakashi 0:8fdf9a60065b 141 kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
kadonotakashi 0:8fdf9a60065b 142 kFTM_QuadCountAndDir /*!< Count and direction encoding mode */
kadonotakashi 0:8fdf9a60065b 143 } ftm_quad_decode_mode_t;
kadonotakashi 0:8fdf9a60065b 144
kadonotakashi 0:8fdf9a60065b 145 /*! @brief FlexTimer quadrature phase polarities */
kadonotakashi 0:8fdf9a60065b 146 typedef enum _ftm_phase_polarity
kadonotakashi 0:8fdf9a60065b 147 {
kadonotakashi 0:8fdf9a60065b 148 kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
kadonotakashi 0:8fdf9a60065b 149 kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */
kadonotakashi 0:8fdf9a60065b 150 } ftm_phase_polarity_t;
kadonotakashi 0:8fdf9a60065b 151
kadonotakashi 0:8fdf9a60065b 152 /*! @brief FlexTimer quadrature decode phase parameters */
kadonotakashi 0:8fdf9a60065b 153 typedef struct _ftm_phase_param
kadonotakashi 0:8fdf9a60065b 154 {
kadonotakashi 0:8fdf9a60065b 155 bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */
kadonotakashi 0:8fdf9a60065b 156 uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */
kadonotakashi 0:8fdf9a60065b 157 ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */
kadonotakashi 0:8fdf9a60065b 158 } ftm_phase_params_t;
kadonotakashi 0:8fdf9a60065b 159
kadonotakashi 0:8fdf9a60065b 160 /*! @brief Structure is used to hold the parameters to configure a FTM fault */
kadonotakashi 0:8fdf9a60065b 161 typedef struct _ftm_fault_param
kadonotakashi 0:8fdf9a60065b 162 {
kadonotakashi 0:8fdf9a60065b 163 bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
kadonotakashi 0:8fdf9a60065b 164 bool faultLevel; /*!< True: Fault polarity is active low; in other words, '0' indicates a fault;
kadonotakashi 0:8fdf9a60065b 165 False: Fault polarity is active high */
kadonotakashi 0:8fdf9a60065b 166 bool useFaultFilter; /*!< True: Use the filtered fault signal;
kadonotakashi 0:8fdf9a60065b 167 False: Use the direct path from fault input */
kadonotakashi 0:8fdf9a60065b 168 } ftm_fault_param_t;
kadonotakashi 0:8fdf9a60065b 169
kadonotakashi 0:8fdf9a60065b 170 /*! @brief FlexTimer pre-scaler factor for the dead time insertion*/
kadonotakashi 0:8fdf9a60065b 171 typedef enum _ftm_deadtime_prescale
kadonotakashi 0:8fdf9a60065b 172 {
kadonotakashi 0:8fdf9a60065b 173 kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */
kadonotakashi 0:8fdf9a60065b 174 kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */
kadonotakashi 0:8fdf9a60065b 175 kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */
kadonotakashi 0:8fdf9a60065b 176 } ftm_deadtime_prescale_t;
kadonotakashi 0:8fdf9a60065b 177
kadonotakashi 0:8fdf9a60065b 178 /*! @brief FlexTimer clock source selection*/
kadonotakashi 0:8fdf9a60065b 179 typedef enum _ftm_clock_source
kadonotakashi 0:8fdf9a60065b 180 {
kadonotakashi 0:8fdf9a60065b 181 kFTM_SystemClock = 1U, /*!< System clock selected */
kadonotakashi 0:8fdf9a60065b 182 kFTM_FixedClock, /*!< Fixed frequency clock */
kadonotakashi 0:8fdf9a60065b 183 kFTM_ExternalClock /*!< External clock */
kadonotakashi 0:8fdf9a60065b 184 } ftm_clock_source_t;
kadonotakashi 0:8fdf9a60065b 185
kadonotakashi 0:8fdf9a60065b 186 /*! @brief FlexTimer pre-scaler factor selection for the clock source*/
kadonotakashi 0:8fdf9a60065b 187 typedef enum _ftm_clock_prescale
kadonotakashi 0:8fdf9a60065b 188 {
kadonotakashi 0:8fdf9a60065b 189 kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
kadonotakashi 0:8fdf9a60065b 190 kFTM_Prescale_Divide_2, /*!< Divide by 2 */
kadonotakashi 0:8fdf9a60065b 191 kFTM_Prescale_Divide_4, /*!< Divide by 4 */
kadonotakashi 0:8fdf9a60065b 192 kFTM_Prescale_Divide_8, /*!< Divide by 8 */
kadonotakashi 0:8fdf9a60065b 193 kFTM_Prescale_Divide_16, /*!< Divide by 16 */
kadonotakashi 0:8fdf9a60065b 194 kFTM_Prescale_Divide_32, /*!< Divide by 32 */
kadonotakashi 0:8fdf9a60065b 195 kFTM_Prescale_Divide_64, /*!< Divide by 64 */
kadonotakashi 0:8fdf9a60065b 196 kFTM_Prescale_Divide_128 /*!< Divide by 128 */
kadonotakashi 0:8fdf9a60065b 197 } ftm_clock_prescale_t;
kadonotakashi 0:8fdf9a60065b 198
kadonotakashi 0:8fdf9a60065b 199 /*! @brief Options for the FlexTimer behaviour in BDM Mode */
kadonotakashi 0:8fdf9a60065b 200 typedef enum _ftm_bdm_mode
kadonotakashi 0:8fdf9a60065b 201 {
kadonotakashi 0:8fdf9a60065b 202 kFTM_BdmMode_0 = 0U,
kadonotakashi 0:8fdf9a60065b 203 /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V
kadonotakashi 0:8fdf9a60065b 204 registers bypass the register buffers */
kadonotakashi 0:8fdf9a60065b 205 kFTM_BdmMode_1,
kadonotakashi 0:8fdf9a60065b 206 /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to
kadonotakashi 0:8fdf9a60065b 207 MOD,CNTIN and C(n)V registers bypass the register buffers */
kadonotakashi 0:8fdf9a60065b 208 kFTM_BdmMode_2,
kadonotakashi 0:8fdf9a60065b 209 /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode,
kadonotakashi 0:8fdf9a60065b 210 writes to MOD,CNTIN and C(n)V registers bypass the register buffers */
kadonotakashi 0:8fdf9a60065b 211 kFTM_BdmMode_3
kadonotakashi 0:8fdf9a60065b 212 /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and
kadonotakashi 0:8fdf9a60065b 213 C(n)V registers is in fully functional mode */
kadonotakashi 0:8fdf9a60065b 214 } ftm_bdm_mode_t;
kadonotakashi 0:8fdf9a60065b 215
kadonotakashi 0:8fdf9a60065b 216 /*! @brief Options for the FTM fault control mode */
kadonotakashi 0:8fdf9a60065b 217 typedef enum _ftm_fault_mode
kadonotakashi 0:8fdf9a60065b 218 {
kadonotakashi 0:8fdf9a60065b 219 kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */
kadonotakashi 0:8fdf9a60065b 220 kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */
kadonotakashi 0:8fdf9a60065b 221 kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */
kadonotakashi 0:8fdf9a60065b 222 kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */
kadonotakashi 0:8fdf9a60065b 223 } ftm_fault_mode_t;
kadonotakashi 0:8fdf9a60065b 224
kadonotakashi 0:8fdf9a60065b 225 /*!
kadonotakashi 0:8fdf9a60065b 226 * @brief FTM external trigger options
kadonotakashi 0:8fdf9a60065b 227 * @note Actual available external trigger sources are SoC-specific
kadonotakashi 0:8fdf9a60065b 228 */
kadonotakashi 0:8fdf9a60065b 229 typedef enum _ftm_external_trigger
kadonotakashi 0:8fdf9a60065b 230 {
kadonotakashi 0:8fdf9a60065b 231 kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */
kadonotakashi 0:8fdf9a60065b 232 kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */
kadonotakashi 0:8fdf9a60065b 233 kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */
kadonotakashi 0:8fdf9a60065b 234 kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */
kadonotakashi 0:8fdf9a60065b 235 kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */
kadonotakashi 0:8fdf9a60065b 236 kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */
kadonotakashi 0:8fdf9a60065b 237 kFTM_Chnl6Trigger =
kadonotakashi 0:8fdf9a60065b 238 (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */
kadonotakashi 0:8fdf9a60065b 239 kFTM_Chnl7Trigger =
kadonotakashi 0:8fdf9a60065b 240 (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */
kadonotakashi 0:8fdf9a60065b 241 kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */
kadonotakashi 0:8fdf9a60065b 242 kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */
kadonotakashi 0:8fdf9a60065b 243 } ftm_external_trigger_t;
kadonotakashi 0:8fdf9a60065b 244
kadonotakashi 0:8fdf9a60065b 245 /*! @brief FlexTimer PWM sync options to update registers with buffer */
kadonotakashi 0:8fdf9a60065b 246 typedef enum _ftm_pwm_sync_method
kadonotakashi 0:8fdf9a60065b 247 {
kadonotakashi 0:8fdf9a60065b 248 kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */
kadonotakashi 0:8fdf9a60065b 249 kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */
kadonotakashi 0:8fdf9a60065b 250 kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */
kadonotakashi 0:8fdf9a60065b 251 kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */
kadonotakashi 0:8fdf9a60065b 252 } ftm_pwm_sync_method_t;
kadonotakashi 0:8fdf9a60065b 253
kadonotakashi 0:8fdf9a60065b 254 /*!
kadonotakashi 0:8fdf9a60065b 255 * @brief FTM options available as loading point for register reload
kadonotakashi 0:8fdf9a60065b 256 * @note Actual available reload points are SoC-specific
kadonotakashi 0:8fdf9a60065b 257 */
kadonotakashi 0:8fdf9a60065b 258 typedef enum _ftm_reload_point
kadonotakashi 0:8fdf9a60065b 259 {
kadonotakashi 0:8fdf9a60065b 260 kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 261 kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 262 kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 263 kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 264 kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 265 kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 266 kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 267 kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */
kadonotakashi 0:8fdf9a60065b 268 kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */
kadonotakashi 0:8fdf9a60065b 269 kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */
kadonotakashi 0:8fdf9a60065b 270 kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */
kadonotakashi 0:8fdf9a60065b 271 } ftm_reload_point_t;
kadonotakashi 0:8fdf9a60065b 272
kadonotakashi 0:8fdf9a60065b 273 /*!
kadonotakashi 0:8fdf9a60065b 274 * @brief List of FTM interrupts
kadonotakashi 0:8fdf9a60065b 275 * @note Actual available interrupts are SoC-specific
kadonotakashi 0:8fdf9a60065b 276 */
kadonotakashi 0:8fdf9a60065b 277 typedef enum _ftm_interrupt_enable
kadonotakashi 0:8fdf9a60065b 278 {
kadonotakashi 0:8fdf9a60065b 279 kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */
kadonotakashi 0:8fdf9a60065b 280 kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */
kadonotakashi 0:8fdf9a60065b 281 kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */
kadonotakashi 0:8fdf9a60065b 282 kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */
kadonotakashi 0:8fdf9a60065b 283 kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */
kadonotakashi 0:8fdf9a60065b 284 kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */
kadonotakashi 0:8fdf9a60065b 285 kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */
kadonotakashi 0:8fdf9a60065b 286 kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */
kadonotakashi 0:8fdf9a60065b 287 kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */
kadonotakashi 0:8fdf9a60065b 288 kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */
kadonotakashi 0:8fdf9a60065b 289 kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */
kadonotakashi 0:8fdf9a60065b 290 } ftm_interrupt_enable_t;
kadonotakashi 0:8fdf9a60065b 291
kadonotakashi 0:8fdf9a60065b 292 /*!
kadonotakashi 0:8fdf9a60065b 293 * @brief List of FTM flags
kadonotakashi 0:8fdf9a60065b 294 * @note Actual available flags are SoC-specific
kadonotakashi 0:8fdf9a60065b 295 */
kadonotakashi 0:8fdf9a60065b 296 typedef enum _ftm_status_flags
kadonotakashi 0:8fdf9a60065b 297 {
kadonotakashi 0:8fdf9a60065b 298 kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */
kadonotakashi 0:8fdf9a60065b 299 kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */
kadonotakashi 0:8fdf9a60065b 300 kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */
kadonotakashi 0:8fdf9a60065b 301 kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */
kadonotakashi 0:8fdf9a60065b 302 kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */
kadonotakashi 0:8fdf9a60065b 303 kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */
kadonotakashi 0:8fdf9a60065b 304 kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */
kadonotakashi 0:8fdf9a60065b 305 kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */
kadonotakashi 0:8fdf9a60065b 306 kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */
kadonotakashi 0:8fdf9a60065b 307 kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */
kadonotakashi 0:8fdf9a60065b 308 kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */
kadonotakashi 0:8fdf9a60065b 309 kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */
kadonotakashi 0:8fdf9a60065b 310 } ftm_status_flags_t;
kadonotakashi 0:8fdf9a60065b 311
kadonotakashi 0:8fdf9a60065b 312 /*!
kadonotakashi 0:8fdf9a60065b 313 * @brief List of FTM Quad Decoder flags.
kadonotakashi 0:8fdf9a60065b 314 */
kadonotakashi 0:8fdf9a60065b 315 enum _ftm_quad_decoder_flags
kadonotakashi 0:8fdf9a60065b 316 {
kadonotakashi 0:8fdf9a60065b 317 kFTM_QuadDecoderCountingIncreaseFlag = FTM_QDCTRL_QUADIR_MASK, /*!< Counting direction is increasing (FTM counter
kadonotakashi 0:8fdf9a60065b 318 increment), or the direction is decreasing. */
kadonotakashi 0:8fdf9a60065b 319 kFTM_QuadDecoderCountingOverflowOnTopFlag = FTM_QDCTRL_TOFDIR_MASK, /*!< Indicates if the TOF bit was set on the top
kadonotakashi 0:8fdf9a60065b 320 or the bottom of counting. */
kadonotakashi 0:8fdf9a60065b 321 };
kadonotakashi 0:8fdf9a60065b 322
kadonotakashi 0:8fdf9a60065b 323 /*!
kadonotakashi 0:8fdf9a60065b 324 * @brief FTM configuration structure
kadonotakashi 0:8fdf9a60065b 325 *
kadonotakashi 0:8fdf9a60065b 326 * This structure holds the configuration settings for the FTM peripheral. To initialize this
kadonotakashi 0:8fdf9a60065b 327 * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a
kadonotakashi 0:8fdf9a60065b 328 * pointer to the configuration structure instance.
kadonotakashi 0:8fdf9a60065b 329 *
kadonotakashi 0:8fdf9a60065b 330 * The configuration structure can be made constant so as to reside in flash.
kadonotakashi 0:8fdf9a60065b 331 */
kadonotakashi 0:8fdf9a60065b 332 typedef struct _ftm_config
kadonotakashi 0:8fdf9a60065b 333 {
kadonotakashi 0:8fdf9a60065b 334 ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */
kadonotakashi 0:8fdf9a60065b 335 ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */
kadonotakashi 0:8fdf9a60065b 336 uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple
kadonotakashi 0:8fdf9a60065b 337 update modes can be used by providing an OR'ed list of options
kadonotakashi 0:8fdf9a60065b 338 available in enumeration ::ftm_pwm_sync_method_t. */
kadonotakashi 0:8fdf9a60065b 339 uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM
kadonotakashi 0:8fdf9a60065b 340 synchronization is not required. Multiple reload points can be used by providing
kadonotakashi 0:8fdf9a60065b 341 an OR'ed list of options available in
kadonotakashi 0:8fdf9a60065b 342 enumeration ::ftm_reload_point_t. */
kadonotakashi 0:8fdf9a60065b 343 ftm_fault_mode_t faultMode; /*!< FTM fault control mode */
kadonotakashi 0:8fdf9a60065b 344 uint8_t faultFilterValue; /*!< Fault input filter value */
kadonotakashi 0:8fdf9a60065b 345 ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */
kadonotakashi 0:8fdf9a60065b 346 uint32_t deadTimeValue; /*!< The dead time value
kadonotakashi 0:8fdf9a60065b 347 deadTimeValue's available range is 0-1023 when register has DTVALEX,
kadonotakashi 0:8fdf9a60065b 348 otherwise its available range is 0-63. */
kadonotakashi 0:8fdf9a60065b 349 uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be
kadonotakashi 0:8fdf9a60065b 350 enabled by providing an OR'ed list of options available in
kadonotakashi 0:8fdf9a60065b 351 enumeration ::ftm_external_trigger_t. */
kadonotakashi 0:8fdf9a60065b 352 uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */
kadonotakashi 0:8fdf9a60065b 353 uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */
kadonotakashi 0:8fdf9a60065b 354 bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled;
kadonotakashi 0:8fdf9a60065b 355 False: disabled */
kadonotakashi 0:8fdf9a60065b 356 } ftm_config_t;
kadonotakashi 0:8fdf9a60065b 357
kadonotakashi 0:8fdf9a60065b 358 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 359 * API
kadonotakashi 0:8fdf9a60065b 360 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 361
kadonotakashi 0:8fdf9a60065b 362 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 363 extern "C" {
kadonotakashi 0:8fdf9a60065b 364 #endif
kadonotakashi 0:8fdf9a60065b 365
kadonotakashi 0:8fdf9a60065b 366 /*!
kadonotakashi 0:8fdf9a60065b 367 * @name Initialization and deinitialization
kadonotakashi 0:8fdf9a60065b 368 * @{
kadonotakashi 0:8fdf9a60065b 369 */
kadonotakashi 0:8fdf9a60065b 370
kadonotakashi 0:8fdf9a60065b 371 /*!
kadonotakashi 0:8fdf9a60065b 372 * @brief Ungates the FTM clock and configures the peripheral for basic operation.
kadonotakashi 0:8fdf9a60065b 373 *
kadonotakashi 0:8fdf9a60065b 374 * @note This API should be called at the beginning of the application which is using the FTM driver.
kadonotakashi 0:8fdf9a60065b 375 *
kadonotakashi 0:8fdf9a60065b 376 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 377 * @param config Pointer to the user configuration structure.
kadonotakashi 0:8fdf9a60065b 378 *
kadonotakashi 0:8fdf9a60065b 379 * @return kStatus_Success indicates success; Else indicates failure.
kadonotakashi 0:8fdf9a60065b 380 */
kadonotakashi 0:8fdf9a60065b 381 status_t FTM_Init(FTM_Type *base, const ftm_config_t *config);
kadonotakashi 0:8fdf9a60065b 382
kadonotakashi 0:8fdf9a60065b 383 /*!
kadonotakashi 0:8fdf9a60065b 384 * @brief Gates the FTM clock.
kadonotakashi 0:8fdf9a60065b 385 *
kadonotakashi 0:8fdf9a60065b 386 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 387 */
kadonotakashi 0:8fdf9a60065b 388 void FTM_Deinit(FTM_Type *base);
kadonotakashi 0:8fdf9a60065b 389
kadonotakashi 0:8fdf9a60065b 390 /*!
kadonotakashi 0:8fdf9a60065b 391 * @brief Fills in the FTM configuration structure with the default settings.
kadonotakashi 0:8fdf9a60065b 392 *
kadonotakashi 0:8fdf9a60065b 393 * The default values are:
kadonotakashi 0:8fdf9a60065b 394 * @code
kadonotakashi 0:8fdf9a60065b 395 * config->prescale = kFTM_Prescale_Divide_1;
kadonotakashi 0:8fdf9a60065b 396 * config->bdmMode = kFTM_BdmMode_0;
kadonotakashi 0:8fdf9a60065b 397 * config->pwmSyncMode = kFTM_SoftwareTrigger;
kadonotakashi 0:8fdf9a60065b 398 * config->reloadPoints = 0;
kadonotakashi 0:8fdf9a60065b 399 * config->faultMode = kFTM_Fault_Disable;
kadonotakashi 0:8fdf9a60065b 400 * config->faultFilterValue = 0;
kadonotakashi 0:8fdf9a60065b 401 * config->deadTimePrescale = kFTM_Deadtime_Prescale_1;
kadonotakashi 0:8fdf9a60065b 402 * config->deadTimeValue = 0;
kadonotakashi 0:8fdf9a60065b 403 * config->extTriggers = 0;
kadonotakashi 0:8fdf9a60065b 404 * config->chnlInitState = 0;
kadonotakashi 0:8fdf9a60065b 405 * config->chnlPolarity = 0;
kadonotakashi 0:8fdf9a60065b 406 * config->useGlobalTimeBase = false;
kadonotakashi 0:8fdf9a60065b 407 * @endcode
kadonotakashi 0:8fdf9a60065b 408 * @param config Pointer to the user configuration structure.
kadonotakashi 0:8fdf9a60065b 409 */
kadonotakashi 0:8fdf9a60065b 410 void FTM_GetDefaultConfig(ftm_config_t *config);
kadonotakashi 0:8fdf9a60065b 411
kadonotakashi 0:8fdf9a60065b 412 /*! @}*/
kadonotakashi 0:8fdf9a60065b 413
kadonotakashi 0:8fdf9a60065b 414 /*!
kadonotakashi 0:8fdf9a60065b 415 * @name Channel mode operations
kadonotakashi 0:8fdf9a60065b 416 * @{
kadonotakashi 0:8fdf9a60065b 417 */
kadonotakashi 0:8fdf9a60065b 418
kadonotakashi 0:8fdf9a60065b 419 /*!
kadonotakashi 0:8fdf9a60065b 420 * @brief Configures the PWM signal parameters.
kadonotakashi 0:8fdf9a60065b 421 *
kadonotakashi 0:8fdf9a60065b 422 * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this
kadonotakashi 0:8fdf9a60065b 423 * function to configure all FTM channels that are used to output a PWM signal.
kadonotakashi 0:8fdf9a60065b 424 *
kadonotakashi 0:8fdf9a60065b 425 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 426 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
kadonotakashi 0:8fdf9a60065b 427 * @param numOfChnls Number of channels to configure; This should be the size of the array passed in
kadonotakashi 0:8fdf9a60065b 428 * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t
kadonotakashi 0:8fdf9a60065b 429 * @param pwmFreq_Hz PWM signal frequency in Hz
kadonotakashi 0:8fdf9a60065b 430 * @param srcClock_Hz FTM counter clock in Hz
kadonotakashi 0:8fdf9a60065b 431 *
kadonotakashi 0:8fdf9a60065b 432 * @return kStatus_Success if the PWM setup was successful
kadonotakashi 0:8fdf9a60065b 433 * kStatus_Error on failure
kadonotakashi 0:8fdf9a60065b 434 */
kadonotakashi 0:8fdf9a60065b 435 status_t FTM_SetupPwm(FTM_Type *base,
kadonotakashi 0:8fdf9a60065b 436 const ftm_chnl_pwm_signal_param_t *chnlParams,
kadonotakashi 0:8fdf9a60065b 437 uint8_t numOfChnls,
kadonotakashi 0:8fdf9a60065b 438 ftm_pwm_mode_t mode,
kadonotakashi 0:8fdf9a60065b 439 uint32_t pwmFreq_Hz,
kadonotakashi 0:8fdf9a60065b 440 uint32_t srcClock_Hz);
kadonotakashi 0:8fdf9a60065b 441
kadonotakashi 0:8fdf9a60065b 442 /*!
kadonotakashi 0:8fdf9a60065b 443 * @brief Updates the duty cycle of an active PWM signal.
kadonotakashi 0:8fdf9a60065b 444 *
kadonotakashi 0:8fdf9a60065b 445 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 446 * @param chnlNumber The channel/channel pair number. In combined mode, this represents
kadonotakashi 0:8fdf9a60065b 447 * the channel pair number
kadonotakashi 0:8fdf9a60065b 448 * @param currentPwmMode The current PWM mode set during PWM setup
kadonotakashi 0:8fdf9a60065b 449 * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100
kadonotakashi 0:8fdf9a60065b 450 * 0=inactive signal(0% duty cycle)...
kadonotakashi 0:8fdf9a60065b 451 * 100=active signal (100% duty cycle)
kadonotakashi 0:8fdf9a60065b 452 */
kadonotakashi 0:8fdf9a60065b 453 void FTM_UpdatePwmDutycycle(FTM_Type *base,
kadonotakashi 0:8fdf9a60065b 454 ftm_chnl_t chnlNumber,
kadonotakashi 0:8fdf9a60065b 455 ftm_pwm_mode_t currentPwmMode,
kadonotakashi 0:8fdf9a60065b 456 uint8_t dutyCyclePercent);
kadonotakashi 0:8fdf9a60065b 457
kadonotakashi 0:8fdf9a60065b 458 /*!
kadonotakashi 0:8fdf9a60065b 459 * @brief Updates the edge level selection for a channel.
kadonotakashi 0:8fdf9a60065b 460 *
kadonotakashi 0:8fdf9a60065b 461 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 462 * @param chnlNumber The channel number
kadonotakashi 0:8fdf9a60065b 463 * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11.
kadonotakashi 0:8fdf9a60065b 464 * See the Kinetis SoC reference manual for details about this field.
kadonotakashi 0:8fdf9a60065b 465 */
kadonotakashi 0:8fdf9a60065b 466 void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level);
kadonotakashi 0:8fdf9a60065b 467
kadonotakashi 0:8fdf9a60065b 468 /*!
kadonotakashi 0:8fdf9a60065b 469 * @brief Enables capturing an input signal on the channel using the function parameters.
kadonotakashi 0:8fdf9a60065b 470 *
kadonotakashi 0:8fdf9a60065b 471 * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is
kadonotakashi 0:8fdf9a60065b 472 * captured into the CnV register. The user has to read the CnV register separately to get this
kadonotakashi 0:8fdf9a60065b 473 * value. The filter function is disabled if the filterVal argument passed in is 0. The filter
kadonotakashi 0:8fdf9a60065b 474 * function is available only for channels 0, 1, 2, 3.
kadonotakashi 0:8fdf9a60065b 475 *
kadonotakashi 0:8fdf9a60065b 476 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 477 * @param chnlNumber The channel number
kadonotakashi 0:8fdf9a60065b 478 * @param captureMode Specifies which edge to capture
kadonotakashi 0:8fdf9a60065b 479 * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3.
kadonotakashi 0:8fdf9a60065b 480 */
kadonotakashi 0:8fdf9a60065b 481 void FTM_SetupInputCapture(FTM_Type *base,
kadonotakashi 0:8fdf9a60065b 482 ftm_chnl_t chnlNumber,
kadonotakashi 0:8fdf9a60065b 483 ftm_input_capture_edge_t captureMode,
kadonotakashi 0:8fdf9a60065b 484 uint32_t filterValue);
kadonotakashi 0:8fdf9a60065b 485
kadonotakashi 0:8fdf9a60065b 486 /*!
kadonotakashi 0:8fdf9a60065b 487 * @brief Configures the FTM to generate timed pulses.
kadonotakashi 0:8fdf9a60065b 488 *
kadonotakashi 0:8fdf9a60065b 489 * When the FTM counter matches the value of compareVal argument (this is written into CnV reg),
kadonotakashi 0:8fdf9a60065b 490 * the channel output is changed based on what is specified in the compareMode argument.
kadonotakashi 0:8fdf9a60065b 491 *
kadonotakashi 0:8fdf9a60065b 492 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 493 * @param chnlNumber The channel number
kadonotakashi 0:8fdf9a60065b 494 * @param compareMode Action to take on the channel output when the compare condition is met
kadonotakashi 0:8fdf9a60065b 495 * @param compareValue Value to be programmed in the CnV register.
kadonotakashi 0:8fdf9a60065b 496 */
kadonotakashi 0:8fdf9a60065b 497 void FTM_SetupOutputCompare(FTM_Type *base,
kadonotakashi 0:8fdf9a60065b 498 ftm_chnl_t chnlNumber,
kadonotakashi 0:8fdf9a60065b 499 ftm_output_compare_mode_t compareMode,
kadonotakashi 0:8fdf9a60065b 500 uint32_t compareValue);
kadonotakashi 0:8fdf9a60065b 501
kadonotakashi 0:8fdf9a60065b 502 /*!
kadonotakashi 0:8fdf9a60065b 503 * @brief Configures the dual edge capture mode of the FTM.
kadonotakashi 0:8fdf9a60065b 504 *
kadonotakashi 0:8fdf9a60065b 505 * This function sets up the dual edge capture mode on a channel pair. The capture edge for the
kadonotakashi 0:8fdf9a60065b 506 * channel pair and the capture mode (one-shot or continuous) is specified in the parameter
kadonotakashi 0:8fdf9a60065b 507 * argument. The filter function is disabled if the filterVal argument passed is zero. The filter
kadonotakashi 0:8fdf9a60065b 508 * function is available only on channels 0 and 2. The user has to read the channel CnV registers
kadonotakashi 0:8fdf9a60065b 509 * separately to get the capture values.
kadonotakashi 0:8fdf9a60065b 510 *
kadonotakashi 0:8fdf9a60065b 511 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 512 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
kadonotakashi 0:8fdf9a60065b 513 * @param edgeParam Sets up the dual edge capture function
kadonotakashi 0:8fdf9a60065b 514 * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1.
kadonotakashi 0:8fdf9a60065b 515 */
kadonotakashi 0:8fdf9a60065b 516 void FTM_SetupDualEdgeCapture(FTM_Type *base,
kadonotakashi 0:8fdf9a60065b 517 ftm_chnl_t chnlPairNumber,
kadonotakashi 0:8fdf9a60065b 518 const ftm_dual_edge_capture_param_t *edgeParam,
kadonotakashi 0:8fdf9a60065b 519 uint32_t filterValue);
kadonotakashi 0:8fdf9a60065b 520
kadonotakashi 0:8fdf9a60065b 521 /*! @}*/
kadonotakashi 0:8fdf9a60065b 522
kadonotakashi 0:8fdf9a60065b 523 /*!
kadonotakashi 0:8fdf9a60065b 524 * @brief Sets up the working of the FTM fault protection.
kadonotakashi 0:8fdf9a60065b 525 *
kadonotakashi 0:8fdf9a60065b 526 * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter.
kadonotakashi 0:8fdf9a60065b 527 *
kadonotakashi 0:8fdf9a60065b 528 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 529 * @param faultNumber FTM fault to configure.
kadonotakashi 0:8fdf9a60065b 530 * @param faultParams Parameters passed in to set up the fault
kadonotakashi 0:8fdf9a60065b 531 */
kadonotakashi 0:8fdf9a60065b 532 void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams);
kadonotakashi 0:8fdf9a60065b 533
kadonotakashi 0:8fdf9a60065b 534 /*!
kadonotakashi 0:8fdf9a60065b 535 * @name Interrupt Interface
kadonotakashi 0:8fdf9a60065b 536 * @{
kadonotakashi 0:8fdf9a60065b 537 */
kadonotakashi 0:8fdf9a60065b 538
kadonotakashi 0:8fdf9a60065b 539 /*!
kadonotakashi 0:8fdf9a60065b 540 * @brief Enables the selected FTM interrupts.
kadonotakashi 0:8fdf9a60065b 541 *
kadonotakashi 0:8fdf9a60065b 542 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 543 * @param mask The interrupts to enable. This is a logical OR of members of the
kadonotakashi 0:8fdf9a60065b 544 * enumeration ::ftm_interrupt_enable_t
kadonotakashi 0:8fdf9a60065b 545 */
kadonotakashi 0:8fdf9a60065b 546 void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 547
kadonotakashi 0:8fdf9a60065b 548 /*!
kadonotakashi 0:8fdf9a60065b 549 * @brief Disables the selected FTM interrupts.
kadonotakashi 0:8fdf9a60065b 550 *
kadonotakashi 0:8fdf9a60065b 551 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 552 * @param mask The interrupts to enable. This is a logical OR of members of the
kadonotakashi 0:8fdf9a60065b 553 * enumeration ::ftm_interrupt_enable_t
kadonotakashi 0:8fdf9a60065b 554 */
kadonotakashi 0:8fdf9a60065b 555 void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 556
kadonotakashi 0:8fdf9a60065b 557 /*!
kadonotakashi 0:8fdf9a60065b 558 * @brief Gets the enabled FTM interrupts.
kadonotakashi 0:8fdf9a60065b 559 *
kadonotakashi 0:8fdf9a60065b 560 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 561 *
kadonotakashi 0:8fdf9a60065b 562 * @return The enabled interrupts. This is the logical OR of members of the
kadonotakashi 0:8fdf9a60065b 563 * enumeration ::ftm_interrupt_enable_t
kadonotakashi 0:8fdf9a60065b 564 */
kadonotakashi 0:8fdf9a60065b 565 uint32_t FTM_GetEnabledInterrupts(FTM_Type *base);
kadonotakashi 0:8fdf9a60065b 566
kadonotakashi 0:8fdf9a60065b 567 /*! @}*/
kadonotakashi 0:8fdf9a60065b 568
kadonotakashi 0:8fdf9a60065b 569 /*!
kadonotakashi 0:8fdf9a60065b 570 * @name Status Interface
kadonotakashi 0:8fdf9a60065b 571 * @{
kadonotakashi 0:8fdf9a60065b 572 */
kadonotakashi 0:8fdf9a60065b 573
kadonotakashi 0:8fdf9a60065b 574 /*!
kadonotakashi 0:8fdf9a60065b 575 * @brief Gets the FTM status flags.
kadonotakashi 0:8fdf9a60065b 576 *
kadonotakashi 0:8fdf9a60065b 577 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 578 *
kadonotakashi 0:8fdf9a60065b 579 * @return The status flags. This is the logical OR of members of the
kadonotakashi 0:8fdf9a60065b 580 * enumeration ::ftm_status_flags_t
kadonotakashi 0:8fdf9a60065b 581 */
kadonotakashi 0:8fdf9a60065b 582 uint32_t FTM_GetStatusFlags(FTM_Type *base);
kadonotakashi 0:8fdf9a60065b 583
kadonotakashi 0:8fdf9a60065b 584 /*!
kadonotakashi 0:8fdf9a60065b 585 * @brief Clears the FTM status flags.
kadonotakashi 0:8fdf9a60065b 586 *
kadonotakashi 0:8fdf9a60065b 587 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 588 * @param mask The status flags to clear. This is a logical OR of members of the
kadonotakashi 0:8fdf9a60065b 589 * enumeration ::ftm_status_flags_t
kadonotakashi 0:8fdf9a60065b 590 */
kadonotakashi 0:8fdf9a60065b 591 void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 592
kadonotakashi 0:8fdf9a60065b 593 /*! @}*/
kadonotakashi 0:8fdf9a60065b 594
kadonotakashi 0:8fdf9a60065b 595 /*!
kadonotakashi 0:8fdf9a60065b 596 * @name Timer Start and Stop
kadonotakashi 0:8fdf9a60065b 597 * @{
kadonotakashi 0:8fdf9a60065b 598 */
kadonotakashi 0:8fdf9a60065b 599
kadonotakashi 0:8fdf9a60065b 600 /*!
kadonotakashi 0:8fdf9a60065b 601 * @brief Starts the FTM counter.
kadonotakashi 0:8fdf9a60065b 602 *
kadonotakashi 0:8fdf9a60065b 603 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 604 * @param clockSource FTM clock source; After the clock source is set, the counter starts running.
kadonotakashi 0:8fdf9a60065b 605 */
kadonotakashi 0:8fdf9a60065b 606 static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource)
kadonotakashi 0:8fdf9a60065b 607 {
kadonotakashi 0:8fdf9a60065b 608 uint32_t reg = base->SC;
kadonotakashi 0:8fdf9a60065b 609
kadonotakashi 0:8fdf9a60065b 610 reg &= ~(FTM_SC_CLKS_MASK);
kadonotakashi 0:8fdf9a60065b 611 reg |= FTM_SC_CLKS(clockSource);
kadonotakashi 0:8fdf9a60065b 612 base->SC = reg;
kadonotakashi 0:8fdf9a60065b 613 }
kadonotakashi 0:8fdf9a60065b 614
kadonotakashi 0:8fdf9a60065b 615 /*!
kadonotakashi 0:8fdf9a60065b 616 * @brief Stops the FTM counter.
kadonotakashi 0:8fdf9a60065b 617 *
kadonotakashi 0:8fdf9a60065b 618 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 619 */
kadonotakashi 0:8fdf9a60065b 620 static inline void FTM_StopTimer(FTM_Type *base)
kadonotakashi 0:8fdf9a60065b 621 {
kadonotakashi 0:8fdf9a60065b 622 /* Set clock source to none to disable counter */
kadonotakashi 0:8fdf9a60065b 623 base->SC &= ~(FTM_SC_CLKS_MASK);
kadonotakashi 0:8fdf9a60065b 624 }
kadonotakashi 0:8fdf9a60065b 625
kadonotakashi 0:8fdf9a60065b 626 /*! @}*/
kadonotakashi 0:8fdf9a60065b 627
kadonotakashi 0:8fdf9a60065b 628 /*!
kadonotakashi 0:8fdf9a60065b 629 * @name Software output control
kadonotakashi 0:8fdf9a60065b 630 * @{
kadonotakashi 0:8fdf9a60065b 631 */
kadonotakashi 0:8fdf9a60065b 632
kadonotakashi 0:8fdf9a60065b 633 /*!
kadonotakashi 0:8fdf9a60065b 634 * @brief Enables or disables the channel software output control.
kadonotakashi 0:8fdf9a60065b 635 *
kadonotakashi 0:8fdf9a60065b 636 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 637 * @param chnlNumber Channel to be enabled or disabled
kadonotakashi 0:8fdf9a60065b 638 * @param value true: channel output is affected by software output control
kadonotakashi 0:8fdf9a60065b 639 false: channel output is unaffected by software output control
kadonotakashi 0:8fdf9a60065b 640 */
kadonotakashi 0:8fdf9a60065b 641 static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
kadonotakashi 0:8fdf9a60065b 642 {
kadonotakashi 0:8fdf9a60065b 643 if (value)
kadonotakashi 0:8fdf9a60065b 644 {
kadonotakashi 0:8fdf9a60065b 645 base->SWOCTRL |= (1U << chnlNumber);
kadonotakashi 0:8fdf9a60065b 646 }
kadonotakashi 0:8fdf9a60065b 647 else
kadonotakashi 0:8fdf9a60065b 648 {
kadonotakashi 0:8fdf9a60065b 649 base->SWOCTRL &= ~(1U << chnlNumber);
kadonotakashi 0:8fdf9a60065b 650 }
kadonotakashi 0:8fdf9a60065b 651 }
kadonotakashi 0:8fdf9a60065b 652
kadonotakashi 0:8fdf9a60065b 653 /*!
kadonotakashi 0:8fdf9a60065b 654 * @brief Sets the channel software output control value.
kadonotakashi 0:8fdf9a60065b 655 *
kadonotakashi 0:8fdf9a60065b 656 * @param base FTM peripheral base address.
kadonotakashi 0:8fdf9a60065b 657 * @param chnlNumber Channel to be configured
kadonotakashi 0:8fdf9a60065b 658 * @param value true to set 1, false to set 0
kadonotakashi 0:8fdf9a60065b 659 */
kadonotakashi 0:8fdf9a60065b 660 static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
kadonotakashi 0:8fdf9a60065b 661 {
kadonotakashi 0:8fdf9a60065b 662 if (value)
kadonotakashi 0:8fdf9a60065b 663 {
kadonotakashi 0:8fdf9a60065b 664 base->SWOCTRL |= (1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT));
kadonotakashi 0:8fdf9a60065b 665 }
kadonotakashi 0:8fdf9a60065b 666 else
kadonotakashi 0:8fdf9a60065b 667 {
kadonotakashi 0:8fdf9a60065b 668 base->SWOCTRL &= ~(1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT));
kadonotakashi 0:8fdf9a60065b 669 }
kadonotakashi 0:8fdf9a60065b 670 }
kadonotakashi 0:8fdf9a60065b 671
kadonotakashi 0:8fdf9a60065b 672 /*! @}*/
kadonotakashi 0:8fdf9a60065b 673
kadonotakashi 0:8fdf9a60065b 674 /*!
kadonotakashi 0:8fdf9a60065b 675 * @brief Enables or disables the FTM global time base signal generation to other FTMs.
kadonotakashi 0:8fdf9a60065b 676 *
kadonotakashi 0:8fdf9a60065b 677 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 678 * @param enable true to enable, false to disable
kadonotakashi 0:8fdf9a60065b 679 */
kadonotakashi 0:8fdf9a60065b 680 static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 681 {
kadonotakashi 0:8fdf9a60065b 682 if (enable)
kadonotakashi 0:8fdf9a60065b 683 {
kadonotakashi 0:8fdf9a60065b 684 base->CONF |= FTM_CONF_GTBEOUT_MASK;
kadonotakashi 0:8fdf9a60065b 685 }
kadonotakashi 0:8fdf9a60065b 686 else
kadonotakashi 0:8fdf9a60065b 687 {
kadonotakashi 0:8fdf9a60065b 688 base->CONF &= ~FTM_CONF_GTBEOUT_MASK;
kadonotakashi 0:8fdf9a60065b 689 }
kadonotakashi 0:8fdf9a60065b 690 }
kadonotakashi 0:8fdf9a60065b 691
kadonotakashi 0:8fdf9a60065b 692 /*!
kadonotakashi 0:8fdf9a60065b 693 * @brief Sets the FTM peripheral timer channel output mask.
kadonotakashi 0:8fdf9a60065b 694 *
kadonotakashi 0:8fdf9a60065b 695 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 696 * @param chnlNumber Channel to be configured
kadonotakashi 0:8fdf9a60065b 697 * @param mask true: masked, channel is forced to its inactive state; false: unmasked
kadonotakashi 0:8fdf9a60065b 698 */
kadonotakashi 0:8fdf9a60065b 699 static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask)
kadonotakashi 0:8fdf9a60065b 700 {
kadonotakashi 0:8fdf9a60065b 701 if (mask)
kadonotakashi 0:8fdf9a60065b 702 {
kadonotakashi 0:8fdf9a60065b 703 base->OUTMASK |= (1U << chnlNumber);
kadonotakashi 0:8fdf9a60065b 704 }
kadonotakashi 0:8fdf9a60065b 705 else
kadonotakashi 0:8fdf9a60065b 706 {
kadonotakashi 0:8fdf9a60065b 707 base->OUTMASK &= ~(1U << chnlNumber);
kadonotakashi 0:8fdf9a60065b 708 }
kadonotakashi 0:8fdf9a60065b 709 }
kadonotakashi 0:8fdf9a60065b 710
kadonotakashi 0:8fdf9a60065b 711 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
kadonotakashi 0:8fdf9a60065b 712 /*!
kadonotakashi 0:8fdf9a60065b 713 * @brief Allows users to enable an output on an FTM channel.
kadonotakashi 0:8fdf9a60065b 714 *
kadonotakashi 0:8fdf9a60065b 715 * To enable the PWM channel output call this function with val=true. For input mode,
kadonotakashi 0:8fdf9a60065b 716 * call this function with val=false.
kadonotakashi 0:8fdf9a60065b 717 *
kadonotakashi 0:8fdf9a60065b 718 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 719 * @param chnlNumber Channel to be configured
kadonotakashi 0:8fdf9a60065b 720 * @param value true: enable output; false: output is disabled, used in input mode
kadonotakashi 0:8fdf9a60065b 721 */
kadonotakashi 0:8fdf9a60065b 722 static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)
kadonotakashi 0:8fdf9a60065b 723 {
kadonotakashi 0:8fdf9a60065b 724 if (value)
kadonotakashi 0:8fdf9a60065b 725 {
kadonotakashi 0:8fdf9a60065b 726 base->SC |= (1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT));
kadonotakashi 0:8fdf9a60065b 727 }
kadonotakashi 0:8fdf9a60065b 728 else
kadonotakashi 0:8fdf9a60065b 729 {
kadonotakashi 0:8fdf9a60065b 730 base->SC &= ~(1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT));
kadonotakashi 0:8fdf9a60065b 731 }
kadonotakashi 0:8fdf9a60065b 732 }
kadonotakashi 0:8fdf9a60065b 733 #endif
kadonotakashi 0:8fdf9a60065b 734
kadonotakashi 0:8fdf9a60065b 735 /*!
kadonotakashi 0:8fdf9a60065b 736 * @name Channel pair operations
kadonotakashi 0:8fdf9a60065b 737 * @{
kadonotakashi 0:8fdf9a60065b 738 */
kadonotakashi 0:8fdf9a60065b 739
kadonotakashi 0:8fdf9a60065b 740 /*!
kadonotakashi 0:8fdf9a60065b 741 * @brief This function enables/disables the fault control in a channel pair.
kadonotakashi 0:8fdf9a60065b 742 *
kadonotakashi 0:8fdf9a60065b 743 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 744 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
kadonotakashi 0:8fdf9a60065b 745 * @param value true: Enable fault control for this channel pair; false: No fault control
kadonotakashi 0:8fdf9a60065b 746 */
kadonotakashi 0:8fdf9a60065b 747 static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
kadonotakashi 0:8fdf9a60065b 748 {
kadonotakashi 0:8fdf9a60065b 749 if (value)
kadonotakashi 0:8fdf9a60065b 750 {
kadonotakashi 0:8fdf9a60065b 751 base->COMBINE |= (1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
kadonotakashi 0:8fdf9a60065b 752 }
kadonotakashi 0:8fdf9a60065b 753 else
kadonotakashi 0:8fdf9a60065b 754 {
kadonotakashi 0:8fdf9a60065b 755 base->COMBINE &= ~(1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
kadonotakashi 0:8fdf9a60065b 756 }
kadonotakashi 0:8fdf9a60065b 757 }
kadonotakashi 0:8fdf9a60065b 758
kadonotakashi 0:8fdf9a60065b 759 /*!
kadonotakashi 0:8fdf9a60065b 760 * @brief This function enables/disables the dead time insertion in a channel pair.
kadonotakashi 0:8fdf9a60065b 761 *
kadonotakashi 0:8fdf9a60065b 762 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 763 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
kadonotakashi 0:8fdf9a60065b 764 * @param value true: Insert dead time in this channel pair; false: No dead time inserted
kadonotakashi 0:8fdf9a60065b 765 */
kadonotakashi 0:8fdf9a60065b 766 static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
kadonotakashi 0:8fdf9a60065b 767 {
kadonotakashi 0:8fdf9a60065b 768 if (value)
kadonotakashi 0:8fdf9a60065b 769 {
kadonotakashi 0:8fdf9a60065b 770 base->COMBINE |= (1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
kadonotakashi 0:8fdf9a60065b 771 }
kadonotakashi 0:8fdf9a60065b 772 else
kadonotakashi 0:8fdf9a60065b 773 {
kadonotakashi 0:8fdf9a60065b 774 base->COMBINE &= ~(1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
kadonotakashi 0:8fdf9a60065b 775 }
kadonotakashi 0:8fdf9a60065b 776 }
kadonotakashi 0:8fdf9a60065b 777
kadonotakashi 0:8fdf9a60065b 778 /*!
kadonotakashi 0:8fdf9a60065b 779 * @brief This function enables/disables complementary mode in a channel pair.
kadonotakashi 0:8fdf9a60065b 780 *
kadonotakashi 0:8fdf9a60065b 781 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 782 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
kadonotakashi 0:8fdf9a60065b 783 * @param value true: enable complementary mode; false: disable complementary mode
kadonotakashi 0:8fdf9a60065b 784 */
kadonotakashi 0:8fdf9a60065b 785 static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
kadonotakashi 0:8fdf9a60065b 786 {
kadonotakashi 0:8fdf9a60065b 787 if (value)
kadonotakashi 0:8fdf9a60065b 788 {
kadonotakashi 0:8fdf9a60065b 789 base->COMBINE |= (1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
kadonotakashi 0:8fdf9a60065b 790 }
kadonotakashi 0:8fdf9a60065b 791 else
kadonotakashi 0:8fdf9a60065b 792 {
kadonotakashi 0:8fdf9a60065b 793 base->COMBINE &= ~(1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
kadonotakashi 0:8fdf9a60065b 794 }
kadonotakashi 0:8fdf9a60065b 795 }
kadonotakashi 0:8fdf9a60065b 796
kadonotakashi 0:8fdf9a60065b 797 /*!
kadonotakashi 0:8fdf9a60065b 798 * @brief This function enables/disables inverting control in a channel pair.
kadonotakashi 0:8fdf9a60065b 799 *
kadonotakashi 0:8fdf9a60065b 800 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 801 * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3
kadonotakashi 0:8fdf9a60065b 802 * @param value true: enable inverting; false: disable inverting
kadonotakashi 0:8fdf9a60065b 803 */
kadonotakashi 0:8fdf9a60065b 804 static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)
kadonotakashi 0:8fdf9a60065b 805 {
kadonotakashi 0:8fdf9a60065b 806 if (value)
kadonotakashi 0:8fdf9a60065b 807 {
kadonotakashi 0:8fdf9a60065b 808 base->INVCTRL |= (1U << chnlPairNumber);
kadonotakashi 0:8fdf9a60065b 809 }
kadonotakashi 0:8fdf9a60065b 810 else
kadonotakashi 0:8fdf9a60065b 811 {
kadonotakashi 0:8fdf9a60065b 812 base->INVCTRL &= ~(1U << chnlPairNumber);
kadonotakashi 0:8fdf9a60065b 813 }
kadonotakashi 0:8fdf9a60065b 814 }
kadonotakashi 0:8fdf9a60065b 815
kadonotakashi 0:8fdf9a60065b 816 /*! @}*/
kadonotakashi 0:8fdf9a60065b 817
kadonotakashi 0:8fdf9a60065b 818 /*!
kadonotakashi 0:8fdf9a60065b 819 * @name Quad Decoder
kadonotakashi 0:8fdf9a60065b 820 * @{
kadonotakashi 0:8fdf9a60065b 821 */
kadonotakashi 0:8fdf9a60065b 822
kadonotakashi 0:8fdf9a60065b 823 /*!
kadonotakashi 0:8fdf9a60065b 824 * @brief Configures the parameters and activates the quadrature decoder mode.
kadonotakashi 0:8fdf9a60065b 825 *
kadonotakashi 0:8fdf9a60065b 826 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 827 * @param phaseAParams Phase A configuration parameters
kadonotakashi 0:8fdf9a60065b 828 * @param phaseBParams Phase B configuration parameters
kadonotakashi 0:8fdf9a60065b 829 * @param quadMode Selects encoding mode used in quadrature decoder mode
kadonotakashi 0:8fdf9a60065b 830 */
kadonotakashi 0:8fdf9a60065b 831 void FTM_SetupQuadDecode(FTM_Type *base,
kadonotakashi 0:8fdf9a60065b 832 const ftm_phase_params_t *phaseAParams,
kadonotakashi 0:8fdf9a60065b 833 const ftm_phase_params_t *phaseBParams,
kadonotakashi 0:8fdf9a60065b 834 ftm_quad_decode_mode_t quadMode);
kadonotakashi 0:8fdf9a60065b 835
kadonotakashi 0:8fdf9a60065b 836 /*!
kadonotakashi 0:8fdf9a60065b 837 * @brief Gets the FTM Quad Decoder flags.
kadonotakashi 0:8fdf9a60065b 838 *
kadonotakashi 0:8fdf9a60065b 839 * @param base FTM peripheral base address.
kadonotakashi 0:8fdf9a60065b 840 * @return Flag mask of FTM Quad Decoder, see #_ftm_quad_decoder_flags.
kadonotakashi 0:8fdf9a60065b 841 */
kadonotakashi 0:8fdf9a60065b 842 static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base)
kadonotakashi 0:8fdf9a60065b 843 {
kadonotakashi 0:8fdf9a60065b 844 return base->QDCTRL & (FTM_QDCTRL_QUADIR_MASK | FTM_QDCTRL_TOFDIR_MASK);
kadonotakashi 0:8fdf9a60065b 845 }
kadonotakashi 0:8fdf9a60065b 846
kadonotakashi 0:8fdf9a60065b 847 /*!
kadonotakashi 0:8fdf9a60065b 848 * @brief Sets the modulo values for Quad Decoder.
kadonotakashi 0:8fdf9a60065b 849 *
kadonotakashi 0:8fdf9a60065b 850 * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes
kadonotakashi 0:8fdf9a60065b 851 * over, the counter value goes to the other side and decrease/increase again.
kadonotakashi 0:8fdf9a60065b 852 *
kadonotakashi 0:8fdf9a60065b 853 * @param base FTM peripheral base address.
kadonotakashi 0:8fdf9a60065b 854 * @param startValue The low limit value for Quad Decoder counter.
kadonotakashi 0:8fdf9a60065b 855 * @param overValue The high limit value for Quad Decoder counter.
kadonotakashi 0:8fdf9a60065b 856 */
kadonotakashi 0:8fdf9a60065b 857 static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue)
kadonotakashi 0:8fdf9a60065b 858 {
kadonotakashi 0:8fdf9a60065b 859 base->CNTIN = startValue;
kadonotakashi 0:8fdf9a60065b 860 base->MOD = overValue;
kadonotakashi 0:8fdf9a60065b 861 }
kadonotakashi 0:8fdf9a60065b 862
kadonotakashi 0:8fdf9a60065b 863 /*!
kadonotakashi 0:8fdf9a60065b 864 * @brief Gets the current Quad Decoder counter value.
kadonotakashi 0:8fdf9a60065b 865 *
kadonotakashi 0:8fdf9a60065b 866 * @param base FTM peripheral base address.
kadonotakashi 0:8fdf9a60065b 867 * @return Current quad Decoder counter value.
kadonotakashi 0:8fdf9a60065b 868 */
kadonotakashi 0:8fdf9a60065b 869 static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base)
kadonotakashi 0:8fdf9a60065b 870 {
kadonotakashi 0:8fdf9a60065b 871 return base->CNT;
kadonotakashi 0:8fdf9a60065b 872 }
kadonotakashi 0:8fdf9a60065b 873
kadonotakashi 0:8fdf9a60065b 874 /*!
kadonotakashi 0:8fdf9a60065b 875 * @brief Clears the current Quad Decoder counter value.
kadonotakashi 0:8fdf9a60065b 876 *
kadonotakashi 0:8fdf9a60065b 877 * The counter is set as the initial value.
kadonotakashi 0:8fdf9a60065b 878 *
kadonotakashi 0:8fdf9a60065b 879 * @param base FTM peripheral base address.
kadonotakashi 0:8fdf9a60065b 880 */
kadonotakashi 0:8fdf9a60065b 881 static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base)
kadonotakashi 0:8fdf9a60065b 882 {
kadonotakashi 0:8fdf9a60065b 883 base->CNT = base->CNTIN;
kadonotakashi 0:8fdf9a60065b 884 }
kadonotakashi 0:8fdf9a60065b 885
kadonotakashi 0:8fdf9a60065b 886 /*! @}*/
kadonotakashi 0:8fdf9a60065b 887
kadonotakashi 0:8fdf9a60065b 888 /*!
kadonotakashi 0:8fdf9a60065b 889 * @brief Enables or disables the FTM software trigger for PWM synchronization.
kadonotakashi 0:8fdf9a60065b 890 *
kadonotakashi 0:8fdf9a60065b 891 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 892 * @param enable true: software trigger is selected, false: software trigger is not selected
kadonotakashi 0:8fdf9a60065b 893 */
kadonotakashi 0:8fdf9a60065b 894 static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 895 {
kadonotakashi 0:8fdf9a60065b 896 if (enable)
kadonotakashi 0:8fdf9a60065b 897 {
kadonotakashi 0:8fdf9a60065b 898 base->SYNC |= FTM_SYNC_SWSYNC_MASK;
kadonotakashi 0:8fdf9a60065b 899 }
kadonotakashi 0:8fdf9a60065b 900 else
kadonotakashi 0:8fdf9a60065b 901 {
kadonotakashi 0:8fdf9a60065b 902 base->SYNC &= ~FTM_SYNC_SWSYNC_MASK;
kadonotakashi 0:8fdf9a60065b 903 }
kadonotakashi 0:8fdf9a60065b 904 }
kadonotakashi 0:8fdf9a60065b 905
kadonotakashi 0:8fdf9a60065b 906 /*!
kadonotakashi 0:8fdf9a60065b 907 * @brief Enables or disables the FTM write protection.
kadonotakashi 0:8fdf9a60065b 908 *
kadonotakashi 0:8fdf9a60065b 909 * @param base FTM peripheral base address
kadonotakashi 0:8fdf9a60065b 910 * @param enable true: Write-protection is enabled, false: Write-protection is disabled
kadonotakashi 0:8fdf9a60065b 911 */
kadonotakashi 0:8fdf9a60065b 912 static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 913 {
kadonotakashi 0:8fdf9a60065b 914 /* Configure write protection */
kadonotakashi 0:8fdf9a60065b 915 if (enable)
kadonotakashi 0:8fdf9a60065b 916 {
kadonotakashi 0:8fdf9a60065b 917 base->FMS |= FTM_FMS_WPEN_MASK;
kadonotakashi 0:8fdf9a60065b 918 }
kadonotakashi 0:8fdf9a60065b 919 else
kadonotakashi 0:8fdf9a60065b 920 {
kadonotakashi 0:8fdf9a60065b 921 base->MODE |= FTM_MODE_WPDIS_MASK;
kadonotakashi 0:8fdf9a60065b 922 }
kadonotakashi 0:8fdf9a60065b 923 }
kadonotakashi 0:8fdf9a60065b 924
kadonotakashi 0:8fdf9a60065b 925 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 926 }
kadonotakashi 0:8fdf9a60065b 927 #endif
kadonotakashi 0:8fdf9a60065b 928
kadonotakashi 0:8fdf9a60065b 929 /*! @}*/
kadonotakashi 0:8fdf9a60065b 930
kadonotakashi 0:8fdf9a60065b 931 #endif /* _FSL_FTM_H_*/