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mbed-os/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/pll.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /** |
kadonotakashi | 0:8fdf9a60065b | 2 | * \file |
kadonotakashi | 0:8fdf9a60065b | 3 | * |
kadonotakashi | 0:8fdf9a60065b | 4 | * \brief PLL management |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * \asf_license_start |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * \page License |
kadonotakashi | 0:8fdf9a60065b | 11 | * |
kadonotakashi | 0:8fdf9a60065b | 12 | * Redistribution and use in source and binary forms, with or without |
kadonotakashi | 0:8fdf9a60065b | 13 | * modification, are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
kadonotakashi | 0:8fdf9a60065b | 16 | * this list of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 17 | * |
kadonotakashi | 0:8fdf9a60065b | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
kadonotakashi | 0:8fdf9a60065b | 19 | * this list of conditions and the following disclaimer in the documentation |
kadonotakashi | 0:8fdf9a60065b | 20 | * and/or other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 21 | * |
kadonotakashi | 0:8fdf9a60065b | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
kadonotakashi | 0:8fdf9a60065b | 23 | * from this software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 24 | * |
kadonotakashi | 0:8fdf9a60065b | 25 | * 4. This software may only be redistributed and used in connection with an |
kadonotakashi | 0:8fdf9a60065b | 26 | * Atmel microcontroller product. |
kadonotakashi | 0:8fdf9a60065b | 27 | * |
kadonotakashi | 0:8fdf9a60065b | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
kadonotakashi | 0:8fdf9a60065b | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
kadonotakashi | 0:8fdf9a60065b | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
kadonotakashi | 0:8fdf9a60065b | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
kadonotakashi | 0:8fdf9a60065b | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
kadonotakashi | 0:8fdf9a60065b | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
kadonotakashi | 0:8fdf9a60065b | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
kadonotakashi | 0:8fdf9a60065b | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
kadonotakashi | 0:8fdf9a60065b | 38 | * POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 39 | * |
kadonotakashi | 0:8fdf9a60065b | 40 | * \asf_license_stop |
kadonotakashi | 0:8fdf9a60065b | 41 | * |
kadonotakashi | 0:8fdf9a60065b | 42 | */ |
kadonotakashi | 0:8fdf9a60065b | 43 | /* |
kadonotakashi | 0:8fdf9a60065b | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
kadonotakashi | 0:8fdf9a60065b | 45 | */ |
kadonotakashi | 0:8fdf9a60065b | 46 | #ifndef CLK_PLL_H_INCLUDED |
kadonotakashi | 0:8fdf9a60065b | 47 | #define CLK_PLL_H_INCLUDED |
kadonotakashi | 0:8fdf9a60065b | 48 | |
kadonotakashi | 0:8fdf9a60065b | 49 | #include "parts.h" |
kadonotakashi | 0:8fdf9a60065b | 50 | #include "conf_clock.h" |
kadonotakashi | 0:8fdf9a60065b | 51 | |
kadonotakashi | 0:8fdf9a60065b | 52 | #if SAM3S |
kadonotakashi | 0:8fdf9a60065b | 53 | # include "sam3s/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 54 | #elif SAM3XA |
kadonotakashi | 0:8fdf9a60065b | 55 | # include "sam3x/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 56 | #elif SAM3U |
kadonotakashi | 0:8fdf9a60065b | 57 | # include "sam3u/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 58 | #elif SAM3N |
kadonotakashi | 0:8fdf9a60065b | 59 | # include "sam3n/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 60 | #elif SAM4S |
kadonotakashi | 0:8fdf9a60065b | 61 | # include "sam4s/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 62 | #elif SAM4E |
kadonotakashi | 0:8fdf9a60065b | 63 | # include "sam4e/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 64 | #elif SAM4C |
kadonotakashi | 0:8fdf9a60065b | 65 | # include "sam4c/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 66 | #elif SAM4CM |
kadonotakashi | 0:8fdf9a60065b | 67 | # include "sam4cm/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 68 | #elif SAM4CP |
kadonotakashi | 0:8fdf9a60065b | 69 | # include "sam4cp/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 70 | #elif SAM4L |
kadonotakashi | 0:8fdf9a60065b | 71 | # include "sam4l/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 72 | #elif SAM4N |
kadonotakashi | 0:8fdf9a60065b | 73 | # include "sam4n/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 74 | #elif SAMG |
kadonotakashi | 0:8fdf9a60065b | 75 | # include "samg/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 76 | #elif SAMV71 |
kadonotakashi | 0:8fdf9a60065b | 77 | # include "samv71/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 78 | #elif SAMV70 |
kadonotakashi | 0:8fdf9a60065b | 79 | # include "samv70/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 80 | #elif SAME70 |
kadonotakashi | 0:8fdf9a60065b | 81 | # include "same70/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 82 | #elif SAMS70 |
kadonotakashi | 0:8fdf9a60065b | 83 | # include "sams70/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 84 | #elif (UC3A0 || UC3A1) |
kadonotakashi | 0:8fdf9a60065b | 85 | # include "uc3a0_a1/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 86 | #elif UC3A3 |
kadonotakashi | 0:8fdf9a60065b | 87 | # include "uc3a3_a4/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 88 | #elif UC3B |
kadonotakashi | 0:8fdf9a60065b | 89 | # include "uc3b0_b1/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 90 | #elif UC3C |
kadonotakashi | 0:8fdf9a60065b | 91 | # include "uc3c/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 92 | #elif UC3D |
kadonotakashi | 0:8fdf9a60065b | 93 | # include "uc3d/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 94 | #elif (UC3L0128 || UC3L0256 || UC3L3_L4) |
kadonotakashi | 0:8fdf9a60065b | 95 | # include "uc3l/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 96 | #elif XMEGA |
kadonotakashi | 0:8fdf9a60065b | 97 | # include "xmega/pll.h" |
kadonotakashi | 0:8fdf9a60065b | 98 | #else |
kadonotakashi | 0:8fdf9a60065b | 99 | # error Unsupported chip type |
kadonotakashi | 0:8fdf9a60065b | 100 | #endif |
kadonotakashi | 0:8fdf9a60065b | 101 | |
kadonotakashi | 0:8fdf9a60065b | 102 | /** |
kadonotakashi | 0:8fdf9a60065b | 103 | * \ingroup clk_group |
kadonotakashi | 0:8fdf9a60065b | 104 | * \defgroup pll_group PLL Management |
kadonotakashi | 0:8fdf9a60065b | 105 | * |
kadonotakashi | 0:8fdf9a60065b | 106 | * This group contains functions and definitions related to configuring |
kadonotakashi | 0:8fdf9a60065b | 107 | * and enabling/disabling on-chip PLLs. A PLL will take an input signal |
kadonotakashi | 0:8fdf9a60065b | 108 | * (the \em source), optionally divide the frequency by a configurable |
kadonotakashi | 0:8fdf9a60065b | 109 | * \em divider, and then multiply the frequency by a configurable \em |
kadonotakashi | 0:8fdf9a60065b | 110 | * multiplier. |
kadonotakashi | 0:8fdf9a60065b | 111 | * |
kadonotakashi | 0:8fdf9a60065b | 112 | * Some devices don't support input dividers; specifying any other |
kadonotakashi | 0:8fdf9a60065b | 113 | * divisor than 1 on these devices will result in an assertion failure. |
kadonotakashi | 0:8fdf9a60065b | 114 | * Other devices may have various restrictions to the frequency range of |
kadonotakashi | 0:8fdf9a60065b | 115 | * the input and output signals. |
kadonotakashi | 0:8fdf9a60065b | 116 | * |
kadonotakashi | 0:8fdf9a60065b | 117 | * \par Example: Setting up PLL0 with default parameters |
kadonotakashi | 0:8fdf9a60065b | 118 | * |
kadonotakashi | 0:8fdf9a60065b | 119 | * The following example shows how to configure and enable PLL0 using |
kadonotakashi | 0:8fdf9a60065b | 120 | * the default parameters specified using the configuration symbols |
kadonotakashi | 0:8fdf9a60065b | 121 | * listed above. |
kadonotakashi | 0:8fdf9a60065b | 122 | * \code |
kadonotakashi | 0:8fdf9a60065b | 123 | pll_enable_config_defaults(0); \endcode |
kadonotakashi | 0:8fdf9a60065b | 124 | * |
kadonotakashi | 0:8fdf9a60065b | 125 | * To configure, enable PLL0 using the default parameters and to disable |
kadonotakashi | 0:8fdf9a60065b | 126 | * a specific feature like Wide Bandwidth Mode (a UC3A3-specific |
kadonotakashi | 0:8fdf9a60065b | 127 | * PLL option.), you can use this initialization process. |
kadonotakashi | 0:8fdf9a60065b | 128 | * \code |
kadonotakashi | 0:8fdf9a60065b | 129 | struct pll_config pllcfg; |
kadonotakashi | 0:8fdf9a60065b | 130 | if (pll_is_locked(pll_id)) { |
kadonotakashi | 0:8fdf9a60065b | 131 | return; // Pll already running |
kadonotakashi | 0:8fdf9a60065b | 132 | } |
kadonotakashi | 0:8fdf9a60065b | 133 | pll_enable_source(CONFIG_PLL0_SOURCE); |
kadonotakashi | 0:8fdf9a60065b | 134 | pll_config_defaults(&pllcfg, 0); |
kadonotakashi | 0:8fdf9a60065b | 135 | pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); |
kadonotakashi | 0:8fdf9a60065b | 136 | pll_enable(&pllcfg, 0); |
kadonotakashi | 0:8fdf9a60065b | 137 | pll_wait_for_lock(0); \endcode |
kadonotakashi | 0:8fdf9a60065b | 138 | * |
kadonotakashi | 0:8fdf9a60065b | 139 | * When the last function call returns, PLL0 is ready to be used as the |
kadonotakashi | 0:8fdf9a60065b | 140 | * main system clock source. |
kadonotakashi | 0:8fdf9a60065b | 141 | * |
kadonotakashi | 0:8fdf9a60065b | 142 | * \section pll_group_config Configuration Symbols |
kadonotakashi | 0:8fdf9a60065b | 143 | * |
kadonotakashi | 0:8fdf9a60065b | 144 | * Each PLL has a set of default parameters determined by the following |
kadonotakashi | 0:8fdf9a60065b | 145 | * configuration symbols in the application's configuration file: |
kadonotakashi | 0:8fdf9a60065b | 146 | * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the |
kadonotakashi | 0:8fdf9a60065b | 147 | * input of PLL \a n. Must be one of the values defined by the |
kadonotakashi | 0:8fdf9a60065b | 148 | * #pll_source enum. |
kadonotakashi | 0:8fdf9a60065b | 149 | * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL |
kadonotakashi | 0:8fdf9a60065b | 150 | * \a n. |
kadonotakashi | 0:8fdf9a60065b | 151 | * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. |
kadonotakashi | 0:8fdf9a60065b | 152 | * |
kadonotakashi | 0:8fdf9a60065b | 153 | * These configuration symbols determine the result of calling |
kadonotakashi | 0:8fdf9a60065b | 154 | * pll_config_defaults() and pll_get_default_rate(). |
kadonotakashi | 0:8fdf9a60065b | 155 | * |
kadonotakashi | 0:8fdf9a60065b | 156 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 157 | */ |
kadonotakashi | 0:8fdf9a60065b | 158 | |
kadonotakashi | 0:8fdf9a60065b | 159 | //! \name Chip-specific PLL characteristics |
kadonotakashi | 0:8fdf9a60065b | 160 | //@{ |
kadonotakashi | 0:8fdf9a60065b | 161 | /** |
kadonotakashi | 0:8fdf9a60065b | 162 | * \def PLL_MAX_STARTUP_CYCLES |
kadonotakashi | 0:8fdf9a60065b | 163 | * \brief Maximum PLL startup time in number of slow clock cycles |
kadonotakashi | 0:8fdf9a60065b | 164 | */ |
kadonotakashi | 0:8fdf9a60065b | 165 | /** |
kadonotakashi | 0:8fdf9a60065b | 166 | * \def NR_PLLS |
kadonotakashi | 0:8fdf9a60065b | 167 | * \brief Number of on-chip PLLs |
kadonotakashi | 0:8fdf9a60065b | 168 | */ |
kadonotakashi | 0:8fdf9a60065b | 169 | |
kadonotakashi | 0:8fdf9a60065b | 170 | /** |
kadonotakashi | 0:8fdf9a60065b | 171 | * \def PLL_MIN_HZ |
kadonotakashi | 0:8fdf9a60065b | 172 | * \brief Minimum frequency that the PLL can generate |
kadonotakashi | 0:8fdf9a60065b | 173 | */ |
kadonotakashi | 0:8fdf9a60065b | 174 | /** |
kadonotakashi | 0:8fdf9a60065b | 175 | * \def PLL_MAX_HZ |
kadonotakashi | 0:8fdf9a60065b | 176 | * \brief Maximum frequency that the PLL can generate |
kadonotakashi | 0:8fdf9a60065b | 177 | */ |
kadonotakashi | 0:8fdf9a60065b | 178 | /** |
kadonotakashi | 0:8fdf9a60065b | 179 | * \def PLL_NR_OPTIONS |
kadonotakashi | 0:8fdf9a60065b | 180 | * \brief Number of PLL option bits |
kadonotakashi | 0:8fdf9a60065b | 181 | */ |
kadonotakashi | 0:8fdf9a60065b | 182 | //@} |
kadonotakashi | 0:8fdf9a60065b | 183 | |
kadonotakashi | 0:8fdf9a60065b | 184 | /** |
kadonotakashi | 0:8fdf9a60065b | 185 | * \enum pll_source |
kadonotakashi | 0:8fdf9a60065b | 186 | * \brief PLL clock source |
kadonotakashi | 0:8fdf9a60065b | 187 | */ |
kadonotakashi | 0:8fdf9a60065b | 188 | |
kadonotakashi | 0:8fdf9a60065b | 189 | //! \name PLL configuration |
kadonotakashi | 0:8fdf9a60065b | 190 | //@{ |
kadonotakashi | 0:8fdf9a60065b | 191 | |
kadonotakashi | 0:8fdf9a60065b | 192 | /** |
kadonotakashi | 0:8fdf9a60065b | 193 | * \struct pll_config |
kadonotakashi | 0:8fdf9a60065b | 194 | * \brief Hardware-specific representation of PLL configuration. |
kadonotakashi | 0:8fdf9a60065b | 195 | * |
kadonotakashi | 0:8fdf9a60065b | 196 | * This structure contains one or more device-specific values |
kadonotakashi | 0:8fdf9a60065b | 197 | * representing the current PLL configuration. The contents of this |
kadonotakashi | 0:8fdf9a60065b | 198 | * structure is typically different from platform to platform, and the |
kadonotakashi | 0:8fdf9a60065b | 199 | * user should not access any fields except through the PLL |
kadonotakashi | 0:8fdf9a60065b | 200 | * configuration API. |
kadonotakashi | 0:8fdf9a60065b | 201 | */ |
kadonotakashi | 0:8fdf9a60065b | 202 | |
kadonotakashi | 0:8fdf9a60065b | 203 | /** |
kadonotakashi | 0:8fdf9a60065b | 204 | * \fn void pll_config_init(struct pll_config *cfg, |
kadonotakashi | 0:8fdf9a60065b | 205 | * enum pll_source src, unsigned int div, unsigned int mul) |
kadonotakashi | 0:8fdf9a60065b | 206 | * \brief Initialize PLL configuration from standard parameters. |
kadonotakashi | 0:8fdf9a60065b | 207 | * |
kadonotakashi | 0:8fdf9a60065b | 208 | * \note This function may be defined inline because it is assumed to be |
kadonotakashi | 0:8fdf9a60065b | 209 | * called very few times, and usually with constant parameters. Inlining |
kadonotakashi | 0:8fdf9a60065b | 210 | * it will in such cases reduce the code size significantly. |
kadonotakashi | 0:8fdf9a60065b | 211 | * |
kadonotakashi | 0:8fdf9a60065b | 212 | * \param cfg The PLL configuration to be initialized. |
kadonotakashi | 0:8fdf9a60065b | 213 | * \param src The oscillator to be used as input to the PLL. |
kadonotakashi | 0:8fdf9a60065b | 214 | * \param div PLL input divider. |
kadonotakashi | 0:8fdf9a60065b | 215 | * \param mul PLL loop divider (i.e. multiplier). |
kadonotakashi | 0:8fdf9a60065b | 216 | * |
kadonotakashi | 0:8fdf9a60065b | 217 | * \return A configuration which will make the PLL run at |
kadonotakashi | 0:8fdf9a60065b | 218 | * (\a mul / \a div) times the frequency of \a src |
kadonotakashi | 0:8fdf9a60065b | 219 | */ |
kadonotakashi | 0:8fdf9a60065b | 220 | /** |
kadonotakashi | 0:8fdf9a60065b | 221 | * \def pll_config_defaults(cfg, pll_id) |
kadonotakashi | 0:8fdf9a60065b | 222 | * \brief Initialize PLL configuration using default parameters. |
kadonotakashi | 0:8fdf9a60065b | 223 | * |
kadonotakashi | 0:8fdf9a60065b | 224 | * After this function returns, \a cfg will contain a configuration |
kadonotakashi | 0:8fdf9a60065b | 225 | * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) |
kadonotakashi | 0:8fdf9a60065b | 226 | * times the frequency of CONFIG_PLLx_SOURCE. |
kadonotakashi | 0:8fdf9a60065b | 227 | * |
kadonotakashi | 0:8fdf9a60065b | 228 | * \param cfg The PLL configuration to be initialized. |
kadonotakashi | 0:8fdf9a60065b | 229 | * \param pll_id Use defaults for this PLL. |
kadonotakashi | 0:8fdf9a60065b | 230 | */ |
kadonotakashi | 0:8fdf9a60065b | 231 | /** |
kadonotakashi | 0:8fdf9a60065b | 232 | * \def pll_get_default_rate(pll_id) |
kadonotakashi | 0:8fdf9a60065b | 233 | * \brief Get the default rate in Hz of \a pll_id |
kadonotakashi | 0:8fdf9a60065b | 234 | */ |
kadonotakashi | 0:8fdf9a60065b | 235 | /** |
kadonotakashi | 0:8fdf9a60065b | 236 | * \fn void pll_config_set_option(struct pll_config *cfg, |
kadonotakashi | 0:8fdf9a60065b | 237 | * unsigned int option) |
kadonotakashi | 0:8fdf9a60065b | 238 | * \brief Set the PLL option bit \a option in the configuration \a cfg. |
kadonotakashi | 0:8fdf9a60065b | 239 | * |
kadonotakashi | 0:8fdf9a60065b | 240 | * \param cfg The PLL configuration to be changed. |
kadonotakashi | 0:8fdf9a60065b | 241 | * \param option The PLL option bit to be set. |
kadonotakashi | 0:8fdf9a60065b | 242 | */ |
kadonotakashi | 0:8fdf9a60065b | 243 | /** |
kadonotakashi | 0:8fdf9a60065b | 244 | * \fn void pll_config_clear_option(struct pll_config *cfg, |
kadonotakashi | 0:8fdf9a60065b | 245 | * unsigned int option) |
kadonotakashi | 0:8fdf9a60065b | 246 | * \brief Clear the PLL option bit \a option in the configuration \a cfg. |
kadonotakashi | 0:8fdf9a60065b | 247 | * |
kadonotakashi | 0:8fdf9a60065b | 248 | * \param cfg The PLL configuration to be changed. |
kadonotakashi | 0:8fdf9a60065b | 249 | * \param option The PLL option bit to be cleared. |
kadonotakashi | 0:8fdf9a60065b | 250 | */ |
kadonotakashi | 0:8fdf9a60065b | 251 | /** |
kadonotakashi | 0:8fdf9a60065b | 252 | * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 253 | * \brief Read the currently active configuration of \a pll_id. |
kadonotakashi | 0:8fdf9a60065b | 254 | * |
kadonotakashi | 0:8fdf9a60065b | 255 | * \param cfg The configuration object into which to store the currently |
kadonotakashi | 0:8fdf9a60065b | 256 | * active configuration. |
kadonotakashi | 0:8fdf9a60065b | 257 | * \param pll_id The ID of the PLL to be accessed. |
kadonotakashi | 0:8fdf9a60065b | 258 | */ |
kadonotakashi | 0:8fdf9a60065b | 259 | /** |
kadonotakashi | 0:8fdf9a60065b | 260 | * \fn void pll_config_write(const struct pll_config *cfg, |
kadonotakashi | 0:8fdf9a60065b | 261 | * unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 262 | * \brief Activate the configuration \a cfg on \a pll_id |
kadonotakashi | 0:8fdf9a60065b | 263 | * |
kadonotakashi | 0:8fdf9a60065b | 264 | * \param cfg The configuration object representing the PLL |
kadonotakashi | 0:8fdf9a60065b | 265 | * configuration to be activated. |
kadonotakashi | 0:8fdf9a60065b | 266 | * \param pll_id The ID of the PLL to be updated. |
kadonotakashi | 0:8fdf9a60065b | 267 | */ |
kadonotakashi | 0:8fdf9a60065b | 268 | |
kadonotakashi | 0:8fdf9a60065b | 269 | //@} |
kadonotakashi | 0:8fdf9a60065b | 270 | |
kadonotakashi | 0:8fdf9a60065b | 271 | //! \name Interaction with the PLL hardware |
kadonotakashi | 0:8fdf9a60065b | 272 | //@{ |
kadonotakashi | 0:8fdf9a60065b | 273 | /** |
kadonotakashi | 0:8fdf9a60065b | 274 | * \fn void pll_enable(const struct pll_config *cfg, |
kadonotakashi | 0:8fdf9a60065b | 275 | * unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 276 | * \brief Activate the configuration \a cfg and enable PLL \a pll_id. |
kadonotakashi | 0:8fdf9a60065b | 277 | * |
kadonotakashi | 0:8fdf9a60065b | 278 | * \param cfg The PLL configuration to be activated. |
kadonotakashi | 0:8fdf9a60065b | 279 | * \param pll_id The ID of the PLL to be enabled. |
kadonotakashi | 0:8fdf9a60065b | 280 | */ |
kadonotakashi | 0:8fdf9a60065b | 281 | /** |
kadonotakashi | 0:8fdf9a60065b | 282 | * \fn void pll_disable(unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 283 | * \brief Disable the PLL identified by \a pll_id. |
kadonotakashi | 0:8fdf9a60065b | 284 | * |
kadonotakashi | 0:8fdf9a60065b | 285 | * After this function is called, the PLL identified by \a pll_id will |
kadonotakashi | 0:8fdf9a60065b | 286 | * be disabled. The PLL configuration stored in hardware may be affected |
kadonotakashi | 0:8fdf9a60065b | 287 | * by this, so if the caller needs to restore the same configuration |
kadonotakashi | 0:8fdf9a60065b | 288 | * later, it should either do a pll_config_read() before disabling the |
kadonotakashi | 0:8fdf9a60065b | 289 | * PLL, or remember the last configuration written to the PLL. |
kadonotakashi | 0:8fdf9a60065b | 290 | * |
kadonotakashi | 0:8fdf9a60065b | 291 | * \param pll_id The ID of the PLL to be disabled. |
kadonotakashi | 0:8fdf9a60065b | 292 | */ |
kadonotakashi | 0:8fdf9a60065b | 293 | /** |
kadonotakashi | 0:8fdf9a60065b | 294 | * \fn bool pll_is_locked(unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 295 | * \brief Determine whether the PLL is locked or not. |
kadonotakashi | 0:8fdf9a60065b | 296 | * |
kadonotakashi | 0:8fdf9a60065b | 297 | * \param pll_id The ID of the PLL to check. |
kadonotakashi | 0:8fdf9a60065b | 298 | * |
kadonotakashi | 0:8fdf9a60065b | 299 | * \retval true The PLL is locked and ready to use as a clock source |
kadonotakashi | 0:8fdf9a60065b | 300 | * \retval false The PLL is not yet locked, or has not been enabled. |
kadonotakashi | 0:8fdf9a60065b | 301 | */ |
kadonotakashi | 0:8fdf9a60065b | 302 | /** |
kadonotakashi | 0:8fdf9a60065b | 303 | * \fn void pll_enable_source(enum pll_source src) |
kadonotakashi | 0:8fdf9a60065b | 304 | * \brief Enable the source of the pll. |
kadonotakashi | 0:8fdf9a60065b | 305 | * The source is enabled, if the source is not already running. |
kadonotakashi | 0:8fdf9a60065b | 306 | * |
kadonotakashi | 0:8fdf9a60065b | 307 | * \param src The ID of the PLL source to enable. |
kadonotakashi | 0:8fdf9a60065b | 308 | */ |
kadonotakashi | 0:8fdf9a60065b | 309 | /** |
kadonotakashi | 0:8fdf9a60065b | 310 | * \fn void pll_enable_config_defaults(unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 311 | * \brief Enable the pll with the default configuration. |
kadonotakashi | 0:8fdf9a60065b | 312 | * PLL is enabled, if the PLL is not already locked. |
kadonotakashi | 0:8fdf9a60065b | 313 | * |
kadonotakashi | 0:8fdf9a60065b | 314 | * \param pll_id The ID of the PLL to enable. |
kadonotakashi | 0:8fdf9a60065b | 315 | */ |
kadonotakashi | 0:8fdf9a60065b | 316 | |
kadonotakashi | 0:8fdf9a60065b | 317 | /** |
kadonotakashi | 0:8fdf9a60065b | 318 | * \brief Wait for PLL \a pll_id to become locked |
kadonotakashi | 0:8fdf9a60065b | 319 | * |
kadonotakashi | 0:8fdf9a60065b | 320 | * \todo Use a timeout to avoid waiting forever and hanging the system |
kadonotakashi | 0:8fdf9a60065b | 321 | * |
kadonotakashi | 0:8fdf9a60065b | 322 | * \param pll_id The ID of the PLL to wait for. |
kadonotakashi | 0:8fdf9a60065b | 323 | * |
kadonotakashi | 0:8fdf9a60065b | 324 | * \retval STATUS_OK The PLL is now locked. |
kadonotakashi | 0:8fdf9a60065b | 325 | * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. |
kadonotakashi | 0:8fdf9a60065b | 326 | */ |
kadonotakashi | 0:8fdf9a60065b | 327 | static inline int pll_wait_for_lock(unsigned int pll_id) |
kadonotakashi | 0:8fdf9a60065b | 328 | { |
kadonotakashi | 0:8fdf9a60065b | 329 | Assert(pll_id < NR_PLLS); |
kadonotakashi | 0:8fdf9a60065b | 330 | |
kadonotakashi | 0:8fdf9a60065b | 331 | while (!pll_is_locked(pll_id)) { |
kadonotakashi | 0:8fdf9a60065b | 332 | /* Do nothing */ |
kadonotakashi | 0:8fdf9a60065b | 333 | } |
kadonotakashi | 0:8fdf9a60065b | 334 | |
kadonotakashi | 0:8fdf9a60065b | 335 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 336 | } |
kadonotakashi | 0:8fdf9a60065b | 337 | |
kadonotakashi | 0:8fdf9a60065b | 338 | //@} |
kadonotakashi | 0:8fdf9a60065b | 339 | //! @} |
kadonotakashi | 0:8fdf9a60065b | 340 | |
kadonotakashi | 0:8fdf9a60065b | 341 | #endif /* CLK_PLL_H_INCLUDED */ |