Kazuki Yamamoto / at45db161d

Forked library from okini3939/at45db161d

Fork of at45db161d by Suga koubou

at45db161d.cpp@0:2e953bbaf3a5, 2011-09-11 (annotated)

Committer:
okini3939
Date:
Sun Sep 11 06:12:15 2011 +0000
Revision:
0:2e953bbaf3a5
Child:
1:b379e16fdf6f
AT45DB161D module



AT45DB161D (16Mbits, 2MB, 528B/block) /AT45DB081D (8Mbits, 1MB, 264B/block)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okini3939 0:2e953bbaf3a5 1 /**
okini3939 0:2e953bbaf3a5 2 * AT45DB161D module for arduino (C) Vincent
okini3939 0:2e953bbaf3a5 3 * SPI flash memory
okini3939 0:2e953bbaf3a5 4 * http://blog.blockos.org/?p=27
okini3939 0:2e953bbaf3a5 5 *
okini3939 0:2e953bbaf3a5 6 * bug fix by todotani
okini3939 0:2e953bbaf3a5 7 * http://todotani.cocolog-nifty.com/blog/2009/07/arduino-4cf4.html
okini3939 0:2e953bbaf3a5 8 *
okini3939 0:2e953bbaf3a5 9 * Modified for mbed, 2011 Suga.
okini3939 0:2e953bbaf3a5 10 */
okini3939 0:2e953bbaf3a5 11 #include "at45db161d.h"
okini3939 0:2e953bbaf3a5 12
okini3939 0:2e953bbaf3a5 13 /** CTOR **/
okini3939 0:2e953bbaf3a5 14 ATD45DB161D::ATD45DB161D(PinName mosi, PinName miso, PinName sclk, PinName cs)
okini3939 0:2e953bbaf3a5 15 : _spi(mosi, miso, sclk), _cs(cs)
okini3939 0:2e953bbaf3a5 16 {}
okini3939 0:2e953bbaf3a5 17
okini3939 0:2e953bbaf3a5 18 ATD45DB161D::ATD45DB161D(SPI &spi, PinName cs)
okini3939 0:2e953bbaf3a5 19 : _spi(spi), _cs(cs)
okini3939 0:2e953bbaf3a5 20 {}
okini3939 0:2e953bbaf3a5 21
okini3939 0:2e953bbaf3a5 22 /** DTOR **/
okini3939 0:2e953bbaf3a5 23 ATD45DB161D::~ATD45DB161D()
okini3939 0:2e953bbaf3a5 24 {}
okini3939 0:2e953bbaf3a5 25
okini3939 0:2e953bbaf3a5 26 /** Setup SPI and pinout **/
okini3939 0:2e953bbaf3a5 27 void ATD45DB161D::Init()
okini3939 0:2e953bbaf3a5 28 {
okini3939 0:2e953bbaf3a5 29 // uint8_t clr;
okini3939 0:2e953bbaf3a5 30
okini3939 0:2e953bbaf3a5 31 /* Initialize pinout */
okini3939 0:2e953bbaf3a5 32 /*
okini3939 0:2e953bbaf3a5 33 pinMode(DATAOUT, OUTPUT);
okini3939 0:2e953bbaf3a5 34 pinMode(DATAIN, INPUT);
okini3939 0:2e953bbaf3a5 35 pinMode(SPICLOCK, OUTPUT);
okini3939 0:2e953bbaf3a5 36 pinMode(SLAVESELECT, OUTPUT);
okini3939 0:2e953bbaf3a5 37 pinMode(DATAIN, INPUT);
okini3939 0:2e953bbaf3a5 38 */
okini3939 0:2e953bbaf3a5 39 /* Disable device */
okini3939 0:2e953bbaf3a5 40 DF_CS_inactive;
okini3939 0:2e953bbaf3a5 41
okini3939 0:2e953bbaf3a5 42 /* Setup SPI */
okini3939 0:2e953bbaf3a5 43 // SPCR = (1 << SPE) | (1 << MSTR) | (1 << CPOL) | (1 << CPHA);
okini3939 0:2e953bbaf3a5 44 _spi.format(8, 0);
okini3939 0:2e953bbaf3a5 45 _spi.frequency(1000000);
okini3939 0:2e953bbaf3a5 46
okini3939 0:2e953bbaf3a5 47 /* Cleanup registers */
okini3939 0:2e953bbaf3a5 48 // clr = SPSR;
okini3939 0:2e953bbaf3a5 49 // clr = SPDR;
okini3939 0:2e953bbaf3a5 50 }
okini3939 0:2e953bbaf3a5 51
okini3939 0:2e953bbaf3a5 52 /**
okini3939 0:2e953bbaf3a5 53 * Read status register
okini3939 0:2e953bbaf3a5 54 * @return The content of the status register
okini3939 0:2e953bbaf3a5 55 **/
okini3939 0:2e953bbaf3a5 56 uint8_t ATD45DB161D::ReadStatusRegister()
okini3939 0:2e953bbaf3a5 57 {
okini3939 0:2e953bbaf3a5 58 uint8_t status;
okini3939 0:2e953bbaf3a5 59
okini3939 0:2e953bbaf3a5 60 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 61 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 62
okini3939 0:2e953bbaf3a5 63 /* Send status read command */
okini3939 0:2e953bbaf3a5 64 spi_transfer(AT45DB161D_STATUS_REGISTER_READ);
okini3939 0:2e953bbaf3a5 65 /* Get result with a dummy write */
okini3939 0:2e953bbaf3a5 66 status = spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 67
okini3939 0:2e953bbaf3a5 68 return status;
okini3939 0:2e953bbaf3a5 69 }
okini3939 0:2e953bbaf3a5 70
okini3939 0:2e953bbaf3a5 71 /**
okini3939 0:2e953bbaf3a5 72 * Read Manufacturer and Device ID
okini3939 0:2e953bbaf3a5 73 * @note if id.extendedInfoLength is not equal to zero,
okini3939 0:2e953bbaf3a5 74 * successive calls to spi_transfer(0xff) will return
okini3939 0:2e953bbaf3a5 75 * the extended device information string bytes.
okini3939 0:2e953bbaf3a5 76 * @param id Pointer to the ID structure to initialize
okini3939 0:2e953bbaf3a5 77 **/
okini3939 0:2e953bbaf3a5 78 void ATD45DB161D::ReadManufacturerAndDeviceID(struct ATD45DB161D::ID *id)
okini3939 0:2e953bbaf3a5 79 {
okini3939 0:2e953bbaf3a5 80
okini3939 0:2e953bbaf3a5 81 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 82 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 83
okini3939 0:2e953bbaf3a5 84 /* Send status read command */
okini3939 0:2e953bbaf3a5 85 spi_transfer(AT45DB161D_READ_MANUFACTURER_AND_DEVICE_ID);
okini3939 0:2e953bbaf3a5 86
okini3939 0:2e953bbaf3a5 87 /* Manufacturer ID */
okini3939 0:2e953bbaf3a5 88 id->manufacturer = spi_transfer(0xff);
okini3939 0:2e953bbaf3a5 89 /* Device ID (part 1) */
okini3939 0:2e953bbaf3a5 90 id->device[0] = spi_transfer(0xff);
okini3939 0:2e953bbaf3a5 91 /* Device ID (part 2) */
okini3939 0:2e953bbaf3a5 92 id->device[1] = spi_transfer(0xff);
okini3939 0:2e953bbaf3a5 93 /* Extended Device Information String Length */
okini3939 0:2e953bbaf3a5 94 id->extendedInfoLength = spi_transfer(0xff);
okini3939 0:2e953bbaf3a5 95
okini3939 0:2e953bbaf3a5 96 }
okini3939 0:2e953bbaf3a5 97
okini3939 0:2e953bbaf3a5 98 /**
okini3939 0:2e953bbaf3a5 99 * Main Memory Page Read.
okini3939 0:2e953bbaf3a5 100 * A main memory page read allows the user to read data directly from
okini3939 0:2e953bbaf3a5 101 * any one of the 4096 pages in the main memory, bypassing both of the
okini3939 0:2e953bbaf3a5 102 * data buffers and leaving the contents of the buffers unchanged.
okini3939 0:2e953bbaf3a5 103 *
okini3939 0:2e953bbaf3a5 104 * @param page Page of the main memory to read
okini3939 0:2e953bbaf3a5 105 * @param offset Starting byte address within the page
okini3939 0:2e953bbaf3a5 106 **/
okini3939 0:2e953bbaf3a5 107 void ATD45DB161D::ReadMainMemoryPage(uint16_t page, uint16_t offset)
okini3939 0:2e953bbaf3a5 108 {
okini3939 0:2e953bbaf3a5 109 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 110 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 111
okini3939 0:2e953bbaf3a5 112 /* Send opcode */
okini3939 0:2e953bbaf3a5 113 spi_transfer(AT45DB161D_PAGE_READ);
okini3939 0:2e953bbaf3a5 114
okini3939 0:2e953bbaf3a5 115 /* Address (page | offset) */
okini3939 0:2e953bbaf3a5 116 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 117 spi_transfer((uint8_t)((page << 2) | (offset >> 8)));
okini3939 0:2e953bbaf3a5 118 spi_transfer((uint8_t)(offset & 0xff));
okini3939 0:2e953bbaf3a5 119
okini3939 0:2e953bbaf3a5 120 /* 4 "don't care" bytes */
okini3939 0:2e953bbaf3a5 121 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 122 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 123 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 124 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 125 }
okini3939 0:2e953bbaf3a5 126
okini3939 0:2e953bbaf3a5 127 /**
okini3939 0:2e953bbaf3a5 128 * Continuous Array Read.
okini3939 0:2e953bbaf3a5 129 * Sequentially read a continuous stream of data.
okini3939 0:2e953bbaf3a5 130 * @param page Page of the main memory where the sequential read will start
okini3939 0:2e953bbaf3a5 131 * @param offset Starting byte address within the page
okini3939 0:2e953bbaf3a5 132 * @param low If true the read operation will be performed in low speed mode (and in high speed mode if it's false).
okini3939 0:2e953bbaf3a5 133 * @note The legacy mode is not currently supported
okini3939 0:2e953bbaf3a5 134 **/
okini3939 0:2e953bbaf3a5 135 void ATD45DB161D::ContinuousArrayRead(uint16_t page, uint16_t offset, uint8_t low)
okini3939 0:2e953bbaf3a5 136 {
okini3939 0:2e953bbaf3a5 137 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 138 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 139
okini3939 0:2e953bbaf3a5 140 /* Send opcode */
okini3939 0:2e953bbaf3a5 141 spi_transfer( low ? AT45DB161D_CONTINUOUS_READ_LOW_FREQ :
okini3939 0:2e953bbaf3a5 142 AT45DB161D_CONTINUOUS_READ_HIGH_FREQ );
okini3939 0:2e953bbaf3a5 143
okini3939 0:2e953bbaf3a5 144 /* Address (page | offset) */
okini3939 0:2e953bbaf3a5 145 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 146 spi_transfer((uint8_t)((page << 2) | (offset >> 8)));
okini3939 0:2e953bbaf3a5 147 spi_transfer((uint8_t)(offset & 0xff));
okini3939 0:2e953bbaf3a5 148
okini3939 0:2e953bbaf3a5 149 if (!low) { spi_transfer(0x00); }
okini3939 0:2e953bbaf3a5 150 }
okini3939 0:2e953bbaf3a5 151
okini3939 0:2e953bbaf3a5 152
okini3939 0:2e953bbaf3a5 153 /**
okini3939 0:2e953bbaf3a5 154 * Read the content of one of the SRAM data buffers (in low or high speed mode).
okini3939 0:2e953bbaf3a5 155 * @param bufferNum Buffer to read (1 or 2)
okini3939 0:2e953bbaf3a5 156 * @param offset Starting byte within the buffer
okini3939 0:2e953bbaf3a5 157 * @param low If true the read operation will be performed in low speed mode (and in high speed mode if it's false).
okini3939 0:2e953bbaf3a5 158 **/
okini3939 0:2e953bbaf3a5 159 void ATD45DB161D::BufferRead(uint8_t bufferNum, uint16_t offset, uint8_t low)
okini3939 0:2e953bbaf3a5 160 {
okini3939 0:2e953bbaf3a5 161 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 162 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 163
okini3939 0:2e953bbaf3a5 164 /* Send opcode */
okini3939 0:2e953bbaf3a5 165 if(bufferNum == 1)
okini3939 0:2e953bbaf3a5 166 {
okini3939 0:2e953bbaf3a5 167 spi_transfer(low ? AT45DB161D_BUFFER_1_READ_LOW_FREQ :
okini3939 0:2e953bbaf3a5 168 AT45DB161D_BUFFER_1_READ);
okini3939 0:2e953bbaf3a5 169 }
okini3939 0:2e953bbaf3a5 170 else
okini3939 0:2e953bbaf3a5 171 {
okini3939 0:2e953bbaf3a5 172 spi_transfer(low ? AT45DB161D_BUFFER_2_READ_LOW_FREQ :
okini3939 0:2e953bbaf3a5 173 AT45DB161D_BUFFER_2_READ);
okini3939 0:2e953bbaf3a5 174
okini3939 0:2e953bbaf3a5 175 }
okini3939 0:2e953bbaf3a5 176
okini3939 0:2e953bbaf3a5 177 /* 14 "Don't care" bits */
okini3939 0:2e953bbaf3a5 178 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 179 /* Rest of the "don't care" bits + bits 8,9 of the offset */
okini3939 0:2e953bbaf3a5 180 spi_transfer((uint8_t)(offset >> 8));
okini3939 0:2e953bbaf3a5 181 /* bits 7-0 of the offset */
okini3939 0:2e953bbaf3a5 182 spi_transfer((uint8_t)(offset & 0xff));
okini3939 0:2e953bbaf3a5 183 }
okini3939 0:2e953bbaf3a5 184
okini3939 0:2e953bbaf3a5 185 /**
okini3939 0:2e953bbaf3a5 186 * Write data to one of the SRAM data buffers. Any further call to
okini3939 0:2e953bbaf3a5 187 * spi_tranfer will return bytes contained in the data buffer until
okini3939 0:2e953bbaf3a5 188 * a low-to-high transition is detected on the CS pin. If the end of
okini3939 0:2e953bbaf3a5 189 * the data buffer is reached, the device will wrap around back to the
okini3939 0:2e953bbaf3a5 190 * beginning of the buffer.
okini3939 0:2e953bbaf3a5 191 * @param bufferNum Buffer to read (1 or 2)
okini3939 0:2e953bbaf3a5 192 * @param offset Starting byte within the buffer
okini3939 0:2e953bbaf3a5 193 **/
okini3939 0:2e953bbaf3a5 194 void ATD45DB161D::BufferWrite(uint8_t bufferNum, uint16_t offset)
okini3939 0:2e953bbaf3a5 195 {
okini3939 0:2e953bbaf3a5 196 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 197 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 198
okini3939 0:2e953bbaf3a5 199 spi_transfer( (bufferNum == 1) ? AT45DB161D_BUFFER_1_WRITE :
okini3939 0:2e953bbaf3a5 200 AT45DB161D_BUFFER_2_WRITE);
okini3939 0:2e953bbaf3a5 201
okini3939 0:2e953bbaf3a5 202 /* 14 "Don't care" bits */
okini3939 0:2e953bbaf3a5 203 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 204 /* Rest of the "don't care" bits + bits 8,9 of the offset */
okini3939 0:2e953bbaf3a5 205 spi_transfer((uint8_t)(offset >> 8));
okini3939 0:2e953bbaf3a5 206 /* bits 7-0 of the offset */
okini3939 0:2e953bbaf3a5 207 spi_transfer((uint8_t)(offset & 0xff));
okini3939 0:2e953bbaf3a5 208 }
okini3939 0:2e953bbaf3a5 209
okini3939 0:2e953bbaf3a5 210 /**
okini3939 0:2e953bbaf3a5 211 * Transfer data from buffer 1 or 2 to main memory page.
okini3939 0:2e953bbaf3a5 212 * @param bufferNum Buffer to use (1 or 2)
okini3939 0:2e953bbaf3a5 213 * @param page Page where the content of the buffer will transfered
okini3939 0:2e953bbaf3a5 214 * @param erase If set the page will be first erased before the buffer transfer.
okini3939 0:2e953bbaf3a5 215 * @note If erase is equal to zero, the page must have been previously erased using one of the erase command (Page or Block Erase).
okini3939 0:2e953bbaf3a5 216 **/
okini3939 0:2e953bbaf3a5 217 void ATD45DB161D::BufferToPage(uint8_t bufferNum, uint16_t page, uint8_t erase)
okini3939 0:2e953bbaf3a5 218 {
okini3939 0:2e953bbaf3a5 219 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 220 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 221
okini3939 0:2e953bbaf3a5 222 /* Opcode */
okini3939 0:2e953bbaf3a5 223 if(erase)
okini3939 0:2e953bbaf3a5 224 {
okini3939 0:2e953bbaf3a5 225 spi_transfer( (bufferNum == 1) ? AT45DB161D_BUFFER_1_TO_PAGE_WITH_ERASE :
okini3939 0:2e953bbaf3a5 226 AT45DB161D_BUFFER_2_TO_PAGE_WITH_ERASE);
okini3939 0:2e953bbaf3a5 227 }
okini3939 0:2e953bbaf3a5 228 else
okini3939 0:2e953bbaf3a5 229 {
okini3939 0:2e953bbaf3a5 230 spi_transfer( (bufferNum == 1) ? AT45DB161D_BUFFER_1_TO_PAGE_WITHOUT_ERASE :
okini3939 0:2e953bbaf3a5 231 AT45DB161D_BUFFER_2_TO_PAGE_WITHOUT_ERASE);
okini3939 0:2e953bbaf3a5 232 }
okini3939 0:2e953bbaf3a5 233
okini3939 0:2e953bbaf3a5 234 /*
okini3939 0:2e953bbaf3a5 235 * 3 address bytes consist of :
okini3939 0:2e953bbaf3a5 236 * - 2 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 237 * - 12 page address bits (PA11 - PA0) that specify the page in
okini3939 0:2e953bbaf3a5 238 * the main memory to be written
okini3939 0:2e953bbaf3a5 239 * - 10 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 240 */
okini3939 0:2e953bbaf3a5 241 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 242 spi_transfer((uint8_t)(page << 2));
okini3939 0:2e953bbaf3a5 243 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 244
okini3939 0:2e953bbaf3a5 245 DF_CS_inactive; /* Start transfer */
okini3939 0:2e953bbaf3a5 246 DF_CS_active; /* If erase was set, the page will first be erased */
okini3939 0:2e953bbaf3a5 247
okini3939 0:2e953bbaf3a5 248 /* Wait for the end of the transfer */
okini3939 0:2e953bbaf3a5 249 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 250 {}
okini3939 0:2e953bbaf3a5 251 }
okini3939 0:2e953bbaf3a5 252
okini3939 0:2e953bbaf3a5 253 /**
okini3939 0:2e953bbaf3a5 254 * Transfer a page of data from main memory to buffer 1 or 2.
okini3939 0:2e953bbaf3a5 255 * @param page Main memory page to transfer
okini3939 0:2e953bbaf3a5 256 * @param buffer Buffer (1 or 2) where the data will be written
okini3939 0:2e953bbaf3a5 257 **/
okini3939 0:2e953bbaf3a5 258 void ATD45DB161D::PageToBuffer(uint16_t page, uint8_t bufferNum)
okini3939 0:2e953bbaf3a5 259 {
okini3939 0:2e953bbaf3a5 260 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 261 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 262
okini3939 0:2e953bbaf3a5 263 /* Send opcode */
okini3939 0:2e953bbaf3a5 264 spi_transfer((bufferNum == 1) ? AT45DB161D_TRANSFER_PAGE_TO_BUFFER_1 :
okini3939 0:2e953bbaf3a5 265 AT45DB161D_TRANSFER_PAGE_TO_BUFFER_2);
okini3939 0:2e953bbaf3a5 266
okini3939 0:2e953bbaf3a5 267 /*
okini3939 0:2e953bbaf3a5 268 * 3 address bytes consist of :
okini3939 0:2e953bbaf3a5 269 * - 2 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 270 * - 12 page address bits (PA11 - PA0) that specify the page in
okini3939 0:2e953bbaf3a5 271 * the main memory to be written
okini3939 0:2e953bbaf3a5 272 * - 10 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 273 */
okini3939 0:2e953bbaf3a5 274 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 275 spi_transfer((uint8_t)(page << 2));
okini3939 0:2e953bbaf3a5 276 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 277
okini3939 0:2e953bbaf3a5 278 DF_CS_inactive; /* Start page transfer */
okini3939 0:2e953bbaf3a5 279 DF_CS_active;
okini3939 0:2e953bbaf3a5 280
okini3939 0:2e953bbaf3a5 281 /* Wait for the end of the transfer */
okini3939 0:2e953bbaf3a5 282 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 283 {}
okini3939 0:2e953bbaf3a5 284 }
okini3939 0:2e953bbaf3a5 285
okini3939 0:2e953bbaf3a5 286 /**
okini3939 0:2e953bbaf3a5 287 * Erase a page in the main memory array.
okini3939 0:2e953bbaf3a5 288 * @param page Page to erase
okini3939 0:2e953bbaf3a5 289 **/
okini3939 0:2e953bbaf3a5 290 void ATD45DB161D::PageErase(uint16_t page)
okini3939 0:2e953bbaf3a5 291 {
okini3939 0:2e953bbaf3a5 292 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 293 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 294
okini3939 0:2e953bbaf3a5 295 /* Send opcode */
okini3939 0:2e953bbaf3a5 296 spi_transfer(AT45DB161D_PAGE_ERASE);
okini3939 0:2e953bbaf3a5 297
okini3939 0:2e953bbaf3a5 298 /*
okini3939 0:2e953bbaf3a5 299 * 3 address bytes consist of :
okini3939 0:2e953bbaf3a5 300 * - 2 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 301 * - 12 page address bits (PA11 - PA0) that specify the page in
okini3939 0:2e953bbaf3a5 302 * the main memory to be written
okini3939 0:2e953bbaf3a5 303 * - 10 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 304 */
okini3939 0:2e953bbaf3a5 305 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 306 spi_transfer((uint8_t)(page << 2));
okini3939 0:2e953bbaf3a5 307 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 308
okini3939 0:2e953bbaf3a5 309 DF_CS_inactive; /* Start block erase */
okini3939 0:2e953bbaf3a5 310 DF_CS_active;
okini3939 0:2e953bbaf3a5 311
okini3939 0:2e953bbaf3a5 312 /* Wait for the end of the block erase operation */
okini3939 0:2e953bbaf3a5 313 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 314 {}
okini3939 0:2e953bbaf3a5 315 }
okini3939 0:2e953bbaf3a5 316
okini3939 0:2e953bbaf3a5 317 /**
okini3939 0:2e953bbaf3a5 318 * Erase a block of eight pages at one time.
okini3939 0:2e953bbaf3a5 319 * @param block Index of the block to erase
okini3939 0:2e953bbaf3a5 320 **/
okini3939 0:2e953bbaf3a5 321 void ATD45DB161D::BlockErase(uint16_t block)
okini3939 0:2e953bbaf3a5 322 {
okini3939 0:2e953bbaf3a5 323 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 324 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 325
okini3939 0:2e953bbaf3a5 326 /* Send opcode */
okini3939 0:2e953bbaf3a5 327 spi_transfer(AT45DB161D_BLOCK_ERASE);
okini3939 0:2e953bbaf3a5 328
okini3939 0:2e953bbaf3a5 329 /*
okini3939 0:2e953bbaf3a5 330 * 3 address bytes consist of :
okini3939 0:2e953bbaf3a5 331 * - 2 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 332 * - 9 block address bits (PA11 - PA3)
okini3939 0:2e953bbaf3a5 333 * - 13 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 334 */
okini3939 0:2e953bbaf3a5 335 spi_transfer((uint8_t)(block >> 3));
okini3939 0:2e953bbaf3a5 336 spi_transfer((uint8_t)(block << 5));
okini3939 0:2e953bbaf3a5 337 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 338
okini3939 0:2e953bbaf3a5 339 DF_CS_inactive; /* Start block erase */
okini3939 0:2e953bbaf3a5 340 DF_CS_active;
okini3939 0:2e953bbaf3a5 341
okini3939 0:2e953bbaf3a5 342 /* Wait for the end of the block erase operation */
okini3939 0:2e953bbaf3a5 343 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 344 {}
okini3939 0:2e953bbaf3a5 345 }
okini3939 0:2e953bbaf3a5 346
okini3939 0:2e953bbaf3a5 347 /**
okini3939 0:2e953bbaf3a5 348 * Erase a sector in main memory. There are 16 sector on the
okini3939 0:2e953bbaf3a5 349 * at45db161d and only one can be erased at one time.
okini3939 0:2e953bbaf3a5 350 * @param sector Sector to erase (1-15)
okini3939 0:2e953bbaf3a5 351 **/
okini3939 0:2e953bbaf3a5 352 void ATD45DB161D::SectoreErase(uint8_t sector)
okini3939 0:2e953bbaf3a5 353 {
okini3939 0:2e953bbaf3a5 354 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 355 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 356
okini3939 0:2e953bbaf3a5 357 /* Send opcode */
okini3939 0:2e953bbaf3a5 358 spi_transfer(AT45DB161D_SECTOR_ERASE);
okini3939 0:2e953bbaf3a5 359
okini3939 0:2e953bbaf3a5 360 /*
okini3939 0:2e953bbaf3a5 361 * 3 address bytes consist of :
okini3939 0:2e953bbaf3a5 362 */
okini3939 0:2e953bbaf3a5 363 if((sector == 0x0a) || (sector == 0x0b))
okini3939 0:2e953bbaf3a5 364 {
okini3939 0:2e953bbaf3a5 365 /*
okini3939 0:2e953bbaf3a5 366 * - 11 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 367 * -
okini3939 0:2e953bbaf3a5 368 * - 12 don&#65533;ft care bits
okini3939 0:2e953bbaf3a5 369 */
okini3939 0:2e953bbaf3a5 370 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 371 spi_transfer(((sector & 0x01) << 4));
okini3939 0:2e953bbaf3a5 372 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 373 }
okini3939 0:2e953bbaf3a5 374 else
okini3939 0:2e953bbaf3a5 375 {
okini3939 0:2e953bbaf3a5 376 /*
okini3939 0:2e953bbaf3a5 377 * - 2 don't care bits
okini3939 0:2e953bbaf3a5 378 * - 4 sector number bits
okini3939 0:2e953bbaf3a5 379 * - 18 don't care bits
okini3939 0:2e953bbaf3a5 380 */
okini3939 0:2e953bbaf3a5 381 spi_transfer(sector << 1);
okini3939 0:2e953bbaf3a5 382 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 383 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 384 }
okini3939 0:2e953bbaf3a5 385
okini3939 0:2e953bbaf3a5 386 DF_CS_inactive; /* Start block erase */
okini3939 0:2e953bbaf3a5 387 DF_CS_active;
okini3939 0:2e953bbaf3a5 388
okini3939 0:2e953bbaf3a5 389 /* Wait for the end of the block erase operation */
okini3939 0:2e953bbaf3a5 390 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 391 {}
okini3939 0:2e953bbaf3a5 392 }
okini3939 0:2e953bbaf3a5 393
okini3939 0:2e953bbaf3a5 394 /**
okini3939 0:2e953bbaf3a5 395 * Erase the entire chip memory. Sectors proteced or locked down will
okini3939 0:2e953bbaf3a5 396 * not be erased.
okini3939 0:2e953bbaf3a5 397 **/
okini3939 0:2e953bbaf3a5 398 void ATD45DB161D::ChipErase()
okini3939 0:2e953bbaf3a5 399 {
okini3939 0:2e953bbaf3a5 400 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 401 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 402
okini3939 0:2e953bbaf3a5 403 /* Send chip erase sequence */
okini3939 0:2e953bbaf3a5 404 spi_transfer(AT45DB161D_CHIP_ERASE_0);
okini3939 0:2e953bbaf3a5 405 spi_transfer(AT45DB161D_CHIP_ERASE_1);
okini3939 0:2e953bbaf3a5 406 spi_transfer(AT45DB161D_CHIP_ERASE_2);
okini3939 0:2e953bbaf3a5 407 spi_transfer(AT45DB161D_CHIP_ERASE_3);
okini3939 0:2e953bbaf3a5 408
okini3939 0:2e953bbaf3a5 409 DF_CS_inactive; /* Start chip erase */
okini3939 0:2e953bbaf3a5 410 DF_CS_active;
okini3939 0:2e953bbaf3a5 411
okini3939 0:2e953bbaf3a5 412 /* Wait for the end of the chip erase operation */
okini3939 0:2e953bbaf3a5 413 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 414 {}
okini3939 0:2e953bbaf3a5 415 }
okini3939 0:2e953bbaf3a5 416
okini3939 0:2e953bbaf3a5 417 /**
okini3939 0:2e953bbaf3a5 418 * This a combination of Buffer Write and Buffer to Page with
okini3939 0:2e953bbaf3a5 419 * Built-in Erase.
okini3939 0:2e953bbaf3a5 420 * @note You must call EndAndWait in order to start transfering data from buffer to page
okini3939 0:2e953bbaf3a5 421 * @param page Page where the content of the buffer will transfered
okini3939 0:2e953bbaf3a5 422 * @param offset Starting byte address within the buffer
okini3939 0:2e953bbaf3a5 423 * @param bufferNum Buffer to use (1 or 2)
okini3939 0:2e953bbaf3a5 424 * @warning UNTESTED
okini3939 0:2e953bbaf3a5 425 **/
okini3939 0:2e953bbaf3a5 426 void ATD45DB161D::BeginPageWriteThroughBuffer(uint16_t page, uint16_t offset, uint8_t bufferNum)
okini3939 0:2e953bbaf3a5 427 {
okini3939 0:2e953bbaf3a5 428 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 429 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 430
okini3939 0:2e953bbaf3a5 431 /* Send opcode */
okini3939 0:2e953bbaf3a5 432 spi_transfer((bufferNum == 1) ? AT45DB161D_PAGE_THROUGH_BUFFER_1 :
okini3939 0:2e953bbaf3a5 433 AT45DB161D_PAGE_THROUGH_BUFFER_2);
okini3939 0:2e953bbaf3a5 434
okini3939 0:2e953bbaf3a5 435 /* Address */
okini3939 0:2e953bbaf3a5 436 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 437 spi_transfer((uint8_t)((page << 2) | (offset >> 8)));
okini3939 0:2e953bbaf3a5 438 spi_transfer((uint8_t)offset);
okini3939 0:2e953bbaf3a5 439 }
okini3939 0:2e953bbaf3a5 440
okini3939 0:2e953bbaf3a5 441 /**
okini3939 0:2e953bbaf3a5 442 * Perform a low-to-high transition on the CS pin and then poll
okini3939 0:2e953bbaf3a5 443 * the status register to check if the dataflash is busy.
okini3939 0:2e953bbaf3a5 444 **/
okini3939 0:2e953bbaf3a5 445 void ATD45DB161D::EndAndWait()
okini3939 0:2e953bbaf3a5 446 {
okini3939 0:2e953bbaf3a5 447 DF_CS_inactive; /* End current operation */
okini3939 0:2e953bbaf3a5 448 DF_CS_active; /* Some internal operation may occur
okini3939 0:2e953bbaf3a5 449 * (buffer to page transfer, page erase, etc... ) */
okini3939 0:2e953bbaf3a5 450
okini3939 0:2e953bbaf3a5 451 /* Wait for the chip to be ready */
okini3939 0:2e953bbaf3a5 452 while(!(ReadStatusRegister() & READY_BUSY))
okini3939 0:2e953bbaf3a5 453 {}
okini3939 0:2e953bbaf3a5 454
okini3939 0:2e953bbaf3a5 455 DF_CS_inactive; /* Release SPI Bus */
okini3939 0:2e953bbaf3a5 456 }
okini3939 0:2e953bbaf3a5 457
okini3939 0:2e953bbaf3a5 458 /**
okini3939 0:2e953bbaf3a5 459 * Compare a page of data in main memory to the data in buffer 1 or 2.
okini3939 0:2e953bbaf3a5 460 * @param page Page to test
okini3939 0:2e953bbaf3a5 461 * @param bufferNum Buffer number
okini3939 0:2e953bbaf3a5 462 * @return
okini3939 0:2e953bbaf3a5 463 * - 1 if the page and the buffer contains the same data
okini3939 0:2e953bbaf3a5 464 * - 0 else
okini3939 0:2e953bbaf3a5 465 * @warning UNTESTED
okini3939 0:2e953bbaf3a5 466 **/
okini3939 0:2e953bbaf3a5 467 int8_t ATD45DB161D::ComparePageToBuffer(uint16_t page, uint8_t bufferNum)
okini3939 0:2e953bbaf3a5 468 {
okini3939 0:2e953bbaf3a5 469 uint8_t status;
okini3939 0:2e953bbaf3a5 470
okini3939 0:2e953bbaf3a5 471 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 472 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 473
okini3939 0:2e953bbaf3a5 474 /* Send opcode */
okini3939 0:2e953bbaf3a5 475 spi_transfer((bufferNum == 1) ? AT45DB161D_COMPARE_PAGE_TO_BUFFER_1 :
okini3939 0:2e953bbaf3a5 476 AT45DB161D_COMPARE_PAGE_TO_BUFFER_2);
okini3939 0:2e953bbaf3a5 477
okini3939 0:2e953bbaf3a5 478 /* Page address */
okini3939 0:2e953bbaf3a5 479 spi_transfer((uint8_t)(page >> 6));
okini3939 0:2e953bbaf3a5 480 spi_transfer((uint8_t)(page << 2));
okini3939 0:2e953bbaf3a5 481 spi_transfer(0x00);
okini3939 0:2e953bbaf3a5 482
okini3939 0:2e953bbaf3a5 483 DF_CS_inactive; /* Start comparaison */
okini3939 0:2e953bbaf3a5 484 DF_CS_active;
okini3939 0:2e953bbaf3a5 485
okini3939 0:2e953bbaf3a5 486 /* Wait for the end of the comparaison and get the result */
okini3939 0:2e953bbaf3a5 487 while(!((status = ReadStatusRegister()) & READY_BUSY))
okini3939 0:2e953bbaf3a5 488 {}
okini3939 0:2e953bbaf3a5 489
okini3939 0:2e953bbaf3a5 490 // return ((status & COMPARE) == COMPARE);
okini3939 0:2e953bbaf3a5 491 return ((status & COMPARE) ? 0 : 1);
okini3939 0:2e953bbaf3a5 492 }
okini3939 0:2e953bbaf3a5 493
okini3939 0:2e953bbaf3a5 494 /**
okini3939 0:2e953bbaf3a5 495 * Put the device into the lowest power consumption mode.
okini3939 0:2e953bbaf3a5 496 * Once the device has entered the Deep Power-down mode, all
okini3939 0:2e953bbaf3a5 497 * instructions are ignored except the Resume from Deep
okini3939 0:2e953bbaf3a5 498 * Power-down command.
okini3939 0:2e953bbaf3a5 499 * @warning UNTESTED
okini3939 0:2e953bbaf3a5 500 **/
okini3939 0:2e953bbaf3a5 501 void ATD45DB161D::DeepPowerDown()
okini3939 0:2e953bbaf3a5 502 {
okini3939 0:2e953bbaf3a5 503 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 504 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 505
okini3939 0:2e953bbaf3a5 506 /* Send opcode */
okini3939 0:2e953bbaf3a5 507 spi_transfer(AT45DB161D_DEEP_POWER_DOWN);
okini3939 0:2e953bbaf3a5 508
okini3939 0:2e953bbaf3a5 509 /* Enter Deep Power-Down mode */
okini3939 0:2e953bbaf3a5 510 DF_CS_inactive;
okini3939 0:2e953bbaf3a5 511
okini3939 0:2e953bbaf3a5 512 /* Safety delay */
okini3939 0:2e953bbaf3a5 513 // delay(100);
okini3939 0:2e953bbaf3a5 514 wait_ms(100);
okini3939 0:2e953bbaf3a5 515 }
okini3939 0:2e953bbaf3a5 516
okini3939 0:2e953bbaf3a5 517 /**
okini3939 0:2e953bbaf3a5 518 * Takes the device out of Deep Power-down mode.
okini3939 0:2e953bbaf3a5 519 **/
okini3939 0:2e953bbaf3a5 520 void ATD45DB161D::ResumeFromDeepPowerDown()
okini3939 0:2e953bbaf3a5 521 {
okini3939 0:2e953bbaf3a5 522 DF_CS_inactive; /* Make sure to toggle CS signal in order */
okini3939 0:2e953bbaf3a5 523 DF_CS_active; /* to reset Dataflash command decoder */
okini3939 0:2e953bbaf3a5 524
okini3939 0:2e953bbaf3a5 525 /* Send opcode */
okini3939 0:2e953bbaf3a5 526 spi_transfer(AT45DB161D_RESUME_FROM_DEEP_POWER_DOWN);
okini3939 0:2e953bbaf3a5 527
okini3939 0:2e953bbaf3a5 528 /* Resume device */
okini3939 0:2e953bbaf3a5 529 DF_CS_inactive;
okini3939 0:2e953bbaf3a5 530
okini3939 0:2e953bbaf3a5 531 /* The CS pin must stay high during t_RDPD microseconds before the device
okini3939 0:2e953bbaf3a5 532 * can receive any commands.
okini3939 0:2e953bbaf3a5 533 * On the at45db161D t_RDPD = 35 microseconds. But we will wait 100
okini3939 0:2e953bbaf3a5 534 * (just to be sure). */
okini3939 0:2e953bbaf3a5 535 // delay(100);
okini3939 0:2e953bbaf3a5 536 wait_ms(100);
okini3939 0:2e953bbaf3a5 537 }
okini3939 0:2e953bbaf3a5 538
okini3939 0:2e953bbaf3a5 539 /** **/