fork from va009039/USBLocalFileSystem

Dependencies:   USBDevice

Dependents:   11u35_usbLocalFilesystem

Fork of USBLocalFileSystem by Norimasa Okamoto

Committer:
va009039
Date:
Tue May 06 15:42:30 2014 +0900
Branch:
branch
Revision:
2:97c314eae8b8
Parent:
0:39eb4d5b97df
Child:
11:c396747794c6
add USB MSD block operation.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 0:39eb4d5b97df 1 /* mbed Microcontroller Library
va009039 0:39eb4d5b97df 2 * Copyright (c) 2006-2012 ARM Limited
va009039 0:39eb4d5b97df 3 *
va009039 0:39eb4d5b97df 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
va009039 0:39eb4d5b97df 5 * of this software and associated documentation files (the "Software"), to deal
va009039 0:39eb4d5b97df 6 * in the Software without restriction, including without limitation the rights
va009039 0:39eb4d5b97df 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
va009039 0:39eb4d5b97df 8 * copies of the Software, and to permit persons to whom the Software is
va009039 0:39eb4d5b97df 9 * furnished to do so, subject to the following conditions:
va009039 0:39eb4d5b97df 10 *
va009039 0:39eb4d5b97df 11 * The above copyright notice and this permission notice shall be included in
va009039 0:39eb4d5b97df 12 * all copies or substantial portions of the Software.
va009039 0:39eb4d5b97df 13 *
va009039 0:39eb4d5b97df 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
va009039 0:39eb4d5b97df 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
va009039 0:39eb4d5b97df 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
va009039 0:39eb4d5b97df 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
va009039 0:39eb4d5b97df 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
va009039 0:39eb4d5b97df 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
va009039 0:39eb4d5b97df 20 * SOFTWARE.
va009039 0:39eb4d5b97df 21 */
va009039 0:39eb4d5b97df 22 /* Introduction
va009039 0:39eb4d5b97df 23 * ------------
va009039 0:39eb4d5b97df 24 * SD and MMC cards support a number of interfaces, but common to them all
va009039 0:39eb4d5b97df 25 * is one based on SPI. This is the one I'm implmenting because it means
va009039 0:39eb4d5b97df 26 * it is much more portable even though not so performant, and we already
va009039 0:39eb4d5b97df 27 * have the mbed SPI Interface!
va009039 0:39eb4d5b97df 28 *
va009039 0:39eb4d5b97df 29 * The main reference I'm using is Chapter 7, "SPI Mode" of:
va009039 0:39eb4d5b97df 30 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
va009039 0:39eb4d5b97df 31 *
va009039 0:39eb4d5b97df 32 * SPI Startup
va009039 0:39eb4d5b97df 33 * -----------
va009039 0:39eb4d5b97df 34 * The SD card powers up in SD mode. The SPI interface mode is selected by
va009039 0:39eb4d5b97df 35 * asserting CS low and sending the reset command (CMD0). The card will
va009039 0:39eb4d5b97df 36 * respond with a (R1) response.
va009039 0:39eb4d5b97df 37 *
va009039 0:39eb4d5b97df 38 * CMD8 is optionally sent to determine the voltage range supported, and
va009039 0:39eb4d5b97df 39 * indirectly determine whether it is a version 1.x SD/non-SD card or
va009039 0:39eb4d5b97df 40 * version 2.x. I'll just ignore this for now.
va009039 0:39eb4d5b97df 41 *
va009039 0:39eb4d5b97df 42 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
va009039 0:39eb4d5b97df 43 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
va009039 0:39eb4d5b97df 44 *
va009039 0:39eb4d5b97df 45 * You should also indicate whether the host supports High Capicity cards,
va009039 0:39eb4d5b97df 46 * and check whether the card is high capacity - i'll also ignore this
va009039 0:39eb4d5b97df 47 *
va009039 0:39eb4d5b97df 48 * SPI Protocol
va009039 0:39eb4d5b97df 49 * ------------
va009039 0:39eb4d5b97df 50 * The SD SPI protocol is based on transactions made up of 8-bit words, with
va009039 0:39eb4d5b97df 51 * the host starting every bus transaction by asserting the CS signal low. The
va009039 0:39eb4d5b97df 52 * card always responds to commands, data blocks and errors.
va009039 0:39eb4d5b97df 53 *
va009039 0:39eb4d5b97df 54 * The protocol supports a CRC, but by default it is off (except for the
va009039 0:39eb4d5b97df 55 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
va009039 0:39eb4d5b97df 56 * I'll leave the CRC off I think!
va009039 0:39eb4d5b97df 57 *
va009039 0:39eb4d5b97df 58 * Standard capacity cards have variable data block sizes, whereas High
va009039 0:39eb4d5b97df 59 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
va009039 0:39eb4d5b97df 60 * just always use the Standard Capacity cards with a block size of 512 bytes.
va009039 0:39eb4d5b97df 61 * This is set with CMD16.
va009039 0:39eb4d5b97df 62 *
va009039 0:39eb4d5b97df 63 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
va009039 0:39eb4d5b97df 64 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
va009039 0:39eb4d5b97df 65 * the card gets a read command, it responds with a response token, and then
va009039 0:39eb4d5b97df 66 * a data token or an error.
va009039 0:39eb4d5b97df 67 *
va009039 0:39eb4d5b97df 68 * SPI Command Format
va009039 0:39eb4d5b97df 69 * ------------------
va009039 0:39eb4d5b97df 70 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
va009039 0:39eb4d5b97df 71 *
va009039 0:39eb4d5b97df 72 * +---------------+------------+------------+-----------+----------+--------------+
va009039 0:39eb4d5b97df 73 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
va009039 0:39eb4d5b97df 74 * +---------------+------------+------------+-----------+----------+--------------+
va009039 0:39eb4d5b97df 75 *
va009039 0:39eb4d5b97df 76 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
va009039 0:39eb4d5b97df 77 *
va009039 0:39eb4d5b97df 78 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
va009039 0:39eb4d5b97df 79 *
va009039 0:39eb4d5b97df 80 * SPI Response Format
va009039 0:39eb4d5b97df 81 * -------------------
va009039 0:39eb4d5b97df 82 * The main response format (R1) is a status byte (normally zero). Key flags:
va009039 0:39eb4d5b97df 83 * idle - 1 if the card is in an idle state/initialising
va009039 0:39eb4d5b97df 84 * cmd - 1 if an illegal command code was detected
va009039 0:39eb4d5b97df 85 *
va009039 0:39eb4d5b97df 86 * +-------------------------------------------------+
va009039 0:39eb4d5b97df 87 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
va009039 0:39eb4d5b97df 88 * +-------------------------------------------------+
va009039 0:39eb4d5b97df 89 *
va009039 0:39eb4d5b97df 90 * R1b is the same, except it is followed by a busy signal (zeros) until
va009039 0:39eb4d5b97df 91 * the first non-zero byte when it is ready again.
va009039 0:39eb4d5b97df 92 *
va009039 0:39eb4d5b97df 93 * Data Response Token
va009039 0:39eb4d5b97df 94 * -------------------
va009039 0:39eb4d5b97df 95 * Every data block written to the card is acknowledged by a byte
va009039 0:39eb4d5b97df 96 * response token
va009039 0:39eb4d5b97df 97 *
va009039 0:39eb4d5b97df 98 * +----------------------+
va009039 0:39eb4d5b97df 99 * | xxx | 0 | status | 1 |
va009039 0:39eb4d5b97df 100 * +----------------------+
va009039 0:39eb4d5b97df 101 * 010 - OK!
va009039 0:39eb4d5b97df 102 * 101 - CRC Error
va009039 0:39eb4d5b97df 103 * 110 - Write Error
va009039 0:39eb4d5b97df 104 *
va009039 0:39eb4d5b97df 105 * Single Block Read and Write
va009039 0:39eb4d5b97df 106 * ---------------------------
va009039 0:39eb4d5b97df 107 *
va009039 0:39eb4d5b97df 108 * Block transfers have a byte header, followed by the data, followed
va009039 0:39eb4d5b97df 109 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
va009039 0:39eb4d5b97df 110 *
va009039 0:39eb4d5b97df 111 * +------+---------+---------+- - - -+---------+-----------+----------+
va009039 0:39eb4d5b97df 112 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
va009039 0:39eb4d5b97df 113 * +------+---------+---------+- - - -+---------+-----------+----------+
va009039 0:39eb4d5b97df 114 */
va009039 0:39eb4d5b97df 115
va009039 0:39eb4d5b97df 116 #include "SDStorage.h"
va009039 0:39eb4d5b97df 117 #include "mbed_debug.h"
va009039 0:39eb4d5b97df 118
va009039 0:39eb4d5b97df 119 #if 0 //#if (DEBUG2 > 3)
va009039 0:39eb4d5b97df 120 #define SD_DBG2(...) do{fprintf(stderr,"[%s@%d] ",__PRETTY_FUNCTION__,__LINE__);fprintf(stderr,__VA_ARGS__);fprintf(stderr,"\r\n");} while(0);
va009039 0:39eb4d5b97df 121 #else
va009039 0:39eb4d5b97df 122 #define SD_DBG2(...) while(0)
va009039 0:39eb4d5b97df 123 #endif
va009039 0:39eb4d5b97df 124
va009039 0:39eb4d5b97df 125 #define SD_COMMAND_TIMEOUT 5000
va009039 0:39eb4d5b97df 126
va009039 0:39eb4d5b97df 127 #define SD_DBG 1
va009039 0:39eb4d5b97df 128
va009039 0:39eb4d5b97df 129 SDStorage::SDStorage(PinName mosi, PinName miso, PinName sclk, PinName cs) :
va009039 0:39eb4d5b97df 130 _spi(mosi, miso, sclk), _cs(cs) {
va009039 0:39eb4d5b97df 131 _cs = 1;
va009039 0:39eb4d5b97df 132
va009039 0:39eb4d5b97df 133 //storage_initialize();
va009039 0:39eb4d5b97df 134 }
va009039 0:39eb4d5b97df 135
va009039 0:39eb4d5b97df 136 #define R1_IDLE_STATE (1 << 0)
va009039 0:39eb4d5b97df 137 #define R1_ERASE_RESET (1 << 1)
va009039 0:39eb4d5b97df 138 #define R1_ILLEGAL_COMMAND (1 << 2)
va009039 0:39eb4d5b97df 139 #define R1_COM_CRC_ERROR (1 << 3)
va009039 0:39eb4d5b97df 140 #define R1_ERASE_SEQUENCE_ERROR (1 << 4)
va009039 0:39eb4d5b97df 141 #define R1_ADDRESS_ERROR (1 << 5)
va009039 0:39eb4d5b97df 142 #define R1_PARAMETER_ERROR (1 << 6)
va009039 0:39eb4d5b97df 143
va009039 0:39eb4d5b97df 144 // Types
va009039 0:39eb4d5b97df 145 // - v1.x Standard Capacity
va009039 0:39eb4d5b97df 146 // - v2.x Standard Capacity
va009039 0:39eb4d5b97df 147 // - v2.x High Capacity
va009039 0:39eb4d5b97df 148 // - Not recognised as an SD Card
va009039 0:39eb4d5b97df 149 #define SDCARD_FAIL 0
va009039 0:39eb4d5b97df 150 #define SDCARD_V1 1
va009039 0:39eb4d5b97df 151 #define SDCARD_V2 2
va009039 0:39eb4d5b97df 152 #define SDCARD_V2HC 3
va009039 0:39eb4d5b97df 153
va009039 0:39eb4d5b97df 154 int SDStorage::initialise_card() {
va009039 0:39eb4d5b97df 155 // Set to 100kHz for initialisation, and clock card with cs = 1
va009039 0:39eb4d5b97df 156 _spi.frequency(100000);
va009039 0:39eb4d5b97df 157 _cs = 1;
va009039 0:39eb4d5b97df 158 for (int i = 0; i < 16; i++) {
va009039 0:39eb4d5b97df 159 _spi.write(0xFF);
va009039 0:39eb4d5b97df 160 }
va009039 0:39eb4d5b97df 161
va009039 0:39eb4d5b97df 162 // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
va009039 0:39eb4d5b97df 163 if (_cmd(0, 0) != R1_IDLE_STATE) {
va009039 0:39eb4d5b97df 164 debug("No disk, or could not put SD card in to SPI idle state\n");
va009039 0:39eb4d5b97df 165 return SDCARD_FAIL;
va009039 0:39eb4d5b97df 166 }
va009039 0:39eb4d5b97df 167
va009039 0:39eb4d5b97df 168 // send CMD8 to determine whther it is ver 2.x
va009039 0:39eb4d5b97df 169 int r = _cmd8();
va009039 0:39eb4d5b97df 170 if (r == R1_IDLE_STATE) {
va009039 0:39eb4d5b97df 171 return initialise_card_v2();
va009039 0:39eb4d5b97df 172 } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
va009039 0:39eb4d5b97df 173 return initialise_card_v1();
va009039 0:39eb4d5b97df 174 } else {
va009039 0:39eb4d5b97df 175 debug("Not in idle state after sending CMD8 (not an SD card?)\n");
va009039 0:39eb4d5b97df 176 return SDCARD_FAIL;
va009039 0:39eb4d5b97df 177 }
va009039 0:39eb4d5b97df 178 }
va009039 0:39eb4d5b97df 179
va009039 0:39eb4d5b97df 180 int SDStorage::initialise_card_v1() {
va009039 0:39eb4d5b97df 181 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
va009039 0:39eb4d5b97df 182 _cmd(55, 0);
va009039 0:39eb4d5b97df 183 if (_cmd(41, 0) == 0) {
va009039 0:39eb4d5b97df 184 cdv = 512;
va009039 0:39eb4d5b97df 185 debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
va009039 0:39eb4d5b97df 186 return SDCARD_V1;
va009039 0:39eb4d5b97df 187 }
va009039 0:39eb4d5b97df 188 }
va009039 0:39eb4d5b97df 189
va009039 0:39eb4d5b97df 190 debug("Timeout waiting for v1.x card\n");
va009039 0:39eb4d5b97df 191 return SDCARD_FAIL;
va009039 0:39eb4d5b97df 192 }
va009039 0:39eb4d5b97df 193
va009039 0:39eb4d5b97df 194 int SDStorage::initialise_card_v2() {
va009039 0:39eb4d5b97df 195 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
va009039 0:39eb4d5b97df 196 wait_ms(50);
va009039 0:39eb4d5b97df 197 _cmd58();
va009039 0:39eb4d5b97df 198 _cmd(55, 0);
va009039 0:39eb4d5b97df 199 if (_cmd(41, 0x40000000) == 0) {
va009039 0:39eb4d5b97df 200 _cmd58();
va009039 0:39eb4d5b97df 201 debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
va009039 0:39eb4d5b97df 202 cdv = 1;
va009039 0:39eb4d5b97df 203 return SDCARD_V2;
va009039 0:39eb4d5b97df 204 }
va009039 0:39eb4d5b97df 205 }
va009039 0:39eb4d5b97df 206
va009039 0:39eb4d5b97df 207 debug("Timeout waiting for v2.x card\n");
va009039 0:39eb4d5b97df 208 return SDCARD_FAIL;
va009039 0:39eb4d5b97df 209 }
va009039 0:39eb4d5b97df 210
va009039 0:39eb4d5b97df 211 int SDStorage::storage_initialize() {
va009039 0:39eb4d5b97df 212 int i = initialise_card();
va009039 0:39eb4d5b97df 213 debug_if(SD_DBG, "init card = %d\n", i);
va009039 0:39eb4d5b97df 214 _sectors = _sd_sectors();
va009039 0:39eb4d5b97df 215
va009039 0:39eb4d5b97df 216 // Set block length to 512 (CMD16)
va009039 0:39eb4d5b97df 217 if (_cmd(16, 512) != 0) {
va009039 0:39eb4d5b97df 218 debug("Set 512-byte block timed out\n");
va009039 0:39eb4d5b97df 219 return 1;
va009039 0:39eb4d5b97df 220 }
va009039 0:39eb4d5b97df 221
va009039 0:39eb4d5b97df 222 _spi.frequency(1000000); // Set to 1MHz for data transfer
va009039 0:39eb4d5b97df 223 return 0;
va009039 0:39eb4d5b97df 224 }
va009039 0:39eb4d5b97df 225
va009039 0:39eb4d5b97df 226 /* virtual */ int SDStorage::storage_write(const uint8_t *buffer, uint32_t block_number) {
va009039 0:39eb4d5b97df 227 SD_DBG2("W %d", block_number);
va009039 2:97c314eae8b8 228 report_write_count++;
va009039 0:39eb4d5b97df 229 // set write address for single block (CMD24)
va009039 0:39eb4d5b97df 230 if (_cmd(24, block_number * cdv) != 0) {
va009039 0:39eb4d5b97df 231 return 1;
va009039 0:39eb4d5b97df 232 }
va009039 0:39eb4d5b97df 233
va009039 0:39eb4d5b97df 234 // send the data block
va009039 0:39eb4d5b97df 235 _write(buffer, 512);
va009039 0:39eb4d5b97df 236 return 0;
va009039 0:39eb4d5b97df 237 }
va009039 0:39eb4d5b97df 238
va009039 0:39eb4d5b97df 239 /* virtual */ int SDStorage::storage_read(uint8_t *buffer, uint32_t block_number) {
va009039 0:39eb4d5b97df 240 SD_DBG2("R %d", block_number);
va009039 2:97c314eae8b8 241 report_read_count++;
va009039 0:39eb4d5b97df 242 // set read address for single block (CMD17)
va009039 0:39eb4d5b97df 243 if (_cmd(17, block_number * cdv) != 0) {
va009039 0:39eb4d5b97df 244 return 1;
va009039 0:39eb4d5b97df 245 }
va009039 0:39eb4d5b97df 246
va009039 0:39eb4d5b97df 247 // receive the data
va009039 0:39eb4d5b97df 248 _read(buffer, 512);
va009039 0:39eb4d5b97df 249 return 0;
va009039 0:39eb4d5b97df 250 }
va009039 0:39eb4d5b97df 251
va009039 0:39eb4d5b97df 252 //int SDStorage::disk_status() { return 0; }
va009039 0:39eb4d5b97df 253 //int SDStorage::disk_sync() { return 0; }
va009039 2:97c314eae8b8 254 /* virtual */ uint32_t SDStorage::storage_sectors() {
va009039 2:97c314eae8b8 255 report_sectors_count++;
va009039 2:97c314eae8b8 256 return _sectors;
va009039 2:97c314eae8b8 257 }
va009039 0:39eb4d5b97df 258
va009039 0:39eb4d5b97df 259
va009039 0:39eb4d5b97df 260 // PRIVATE FUNCTIONS
va009039 0:39eb4d5b97df 261 int SDStorage::_cmd(int cmd, int arg) {
va009039 0:39eb4d5b97df 262 _cs = 0;
va009039 0:39eb4d5b97df 263
va009039 0:39eb4d5b97df 264 // send a command
va009039 0:39eb4d5b97df 265 _spi.write(0x40 | cmd);
va009039 0:39eb4d5b97df 266 _spi.write(arg >> 24);
va009039 0:39eb4d5b97df 267 _spi.write(arg >> 16);
va009039 0:39eb4d5b97df 268 _spi.write(arg >> 8);
va009039 0:39eb4d5b97df 269 _spi.write(arg >> 0);
va009039 0:39eb4d5b97df 270 _spi.write(0x95);
va009039 0:39eb4d5b97df 271
va009039 0:39eb4d5b97df 272 // wait for the repsonse (response[7] == 0)
va009039 0:39eb4d5b97df 273 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
va009039 0:39eb4d5b97df 274 int response = _spi.write(0xFF);
va009039 0:39eb4d5b97df 275 if (!(response & 0x80)) {
va009039 0:39eb4d5b97df 276 _cs = 1;
va009039 0:39eb4d5b97df 277 _spi.write(0xFF);
va009039 0:39eb4d5b97df 278 return response;
va009039 0:39eb4d5b97df 279 }
va009039 0:39eb4d5b97df 280 }
va009039 0:39eb4d5b97df 281 _cs = 1;
va009039 0:39eb4d5b97df 282 _spi.write(0xFF);
va009039 0:39eb4d5b97df 283 return -1; // timeout
va009039 0:39eb4d5b97df 284 }
va009039 0:39eb4d5b97df 285 int SDStorage::_cmdx(int cmd, int arg) {
va009039 0:39eb4d5b97df 286 _cs = 0;
va009039 0:39eb4d5b97df 287
va009039 0:39eb4d5b97df 288 // send a command
va009039 0:39eb4d5b97df 289 _spi.write(0x40 | cmd);
va009039 0:39eb4d5b97df 290 _spi.write(arg >> 24);
va009039 0:39eb4d5b97df 291 _spi.write(arg >> 16);
va009039 0:39eb4d5b97df 292 _spi.write(arg >> 8);
va009039 0:39eb4d5b97df 293 _spi.write(arg >> 0);
va009039 0:39eb4d5b97df 294 _spi.write(0x95);
va009039 0:39eb4d5b97df 295
va009039 0:39eb4d5b97df 296 // wait for the repsonse (response[7] == 0)
va009039 0:39eb4d5b97df 297 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
va009039 0:39eb4d5b97df 298 int response = _spi.write(0xFF);
va009039 0:39eb4d5b97df 299 if (!(response & 0x80)) {
va009039 0:39eb4d5b97df 300 return response;
va009039 0:39eb4d5b97df 301 }
va009039 0:39eb4d5b97df 302 }
va009039 0:39eb4d5b97df 303 _cs = 1;
va009039 0:39eb4d5b97df 304 _spi.write(0xFF);
va009039 0:39eb4d5b97df 305 return -1; // timeout
va009039 0:39eb4d5b97df 306 }
va009039 0:39eb4d5b97df 307
va009039 0:39eb4d5b97df 308
va009039 0:39eb4d5b97df 309 int SDStorage::_cmd58() {
va009039 0:39eb4d5b97df 310 _cs = 0;
va009039 0:39eb4d5b97df 311 int arg = 0;
va009039 0:39eb4d5b97df 312
va009039 0:39eb4d5b97df 313 // send a command
va009039 0:39eb4d5b97df 314 _spi.write(0x40 | 58);
va009039 0:39eb4d5b97df 315 _spi.write(arg >> 24);
va009039 0:39eb4d5b97df 316 _spi.write(arg >> 16);
va009039 0:39eb4d5b97df 317 _spi.write(arg >> 8);
va009039 0:39eb4d5b97df 318 _spi.write(arg >> 0);
va009039 0:39eb4d5b97df 319 _spi.write(0x95);
va009039 0:39eb4d5b97df 320
va009039 0:39eb4d5b97df 321 // wait for the repsonse (response[7] == 0)
va009039 0:39eb4d5b97df 322 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
va009039 0:39eb4d5b97df 323 int response = _spi.write(0xFF);
va009039 0:39eb4d5b97df 324 if (!(response & 0x80)) {
va009039 0:39eb4d5b97df 325 int ocr = _spi.write(0xFF) << 24;
va009039 0:39eb4d5b97df 326 ocr |= _spi.write(0xFF) << 16;
va009039 0:39eb4d5b97df 327 ocr |= _spi.write(0xFF) << 8;
va009039 0:39eb4d5b97df 328 ocr |= _spi.write(0xFF) << 0;
va009039 0:39eb4d5b97df 329 _cs = 1;
va009039 0:39eb4d5b97df 330 _spi.write(0xFF);
va009039 0:39eb4d5b97df 331 return response;
va009039 0:39eb4d5b97df 332 }
va009039 0:39eb4d5b97df 333 }
va009039 0:39eb4d5b97df 334 _cs = 1;
va009039 0:39eb4d5b97df 335 _spi.write(0xFF);
va009039 0:39eb4d5b97df 336 return -1; // timeout
va009039 0:39eb4d5b97df 337 }
va009039 0:39eb4d5b97df 338
va009039 0:39eb4d5b97df 339 int SDStorage::_cmd8() {
va009039 0:39eb4d5b97df 340 _cs = 0;
va009039 0:39eb4d5b97df 341
va009039 0:39eb4d5b97df 342 // send a command
va009039 0:39eb4d5b97df 343 _spi.write(0x40 | 8); // CMD8
va009039 0:39eb4d5b97df 344 _spi.write(0x00); // reserved
va009039 0:39eb4d5b97df 345 _spi.write(0x00); // reserved
va009039 0:39eb4d5b97df 346 _spi.write(0x01); // 3.3v
va009039 0:39eb4d5b97df 347 _spi.write(0xAA); // check pattern
va009039 0:39eb4d5b97df 348 _spi.write(0x87); // crc
va009039 0:39eb4d5b97df 349
va009039 0:39eb4d5b97df 350 // wait for the repsonse (response[7] == 0)
va009039 0:39eb4d5b97df 351 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
va009039 0:39eb4d5b97df 352 char response[5];
va009039 0:39eb4d5b97df 353 response[0] = _spi.write(0xFF);
va009039 0:39eb4d5b97df 354 if (!(response[0] & 0x80)) {
va009039 0:39eb4d5b97df 355 for (int j = 1; j < 5; j++) {
va009039 0:39eb4d5b97df 356 response[i] = _spi.write(0xFF);
va009039 0:39eb4d5b97df 357 }
va009039 0:39eb4d5b97df 358 _cs = 1;
va009039 0:39eb4d5b97df 359 _spi.write(0xFF);
va009039 0:39eb4d5b97df 360 return response[0];
va009039 0:39eb4d5b97df 361 }
va009039 0:39eb4d5b97df 362 }
va009039 0:39eb4d5b97df 363 _cs = 1;
va009039 0:39eb4d5b97df 364 _spi.write(0xFF);
va009039 0:39eb4d5b97df 365 return -1; // timeout
va009039 0:39eb4d5b97df 366 }
va009039 0:39eb4d5b97df 367
va009039 0:39eb4d5b97df 368 int SDStorage::_read(uint8_t *buffer, uint32_t length) {
va009039 0:39eb4d5b97df 369 _cs = 0;
va009039 0:39eb4d5b97df 370
va009039 0:39eb4d5b97df 371 // read until start byte (0xFF)
va009039 0:39eb4d5b97df 372 while (_spi.write(0xFF) != 0xFE);
va009039 0:39eb4d5b97df 373
va009039 0:39eb4d5b97df 374 // read data
va009039 0:39eb4d5b97df 375 for (int i = 0; i < length; i++) {
va009039 0:39eb4d5b97df 376 buffer[i] = _spi.write(0xFF);
va009039 0:39eb4d5b97df 377 }
va009039 0:39eb4d5b97df 378 _spi.write(0xFF); // checksum
va009039 0:39eb4d5b97df 379 _spi.write(0xFF);
va009039 0:39eb4d5b97df 380
va009039 0:39eb4d5b97df 381 _cs = 1;
va009039 0:39eb4d5b97df 382 _spi.write(0xFF);
va009039 0:39eb4d5b97df 383 return 0;
va009039 0:39eb4d5b97df 384 }
va009039 0:39eb4d5b97df 385
va009039 0:39eb4d5b97df 386 int SDStorage::_write(const uint8_t*buffer, uint32_t length) {
va009039 0:39eb4d5b97df 387 _cs = 0;
va009039 0:39eb4d5b97df 388
va009039 0:39eb4d5b97df 389 // indicate start of block
va009039 0:39eb4d5b97df 390 _spi.write(0xFE);
va009039 0:39eb4d5b97df 391
va009039 0:39eb4d5b97df 392 // write the data
va009039 0:39eb4d5b97df 393 for (int i = 0; i < length; i++) {
va009039 0:39eb4d5b97df 394 _spi.write(buffer[i]);
va009039 0:39eb4d5b97df 395 }
va009039 0:39eb4d5b97df 396
va009039 0:39eb4d5b97df 397 // write the checksum
va009039 0:39eb4d5b97df 398 _spi.write(0xFF);
va009039 0:39eb4d5b97df 399 _spi.write(0xFF);
va009039 0:39eb4d5b97df 400
va009039 0:39eb4d5b97df 401 // check the response token
va009039 0:39eb4d5b97df 402 if ((_spi.write(0xFF) & 0x1F) != 0x05) {
va009039 0:39eb4d5b97df 403 _cs = 1;
va009039 0:39eb4d5b97df 404 _spi.write(0xFF);
va009039 0:39eb4d5b97df 405 return 1;
va009039 0:39eb4d5b97df 406 }
va009039 0:39eb4d5b97df 407
va009039 0:39eb4d5b97df 408 // wait for write to finish
va009039 0:39eb4d5b97df 409 while (_spi.write(0xFF) == 0);
va009039 0:39eb4d5b97df 410
va009039 0:39eb4d5b97df 411 _cs = 1;
va009039 0:39eb4d5b97df 412 _spi.write(0xFF);
va009039 0:39eb4d5b97df 413 return 0;
va009039 0:39eb4d5b97df 414 }
va009039 0:39eb4d5b97df 415
va009039 0:39eb4d5b97df 416 static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
va009039 0:39eb4d5b97df 417 uint32_t bits = 0;
va009039 0:39eb4d5b97df 418 uint32_t size = 1 + msb - lsb;
va009039 0:39eb4d5b97df 419 for (int i = 0; i < size; i++) {
va009039 0:39eb4d5b97df 420 uint32_t position = lsb + i;
va009039 0:39eb4d5b97df 421 uint32_t byte = 15 - (position >> 3);
va009039 0:39eb4d5b97df 422 uint32_t bit = position & 0x7;
va009039 0:39eb4d5b97df 423 uint32_t value = (data[byte] >> bit) & 1;
va009039 0:39eb4d5b97df 424 bits |= value << i;
va009039 0:39eb4d5b97df 425 }
va009039 0:39eb4d5b97df 426 return bits;
va009039 0:39eb4d5b97df 427 }
va009039 0:39eb4d5b97df 428
va009039 0:39eb4d5b97df 429 uint64_t SDStorage::_sd_sectors() {
va009039 0:39eb4d5b97df 430 uint32_t c_size, c_size_mult, read_bl_len;
va009039 0:39eb4d5b97df 431 uint32_t block_len, mult, blocknr, capacity;
va009039 0:39eb4d5b97df 432 uint32_t hc_c_size;
va009039 0:39eb4d5b97df 433 uint64_t blocks;
va009039 0:39eb4d5b97df 434
va009039 0:39eb4d5b97df 435 // CMD9, Response R2 (R1 byte + 16-byte block read)
va009039 0:39eb4d5b97df 436 if (_cmdx(9, 0) != 0) {
va009039 0:39eb4d5b97df 437 debug("Didn't get a response from the disk\n");
va009039 0:39eb4d5b97df 438 return 0;
va009039 0:39eb4d5b97df 439 }
va009039 0:39eb4d5b97df 440
va009039 0:39eb4d5b97df 441 uint8_t csd[16];
va009039 0:39eb4d5b97df 442 if (_read(csd, 16) != 0) {
va009039 0:39eb4d5b97df 443 debug("Couldn't read csd response from disk\n");
va009039 0:39eb4d5b97df 444 return 0;
va009039 0:39eb4d5b97df 445 }
va009039 0:39eb4d5b97df 446
va009039 0:39eb4d5b97df 447 // csd_structure : csd[127:126]
va009039 0:39eb4d5b97df 448 // c_size : csd[73:62]
va009039 0:39eb4d5b97df 449 // c_size_mult : csd[49:47]
va009039 0:39eb4d5b97df 450 // read_bl_len : csd[83:80] - the *maximum* read block length
va009039 0:39eb4d5b97df 451
va009039 0:39eb4d5b97df 452 int csd_structure = ext_bits(csd, 127, 126);
va009039 0:39eb4d5b97df 453
va009039 0:39eb4d5b97df 454 switch (csd_structure) {
va009039 0:39eb4d5b97df 455 case 0:
va009039 0:39eb4d5b97df 456 cdv = 512;
va009039 0:39eb4d5b97df 457 c_size = ext_bits(csd, 73, 62);
va009039 0:39eb4d5b97df 458 c_size_mult = ext_bits(csd, 49, 47);
va009039 0:39eb4d5b97df 459 read_bl_len = ext_bits(csd, 83, 80);
va009039 0:39eb4d5b97df 460
va009039 0:39eb4d5b97df 461 block_len = 1 << read_bl_len;
va009039 0:39eb4d5b97df 462 mult = 1 << (c_size_mult + 2);
va009039 0:39eb4d5b97df 463 blocknr = (c_size + 1) * mult;
va009039 0:39eb4d5b97df 464 capacity = blocknr * block_len;
va009039 0:39eb4d5b97df 465 blocks = capacity / 512;
va009039 0:39eb4d5b97df 466 debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
va009039 0:39eb4d5b97df 467 break;
va009039 0:39eb4d5b97df 468
va009039 0:39eb4d5b97df 469 case 1:
va009039 0:39eb4d5b97df 470 cdv = 1;
va009039 0:39eb4d5b97df 471 hc_c_size = ext_bits(csd, 63, 48);
va009039 0:39eb4d5b97df 472 blocks = (hc_c_size+1)*1024;
va009039 0:39eb4d5b97df 473 debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
va009039 0:39eb4d5b97df 474 break;
va009039 0:39eb4d5b97df 475
va009039 0:39eb4d5b97df 476 default:
va009039 0:39eb4d5b97df 477 debug("CSD struct unsupported\r\n");
va009039 0:39eb4d5b97df 478 return 0;
va009039 0:39eb4d5b97df 479 };
va009039 0:39eb4d5b97df 480 return blocks;
va009039 0:39eb4d5b97df 481 }
va009039 0:39eb4d5b97df 482
va009039 0:39eb4d5b97df 483 /* virtual */ uint32_t SDStorage::storage_size()
va009039 0:39eb4d5b97df 484 {
va009039 2:97c314eae8b8 485 report_size_count++;
va009039 0:39eb4d5b97df 486 return _sectors * 512;
va009039 0:39eb4d5b97df 487 }
va009039 0:39eb4d5b97df 488