Juan Salazar / sofi7

test

Dependents:   robotic_fish_6

TARGET_LPC1768/core_ca9.h@0:c792b17d9f78, 2021-12-03 (annotated)

Committer:
juansal12
Date:
Fri Dec 03 23:00:34 2021 +0000
Revision:
0:c792b17d9f78
uploaded sofi code ;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
juansal12 0:c792b17d9f78 1 /**************************************************************************//**
juansal12 0:c792b17d9f78 2 * @file core_ca9.h
juansal12 0:c792b17d9f78 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
juansal12 0:c792b17d9f78 4 * @version
juansal12 0:c792b17d9f78 5 * @date 25 March 2013
juansal12 0:c792b17d9f78 6 *
juansal12 0:c792b17d9f78 7 * @note
juansal12 0:c792b17d9f78 8 *
juansal12 0:c792b17d9f78 9 ******************************************************************************/
juansal12 0:c792b17d9f78 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
juansal12 0:c792b17d9f78 11
juansal12 0:c792b17d9f78 12 All rights reserved.
juansal12 0:c792b17d9f78 13 Redistribution and use in source and binary forms, with or without
juansal12 0:c792b17d9f78 14 modification, are permitted provided that the following conditions are met:
juansal12 0:c792b17d9f78 15 - Redistributions of source code must retain the above copyright
juansal12 0:c792b17d9f78 16 notice, this list of conditions and the following disclaimer.
juansal12 0:c792b17d9f78 17 - Redistributions in binary form must reproduce the above copyright
juansal12 0:c792b17d9f78 18 notice, this list of conditions and the following disclaimer in the
juansal12 0:c792b17d9f78 19 documentation and/or other materials provided with the distribution.
juansal12 0:c792b17d9f78 20 - Neither the name of ARM nor the names of its contributors may be used
juansal12 0:c792b17d9f78 21 to endorse or promote products derived from this software without
juansal12 0:c792b17d9f78 22 specific prior written permission.
juansal12 0:c792b17d9f78 23 *
juansal12 0:c792b17d9f78 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
juansal12 0:c792b17d9f78 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
juansal12 0:c792b17d9f78 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
juansal12 0:c792b17d9f78 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
juansal12 0:c792b17d9f78 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
juansal12 0:c792b17d9f78 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
juansal12 0:c792b17d9f78 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
juansal12 0:c792b17d9f78 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
juansal12 0:c792b17d9f78 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
juansal12 0:c792b17d9f78 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
juansal12 0:c792b17d9f78 34 POSSIBILITY OF SUCH DAMAGE.
juansal12 0:c792b17d9f78 35 ---------------------------------------------------------------------------*/
juansal12 0:c792b17d9f78 36
juansal12 0:c792b17d9f78 37
juansal12 0:c792b17d9f78 38 #if defined ( __ICCARM__ )
juansal12 0:c792b17d9f78 39 #pragma system_include /* treat file as system include file for MISRA check */
juansal12 0:c792b17d9f78 40 #endif
juansal12 0:c792b17d9f78 41
juansal12 0:c792b17d9f78 42 #ifdef __cplusplus
juansal12 0:c792b17d9f78 43 extern "C" {
juansal12 0:c792b17d9f78 44 #endif
juansal12 0:c792b17d9f78 45
juansal12 0:c792b17d9f78 46 #ifndef __CORE_CA9_H_GENERIC
juansal12 0:c792b17d9f78 47 #define __CORE_CA9_H_GENERIC
juansal12 0:c792b17d9f78 48
juansal12 0:c792b17d9f78 49
juansal12 0:c792b17d9f78 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
juansal12 0:c792b17d9f78 51 CMSIS violates the following MISRA-C:2004 rules:
juansal12 0:c792b17d9f78 52
juansal12 0:c792b17d9f78 53 \li Required Rule 8.5, object/function definition in header file.<br>
juansal12 0:c792b17d9f78 54 Function definitions in header files are used to allow 'inlining'.
juansal12 0:c792b17d9f78 55
juansal12 0:c792b17d9f78 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
juansal12 0:c792b17d9f78 57 Unions are used for effective representation of core registers.
juansal12 0:c792b17d9f78 58
juansal12 0:c792b17d9f78 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
juansal12 0:c792b17d9f78 60 Function-like macros are used to allow more efficient code.
juansal12 0:c792b17d9f78 61 */
juansal12 0:c792b17d9f78 62
juansal12 0:c792b17d9f78 63
juansal12 0:c792b17d9f78 64 /*******************************************************************************
juansal12 0:c792b17d9f78 65 * CMSIS definitions
juansal12 0:c792b17d9f78 66 ******************************************************************************/
juansal12 0:c792b17d9f78 67 /** \ingroup Cortex_A9
juansal12 0:c792b17d9f78 68 @{
juansal12 0:c792b17d9f78 69 */
juansal12 0:c792b17d9f78 70
juansal12 0:c792b17d9f78 71 /* CMSIS CA9 definitions */
juansal12 0:c792b17d9f78 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
juansal12 0:c792b17d9f78 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
juansal12 0:c792b17d9f78 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
juansal12 0:c792b17d9f78 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
juansal12 0:c792b17d9f78 76
juansal12 0:c792b17d9f78 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
juansal12 0:c792b17d9f78 78
juansal12 0:c792b17d9f78 79
juansal12 0:c792b17d9f78 80 #if defined ( __CC_ARM )
juansal12 0:c792b17d9f78 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
juansal12 0:c792b17d9f78 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
juansal12 0:c792b17d9f78 83 #define __STATIC_INLINE static __inline
juansal12 0:c792b17d9f78 84 #define __STATIC_ASM static __asm
juansal12 0:c792b17d9f78 85
juansal12 0:c792b17d9f78 86 #elif defined ( __ICCARM__ )
juansal12 0:c792b17d9f78 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
juansal12 0:c792b17d9f78 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
juansal12 0:c792b17d9f78 89 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 90 #define __STATIC_ASM static __asm
juansal12 0:c792b17d9f78 91
juansal12 0:c792b17d9f78 92 #elif defined ( __TMS470__ )
juansal12 0:c792b17d9f78 93 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
juansal12 0:c792b17d9f78 94 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 95 #define __STATIC_ASM static __asm
juansal12 0:c792b17d9f78 96
juansal12 0:c792b17d9f78 97 #elif defined ( __GNUC__ )
juansal12 0:c792b17d9f78 98 #define __ASM __asm /*!< asm keyword for GNU Compiler */
juansal12 0:c792b17d9f78 99 #define __INLINE inline /*!< inline keyword for GNU Compiler */
juansal12 0:c792b17d9f78 100 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 101 #define __STATIC_ASM static __asm
juansal12 0:c792b17d9f78 102
juansal12 0:c792b17d9f78 103 #elif defined ( __TASKING__ )
juansal12 0:c792b17d9f78 104 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
juansal12 0:c792b17d9f78 105 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
juansal12 0:c792b17d9f78 106 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 107 #define __STATIC_ASM static __asm
juansal12 0:c792b17d9f78 108
juansal12 0:c792b17d9f78 109 #endif
juansal12 0:c792b17d9f78 110
juansal12 0:c792b17d9f78 111 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
juansal12 0:c792b17d9f78 112 */
juansal12 0:c792b17d9f78 113 #if defined ( __CC_ARM )
juansal12 0:c792b17d9f78 114 #if defined __TARGET_FPU_VFP
juansal12 0:c792b17d9f78 115 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 116 #define __FPU_USED 1
juansal12 0:c792b17d9f78 117 #else
juansal12 0:c792b17d9f78 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 119 #define __FPU_USED 0
juansal12 0:c792b17d9f78 120 #endif
juansal12 0:c792b17d9f78 121 #else
juansal12 0:c792b17d9f78 122 #define __FPU_USED 0
juansal12 0:c792b17d9f78 123 #endif
juansal12 0:c792b17d9f78 124
juansal12 0:c792b17d9f78 125 #elif defined ( __ICCARM__ )
juansal12 0:c792b17d9f78 126 #if defined __ARMVFP__
juansal12 0:c792b17d9f78 127 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 128 #define __FPU_USED 1
juansal12 0:c792b17d9f78 129 #else
juansal12 0:c792b17d9f78 130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 131 #define __FPU_USED 0
juansal12 0:c792b17d9f78 132 #endif
juansal12 0:c792b17d9f78 133 #else
juansal12 0:c792b17d9f78 134 #define __FPU_USED 0
juansal12 0:c792b17d9f78 135 #endif
juansal12 0:c792b17d9f78 136
juansal12 0:c792b17d9f78 137 #elif defined ( __TMS470__ )
juansal12 0:c792b17d9f78 138 #if defined __TI_VFP_SUPPORT__
juansal12 0:c792b17d9f78 139 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 140 #define __FPU_USED 1
juansal12 0:c792b17d9f78 141 #else
juansal12 0:c792b17d9f78 142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 143 #define __FPU_USED 0
juansal12 0:c792b17d9f78 144 #endif
juansal12 0:c792b17d9f78 145 #else
juansal12 0:c792b17d9f78 146 #define __FPU_USED 0
juansal12 0:c792b17d9f78 147 #endif
juansal12 0:c792b17d9f78 148
juansal12 0:c792b17d9f78 149 #elif defined ( __GNUC__ )
juansal12 0:c792b17d9f78 150 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
juansal12 0:c792b17d9f78 151 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 152 #define __FPU_USED 1
juansal12 0:c792b17d9f78 153 #else
juansal12 0:c792b17d9f78 154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 155 #define __FPU_USED 0
juansal12 0:c792b17d9f78 156 #endif
juansal12 0:c792b17d9f78 157 #else
juansal12 0:c792b17d9f78 158 #define __FPU_USED 0
juansal12 0:c792b17d9f78 159 #endif
juansal12 0:c792b17d9f78 160
juansal12 0:c792b17d9f78 161 #elif defined ( __TASKING__ )
juansal12 0:c792b17d9f78 162 #if defined __FPU_VFP__
juansal12 0:c792b17d9f78 163 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 164 #define __FPU_USED 1
juansal12 0:c792b17d9f78 165 #else
juansal12 0:c792b17d9f78 166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 167 #define __FPU_USED 0
juansal12 0:c792b17d9f78 168 #endif
juansal12 0:c792b17d9f78 169 #else
juansal12 0:c792b17d9f78 170 #define __FPU_USED 0
juansal12 0:c792b17d9f78 171 #endif
juansal12 0:c792b17d9f78 172 #endif
juansal12 0:c792b17d9f78 173
juansal12 0:c792b17d9f78 174 #include <stdint.h> /*!< standard types definitions */
juansal12 0:c792b17d9f78 175 #include "core_caInstr.h" /*!< Core Instruction Access */
juansal12 0:c792b17d9f78 176 #include "core_caFunc.h" /*!< Core Function Access */
juansal12 0:c792b17d9f78 177 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
juansal12 0:c792b17d9f78 178
juansal12 0:c792b17d9f78 179 #endif /* __CORE_CA9_H_GENERIC */
juansal12 0:c792b17d9f78 180
juansal12 0:c792b17d9f78 181 #ifndef __CMSIS_GENERIC
juansal12 0:c792b17d9f78 182
juansal12 0:c792b17d9f78 183 #ifndef __CORE_CA9_H_DEPENDANT
juansal12 0:c792b17d9f78 184 #define __CORE_CA9_H_DEPENDANT
juansal12 0:c792b17d9f78 185
juansal12 0:c792b17d9f78 186 /* check device defines and use defaults */
juansal12 0:c792b17d9f78 187 #if defined __CHECK_DEVICE_DEFINES
juansal12 0:c792b17d9f78 188 #ifndef __CA9_REV
juansal12 0:c792b17d9f78 189 #define __CA9_REV 0x0000
juansal12 0:c792b17d9f78 190 #warning "__CA9_REV not defined in device header file; using default!"
juansal12 0:c792b17d9f78 191 #endif
juansal12 0:c792b17d9f78 192
juansal12 0:c792b17d9f78 193 #ifndef __FPU_PRESENT
juansal12 0:c792b17d9f78 194 #define __FPU_PRESENT 1
juansal12 0:c792b17d9f78 195 #warning "__FPU_PRESENT not defined in device header file; using default!"
juansal12 0:c792b17d9f78 196 #endif
juansal12 0:c792b17d9f78 197
juansal12 0:c792b17d9f78 198 #ifndef __Vendor_SysTickConfig
juansal12 0:c792b17d9f78 199 #define __Vendor_SysTickConfig 1
juansal12 0:c792b17d9f78 200 #endif
juansal12 0:c792b17d9f78 201
juansal12 0:c792b17d9f78 202 #if __Vendor_SysTickConfig == 0
juansal12 0:c792b17d9f78 203 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
juansal12 0:c792b17d9f78 204 #endif
juansal12 0:c792b17d9f78 205 #endif
juansal12 0:c792b17d9f78 206
juansal12 0:c792b17d9f78 207 /* IO definitions (access restrictions to peripheral registers) */
juansal12 0:c792b17d9f78 208 /**
juansal12 0:c792b17d9f78 209 \defgroup CMSIS_glob_defs CMSIS Global Defines
juansal12 0:c792b17d9f78 210
juansal12 0:c792b17d9f78 211 <strong>IO Type Qualifiers</strong> are used
juansal12 0:c792b17d9f78 212 \li to specify the access to peripheral variables.
juansal12 0:c792b17d9f78 213 \li for automatic generation of peripheral register debug information.
juansal12 0:c792b17d9f78 214 */
juansal12 0:c792b17d9f78 215 #ifdef __cplusplus
juansal12 0:c792b17d9f78 216 #define __I volatile /*!< Defines 'read only' permissions */
juansal12 0:c792b17d9f78 217 #else
juansal12 0:c792b17d9f78 218 #define __I volatile const /*!< Defines 'read only' permissions */
juansal12 0:c792b17d9f78 219 #endif
juansal12 0:c792b17d9f78 220 #define __O volatile /*!< Defines 'write only' permissions */
juansal12 0:c792b17d9f78 221 #define __IO volatile /*!< Defines 'read / write' permissions */
juansal12 0:c792b17d9f78 222
juansal12 0:c792b17d9f78 223 /*@} end of group Cortex_A9 */
juansal12 0:c792b17d9f78 224
juansal12 0:c792b17d9f78 225
juansal12 0:c792b17d9f78 226 /*******************************************************************************
juansal12 0:c792b17d9f78 227 * Register Abstraction
juansal12 0:c792b17d9f78 228 ******************************************************************************/
juansal12 0:c792b17d9f78 229 /** \defgroup CMSIS_core_register Defines and Type Definitions
juansal12 0:c792b17d9f78 230 \brief Type definitions and defines for Cortex-A processor based devices.
juansal12 0:c792b17d9f78 231 */
juansal12 0:c792b17d9f78 232
juansal12 0:c792b17d9f78 233 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 234 \defgroup CMSIS_CORE Status and Control Registers
juansal12 0:c792b17d9f78 235 \brief Core Register type definitions.
juansal12 0:c792b17d9f78 236 @{
juansal12 0:c792b17d9f78 237 */
juansal12 0:c792b17d9f78 238
juansal12 0:c792b17d9f78 239 /** \brief Union type to access the Application Program Status Register (APSR).
juansal12 0:c792b17d9f78 240 */
juansal12 0:c792b17d9f78 241 typedef union
juansal12 0:c792b17d9f78 242 {
juansal12 0:c792b17d9f78 243 struct
juansal12 0:c792b17d9f78 244 {
juansal12 0:c792b17d9f78 245 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
juansal12 0:c792b17d9f78 246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
juansal12 0:c792b17d9f78 247 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
juansal12 0:c792b17d9f78 248 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
juansal12 0:c792b17d9f78 249 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
juansal12 0:c792b17d9f78 250 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
juansal12 0:c792b17d9f78 251 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
juansal12 0:c792b17d9f78 252 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
juansal12 0:c792b17d9f78 253 } b; /*!< Structure used for bit access */
juansal12 0:c792b17d9f78 254 uint32_t w; /*!< Type used for word access */
juansal12 0:c792b17d9f78 255 } APSR_Type;
juansal12 0:c792b17d9f78 256
juansal12 0:c792b17d9f78 257
juansal12 0:c792b17d9f78 258 /*@} end of group CMSIS_CORE */
juansal12 0:c792b17d9f78 259
juansal12 0:c792b17d9f78 260 /*@} end of CMSIS_Core_FPUFunctions */
juansal12 0:c792b17d9f78 261
juansal12 0:c792b17d9f78 262
juansal12 0:c792b17d9f78 263 #endif /* __CORE_CA9_H_GENERIC */
juansal12 0:c792b17d9f78 264
juansal12 0:c792b17d9f78 265 #endif /* __CMSIS_GENERIC */
juansal12 0:c792b17d9f78 266
juansal12 0:c792b17d9f78 267 #ifdef __cplusplus
juansal12 0:c792b17d9f78 268 }
juansal12 0:c792b17d9f78 269
juansal12 0:c792b17d9f78 270
juansal12 0:c792b17d9f78 271 #endif