Juan Salazar / sofi7

test

Dependents:   robotic_fish_6

TARGET_LPC1768/core_cm0plus.h@0:c792b17d9f78, 2021-12-03 (annotated)

Committer:
juansal12
Date:
Fri Dec 03 23:00:34 2021 +0000
Revision:
0:c792b17d9f78
uploaded sofi code ;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
juansal12 0:c792b17d9f78 1 /**************************************************************************//**
juansal12 0:c792b17d9f78 2 * @file core_cm0plus.h
juansal12 0:c792b17d9f78 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
juansal12 0:c792b17d9f78 4 * @version V3.20
juansal12 0:c792b17d9f78 5 * @date 25. February 2013
juansal12 0:c792b17d9f78 6 *
juansal12 0:c792b17d9f78 7 * @note
juansal12 0:c792b17d9f78 8 *
juansal12 0:c792b17d9f78 9 ******************************************************************************/
juansal12 0:c792b17d9f78 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
juansal12 0:c792b17d9f78 11
juansal12 0:c792b17d9f78 12 All rights reserved.
juansal12 0:c792b17d9f78 13 Redistribution and use in source and binary forms, with or without
juansal12 0:c792b17d9f78 14 modification, are permitted provided that the following conditions are met:
juansal12 0:c792b17d9f78 15 - Redistributions of source code must retain the above copyright
juansal12 0:c792b17d9f78 16 notice, this list of conditions and the following disclaimer.
juansal12 0:c792b17d9f78 17 - Redistributions in binary form must reproduce the above copyright
juansal12 0:c792b17d9f78 18 notice, this list of conditions and the following disclaimer in the
juansal12 0:c792b17d9f78 19 documentation and/or other materials provided with the distribution.
juansal12 0:c792b17d9f78 20 - Neither the name of ARM nor the names of its contributors may be used
juansal12 0:c792b17d9f78 21 to endorse or promote products derived from this software without
juansal12 0:c792b17d9f78 22 specific prior written permission.
juansal12 0:c792b17d9f78 23 *
juansal12 0:c792b17d9f78 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
juansal12 0:c792b17d9f78 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
juansal12 0:c792b17d9f78 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
juansal12 0:c792b17d9f78 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
juansal12 0:c792b17d9f78 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
juansal12 0:c792b17d9f78 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
juansal12 0:c792b17d9f78 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
juansal12 0:c792b17d9f78 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
juansal12 0:c792b17d9f78 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
juansal12 0:c792b17d9f78 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
juansal12 0:c792b17d9f78 34 POSSIBILITY OF SUCH DAMAGE.
juansal12 0:c792b17d9f78 35 ---------------------------------------------------------------------------*/
juansal12 0:c792b17d9f78 36
juansal12 0:c792b17d9f78 37
juansal12 0:c792b17d9f78 38 #if defined ( __ICCARM__ )
juansal12 0:c792b17d9f78 39 #pragma system_include /* treat file as system include file for MISRA check */
juansal12 0:c792b17d9f78 40 #endif
juansal12 0:c792b17d9f78 41
juansal12 0:c792b17d9f78 42 #ifdef __cplusplus
juansal12 0:c792b17d9f78 43 extern "C" {
juansal12 0:c792b17d9f78 44 #endif
juansal12 0:c792b17d9f78 45
juansal12 0:c792b17d9f78 46 #ifndef __CORE_CM0PLUS_H_GENERIC
juansal12 0:c792b17d9f78 47 #define __CORE_CM0PLUS_H_GENERIC
juansal12 0:c792b17d9f78 48
juansal12 0:c792b17d9f78 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
juansal12 0:c792b17d9f78 50 CMSIS violates the following MISRA-C:2004 rules:
juansal12 0:c792b17d9f78 51
juansal12 0:c792b17d9f78 52 \li Required Rule 8.5, object/function definition in header file.<br>
juansal12 0:c792b17d9f78 53 Function definitions in header files are used to allow 'inlining'.
juansal12 0:c792b17d9f78 54
juansal12 0:c792b17d9f78 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
juansal12 0:c792b17d9f78 56 Unions are used for effective representation of core registers.
juansal12 0:c792b17d9f78 57
juansal12 0:c792b17d9f78 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
juansal12 0:c792b17d9f78 59 Function-like macros are used to allow more efficient code.
juansal12 0:c792b17d9f78 60 */
juansal12 0:c792b17d9f78 61
juansal12 0:c792b17d9f78 62
juansal12 0:c792b17d9f78 63 /*******************************************************************************
juansal12 0:c792b17d9f78 64 * CMSIS definitions
juansal12 0:c792b17d9f78 65 ******************************************************************************/
juansal12 0:c792b17d9f78 66 /** \ingroup Cortex-M0+
juansal12 0:c792b17d9f78 67 @{
juansal12 0:c792b17d9f78 68 */
juansal12 0:c792b17d9f78 69
juansal12 0:c792b17d9f78 70 /* CMSIS CM0P definitions */
juansal12 0:c792b17d9f78 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
juansal12 0:c792b17d9f78 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
juansal12 0:c792b17d9f78 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
juansal12 0:c792b17d9f78 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
juansal12 0:c792b17d9f78 75
juansal12 0:c792b17d9f78 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
juansal12 0:c792b17d9f78 77
juansal12 0:c792b17d9f78 78
juansal12 0:c792b17d9f78 79 #if defined ( __CC_ARM )
juansal12 0:c792b17d9f78 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
juansal12 0:c792b17d9f78 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
juansal12 0:c792b17d9f78 82 #define __STATIC_INLINE static __inline
juansal12 0:c792b17d9f78 83
juansal12 0:c792b17d9f78 84 #elif defined ( __ICCARM__ )
juansal12 0:c792b17d9f78 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
juansal12 0:c792b17d9f78 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
juansal12 0:c792b17d9f78 87 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 88
juansal12 0:c792b17d9f78 89 #elif defined ( __GNUC__ )
juansal12 0:c792b17d9f78 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
juansal12 0:c792b17d9f78 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
juansal12 0:c792b17d9f78 92 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 93
juansal12 0:c792b17d9f78 94 #elif defined ( __TASKING__ )
juansal12 0:c792b17d9f78 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
juansal12 0:c792b17d9f78 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
juansal12 0:c792b17d9f78 97 #define __STATIC_INLINE static inline
juansal12 0:c792b17d9f78 98
juansal12 0:c792b17d9f78 99 #endif
juansal12 0:c792b17d9f78 100
juansal12 0:c792b17d9f78 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
juansal12 0:c792b17d9f78 102 */
juansal12 0:c792b17d9f78 103 #define __FPU_USED 0
juansal12 0:c792b17d9f78 104
juansal12 0:c792b17d9f78 105 #if defined ( __CC_ARM )
juansal12 0:c792b17d9f78 106 #if defined __TARGET_FPU_VFP
juansal12 0:c792b17d9f78 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 108 #endif
juansal12 0:c792b17d9f78 109
juansal12 0:c792b17d9f78 110 #elif defined ( __ICCARM__ )
juansal12 0:c792b17d9f78 111 #if defined __ARMVFP__
juansal12 0:c792b17d9f78 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 113 #endif
juansal12 0:c792b17d9f78 114
juansal12 0:c792b17d9f78 115 #elif defined ( __GNUC__ )
juansal12 0:c792b17d9f78 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
juansal12 0:c792b17d9f78 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 118 #endif
juansal12 0:c792b17d9f78 119
juansal12 0:c792b17d9f78 120 #elif defined ( __TASKING__ )
juansal12 0:c792b17d9f78 121 #if defined __FPU_VFP__
juansal12 0:c792b17d9f78 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12 0:c792b17d9f78 123 #endif
juansal12 0:c792b17d9f78 124 #endif
juansal12 0:c792b17d9f78 125
juansal12 0:c792b17d9f78 126 #include <stdint.h> /* standard types definitions */
juansal12 0:c792b17d9f78 127 #include <core_cmInstr.h> /* Core Instruction Access */
juansal12 0:c792b17d9f78 128 #include <core_cmFunc.h> /* Core Function Access */
juansal12 0:c792b17d9f78 129
juansal12 0:c792b17d9f78 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
juansal12 0:c792b17d9f78 131
juansal12 0:c792b17d9f78 132 #ifndef __CMSIS_GENERIC
juansal12 0:c792b17d9f78 133
juansal12 0:c792b17d9f78 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
juansal12 0:c792b17d9f78 135 #define __CORE_CM0PLUS_H_DEPENDANT
juansal12 0:c792b17d9f78 136
juansal12 0:c792b17d9f78 137 /* check device defines and use defaults */
juansal12 0:c792b17d9f78 138 #if defined __CHECK_DEVICE_DEFINES
juansal12 0:c792b17d9f78 139 #ifndef __CM0PLUS_REV
juansal12 0:c792b17d9f78 140 #define __CM0PLUS_REV 0x0000
juansal12 0:c792b17d9f78 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
juansal12 0:c792b17d9f78 142 #endif
juansal12 0:c792b17d9f78 143
juansal12 0:c792b17d9f78 144 #ifndef __MPU_PRESENT
juansal12 0:c792b17d9f78 145 #define __MPU_PRESENT 0
juansal12 0:c792b17d9f78 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
juansal12 0:c792b17d9f78 147 #endif
juansal12 0:c792b17d9f78 148
juansal12 0:c792b17d9f78 149 #ifndef __VTOR_PRESENT
juansal12 0:c792b17d9f78 150 #define __VTOR_PRESENT 0
juansal12 0:c792b17d9f78 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
juansal12 0:c792b17d9f78 152 #endif
juansal12 0:c792b17d9f78 153
juansal12 0:c792b17d9f78 154 #ifndef __NVIC_PRIO_BITS
juansal12 0:c792b17d9f78 155 #define __NVIC_PRIO_BITS 2
juansal12 0:c792b17d9f78 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
juansal12 0:c792b17d9f78 157 #endif
juansal12 0:c792b17d9f78 158
juansal12 0:c792b17d9f78 159 #ifndef __Vendor_SysTickConfig
juansal12 0:c792b17d9f78 160 #define __Vendor_SysTickConfig 0
juansal12 0:c792b17d9f78 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
juansal12 0:c792b17d9f78 162 #endif
juansal12 0:c792b17d9f78 163 #endif
juansal12 0:c792b17d9f78 164
juansal12 0:c792b17d9f78 165 /* IO definitions (access restrictions to peripheral registers) */
juansal12 0:c792b17d9f78 166 /**
juansal12 0:c792b17d9f78 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
juansal12 0:c792b17d9f78 168
juansal12 0:c792b17d9f78 169 <strong>IO Type Qualifiers</strong> are used
juansal12 0:c792b17d9f78 170 \li to specify the access to peripheral variables.
juansal12 0:c792b17d9f78 171 \li for automatic generation of peripheral register debug information.
juansal12 0:c792b17d9f78 172 */
juansal12 0:c792b17d9f78 173 #ifdef __cplusplus
juansal12 0:c792b17d9f78 174 #define __I volatile /*!< Defines 'read only' permissions */
juansal12 0:c792b17d9f78 175 #else
juansal12 0:c792b17d9f78 176 #define __I volatile const /*!< Defines 'read only' permissions */
juansal12 0:c792b17d9f78 177 #endif
juansal12 0:c792b17d9f78 178 #define __O volatile /*!< Defines 'write only' permissions */
juansal12 0:c792b17d9f78 179 #define __IO volatile /*!< Defines 'read / write' permissions */
juansal12 0:c792b17d9f78 180
juansal12 0:c792b17d9f78 181 /*@} end of group Cortex-M0+ */
juansal12 0:c792b17d9f78 182
juansal12 0:c792b17d9f78 183
juansal12 0:c792b17d9f78 184
juansal12 0:c792b17d9f78 185 /*******************************************************************************
juansal12 0:c792b17d9f78 186 * Register Abstraction
juansal12 0:c792b17d9f78 187 Core Register contain:
juansal12 0:c792b17d9f78 188 - Core Register
juansal12 0:c792b17d9f78 189 - Core NVIC Register
juansal12 0:c792b17d9f78 190 - Core SCB Register
juansal12 0:c792b17d9f78 191 - Core SysTick Register
juansal12 0:c792b17d9f78 192 - Core MPU Register
juansal12 0:c792b17d9f78 193 ******************************************************************************/
juansal12 0:c792b17d9f78 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
juansal12 0:c792b17d9f78 195 \brief Type definitions and defines for Cortex-M processor based devices.
juansal12 0:c792b17d9f78 196 */
juansal12 0:c792b17d9f78 197
juansal12 0:c792b17d9f78 198 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 199 \defgroup CMSIS_CORE Status and Control Registers
juansal12 0:c792b17d9f78 200 \brief Core Register type definitions.
juansal12 0:c792b17d9f78 201 @{
juansal12 0:c792b17d9f78 202 */
juansal12 0:c792b17d9f78 203
juansal12 0:c792b17d9f78 204 /** \brief Union type to access the Application Program Status Register (APSR).
juansal12 0:c792b17d9f78 205 */
juansal12 0:c792b17d9f78 206 typedef union
juansal12 0:c792b17d9f78 207 {
juansal12 0:c792b17d9f78 208 struct
juansal12 0:c792b17d9f78 209 {
juansal12 0:c792b17d9f78 210 #if (__CORTEX_M != 0x04)
juansal12 0:c792b17d9f78 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
juansal12 0:c792b17d9f78 212 #else
juansal12 0:c792b17d9f78 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
juansal12 0:c792b17d9f78 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
juansal12 0:c792b17d9f78 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
juansal12 0:c792b17d9f78 216 #endif
juansal12 0:c792b17d9f78 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
juansal12 0:c792b17d9f78 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
juansal12 0:c792b17d9f78 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
juansal12 0:c792b17d9f78 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
juansal12 0:c792b17d9f78 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
juansal12 0:c792b17d9f78 222 } b; /*!< Structure used for bit access */
juansal12 0:c792b17d9f78 223 uint32_t w; /*!< Type used for word access */
juansal12 0:c792b17d9f78 224 } APSR_Type;
juansal12 0:c792b17d9f78 225
juansal12 0:c792b17d9f78 226
juansal12 0:c792b17d9f78 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
juansal12 0:c792b17d9f78 228 */
juansal12 0:c792b17d9f78 229 typedef union
juansal12 0:c792b17d9f78 230 {
juansal12 0:c792b17d9f78 231 struct
juansal12 0:c792b17d9f78 232 {
juansal12 0:c792b17d9f78 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
juansal12 0:c792b17d9f78 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
juansal12 0:c792b17d9f78 235 } b; /*!< Structure used for bit access */
juansal12 0:c792b17d9f78 236 uint32_t w; /*!< Type used for word access */
juansal12 0:c792b17d9f78 237 } IPSR_Type;
juansal12 0:c792b17d9f78 238
juansal12 0:c792b17d9f78 239
juansal12 0:c792b17d9f78 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
juansal12 0:c792b17d9f78 241 */
juansal12 0:c792b17d9f78 242 typedef union
juansal12 0:c792b17d9f78 243 {
juansal12 0:c792b17d9f78 244 struct
juansal12 0:c792b17d9f78 245 {
juansal12 0:c792b17d9f78 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
juansal12 0:c792b17d9f78 247 #if (__CORTEX_M != 0x04)
juansal12 0:c792b17d9f78 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
juansal12 0:c792b17d9f78 249 #else
juansal12 0:c792b17d9f78 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
juansal12 0:c792b17d9f78 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
juansal12 0:c792b17d9f78 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
juansal12 0:c792b17d9f78 253 #endif
juansal12 0:c792b17d9f78 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
juansal12 0:c792b17d9f78 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
juansal12 0:c792b17d9f78 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
juansal12 0:c792b17d9f78 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
juansal12 0:c792b17d9f78 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
juansal12 0:c792b17d9f78 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
juansal12 0:c792b17d9f78 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
juansal12 0:c792b17d9f78 261 } b; /*!< Structure used for bit access */
juansal12 0:c792b17d9f78 262 uint32_t w; /*!< Type used for word access */
juansal12 0:c792b17d9f78 263 } xPSR_Type;
juansal12 0:c792b17d9f78 264
juansal12 0:c792b17d9f78 265
juansal12 0:c792b17d9f78 266 /** \brief Union type to access the Control Registers (CONTROL).
juansal12 0:c792b17d9f78 267 */
juansal12 0:c792b17d9f78 268 typedef union
juansal12 0:c792b17d9f78 269 {
juansal12 0:c792b17d9f78 270 struct
juansal12 0:c792b17d9f78 271 {
juansal12 0:c792b17d9f78 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
juansal12 0:c792b17d9f78 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
juansal12 0:c792b17d9f78 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
juansal12 0:c792b17d9f78 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
juansal12 0:c792b17d9f78 276 } b; /*!< Structure used for bit access */
juansal12 0:c792b17d9f78 277 uint32_t w; /*!< Type used for word access */
juansal12 0:c792b17d9f78 278 } CONTROL_Type;
juansal12 0:c792b17d9f78 279
juansal12 0:c792b17d9f78 280 /*@} end of group CMSIS_CORE */
juansal12 0:c792b17d9f78 281
juansal12 0:c792b17d9f78 282
juansal12 0:c792b17d9f78 283 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
juansal12 0:c792b17d9f78 285 \brief Type definitions for the NVIC Registers
juansal12 0:c792b17d9f78 286 @{
juansal12 0:c792b17d9f78 287 */
juansal12 0:c792b17d9f78 288
juansal12 0:c792b17d9f78 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
juansal12 0:c792b17d9f78 290 */
juansal12 0:c792b17d9f78 291 typedef struct
juansal12 0:c792b17d9f78 292 {
juansal12 0:c792b17d9f78 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
juansal12 0:c792b17d9f78 294 uint32_t RESERVED0[31];
juansal12 0:c792b17d9f78 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
juansal12 0:c792b17d9f78 296 uint32_t RSERVED1[31];
juansal12 0:c792b17d9f78 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
juansal12 0:c792b17d9f78 298 uint32_t RESERVED2[31];
juansal12 0:c792b17d9f78 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
juansal12 0:c792b17d9f78 300 uint32_t RESERVED3[31];
juansal12 0:c792b17d9f78 301 uint32_t RESERVED4[64];
juansal12 0:c792b17d9f78 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
juansal12 0:c792b17d9f78 303 } NVIC_Type;
juansal12 0:c792b17d9f78 304
juansal12 0:c792b17d9f78 305 /*@} end of group CMSIS_NVIC */
juansal12 0:c792b17d9f78 306
juansal12 0:c792b17d9f78 307
juansal12 0:c792b17d9f78 308 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 309 \defgroup CMSIS_SCB System Control Block (SCB)
juansal12 0:c792b17d9f78 310 \brief Type definitions for the System Control Block Registers
juansal12 0:c792b17d9f78 311 @{
juansal12 0:c792b17d9f78 312 */
juansal12 0:c792b17d9f78 313
juansal12 0:c792b17d9f78 314 /** \brief Structure type to access the System Control Block (SCB).
juansal12 0:c792b17d9f78 315 */
juansal12 0:c792b17d9f78 316 typedef struct
juansal12 0:c792b17d9f78 317 {
juansal12 0:c792b17d9f78 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
juansal12 0:c792b17d9f78 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
juansal12 0:c792b17d9f78 320 #if (__VTOR_PRESENT == 1)
juansal12 0:c792b17d9f78 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
juansal12 0:c792b17d9f78 322 #else
juansal12 0:c792b17d9f78 323 uint32_t RESERVED0;
juansal12 0:c792b17d9f78 324 #endif
juansal12 0:c792b17d9f78 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
juansal12 0:c792b17d9f78 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
juansal12 0:c792b17d9f78 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
juansal12 0:c792b17d9f78 328 uint32_t RESERVED1;
juansal12 0:c792b17d9f78 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
juansal12 0:c792b17d9f78 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
juansal12 0:c792b17d9f78 331 } SCB_Type;
juansal12 0:c792b17d9f78 332
juansal12 0:c792b17d9f78 333 /* SCB CPUID Register Definitions */
juansal12 0:c792b17d9f78 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
juansal12 0:c792b17d9f78 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
juansal12 0:c792b17d9f78 336
juansal12 0:c792b17d9f78 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
juansal12 0:c792b17d9f78 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
juansal12 0:c792b17d9f78 339
juansal12 0:c792b17d9f78 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
juansal12 0:c792b17d9f78 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
juansal12 0:c792b17d9f78 342
juansal12 0:c792b17d9f78 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
juansal12 0:c792b17d9f78 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
juansal12 0:c792b17d9f78 345
juansal12 0:c792b17d9f78 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
juansal12 0:c792b17d9f78 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
juansal12 0:c792b17d9f78 348
juansal12 0:c792b17d9f78 349 /* SCB Interrupt Control State Register Definitions */
juansal12 0:c792b17d9f78 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
juansal12 0:c792b17d9f78 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
juansal12 0:c792b17d9f78 352
juansal12 0:c792b17d9f78 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
juansal12 0:c792b17d9f78 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
juansal12 0:c792b17d9f78 355
juansal12 0:c792b17d9f78 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
juansal12 0:c792b17d9f78 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
juansal12 0:c792b17d9f78 358
juansal12 0:c792b17d9f78 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
juansal12 0:c792b17d9f78 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
juansal12 0:c792b17d9f78 361
juansal12 0:c792b17d9f78 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
juansal12 0:c792b17d9f78 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
juansal12 0:c792b17d9f78 364
juansal12 0:c792b17d9f78 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
juansal12 0:c792b17d9f78 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
juansal12 0:c792b17d9f78 367
juansal12 0:c792b17d9f78 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
juansal12 0:c792b17d9f78 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
juansal12 0:c792b17d9f78 370
juansal12 0:c792b17d9f78 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
juansal12 0:c792b17d9f78 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
juansal12 0:c792b17d9f78 373
juansal12 0:c792b17d9f78 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
juansal12 0:c792b17d9f78 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
juansal12 0:c792b17d9f78 376
juansal12 0:c792b17d9f78 377 #if (__VTOR_PRESENT == 1)
juansal12 0:c792b17d9f78 378 /* SCB Interrupt Control State Register Definitions */
juansal12 0:c792b17d9f78 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
juansal12 0:c792b17d9f78 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
juansal12 0:c792b17d9f78 381 #endif
juansal12 0:c792b17d9f78 382
juansal12 0:c792b17d9f78 383 /* SCB Application Interrupt and Reset Control Register Definitions */
juansal12 0:c792b17d9f78 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
juansal12 0:c792b17d9f78 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
juansal12 0:c792b17d9f78 386
juansal12 0:c792b17d9f78 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
juansal12 0:c792b17d9f78 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
juansal12 0:c792b17d9f78 389
juansal12 0:c792b17d9f78 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
juansal12 0:c792b17d9f78 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
juansal12 0:c792b17d9f78 392
juansal12 0:c792b17d9f78 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
juansal12 0:c792b17d9f78 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
juansal12 0:c792b17d9f78 395
juansal12 0:c792b17d9f78 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
juansal12 0:c792b17d9f78 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
juansal12 0:c792b17d9f78 398
juansal12 0:c792b17d9f78 399 /* SCB System Control Register Definitions */
juansal12 0:c792b17d9f78 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
juansal12 0:c792b17d9f78 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
juansal12 0:c792b17d9f78 402
juansal12 0:c792b17d9f78 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
juansal12 0:c792b17d9f78 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
juansal12 0:c792b17d9f78 405
juansal12 0:c792b17d9f78 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
juansal12 0:c792b17d9f78 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
juansal12 0:c792b17d9f78 408
juansal12 0:c792b17d9f78 409 /* SCB Configuration Control Register Definitions */
juansal12 0:c792b17d9f78 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
juansal12 0:c792b17d9f78 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
juansal12 0:c792b17d9f78 412
juansal12 0:c792b17d9f78 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
juansal12 0:c792b17d9f78 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
juansal12 0:c792b17d9f78 415
juansal12 0:c792b17d9f78 416 /* SCB System Handler Control and State Register Definitions */
juansal12 0:c792b17d9f78 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
juansal12 0:c792b17d9f78 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
juansal12 0:c792b17d9f78 419
juansal12 0:c792b17d9f78 420 /*@} end of group CMSIS_SCB */
juansal12 0:c792b17d9f78 421
juansal12 0:c792b17d9f78 422
juansal12 0:c792b17d9f78 423 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
juansal12 0:c792b17d9f78 425 \brief Type definitions for the System Timer Registers.
juansal12 0:c792b17d9f78 426 @{
juansal12 0:c792b17d9f78 427 */
juansal12 0:c792b17d9f78 428
juansal12 0:c792b17d9f78 429 /** \brief Structure type to access the System Timer (SysTick).
juansal12 0:c792b17d9f78 430 */
juansal12 0:c792b17d9f78 431 typedef struct
juansal12 0:c792b17d9f78 432 {
juansal12 0:c792b17d9f78 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
juansal12 0:c792b17d9f78 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
juansal12 0:c792b17d9f78 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
juansal12 0:c792b17d9f78 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
juansal12 0:c792b17d9f78 437 } SysTick_Type;
juansal12 0:c792b17d9f78 438
juansal12 0:c792b17d9f78 439 /* SysTick Control / Status Register Definitions */
juansal12 0:c792b17d9f78 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
juansal12 0:c792b17d9f78 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
juansal12 0:c792b17d9f78 442
juansal12 0:c792b17d9f78 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
juansal12 0:c792b17d9f78 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
juansal12 0:c792b17d9f78 445
juansal12 0:c792b17d9f78 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
juansal12 0:c792b17d9f78 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
juansal12 0:c792b17d9f78 448
juansal12 0:c792b17d9f78 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
juansal12 0:c792b17d9f78 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
juansal12 0:c792b17d9f78 451
juansal12 0:c792b17d9f78 452 /* SysTick Reload Register Definitions */
juansal12 0:c792b17d9f78 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
juansal12 0:c792b17d9f78 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
juansal12 0:c792b17d9f78 455
juansal12 0:c792b17d9f78 456 /* SysTick Current Register Definitions */
juansal12 0:c792b17d9f78 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
juansal12 0:c792b17d9f78 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
juansal12 0:c792b17d9f78 459
juansal12 0:c792b17d9f78 460 /* SysTick Calibration Register Definitions */
juansal12 0:c792b17d9f78 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
juansal12 0:c792b17d9f78 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
juansal12 0:c792b17d9f78 463
juansal12 0:c792b17d9f78 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
juansal12 0:c792b17d9f78 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
juansal12 0:c792b17d9f78 466
juansal12 0:c792b17d9f78 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
juansal12 0:c792b17d9f78 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
juansal12 0:c792b17d9f78 469
juansal12 0:c792b17d9f78 470 /*@} end of group CMSIS_SysTick */
juansal12 0:c792b17d9f78 471
juansal12 0:c792b17d9f78 472 #if (__MPU_PRESENT == 1)
juansal12 0:c792b17d9f78 473 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
juansal12 0:c792b17d9f78 475 \brief Type definitions for the Memory Protection Unit (MPU)
juansal12 0:c792b17d9f78 476 @{
juansal12 0:c792b17d9f78 477 */
juansal12 0:c792b17d9f78 478
juansal12 0:c792b17d9f78 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
juansal12 0:c792b17d9f78 480 */
juansal12 0:c792b17d9f78 481 typedef struct
juansal12 0:c792b17d9f78 482 {
juansal12 0:c792b17d9f78 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
juansal12 0:c792b17d9f78 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
juansal12 0:c792b17d9f78 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
juansal12 0:c792b17d9f78 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
juansal12 0:c792b17d9f78 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
juansal12 0:c792b17d9f78 488 } MPU_Type;
juansal12 0:c792b17d9f78 489
juansal12 0:c792b17d9f78 490 /* MPU Type Register */
juansal12 0:c792b17d9f78 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
juansal12 0:c792b17d9f78 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
juansal12 0:c792b17d9f78 493
juansal12 0:c792b17d9f78 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
juansal12 0:c792b17d9f78 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
juansal12 0:c792b17d9f78 496
juansal12 0:c792b17d9f78 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
juansal12 0:c792b17d9f78 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
juansal12 0:c792b17d9f78 499
juansal12 0:c792b17d9f78 500 /* MPU Control Register */
juansal12 0:c792b17d9f78 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
juansal12 0:c792b17d9f78 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
juansal12 0:c792b17d9f78 503
juansal12 0:c792b17d9f78 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
juansal12 0:c792b17d9f78 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
juansal12 0:c792b17d9f78 506
juansal12 0:c792b17d9f78 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
juansal12 0:c792b17d9f78 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
juansal12 0:c792b17d9f78 509
juansal12 0:c792b17d9f78 510 /* MPU Region Number Register */
juansal12 0:c792b17d9f78 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
juansal12 0:c792b17d9f78 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
juansal12 0:c792b17d9f78 513
juansal12 0:c792b17d9f78 514 /* MPU Region Base Address Register */
juansal12 0:c792b17d9f78 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
juansal12 0:c792b17d9f78 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
juansal12 0:c792b17d9f78 517
juansal12 0:c792b17d9f78 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
juansal12 0:c792b17d9f78 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
juansal12 0:c792b17d9f78 520
juansal12 0:c792b17d9f78 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
juansal12 0:c792b17d9f78 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
juansal12 0:c792b17d9f78 523
juansal12 0:c792b17d9f78 524 /* MPU Region Attribute and Size Register */
juansal12 0:c792b17d9f78 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
juansal12 0:c792b17d9f78 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
juansal12 0:c792b17d9f78 527
juansal12 0:c792b17d9f78 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
juansal12 0:c792b17d9f78 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
juansal12 0:c792b17d9f78 530
juansal12 0:c792b17d9f78 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
juansal12 0:c792b17d9f78 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
juansal12 0:c792b17d9f78 533
juansal12 0:c792b17d9f78 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
juansal12 0:c792b17d9f78 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
juansal12 0:c792b17d9f78 536
juansal12 0:c792b17d9f78 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
juansal12 0:c792b17d9f78 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
juansal12 0:c792b17d9f78 539
juansal12 0:c792b17d9f78 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
juansal12 0:c792b17d9f78 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
juansal12 0:c792b17d9f78 542
juansal12 0:c792b17d9f78 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
juansal12 0:c792b17d9f78 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
juansal12 0:c792b17d9f78 545
juansal12 0:c792b17d9f78 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
juansal12 0:c792b17d9f78 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
juansal12 0:c792b17d9f78 548
juansal12 0:c792b17d9f78 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
juansal12 0:c792b17d9f78 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
juansal12 0:c792b17d9f78 551
juansal12 0:c792b17d9f78 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
juansal12 0:c792b17d9f78 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
juansal12 0:c792b17d9f78 554
juansal12 0:c792b17d9f78 555 /*@} end of group CMSIS_MPU */
juansal12 0:c792b17d9f78 556 #endif
juansal12 0:c792b17d9f78 557
juansal12 0:c792b17d9f78 558
juansal12 0:c792b17d9f78 559 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
juansal12 0:c792b17d9f78 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
juansal12 0:c792b17d9f78 562 are only accessible over DAP and not via processor. Therefore
juansal12 0:c792b17d9f78 563 they are not covered by the Cortex-M0 header file.
juansal12 0:c792b17d9f78 564 @{
juansal12 0:c792b17d9f78 565 */
juansal12 0:c792b17d9f78 566 /*@} end of group CMSIS_CoreDebug */
juansal12 0:c792b17d9f78 567
juansal12 0:c792b17d9f78 568
juansal12 0:c792b17d9f78 569 /** \ingroup CMSIS_core_register
juansal12 0:c792b17d9f78 570 \defgroup CMSIS_core_base Core Definitions
juansal12 0:c792b17d9f78 571 \brief Definitions for base addresses, unions, and structures.
juansal12 0:c792b17d9f78 572 @{
juansal12 0:c792b17d9f78 573 */
juansal12 0:c792b17d9f78 574
juansal12 0:c792b17d9f78 575 /* Memory mapping of Cortex-M0+ Hardware */
juansal12 0:c792b17d9f78 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
juansal12 0:c792b17d9f78 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
juansal12 0:c792b17d9f78 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
juansal12 0:c792b17d9f78 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
juansal12 0:c792b17d9f78 580
juansal12 0:c792b17d9f78 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
juansal12 0:c792b17d9f78 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
juansal12 0:c792b17d9f78 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
juansal12 0:c792b17d9f78 584
juansal12 0:c792b17d9f78 585 #if (__MPU_PRESENT == 1)
juansal12 0:c792b17d9f78 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
juansal12 0:c792b17d9f78 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
juansal12 0:c792b17d9f78 588 #endif
juansal12 0:c792b17d9f78 589
juansal12 0:c792b17d9f78 590 /*@} */
juansal12 0:c792b17d9f78 591
juansal12 0:c792b17d9f78 592
juansal12 0:c792b17d9f78 593
juansal12 0:c792b17d9f78 594 /*******************************************************************************
juansal12 0:c792b17d9f78 595 * Hardware Abstraction Layer
juansal12 0:c792b17d9f78 596 Core Function Interface contains:
juansal12 0:c792b17d9f78 597 - Core NVIC Functions
juansal12 0:c792b17d9f78 598 - Core SysTick Functions
juansal12 0:c792b17d9f78 599 - Core Register Access Functions
juansal12 0:c792b17d9f78 600 ******************************************************************************/
juansal12 0:c792b17d9f78 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
juansal12 0:c792b17d9f78 602 */
juansal12 0:c792b17d9f78 603
juansal12 0:c792b17d9f78 604
juansal12 0:c792b17d9f78 605
juansal12 0:c792b17d9f78 606 /* ########################## NVIC functions #################################### */
juansal12 0:c792b17d9f78 607 /** \ingroup CMSIS_Core_FunctionInterface
juansal12 0:c792b17d9f78 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
juansal12 0:c792b17d9f78 609 \brief Functions that manage interrupts and exceptions via the NVIC.
juansal12 0:c792b17d9f78 610 @{
juansal12 0:c792b17d9f78 611 */
juansal12 0:c792b17d9f78 612
juansal12 0:c792b17d9f78 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
juansal12 0:c792b17d9f78 614 /* The following MACROS handle generation of the register offset and byte masks */
juansal12 0:c792b17d9f78 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
juansal12 0:c792b17d9f78 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
juansal12 0:c792b17d9f78 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
juansal12 0:c792b17d9f78 618
juansal12 0:c792b17d9f78 619
juansal12 0:c792b17d9f78 620 /** \brief Enable External Interrupt
juansal12 0:c792b17d9f78 621
juansal12 0:c792b17d9f78 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
juansal12 0:c792b17d9f78 623
juansal12 0:c792b17d9f78 624 \param [in] IRQn External interrupt number. Value cannot be negative.
juansal12 0:c792b17d9f78 625 */
juansal12 0:c792b17d9f78 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
juansal12 0:c792b17d9f78 627 {
juansal12 0:c792b17d9f78 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
juansal12 0:c792b17d9f78 629 }
juansal12 0:c792b17d9f78 630
juansal12 0:c792b17d9f78 631
juansal12 0:c792b17d9f78 632 /** \brief Disable External Interrupt
juansal12 0:c792b17d9f78 633
juansal12 0:c792b17d9f78 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
juansal12 0:c792b17d9f78 635
juansal12 0:c792b17d9f78 636 \param [in] IRQn External interrupt number. Value cannot be negative.
juansal12 0:c792b17d9f78 637 */
juansal12 0:c792b17d9f78 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
juansal12 0:c792b17d9f78 639 {
juansal12 0:c792b17d9f78 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
juansal12 0:c792b17d9f78 641 }
juansal12 0:c792b17d9f78 642
juansal12 0:c792b17d9f78 643
juansal12 0:c792b17d9f78 644 /** \brief Get Pending Interrupt
juansal12 0:c792b17d9f78 645
juansal12 0:c792b17d9f78 646 The function reads the pending register in the NVIC and returns the pending bit
juansal12 0:c792b17d9f78 647 for the specified interrupt.
juansal12 0:c792b17d9f78 648
juansal12 0:c792b17d9f78 649 \param [in] IRQn Interrupt number.
juansal12 0:c792b17d9f78 650
juansal12 0:c792b17d9f78 651 \return 0 Interrupt status is not pending.
juansal12 0:c792b17d9f78 652 \return 1 Interrupt status is pending.
juansal12 0:c792b17d9f78 653 */
juansal12 0:c792b17d9f78 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
juansal12 0:c792b17d9f78 655 {
juansal12 0:c792b17d9f78 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
juansal12 0:c792b17d9f78 657 }
juansal12 0:c792b17d9f78 658
juansal12 0:c792b17d9f78 659
juansal12 0:c792b17d9f78 660 /** \brief Set Pending Interrupt
juansal12 0:c792b17d9f78 661
juansal12 0:c792b17d9f78 662 The function sets the pending bit of an external interrupt.
juansal12 0:c792b17d9f78 663
juansal12 0:c792b17d9f78 664 \param [in] IRQn Interrupt number. Value cannot be negative.
juansal12 0:c792b17d9f78 665 */
juansal12 0:c792b17d9f78 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
juansal12 0:c792b17d9f78 667 {
juansal12 0:c792b17d9f78 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
juansal12 0:c792b17d9f78 669 }
juansal12 0:c792b17d9f78 670
juansal12 0:c792b17d9f78 671
juansal12 0:c792b17d9f78 672 /** \brief Clear Pending Interrupt
juansal12 0:c792b17d9f78 673
juansal12 0:c792b17d9f78 674 The function clears the pending bit of an external interrupt.
juansal12 0:c792b17d9f78 675
juansal12 0:c792b17d9f78 676 \param [in] IRQn External interrupt number. Value cannot be negative.
juansal12 0:c792b17d9f78 677 */
juansal12 0:c792b17d9f78 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
juansal12 0:c792b17d9f78 679 {
juansal12 0:c792b17d9f78 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
juansal12 0:c792b17d9f78 681 }
juansal12 0:c792b17d9f78 682
juansal12 0:c792b17d9f78 683
juansal12 0:c792b17d9f78 684 /** \brief Set Interrupt Priority
juansal12 0:c792b17d9f78 685
juansal12 0:c792b17d9f78 686 The function sets the priority of an interrupt.
juansal12 0:c792b17d9f78 687
juansal12 0:c792b17d9f78 688 \note The priority cannot be set for every core interrupt.
juansal12 0:c792b17d9f78 689
juansal12 0:c792b17d9f78 690 \param [in] IRQn Interrupt number.
juansal12 0:c792b17d9f78 691 \param [in] priority Priority to set.
juansal12 0:c792b17d9f78 692 */
juansal12 0:c792b17d9f78 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
juansal12 0:c792b17d9f78 694 {
juansal12 0:c792b17d9f78 695 if(IRQn < 0) {
juansal12 0:c792b17d9f78 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
juansal12 0:c792b17d9f78 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
juansal12 0:c792b17d9f78 698 else {
juansal12 0:c792b17d9f78 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
juansal12 0:c792b17d9f78 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
juansal12 0:c792b17d9f78 701 }
juansal12 0:c792b17d9f78 702
juansal12 0:c792b17d9f78 703
juansal12 0:c792b17d9f78 704 /** \brief Get Interrupt Priority
juansal12 0:c792b17d9f78 705
juansal12 0:c792b17d9f78 706 The function reads the priority of an interrupt. The interrupt
juansal12 0:c792b17d9f78 707 number can be positive to specify an external (device specific)
juansal12 0:c792b17d9f78 708 interrupt, or negative to specify an internal (core) interrupt.
juansal12 0:c792b17d9f78 709
juansal12 0:c792b17d9f78 710
juansal12 0:c792b17d9f78 711 \param [in] IRQn Interrupt number.
juansal12 0:c792b17d9f78 712 \return Interrupt Priority. Value is aligned automatically to the implemented
juansal12 0:c792b17d9f78 713 priority bits of the microcontroller.
juansal12 0:c792b17d9f78 714 */
juansal12 0:c792b17d9f78 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
juansal12 0:c792b17d9f78 716 {
juansal12 0:c792b17d9f78 717
juansal12 0:c792b17d9f78 718 if(IRQn < 0) {
juansal12 0:c792b17d9f78 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
juansal12 0:c792b17d9f78 720 else {
juansal12 0:c792b17d9f78 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
juansal12 0:c792b17d9f78 722 }
juansal12 0:c792b17d9f78 723
juansal12 0:c792b17d9f78 724
juansal12 0:c792b17d9f78 725 /** \brief System Reset
juansal12 0:c792b17d9f78 726
juansal12 0:c792b17d9f78 727 The function initiates a system reset request to reset the MCU.
juansal12 0:c792b17d9f78 728 */
juansal12 0:c792b17d9f78 729 __STATIC_INLINE void NVIC_SystemReset(void)
juansal12 0:c792b17d9f78 730 {
juansal12 0:c792b17d9f78 731 __DSB(); /* Ensure all outstanding memory accesses included
juansal12 0:c792b17d9f78 732 buffered write are completed before reset */
juansal12 0:c792b17d9f78 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
juansal12 0:c792b17d9f78 734 SCB_AIRCR_SYSRESETREQ_Msk);
juansal12 0:c792b17d9f78 735 __DSB(); /* Ensure completion of memory access */
juansal12 0:c792b17d9f78 736 while(1); /* wait until reset */
juansal12 0:c792b17d9f78 737 }
juansal12 0:c792b17d9f78 738
juansal12 0:c792b17d9f78 739 /*@} end of CMSIS_Core_NVICFunctions */
juansal12 0:c792b17d9f78 740
juansal12 0:c792b17d9f78 741
juansal12 0:c792b17d9f78 742
juansal12 0:c792b17d9f78 743 /* ################################## SysTick function ############################################ */
juansal12 0:c792b17d9f78 744 /** \ingroup CMSIS_Core_FunctionInterface
juansal12 0:c792b17d9f78 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
juansal12 0:c792b17d9f78 746 \brief Functions that configure the System.
juansal12 0:c792b17d9f78 747 @{
juansal12 0:c792b17d9f78 748 */
juansal12 0:c792b17d9f78 749
juansal12 0:c792b17d9f78 750 #if (__Vendor_SysTickConfig == 0)
juansal12 0:c792b17d9f78 751
juansal12 0:c792b17d9f78 752 /** \brief System Tick Configuration
juansal12 0:c792b17d9f78 753
juansal12 0:c792b17d9f78 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
juansal12 0:c792b17d9f78 755 Counter is in free running mode to generate periodic interrupts.
juansal12 0:c792b17d9f78 756
juansal12 0:c792b17d9f78 757 \param [in] ticks Number of ticks between two interrupts.
juansal12 0:c792b17d9f78 758
juansal12 0:c792b17d9f78 759 \return 0 Function succeeded.
juansal12 0:c792b17d9f78 760 \return 1 Function failed.
juansal12 0:c792b17d9f78 761
juansal12 0:c792b17d9f78 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
juansal12 0:c792b17d9f78 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
juansal12 0:c792b17d9f78 764 must contain a vendor-specific implementation of this function.
juansal12 0:c792b17d9f78 765
juansal12 0:c792b17d9f78 766 */
juansal12 0:c792b17d9f78 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
juansal12 0:c792b17d9f78 768 {
juansal12 0:c792b17d9f78 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
juansal12 0:c792b17d9f78 770
juansal12 0:c792b17d9f78 771 SysTick->LOAD = ticks - 1; /* set reload register */
juansal12 0:c792b17d9f78 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
juansal12 0:c792b17d9f78 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
juansal12 0:c792b17d9f78 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
juansal12 0:c792b17d9f78 775 SysTick_CTRL_TICKINT_Msk |
juansal12 0:c792b17d9f78 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
juansal12 0:c792b17d9f78 777 return (0); /* Function successful */
juansal12 0:c792b17d9f78 778 }
juansal12 0:c792b17d9f78 779
juansal12 0:c792b17d9f78 780 #endif
juansal12 0:c792b17d9f78 781
juansal12 0:c792b17d9f78 782 /*@} end of CMSIS_Core_SysTickFunctions */
juansal12 0:c792b17d9f78 783
juansal12 0:c792b17d9f78 784
juansal12 0:c792b17d9f78 785
juansal12 0:c792b17d9f78 786
juansal12 0:c792b17d9f78 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
juansal12 0:c792b17d9f78 788
juansal12 0:c792b17d9f78 789 #endif /* __CMSIS_GENERIC */
juansal12 0:c792b17d9f78 790
juansal12 0:c792b17d9f78 791 #ifdef __cplusplus
juansal12 0:c792b17d9f78 792 }
juansal12 0:c792b17d9f78 793 #endif