Juan Salazar / sofi7

test

Dependents:   robotic_fish_6

TARGET_LPC1768/core_caFunc.h@0:c792b17d9f78, 2021-12-03 (annotated)

Committer:
juansal12
Date:
Fri Dec 03 23:00:34 2021 +0000
Revision:
0:c792b17d9f78
uploaded sofi code ;

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juansal12 0:c792b17d9f78 1 /**************************************************************************//**
juansal12 0:c792b17d9f78 2 * @file core_caFunc.h
juansal12 0:c792b17d9f78 3 * @brief CMSIS Cortex-A Core Function Access Header File
juansal12 0:c792b17d9f78 4 * @version V3.10
juansal12 0:c792b17d9f78 5 * @date 9 May 2013
juansal12 0:c792b17d9f78 6 *
juansal12 0:c792b17d9f78 7 * @note
juansal12 0:c792b17d9f78 8 *
juansal12 0:c792b17d9f78 9 ******************************************************************************/
juansal12 0:c792b17d9f78 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
juansal12 0:c792b17d9f78 11
juansal12 0:c792b17d9f78 12 All rights reserved.
juansal12 0:c792b17d9f78 13 Redistribution and use in source and binary forms, with or without
juansal12 0:c792b17d9f78 14 modification, are permitted provided that the following conditions are met:
juansal12 0:c792b17d9f78 15 - Redistributions of source code must retain the above copyright
juansal12 0:c792b17d9f78 16 notice, this list of conditions and the following disclaimer.
juansal12 0:c792b17d9f78 17 - Redistributions in binary form must reproduce the above copyright
juansal12 0:c792b17d9f78 18 notice, this list of conditions and the following disclaimer in the
juansal12 0:c792b17d9f78 19 documentation and/or other materials provided with the distribution.
juansal12 0:c792b17d9f78 20 - Neither the name of ARM nor the names of its contributors may be used
juansal12 0:c792b17d9f78 21 to endorse or promote products derived from this software without
juansal12 0:c792b17d9f78 22 specific prior written permission.
juansal12 0:c792b17d9f78 23 *
juansal12 0:c792b17d9f78 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
juansal12 0:c792b17d9f78 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
juansal12 0:c792b17d9f78 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
juansal12 0:c792b17d9f78 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
juansal12 0:c792b17d9f78 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
juansal12 0:c792b17d9f78 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
juansal12 0:c792b17d9f78 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
juansal12 0:c792b17d9f78 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
juansal12 0:c792b17d9f78 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
juansal12 0:c792b17d9f78 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
juansal12 0:c792b17d9f78 34 POSSIBILITY OF SUCH DAMAGE.
juansal12 0:c792b17d9f78 35 ---------------------------------------------------------------------------*/
juansal12 0:c792b17d9f78 36
juansal12 0:c792b17d9f78 37
juansal12 0:c792b17d9f78 38 #ifndef __CORE_CAFUNC_H__
juansal12 0:c792b17d9f78 39 #define __CORE_CAFUNC_H__
juansal12 0:c792b17d9f78 40
juansal12 0:c792b17d9f78 41
juansal12 0:c792b17d9f78 42 /* ########################### Core Function Access ########################### */
juansal12 0:c792b17d9f78 43 /** \ingroup CMSIS_Core_FunctionInterface
juansal12 0:c792b17d9f78 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
juansal12 0:c792b17d9f78 45 @{
juansal12 0:c792b17d9f78 46 */
juansal12 0:c792b17d9f78 47
juansal12 0:c792b17d9f78 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
juansal12 0:c792b17d9f78 49 /* ARM armcc specific functions */
juansal12 0:c792b17d9f78 50
juansal12 0:c792b17d9f78 51 #if (__ARMCC_VERSION < 400677)
juansal12 0:c792b17d9f78 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
juansal12 0:c792b17d9f78 53 #endif
juansal12 0:c792b17d9f78 54
juansal12 0:c792b17d9f78 55 #define MODE_USR 0x10
juansal12 0:c792b17d9f78 56 #define MODE_FIQ 0x11
juansal12 0:c792b17d9f78 57 #define MODE_IRQ 0x12
juansal12 0:c792b17d9f78 58 #define MODE_SVC 0x13
juansal12 0:c792b17d9f78 59 #define MODE_MON 0x16
juansal12 0:c792b17d9f78 60 #define MODE_ABT 0x17
juansal12 0:c792b17d9f78 61 #define MODE_HYP 0x1A
juansal12 0:c792b17d9f78 62 #define MODE_UND 0x1B
juansal12 0:c792b17d9f78 63 #define MODE_SYS 0x1F
juansal12 0:c792b17d9f78 64
juansal12 0:c792b17d9f78 65 /** \brief Get APSR Register
juansal12 0:c792b17d9f78 66
juansal12 0:c792b17d9f78 67 This function returns the content of the APSR Register.
juansal12 0:c792b17d9f78 68
juansal12 0:c792b17d9f78 69 \return APSR Register value
juansal12 0:c792b17d9f78 70 */
juansal12 0:c792b17d9f78 71 __STATIC_INLINE uint32_t __get_APSR(void)
juansal12 0:c792b17d9f78 72 {
juansal12 0:c792b17d9f78 73 register uint32_t __regAPSR __ASM("apsr");
juansal12 0:c792b17d9f78 74 return(__regAPSR);
juansal12 0:c792b17d9f78 75 }
juansal12 0:c792b17d9f78 76
juansal12 0:c792b17d9f78 77
juansal12 0:c792b17d9f78 78 /** \brief Get CPSR Register
juansal12 0:c792b17d9f78 79
juansal12 0:c792b17d9f78 80 This function returns the content of the CPSR Register.
juansal12 0:c792b17d9f78 81
juansal12 0:c792b17d9f78 82 \return CPSR Register value
juansal12 0:c792b17d9f78 83 */
juansal12 0:c792b17d9f78 84 __STATIC_INLINE uint32_t __get_CPSR(void)
juansal12 0:c792b17d9f78 85 {
juansal12 0:c792b17d9f78 86 register uint32_t __regCPSR __ASM("cpsr");
juansal12 0:c792b17d9f78 87 return(__regCPSR);
juansal12 0:c792b17d9f78 88 }
juansal12 0:c792b17d9f78 89
juansal12 0:c792b17d9f78 90 /** \brief Set Stack Pointer
juansal12 0:c792b17d9f78 91
juansal12 0:c792b17d9f78 92 This function assigns the given value to the current stack pointer.
juansal12 0:c792b17d9f78 93
juansal12 0:c792b17d9f78 94 \param [in] topOfStack Stack Pointer value to set
juansal12 0:c792b17d9f78 95 */
juansal12 0:c792b17d9f78 96 register uint32_t __regSP __ASM("sp");
juansal12 0:c792b17d9f78 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
juansal12 0:c792b17d9f78 98 {
juansal12 0:c792b17d9f78 99 __regSP = topOfStack;
juansal12 0:c792b17d9f78 100 }
juansal12 0:c792b17d9f78 101
juansal12 0:c792b17d9f78 102
juansal12 0:c792b17d9f78 103 /** \brief Get link register
juansal12 0:c792b17d9f78 104
juansal12 0:c792b17d9f78 105 This function returns the value of the link register
juansal12 0:c792b17d9f78 106
juansal12 0:c792b17d9f78 107 \return Value of link register
juansal12 0:c792b17d9f78 108 */
juansal12 0:c792b17d9f78 109 register uint32_t __reglr __ASM("lr");
juansal12 0:c792b17d9f78 110 __STATIC_INLINE uint32_t __get_LR(void)
juansal12 0:c792b17d9f78 111 {
juansal12 0:c792b17d9f78 112 return(__reglr);
juansal12 0:c792b17d9f78 113 }
juansal12 0:c792b17d9f78 114
juansal12 0:c792b17d9f78 115 /** \brief Set link register
juansal12 0:c792b17d9f78 116
juansal12 0:c792b17d9f78 117 This function sets the value of the link register
juansal12 0:c792b17d9f78 118
juansal12 0:c792b17d9f78 119 \param [in] lr LR value to set
juansal12 0:c792b17d9f78 120 */
juansal12 0:c792b17d9f78 121 __STATIC_INLINE void __set_LR(uint32_t lr)
juansal12 0:c792b17d9f78 122 {
juansal12 0:c792b17d9f78 123 __reglr = lr;
juansal12 0:c792b17d9f78 124 }
juansal12 0:c792b17d9f78 125
juansal12 0:c792b17d9f78 126 /** \brief Set Process Stack Pointer
juansal12 0:c792b17d9f78 127
juansal12 0:c792b17d9f78 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
juansal12 0:c792b17d9f78 129
juansal12 0:c792b17d9f78 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
juansal12 0:c792b17d9f78 131 */
juansal12 0:c792b17d9f78 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
juansal12 0:c792b17d9f78 133 {
juansal12 0:c792b17d9f78 134 ARM
juansal12 0:c792b17d9f78 135 PRESERVE8
juansal12 0:c792b17d9f78 136
juansal12 0:c792b17d9f78 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
juansal12 0:c792b17d9f78 138 MRS R1, CPSR
juansal12 0:c792b17d9f78 139 CPS #MODE_SYS ;no effect in USR mode
juansal12 0:c792b17d9f78 140 MOV SP, R0
juansal12 0:c792b17d9f78 141 MSR CPSR_c, R1 ;no effect in USR mode
juansal12 0:c792b17d9f78 142 ISB
juansal12 0:c792b17d9f78 143 BX LR
juansal12 0:c792b17d9f78 144
juansal12 0:c792b17d9f78 145 }
juansal12 0:c792b17d9f78 146
juansal12 0:c792b17d9f78 147 /** \brief Set User Mode
juansal12 0:c792b17d9f78 148
juansal12 0:c792b17d9f78 149 This function changes the processor state to User Mode
juansal12 0:c792b17d9f78 150
juansal12 0:c792b17d9f78 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
juansal12 0:c792b17d9f78 152 */
juansal12 0:c792b17d9f78 153 __STATIC_ASM void __set_CPS_USR(void)
juansal12 0:c792b17d9f78 154 {
juansal12 0:c792b17d9f78 155 ARM
juansal12 0:c792b17d9f78 156
juansal12 0:c792b17d9f78 157 CPS #MODE_USR
juansal12 0:c792b17d9f78 158 BX LR
juansal12 0:c792b17d9f78 159 }
juansal12 0:c792b17d9f78 160
juansal12 0:c792b17d9f78 161
juansal12 0:c792b17d9f78 162 /** \brief Enable FIQ
juansal12 0:c792b17d9f78 163
juansal12 0:c792b17d9f78 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
juansal12 0:c792b17d9f78 165 Can only be executed in Privileged modes.
juansal12 0:c792b17d9f78 166 */
juansal12 0:c792b17d9f78 167 #define __enable_fault_irq __enable_fiq
juansal12 0:c792b17d9f78 168
juansal12 0:c792b17d9f78 169
juansal12 0:c792b17d9f78 170 /** \brief Disable FIQ
juansal12 0:c792b17d9f78 171
juansal12 0:c792b17d9f78 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
juansal12 0:c792b17d9f78 173 Can only be executed in Privileged modes.
juansal12 0:c792b17d9f78 174 */
juansal12 0:c792b17d9f78 175 #define __disable_fault_irq __disable_fiq
juansal12 0:c792b17d9f78 176
juansal12 0:c792b17d9f78 177
juansal12 0:c792b17d9f78 178 /** \brief Get FPSCR
juansal12 0:c792b17d9f78 179
juansal12 0:c792b17d9f78 180 This function returns the current value of the Floating Point Status/Control register.
juansal12 0:c792b17d9f78 181
juansal12 0:c792b17d9f78 182 \return Floating Point Status/Control register value
juansal12 0:c792b17d9f78 183 */
juansal12 0:c792b17d9f78 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
juansal12 0:c792b17d9f78 185 {
juansal12 0:c792b17d9f78 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
juansal12 0:c792b17d9f78 187 register uint32_t __regfpscr __ASM("fpscr");
juansal12 0:c792b17d9f78 188 return(__regfpscr);
juansal12 0:c792b17d9f78 189 #else
juansal12 0:c792b17d9f78 190 return(0);
juansal12 0:c792b17d9f78 191 #endif
juansal12 0:c792b17d9f78 192 }
juansal12 0:c792b17d9f78 193
juansal12 0:c792b17d9f78 194
juansal12 0:c792b17d9f78 195 /** \brief Set FPSCR
juansal12 0:c792b17d9f78 196
juansal12 0:c792b17d9f78 197 This function assigns the given value to the Floating Point Status/Control register.
juansal12 0:c792b17d9f78 198
juansal12 0:c792b17d9f78 199 \param [in] fpscr Floating Point Status/Control value to set
juansal12 0:c792b17d9f78 200 */
juansal12 0:c792b17d9f78 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
juansal12 0:c792b17d9f78 202 {
juansal12 0:c792b17d9f78 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
juansal12 0:c792b17d9f78 204 register uint32_t __regfpscr __ASM("fpscr");
juansal12 0:c792b17d9f78 205 __regfpscr = (fpscr);
juansal12 0:c792b17d9f78 206 #endif
juansal12 0:c792b17d9f78 207 }
juansal12 0:c792b17d9f78 208
juansal12 0:c792b17d9f78 209 /** \brief Get FPEXC
juansal12 0:c792b17d9f78 210
juansal12 0:c792b17d9f78 211 This function returns the current value of the Floating Point Exception Control register.
juansal12 0:c792b17d9f78 212
juansal12 0:c792b17d9f78 213 \return Floating Point Exception Control register value
juansal12 0:c792b17d9f78 214 */
juansal12 0:c792b17d9f78 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
juansal12 0:c792b17d9f78 216 {
juansal12 0:c792b17d9f78 217 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 218 register uint32_t __regfpexc __ASM("fpexc");
juansal12 0:c792b17d9f78 219 return(__regfpexc);
juansal12 0:c792b17d9f78 220 #else
juansal12 0:c792b17d9f78 221 return(0);
juansal12 0:c792b17d9f78 222 #endif
juansal12 0:c792b17d9f78 223 }
juansal12 0:c792b17d9f78 224
juansal12 0:c792b17d9f78 225
juansal12 0:c792b17d9f78 226 /** \brief Set FPEXC
juansal12 0:c792b17d9f78 227
juansal12 0:c792b17d9f78 228 This function assigns the given value to the Floating Point Exception Control register.
juansal12 0:c792b17d9f78 229
juansal12 0:c792b17d9f78 230 \param [in] fpscr Floating Point Exception Control value to set
juansal12 0:c792b17d9f78 231 */
juansal12 0:c792b17d9f78 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
juansal12 0:c792b17d9f78 233 {
juansal12 0:c792b17d9f78 234 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 235 register uint32_t __regfpexc __ASM("fpexc");
juansal12 0:c792b17d9f78 236 __regfpexc = (fpexc);
juansal12 0:c792b17d9f78 237 #endif
juansal12 0:c792b17d9f78 238 }
juansal12 0:c792b17d9f78 239
juansal12 0:c792b17d9f78 240 /** \brief Get CPACR
juansal12 0:c792b17d9f78 241
juansal12 0:c792b17d9f78 242 This function returns the current value of the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 243
juansal12 0:c792b17d9f78 244 \return Coprocessor Access Control register value
juansal12 0:c792b17d9f78 245 */
juansal12 0:c792b17d9f78 246 __STATIC_INLINE uint32_t __get_CPACR(void)
juansal12 0:c792b17d9f78 247 {
juansal12 0:c792b17d9f78 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
juansal12 0:c792b17d9f78 249 return __regCPACR;
juansal12 0:c792b17d9f78 250 }
juansal12 0:c792b17d9f78 251
juansal12 0:c792b17d9f78 252 /** \brief Set CPACR
juansal12 0:c792b17d9f78 253
juansal12 0:c792b17d9f78 254 This function assigns the given value to the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 255
juansal12 0:c792b17d9f78 256 \param [in] cpacr Coporcessor Acccess Control value to set
juansal12 0:c792b17d9f78 257 */
juansal12 0:c792b17d9f78 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
juansal12 0:c792b17d9f78 259 {
juansal12 0:c792b17d9f78 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
juansal12 0:c792b17d9f78 261 __regCPACR = cpacr;
juansal12 0:c792b17d9f78 262 __ISB();
juansal12 0:c792b17d9f78 263 }
juansal12 0:c792b17d9f78 264
juansal12 0:c792b17d9f78 265 /** \brief Get CBAR
juansal12 0:c792b17d9f78 266
juansal12 0:c792b17d9f78 267 This function returns the value of the Configuration Base Address register.
juansal12 0:c792b17d9f78 268
juansal12 0:c792b17d9f78 269 \return Configuration Base Address register value
juansal12 0:c792b17d9f78 270 */
juansal12 0:c792b17d9f78 271 __STATIC_INLINE uint32_t __get_CBAR() {
juansal12 0:c792b17d9f78 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
juansal12 0:c792b17d9f78 273 return(__regCBAR);
juansal12 0:c792b17d9f78 274 }
juansal12 0:c792b17d9f78 275
juansal12 0:c792b17d9f78 276 /** \brief Get TTBR0
juansal12 0:c792b17d9f78 277
juansal12 0:c792b17d9f78 278 This function returns the value of the Configuration Base Address register.
juansal12 0:c792b17d9f78 279
juansal12 0:c792b17d9f78 280 \return Translation Table Base Register 0 value
juansal12 0:c792b17d9f78 281 */
juansal12 0:c792b17d9f78 282 __STATIC_INLINE uint32_t __get_TTBR0() {
juansal12 0:c792b17d9f78 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
juansal12 0:c792b17d9f78 284 return(__regTTBR0);
juansal12 0:c792b17d9f78 285 }
juansal12 0:c792b17d9f78 286
juansal12 0:c792b17d9f78 287 /** \brief Set TTBR0
juansal12 0:c792b17d9f78 288
juansal12 0:c792b17d9f78 289 This function assigns the given value to the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 290
juansal12 0:c792b17d9f78 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
juansal12 0:c792b17d9f78 292 */
juansal12 0:c792b17d9f78 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
juansal12 0:c792b17d9f78 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
juansal12 0:c792b17d9f78 295 __regTTBR0 = ttbr0;
juansal12 0:c792b17d9f78 296 __ISB();
juansal12 0:c792b17d9f78 297 }
juansal12 0:c792b17d9f78 298
juansal12 0:c792b17d9f78 299 /** \brief Get DACR
juansal12 0:c792b17d9f78 300
juansal12 0:c792b17d9f78 301 This function returns the value of the Domain Access Control Register.
juansal12 0:c792b17d9f78 302
juansal12 0:c792b17d9f78 303 \return Domain Access Control Register value
juansal12 0:c792b17d9f78 304 */
juansal12 0:c792b17d9f78 305 __STATIC_INLINE uint32_t __get_DACR() {
juansal12 0:c792b17d9f78 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
juansal12 0:c792b17d9f78 307 return(__regDACR);
juansal12 0:c792b17d9f78 308 }
juansal12 0:c792b17d9f78 309
juansal12 0:c792b17d9f78 310 /** \brief Set DACR
juansal12 0:c792b17d9f78 311
juansal12 0:c792b17d9f78 312 This function assigns the given value to the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 313
juansal12 0:c792b17d9f78 314 \param [in] dacr Domain Access Control Register value to set
juansal12 0:c792b17d9f78 315 */
juansal12 0:c792b17d9f78 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
juansal12 0:c792b17d9f78 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
juansal12 0:c792b17d9f78 318 __regDACR = dacr;
juansal12 0:c792b17d9f78 319 __ISB();
juansal12 0:c792b17d9f78 320 }
juansal12 0:c792b17d9f78 321
juansal12 0:c792b17d9f78 322 /******************************** Cache and BTAC enable ****************************************************/
juansal12 0:c792b17d9f78 323
juansal12 0:c792b17d9f78 324 /** \brief Set SCTLR
juansal12 0:c792b17d9f78 325
juansal12 0:c792b17d9f78 326 This function assigns the given value to the System Control Register.
juansal12 0:c792b17d9f78 327
juansal12 0:c792b17d9f78 328 \param [in] sctlr System Control Register, value to set
juansal12 0:c792b17d9f78 329 */
juansal12 0:c792b17d9f78 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
juansal12 0:c792b17d9f78 331 {
juansal12 0:c792b17d9f78 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
juansal12 0:c792b17d9f78 333 __regSCTLR = sctlr;
juansal12 0:c792b17d9f78 334 }
juansal12 0:c792b17d9f78 335
juansal12 0:c792b17d9f78 336 /** \brief Get SCTLR
juansal12 0:c792b17d9f78 337
juansal12 0:c792b17d9f78 338 This function returns the value of the System Control Register.
juansal12 0:c792b17d9f78 339
juansal12 0:c792b17d9f78 340 \return System Control Register value
juansal12 0:c792b17d9f78 341 */
juansal12 0:c792b17d9f78 342 __STATIC_INLINE uint32_t __get_SCTLR() {
juansal12 0:c792b17d9f78 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
juansal12 0:c792b17d9f78 344 return(__regSCTLR);
juansal12 0:c792b17d9f78 345 }
juansal12 0:c792b17d9f78 346
juansal12 0:c792b17d9f78 347 /** \brief Enable Caches
juansal12 0:c792b17d9f78 348
juansal12 0:c792b17d9f78 349 Enable Caches
juansal12 0:c792b17d9f78 350 */
juansal12 0:c792b17d9f78 351 __STATIC_INLINE void __enable_caches(void) {
juansal12 0:c792b17d9f78 352 // Set I bit 12 to enable I Cache
juansal12 0:c792b17d9f78 353 // Set C bit 2 to enable D Cache
juansal12 0:c792b17d9f78 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
juansal12 0:c792b17d9f78 355 }
juansal12 0:c792b17d9f78 356
juansal12 0:c792b17d9f78 357 /** \brief Disable Caches
juansal12 0:c792b17d9f78 358
juansal12 0:c792b17d9f78 359 Disable Caches
juansal12 0:c792b17d9f78 360 */
juansal12 0:c792b17d9f78 361 __STATIC_INLINE void __disable_caches(void) {
juansal12 0:c792b17d9f78 362 // Clear I bit 12 to disable I Cache
juansal12 0:c792b17d9f78 363 // Clear C bit 2 to disable D Cache
juansal12 0:c792b17d9f78 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
juansal12 0:c792b17d9f78 365 __ISB();
juansal12 0:c792b17d9f78 366 }
juansal12 0:c792b17d9f78 367
juansal12 0:c792b17d9f78 368 /** \brief Enable BTAC
juansal12 0:c792b17d9f78 369
juansal12 0:c792b17d9f78 370 Enable BTAC
juansal12 0:c792b17d9f78 371 */
juansal12 0:c792b17d9f78 372 __STATIC_INLINE void __enable_btac(void) {
juansal12 0:c792b17d9f78 373 // Set Z bit 11 to enable branch prediction
juansal12 0:c792b17d9f78 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
juansal12 0:c792b17d9f78 375 __ISB();
juansal12 0:c792b17d9f78 376 }
juansal12 0:c792b17d9f78 377
juansal12 0:c792b17d9f78 378 /** \brief Disable BTAC
juansal12 0:c792b17d9f78 379
juansal12 0:c792b17d9f78 380 Disable BTAC
juansal12 0:c792b17d9f78 381 */
juansal12 0:c792b17d9f78 382 __STATIC_INLINE void __disable_btac(void) {
juansal12 0:c792b17d9f78 383 // Clear Z bit 11 to disable branch prediction
juansal12 0:c792b17d9f78 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
juansal12 0:c792b17d9f78 385 }
juansal12 0:c792b17d9f78 386
juansal12 0:c792b17d9f78 387
juansal12 0:c792b17d9f78 388 /** \brief Enable MMU
juansal12 0:c792b17d9f78 389
juansal12 0:c792b17d9f78 390 Enable MMU
juansal12 0:c792b17d9f78 391 */
juansal12 0:c792b17d9f78 392 __STATIC_INLINE void __enable_mmu(void) {
juansal12 0:c792b17d9f78 393 // Set M bit 0 to enable the MMU
juansal12 0:c792b17d9f78 394 // Set AFE bit to enable simplified access permissions model
juansal12 0:c792b17d9f78 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
juansal12 0:c792b17d9f78 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
juansal12 0:c792b17d9f78 397 __ISB();
juansal12 0:c792b17d9f78 398 }
juansal12 0:c792b17d9f78 399
juansal12 0:c792b17d9f78 400 /** \brief Enable MMU
juansal12 0:c792b17d9f78 401
juansal12 0:c792b17d9f78 402 Enable MMU
juansal12 0:c792b17d9f78 403 */
juansal12 0:c792b17d9f78 404 __STATIC_INLINE void __disable_mmu(void) {
juansal12 0:c792b17d9f78 405 // Clear M bit 0 to disable the MMU
juansal12 0:c792b17d9f78 406 __set_SCTLR( __get_SCTLR() & ~1);
juansal12 0:c792b17d9f78 407 __ISB();
juansal12 0:c792b17d9f78 408 }
juansal12 0:c792b17d9f78 409
juansal12 0:c792b17d9f78 410 /******************************** TLB maintenance operations ************************************************/
juansal12 0:c792b17d9f78 411 /** \brief Invalidate the whole tlb
juansal12 0:c792b17d9f78 412
juansal12 0:c792b17d9f78 413 TLBIALL. Invalidate the whole tlb
juansal12 0:c792b17d9f78 414 */
juansal12 0:c792b17d9f78 415
juansal12 0:c792b17d9f78 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
juansal12 0:c792b17d9f78 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
juansal12 0:c792b17d9f78 418 __TLBIALL = 0;
juansal12 0:c792b17d9f78 419 __DSB();
juansal12 0:c792b17d9f78 420 __ISB();
juansal12 0:c792b17d9f78 421 }
juansal12 0:c792b17d9f78 422
juansal12 0:c792b17d9f78 423 /******************************** BTB maintenance operations ************************************************/
juansal12 0:c792b17d9f78 424 /** \brief Invalidate entire branch predictor array
juansal12 0:c792b17d9f78 425
juansal12 0:c792b17d9f78 426 BPIALL. Branch Predictor Invalidate All.
juansal12 0:c792b17d9f78 427 */
juansal12 0:c792b17d9f78 428
juansal12 0:c792b17d9f78 429 __STATIC_INLINE void __v7_inv_btac(void) {
juansal12 0:c792b17d9f78 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
juansal12 0:c792b17d9f78 431 __BPIALL = 0;
juansal12 0:c792b17d9f78 432 __DSB(); //ensure completion of the invalidation
juansal12 0:c792b17d9f78 433 __ISB(); //ensure instruction fetch path sees new state
juansal12 0:c792b17d9f78 434 }
juansal12 0:c792b17d9f78 435
juansal12 0:c792b17d9f78 436
juansal12 0:c792b17d9f78 437 /******************************** L1 cache operations ******************************************************/
juansal12 0:c792b17d9f78 438
juansal12 0:c792b17d9f78 439 /** \brief Invalidate the whole I$
juansal12 0:c792b17d9f78 440
juansal12 0:c792b17d9f78 441 ICIALLU. Instruction Cache Invalidate All to PoU
juansal12 0:c792b17d9f78 442 */
juansal12 0:c792b17d9f78 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
juansal12 0:c792b17d9f78 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
juansal12 0:c792b17d9f78 445 __ICIALLU = 0;
juansal12 0:c792b17d9f78 446 __DSB(); //ensure completion of the invalidation
juansal12 0:c792b17d9f78 447 __ISB(); //ensure instruction fetch path sees new I cache state
juansal12 0:c792b17d9f78 448 }
juansal12 0:c792b17d9f78 449
juansal12 0:c792b17d9f78 450 /** \brief Clean D$ by MVA
juansal12 0:c792b17d9f78 451
juansal12 0:c792b17d9f78 452 DCCMVAC. Data cache clean by MVA to PoC
juansal12 0:c792b17d9f78 453 */
juansal12 0:c792b17d9f78 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
juansal12 0:c792b17d9f78 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
juansal12 0:c792b17d9f78 456 __DCCMVAC = (uint32_t)va;
juansal12 0:c792b17d9f78 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
juansal12 0:c792b17d9f78 458 }
juansal12 0:c792b17d9f78 459
juansal12 0:c792b17d9f78 460 /** \brief Invalidate D$ by MVA
juansal12 0:c792b17d9f78 461
juansal12 0:c792b17d9f78 462 DCIMVAC. Data cache invalidate by MVA to PoC
juansal12 0:c792b17d9f78 463 */
juansal12 0:c792b17d9f78 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
juansal12 0:c792b17d9f78 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
juansal12 0:c792b17d9f78 466 __DCIMVAC = (uint32_t)va;
juansal12 0:c792b17d9f78 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
juansal12 0:c792b17d9f78 468 }
juansal12 0:c792b17d9f78 469
juansal12 0:c792b17d9f78 470 /** \brief Clean and Invalidate D$ by MVA
juansal12 0:c792b17d9f78 471
juansal12 0:c792b17d9f78 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
juansal12 0:c792b17d9f78 473 */
juansal12 0:c792b17d9f78 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
juansal12 0:c792b17d9f78 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
juansal12 0:c792b17d9f78 476 __DCCIMVAC = (uint32_t)va;
juansal12 0:c792b17d9f78 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
juansal12 0:c792b17d9f78 478 }
juansal12 0:c792b17d9f78 479
juansal12 0:c792b17d9f78 480 /** \brief
juansal12 0:c792b17d9f78 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
juansal12 0:c792b17d9f78 482 */
juansal12 0:c792b17d9f78 483 #pragma push
juansal12 0:c792b17d9f78 484 #pragma arm
juansal12 0:c792b17d9f78 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
juansal12 0:c792b17d9f78 486 ARM
juansal12 0:c792b17d9f78 487
juansal12 0:c792b17d9f78 488 PUSH {R4-R11}
juansal12 0:c792b17d9f78 489
juansal12 0:c792b17d9f78 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
juansal12 0:c792b17d9f78 491 ANDS R3, R6, #0x07000000 // Extract coherency level
juansal12 0:c792b17d9f78 492 MOV R3, R3, LSR #23 // Total cache levels << 1
juansal12 0:c792b17d9f78 493 BEQ Finished // If 0, no need to clean
juansal12 0:c792b17d9f78 494
juansal12 0:c792b17d9f78 495 MOV R10, #0 // R10 holds current cache level << 1
juansal12 0:c792b17d9f78 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
juansal12 0:c792b17d9f78 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
juansal12 0:c792b17d9f78 498 AND R1, R1, #7 // Isolate those lower 3 bits
juansal12 0:c792b17d9f78 499 CMP R1, #2
juansal12 0:c792b17d9f78 500 BLT Skip // No cache or only instruction cache at this level
juansal12 0:c792b17d9f78 501
juansal12 0:c792b17d9f78 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
juansal12 0:c792b17d9f78 503 ISB // ISB to sync the change to the CacheSizeID reg
juansal12 0:c792b17d9f78 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
juansal12 0:c792b17d9f78 505 AND R2, R1, #7 // Extract the line length field
juansal12 0:c792b17d9f78 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
juansal12 0:c792b17d9f78 507 LDR R4, =0x3FF
juansal12 0:c792b17d9f78 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
juansal12 0:c792b17d9f78 509 CLZ R5, R4 // R5 is the bit position of the way size increment
juansal12 0:c792b17d9f78 510 LDR R7, =0x7FFF
juansal12 0:c792b17d9f78 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
juansal12 0:c792b17d9f78 512
juansal12 0:c792b17d9f78 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
juansal12 0:c792b17d9f78 514
juansal12 0:c792b17d9f78 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
juansal12 0:c792b17d9f78 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
juansal12 0:c792b17d9f78 517 CMP R0, #0
juansal12 0:c792b17d9f78 518 BNE Dccsw
juansal12 0:c792b17d9f78 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
juansal12 0:c792b17d9f78 520 B cont
juansal12 0:c792b17d9f78 521 Dccsw CMP R0, #1
juansal12 0:c792b17d9f78 522 BNE Dccisw
juansal12 0:c792b17d9f78 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
juansal12 0:c792b17d9f78 524 B cont
juansal12 0:c792b17d9f78 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
juansal12 0:c792b17d9f78 526 cont SUBS R9, R9, #1 // Decrement the Way number
juansal12 0:c792b17d9f78 527 BGE Loop3
juansal12 0:c792b17d9f78 528 SUBS R7, R7, #1 // Decrement the Set number
juansal12 0:c792b17d9f78 529 BGE Loop2
juansal12 0:c792b17d9f78 530 Skip ADD R10, R10, #2 // increment the cache number
juansal12 0:c792b17d9f78 531 CMP R3, R10
juansal12 0:c792b17d9f78 532 BGT Loop1
juansal12 0:c792b17d9f78 533
juansal12 0:c792b17d9f78 534 Finished
juansal12 0:c792b17d9f78 535 DSB
juansal12 0:c792b17d9f78 536 POP {R4-R11}
juansal12 0:c792b17d9f78 537 BX lr
juansal12 0:c792b17d9f78 538
juansal12 0:c792b17d9f78 539 }
juansal12 0:c792b17d9f78 540 #pragma pop
juansal12 0:c792b17d9f78 541
juansal12 0:c792b17d9f78 542 /** \brief __v7_all_cache - helper function
juansal12 0:c792b17d9f78 543
juansal12 0:c792b17d9f78 544 */
juansal12 0:c792b17d9f78 545
juansal12 0:c792b17d9f78 546 /** \brief Invalidate the whole D$
juansal12 0:c792b17d9f78 547
juansal12 0:c792b17d9f78 548 DCISW. Invalidate by Set/Way
juansal12 0:c792b17d9f78 549 */
juansal12 0:c792b17d9f78 550
juansal12 0:c792b17d9f78 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
juansal12 0:c792b17d9f78 552 __v7_all_cache(0);
juansal12 0:c792b17d9f78 553 }
juansal12 0:c792b17d9f78 554
juansal12 0:c792b17d9f78 555 /** \brief Clean the whole D$
juansal12 0:c792b17d9f78 556
juansal12 0:c792b17d9f78 557 DCCSW. Clean by Set/Way
juansal12 0:c792b17d9f78 558 */
juansal12 0:c792b17d9f78 559
juansal12 0:c792b17d9f78 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
juansal12 0:c792b17d9f78 561 __v7_all_cache(1);
juansal12 0:c792b17d9f78 562 }
juansal12 0:c792b17d9f78 563
juansal12 0:c792b17d9f78 564 /** \brief Clean and invalidate the whole D$
juansal12 0:c792b17d9f78 565
juansal12 0:c792b17d9f78 566 DCCISW. Clean and Invalidate by Set/Way
juansal12 0:c792b17d9f78 567 */
juansal12 0:c792b17d9f78 568
juansal12 0:c792b17d9f78 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
juansal12 0:c792b17d9f78 570 __v7_all_cache(2);
juansal12 0:c792b17d9f78 571 }
juansal12 0:c792b17d9f78 572
juansal12 0:c792b17d9f78 573 #include "core_ca_mmu.h"
juansal12 0:c792b17d9f78 574
juansal12 0:c792b17d9f78 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
juansal12 0:c792b17d9f78 576
juansal12 0:c792b17d9f78 577 #error IAR Compiler support not implemented for Cortex-A
juansal12 0:c792b17d9f78 578
juansal12 0:c792b17d9f78 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
juansal12 0:c792b17d9f78 580
juansal12 0:c792b17d9f78 581 /* GNU gcc specific functions */
juansal12 0:c792b17d9f78 582
juansal12 0:c792b17d9f78 583 #define MODE_USR 0x10
juansal12 0:c792b17d9f78 584 #define MODE_FIQ 0x11
juansal12 0:c792b17d9f78 585 #define MODE_IRQ 0x12
juansal12 0:c792b17d9f78 586 #define MODE_SVC 0x13
juansal12 0:c792b17d9f78 587 #define MODE_MON 0x16
juansal12 0:c792b17d9f78 588 #define MODE_ABT 0x17
juansal12 0:c792b17d9f78 589 #define MODE_HYP 0x1A
juansal12 0:c792b17d9f78 590 #define MODE_UND 0x1B
juansal12 0:c792b17d9f78 591 #define MODE_SYS 0x1F
juansal12 0:c792b17d9f78 592
juansal12 0:c792b17d9f78 593
juansal12 0:c792b17d9f78 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
juansal12 0:c792b17d9f78 595 {
juansal12 0:c792b17d9f78 596 __ASM volatile ("cpsie i");
juansal12 0:c792b17d9f78 597 }
juansal12 0:c792b17d9f78 598
juansal12 0:c792b17d9f78 599 /** \brief Disable IRQ Interrupts
juansal12 0:c792b17d9f78 600
juansal12 0:c792b17d9f78 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
juansal12 0:c792b17d9f78 602 Can only be executed in Privileged modes.
juansal12 0:c792b17d9f78 603 */
juansal12 0:c792b17d9f78 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
juansal12 0:c792b17d9f78 605 {
juansal12 0:c792b17d9f78 606 uint32_t result;
juansal12 0:c792b17d9f78 607
juansal12 0:c792b17d9f78 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
juansal12 0:c792b17d9f78 609 __ASM volatile ("cpsid i");
juansal12 0:c792b17d9f78 610 return(result & 0x80);
juansal12 0:c792b17d9f78 611 }
juansal12 0:c792b17d9f78 612
juansal12 0:c792b17d9f78 613
juansal12 0:c792b17d9f78 614 /** \brief Get APSR Register
juansal12 0:c792b17d9f78 615
juansal12 0:c792b17d9f78 616 This function returns the content of the APSR Register.
juansal12 0:c792b17d9f78 617
juansal12 0:c792b17d9f78 618 \return APSR Register value
juansal12 0:c792b17d9f78 619 */
juansal12 0:c792b17d9f78 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
juansal12 0:c792b17d9f78 621 {
juansal12 0:c792b17d9f78 622 #if 1
juansal12 0:c792b17d9f78 623 uint32_t result;
juansal12 0:c792b17d9f78 624
juansal12 0:c792b17d9f78 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
juansal12 0:c792b17d9f78 626 return (result);
juansal12 0:c792b17d9f78 627 #else
juansal12 0:c792b17d9f78 628 register uint32_t __regAPSR __ASM("apsr");
juansal12 0:c792b17d9f78 629 return(__regAPSR);
juansal12 0:c792b17d9f78 630 #endif
juansal12 0:c792b17d9f78 631 }
juansal12 0:c792b17d9f78 632
juansal12 0:c792b17d9f78 633
juansal12 0:c792b17d9f78 634 /** \brief Get CPSR Register
juansal12 0:c792b17d9f78 635
juansal12 0:c792b17d9f78 636 This function returns the content of the CPSR Register.
juansal12 0:c792b17d9f78 637
juansal12 0:c792b17d9f78 638 \return CPSR Register value
juansal12 0:c792b17d9f78 639 */
juansal12 0:c792b17d9f78 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
juansal12 0:c792b17d9f78 641 {
juansal12 0:c792b17d9f78 642 #if 1
juansal12 0:c792b17d9f78 643 register uint32_t __regCPSR;
juansal12 0:c792b17d9f78 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
juansal12 0:c792b17d9f78 645 #else
juansal12 0:c792b17d9f78 646 register uint32_t __regCPSR __ASM("cpsr");
juansal12 0:c792b17d9f78 647 #endif
juansal12 0:c792b17d9f78 648 return(__regCPSR);
juansal12 0:c792b17d9f78 649 }
juansal12 0:c792b17d9f78 650
juansal12 0:c792b17d9f78 651 #if 0
juansal12 0:c792b17d9f78 652 /** \brief Set Stack Pointer
juansal12 0:c792b17d9f78 653
juansal12 0:c792b17d9f78 654 This function assigns the given value to the current stack pointer.
juansal12 0:c792b17d9f78 655
juansal12 0:c792b17d9f78 656 \param [in] topOfStack Stack Pointer value to set
juansal12 0:c792b17d9f78 657 */
juansal12 0:c792b17d9f78 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
juansal12 0:c792b17d9f78 659 {
juansal12 0:c792b17d9f78 660 register uint32_t __regSP __ASM("sp");
juansal12 0:c792b17d9f78 661 __regSP = topOfStack;
juansal12 0:c792b17d9f78 662 }
juansal12 0:c792b17d9f78 663 #endif
juansal12 0:c792b17d9f78 664
juansal12 0:c792b17d9f78 665 /** \brief Get link register
juansal12 0:c792b17d9f78 666
juansal12 0:c792b17d9f78 667 This function returns the value of the link register
juansal12 0:c792b17d9f78 668
juansal12 0:c792b17d9f78 669 \return Value of link register
juansal12 0:c792b17d9f78 670 */
juansal12 0:c792b17d9f78 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
juansal12 0:c792b17d9f78 672 {
juansal12 0:c792b17d9f78 673 register uint32_t __reglr __ASM("lr");
juansal12 0:c792b17d9f78 674 return(__reglr);
juansal12 0:c792b17d9f78 675 }
juansal12 0:c792b17d9f78 676
juansal12 0:c792b17d9f78 677 #if 0
juansal12 0:c792b17d9f78 678 /** \brief Set link register
juansal12 0:c792b17d9f78 679
juansal12 0:c792b17d9f78 680 This function sets the value of the link register
juansal12 0:c792b17d9f78 681
juansal12 0:c792b17d9f78 682 \param [in] lr LR value to set
juansal12 0:c792b17d9f78 683 */
juansal12 0:c792b17d9f78 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
juansal12 0:c792b17d9f78 685 {
juansal12 0:c792b17d9f78 686 register uint32_t __reglr __ASM("lr");
juansal12 0:c792b17d9f78 687 __reglr = lr;
juansal12 0:c792b17d9f78 688 }
juansal12 0:c792b17d9f78 689 #endif
juansal12 0:c792b17d9f78 690
juansal12 0:c792b17d9f78 691 /** \brief Set Process Stack Pointer
juansal12 0:c792b17d9f78 692
juansal12 0:c792b17d9f78 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
juansal12 0:c792b17d9f78 694
juansal12 0:c792b17d9f78 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
juansal12 0:c792b17d9f78 696 */
juansal12 0:c792b17d9f78 697 extern void __set_PSP(uint32_t topOfProcStack);
juansal12 0:c792b17d9f78 698
juansal12 0:c792b17d9f78 699 /** \brief Set User Mode
juansal12 0:c792b17d9f78 700
juansal12 0:c792b17d9f78 701 This function changes the processor state to User Mode
juansal12 0:c792b17d9f78 702
juansal12 0:c792b17d9f78 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
juansal12 0:c792b17d9f78 704 */
juansal12 0:c792b17d9f78 705 extern void __set_CPS_USR(void);
juansal12 0:c792b17d9f78 706
juansal12 0:c792b17d9f78 707 /** \brief Enable FIQ
juansal12 0:c792b17d9f78 708
juansal12 0:c792b17d9f78 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
juansal12 0:c792b17d9f78 710 Can only be executed in Privileged modes.
juansal12 0:c792b17d9f78 711 */
juansal12 0:c792b17d9f78 712 #define __enable_fault_irq __enable_fiq
juansal12 0:c792b17d9f78 713
juansal12 0:c792b17d9f78 714
juansal12 0:c792b17d9f78 715 /** \brief Disable FIQ
juansal12 0:c792b17d9f78 716
juansal12 0:c792b17d9f78 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
juansal12 0:c792b17d9f78 718 Can only be executed in Privileged modes.
juansal12 0:c792b17d9f78 719 */
juansal12 0:c792b17d9f78 720 #define __disable_fault_irq __disable_fiq
juansal12 0:c792b17d9f78 721
juansal12 0:c792b17d9f78 722
juansal12 0:c792b17d9f78 723 /** \brief Get FPSCR
juansal12 0:c792b17d9f78 724
juansal12 0:c792b17d9f78 725 This function returns the current value of the Floating Point Status/Control register.
juansal12 0:c792b17d9f78 726
juansal12 0:c792b17d9f78 727 \return Floating Point Status/Control register value
juansal12 0:c792b17d9f78 728 */
juansal12 0:c792b17d9f78 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
juansal12 0:c792b17d9f78 730 {
juansal12 0:c792b17d9f78 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
juansal12 0:c792b17d9f78 732 #if 1
juansal12 0:c792b17d9f78 733 uint32_t result;
juansal12 0:c792b17d9f78 734
juansal12 0:c792b17d9f78 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
juansal12 0:c792b17d9f78 736 return (result);
juansal12 0:c792b17d9f78 737 #else
juansal12 0:c792b17d9f78 738 register uint32_t __regfpscr __ASM("fpscr");
juansal12 0:c792b17d9f78 739 return(__regfpscr);
juansal12 0:c792b17d9f78 740 #endif
juansal12 0:c792b17d9f78 741 #else
juansal12 0:c792b17d9f78 742 return(0);
juansal12 0:c792b17d9f78 743 #endif
juansal12 0:c792b17d9f78 744 }
juansal12 0:c792b17d9f78 745
juansal12 0:c792b17d9f78 746
juansal12 0:c792b17d9f78 747 /** \brief Set FPSCR
juansal12 0:c792b17d9f78 748
juansal12 0:c792b17d9f78 749 This function assigns the given value to the Floating Point Status/Control register.
juansal12 0:c792b17d9f78 750
juansal12 0:c792b17d9f78 751 \param [in] fpscr Floating Point Status/Control value to set
juansal12 0:c792b17d9f78 752 */
juansal12 0:c792b17d9f78 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
juansal12 0:c792b17d9f78 754 {
juansal12 0:c792b17d9f78 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
juansal12 0:c792b17d9f78 756 #if 1
juansal12 0:c792b17d9f78 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
juansal12 0:c792b17d9f78 758 #else
juansal12 0:c792b17d9f78 759 register uint32_t __regfpscr __ASM("fpscr");
juansal12 0:c792b17d9f78 760 __regfpscr = (fpscr);
juansal12 0:c792b17d9f78 761 #endif
juansal12 0:c792b17d9f78 762 #endif
juansal12 0:c792b17d9f78 763 }
juansal12 0:c792b17d9f78 764
juansal12 0:c792b17d9f78 765 /** \brief Get FPEXC
juansal12 0:c792b17d9f78 766
juansal12 0:c792b17d9f78 767 This function returns the current value of the Floating Point Exception Control register.
juansal12 0:c792b17d9f78 768
juansal12 0:c792b17d9f78 769 \return Floating Point Exception Control register value
juansal12 0:c792b17d9f78 770 */
juansal12 0:c792b17d9f78 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
juansal12 0:c792b17d9f78 772 {
juansal12 0:c792b17d9f78 773 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 774 #if 1
juansal12 0:c792b17d9f78 775 uint32_t result;
juansal12 0:c792b17d9f78 776
juansal12 0:c792b17d9f78 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
juansal12 0:c792b17d9f78 778 return (result);
juansal12 0:c792b17d9f78 779 #else
juansal12 0:c792b17d9f78 780 register uint32_t __regfpexc __ASM("fpexc");
juansal12 0:c792b17d9f78 781 return(__regfpexc);
juansal12 0:c792b17d9f78 782 #endif
juansal12 0:c792b17d9f78 783 #else
juansal12 0:c792b17d9f78 784 return(0);
juansal12 0:c792b17d9f78 785 #endif
juansal12 0:c792b17d9f78 786 }
juansal12 0:c792b17d9f78 787
juansal12 0:c792b17d9f78 788
juansal12 0:c792b17d9f78 789 /** \brief Set FPEXC
juansal12 0:c792b17d9f78 790
juansal12 0:c792b17d9f78 791 This function assigns the given value to the Floating Point Exception Control register.
juansal12 0:c792b17d9f78 792
juansal12 0:c792b17d9f78 793 \param [in] fpscr Floating Point Exception Control value to set
juansal12 0:c792b17d9f78 794 */
juansal12 0:c792b17d9f78 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
juansal12 0:c792b17d9f78 796 {
juansal12 0:c792b17d9f78 797 #if (__FPU_PRESENT == 1)
juansal12 0:c792b17d9f78 798 #if 1
juansal12 0:c792b17d9f78 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
juansal12 0:c792b17d9f78 800 #else
juansal12 0:c792b17d9f78 801 register uint32_t __regfpexc __ASM("fpexc");
juansal12 0:c792b17d9f78 802 __regfpexc = (fpexc);
juansal12 0:c792b17d9f78 803 #endif
juansal12 0:c792b17d9f78 804 #endif
juansal12 0:c792b17d9f78 805 }
juansal12 0:c792b17d9f78 806
juansal12 0:c792b17d9f78 807 /** \brief Get CPACR
juansal12 0:c792b17d9f78 808
juansal12 0:c792b17d9f78 809 This function returns the current value of the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 810
juansal12 0:c792b17d9f78 811 \return Coprocessor Access Control register value
juansal12 0:c792b17d9f78 812 */
juansal12 0:c792b17d9f78 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
juansal12 0:c792b17d9f78 814 {
juansal12 0:c792b17d9f78 815 #if 1
juansal12 0:c792b17d9f78 816 register uint32_t __regCPACR;
juansal12 0:c792b17d9f78 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
juansal12 0:c792b17d9f78 818 #else
juansal12 0:c792b17d9f78 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
juansal12 0:c792b17d9f78 820 #endif
juansal12 0:c792b17d9f78 821 return __regCPACR;
juansal12 0:c792b17d9f78 822 }
juansal12 0:c792b17d9f78 823
juansal12 0:c792b17d9f78 824 /** \brief Set CPACR
juansal12 0:c792b17d9f78 825
juansal12 0:c792b17d9f78 826 This function assigns the given value to the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 827
juansal12 0:c792b17d9f78 828 \param [in] cpacr Coporcessor Acccess Control value to set
juansal12 0:c792b17d9f78 829 */
juansal12 0:c792b17d9f78 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
juansal12 0:c792b17d9f78 831 {
juansal12 0:c792b17d9f78 832 #if 1
juansal12 0:c792b17d9f78 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
juansal12 0:c792b17d9f78 834 #else
juansal12 0:c792b17d9f78 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
juansal12 0:c792b17d9f78 836 __regCPACR = cpacr;
juansal12 0:c792b17d9f78 837 #endif
juansal12 0:c792b17d9f78 838 __ISB();
juansal12 0:c792b17d9f78 839 }
juansal12 0:c792b17d9f78 840
juansal12 0:c792b17d9f78 841 /** \brief Get CBAR
juansal12 0:c792b17d9f78 842
juansal12 0:c792b17d9f78 843 This function returns the value of the Configuration Base Address register.
juansal12 0:c792b17d9f78 844
juansal12 0:c792b17d9f78 845 \return Configuration Base Address register value
juansal12 0:c792b17d9f78 846 */
juansal12 0:c792b17d9f78 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
juansal12 0:c792b17d9f78 848 #if 1
juansal12 0:c792b17d9f78 849 register uint32_t __regCBAR;
juansal12 0:c792b17d9f78 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
juansal12 0:c792b17d9f78 851 #else
juansal12 0:c792b17d9f78 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
juansal12 0:c792b17d9f78 853 #endif
juansal12 0:c792b17d9f78 854 return(__regCBAR);
juansal12 0:c792b17d9f78 855 }
juansal12 0:c792b17d9f78 856
juansal12 0:c792b17d9f78 857 /** \brief Get TTBR0
juansal12 0:c792b17d9f78 858
juansal12 0:c792b17d9f78 859 This function returns the value of the Configuration Base Address register.
juansal12 0:c792b17d9f78 860
juansal12 0:c792b17d9f78 861 \return Translation Table Base Register 0 value
juansal12 0:c792b17d9f78 862 */
juansal12 0:c792b17d9f78 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
juansal12 0:c792b17d9f78 864 #if 1
juansal12 0:c792b17d9f78 865 register uint32_t __regTTBR0;
juansal12 0:c792b17d9f78 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
juansal12 0:c792b17d9f78 867 #else
juansal12 0:c792b17d9f78 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
juansal12 0:c792b17d9f78 869 #endif
juansal12 0:c792b17d9f78 870 return(__regTTBR0);
juansal12 0:c792b17d9f78 871 }
juansal12 0:c792b17d9f78 872
juansal12 0:c792b17d9f78 873 /** \brief Set TTBR0
juansal12 0:c792b17d9f78 874
juansal12 0:c792b17d9f78 875 This function assigns the given value to the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 876
juansal12 0:c792b17d9f78 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
juansal12 0:c792b17d9f78 878 */
juansal12 0:c792b17d9f78 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
juansal12 0:c792b17d9f78 880 #if 1
juansal12 0:c792b17d9f78 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
juansal12 0:c792b17d9f78 882 #else
juansal12 0:c792b17d9f78 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
juansal12 0:c792b17d9f78 884 __regTTBR0 = ttbr0;
juansal12 0:c792b17d9f78 885 #endif
juansal12 0:c792b17d9f78 886 __ISB();
juansal12 0:c792b17d9f78 887 }
juansal12 0:c792b17d9f78 888
juansal12 0:c792b17d9f78 889 /** \brief Get DACR
juansal12 0:c792b17d9f78 890
juansal12 0:c792b17d9f78 891 This function returns the value of the Domain Access Control Register.
juansal12 0:c792b17d9f78 892
juansal12 0:c792b17d9f78 893 \return Domain Access Control Register value
juansal12 0:c792b17d9f78 894 */
juansal12 0:c792b17d9f78 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
juansal12 0:c792b17d9f78 896 #if 1
juansal12 0:c792b17d9f78 897 register uint32_t __regDACR;
juansal12 0:c792b17d9f78 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
juansal12 0:c792b17d9f78 899 #else
juansal12 0:c792b17d9f78 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
juansal12 0:c792b17d9f78 901 #endif
juansal12 0:c792b17d9f78 902 return(__regDACR);
juansal12 0:c792b17d9f78 903 }
juansal12 0:c792b17d9f78 904
juansal12 0:c792b17d9f78 905 /** \brief Set DACR
juansal12 0:c792b17d9f78 906
juansal12 0:c792b17d9f78 907 This function assigns the given value to the Coprocessor Access Control register.
juansal12 0:c792b17d9f78 908
juansal12 0:c792b17d9f78 909 \param [in] dacr Domain Access Control Register value to set
juansal12 0:c792b17d9f78 910 */
juansal12 0:c792b17d9f78 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
juansal12 0:c792b17d9f78 912 #if 1
juansal12 0:c792b17d9f78 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
juansal12 0:c792b17d9f78 914 #else
juansal12 0:c792b17d9f78 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
juansal12 0:c792b17d9f78 916 __regDACR = dacr;
juansal12 0:c792b17d9f78 917 #endif
juansal12 0:c792b17d9f78 918 __ISB();
juansal12 0:c792b17d9f78 919 }
juansal12 0:c792b17d9f78 920
juansal12 0:c792b17d9f78 921 /******************************** Cache and BTAC enable ****************************************************/
juansal12 0:c792b17d9f78 922
juansal12 0:c792b17d9f78 923 /** \brief Set SCTLR
juansal12 0:c792b17d9f78 924
juansal12 0:c792b17d9f78 925 This function assigns the given value to the System Control Register.
juansal12 0:c792b17d9f78 926
juansal12 0:c792b17d9f78 927 \param [in] sctlr System Control Register, value to set
juansal12 0:c792b17d9f78 928 */
juansal12 0:c792b17d9f78 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
juansal12 0:c792b17d9f78 930 {
juansal12 0:c792b17d9f78 931 #if 1
juansal12 0:c792b17d9f78 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
juansal12 0:c792b17d9f78 933 #else
juansal12 0:c792b17d9f78 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
juansal12 0:c792b17d9f78 935 __regSCTLR = sctlr;
juansal12 0:c792b17d9f78 936 #endif
juansal12 0:c792b17d9f78 937 }
juansal12 0:c792b17d9f78 938
juansal12 0:c792b17d9f78 939 /** \brief Get SCTLR
juansal12 0:c792b17d9f78 940
juansal12 0:c792b17d9f78 941 This function returns the value of the System Control Register.
juansal12 0:c792b17d9f78 942
juansal12 0:c792b17d9f78 943 \return System Control Register value
juansal12 0:c792b17d9f78 944 */
juansal12 0:c792b17d9f78 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
juansal12 0:c792b17d9f78 946 #if 1
juansal12 0:c792b17d9f78 947 register uint32_t __regSCTLR;
juansal12 0:c792b17d9f78 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
juansal12 0:c792b17d9f78 949 #else
juansal12 0:c792b17d9f78 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
juansal12 0:c792b17d9f78 951 #endif
juansal12 0:c792b17d9f78 952 return(__regSCTLR);
juansal12 0:c792b17d9f78 953 }
juansal12 0:c792b17d9f78 954
juansal12 0:c792b17d9f78 955 /** \brief Enable Caches
juansal12 0:c792b17d9f78 956
juansal12 0:c792b17d9f78 957 Enable Caches
juansal12 0:c792b17d9f78 958 */
juansal12 0:c792b17d9f78 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
juansal12 0:c792b17d9f78 960 // Set I bit 12 to enable I Cache
juansal12 0:c792b17d9f78 961 // Set C bit 2 to enable D Cache
juansal12 0:c792b17d9f78 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
juansal12 0:c792b17d9f78 963 }
juansal12 0:c792b17d9f78 964
juansal12 0:c792b17d9f78 965 /** \brief Disable Caches
juansal12 0:c792b17d9f78 966
juansal12 0:c792b17d9f78 967 Disable Caches
juansal12 0:c792b17d9f78 968 */
juansal12 0:c792b17d9f78 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
juansal12 0:c792b17d9f78 970 // Clear I bit 12 to disable I Cache
juansal12 0:c792b17d9f78 971 // Clear C bit 2 to disable D Cache
juansal12 0:c792b17d9f78 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
juansal12 0:c792b17d9f78 973 __ISB();
juansal12 0:c792b17d9f78 974 }
juansal12 0:c792b17d9f78 975
juansal12 0:c792b17d9f78 976 /** \brief Enable BTAC
juansal12 0:c792b17d9f78 977
juansal12 0:c792b17d9f78 978 Enable BTAC
juansal12 0:c792b17d9f78 979 */
juansal12 0:c792b17d9f78 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
juansal12 0:c792b17d9f78 981 // Set Z bit 11 to enable branch prediction
juansal12 0:c792b17d9f78 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
juansal12 0:c792b17d9f78 983 __ISB();
juansal12 0:c792b17d9f78 984 }
juansal12 0:c792b17d9f78 985
juansal12 0:c792b17d9f78 986 /** \brief Disable BTAC
juansal12 0:c792b17d9f78 987
juansal12 0:c792b17d9f78 988 Disable BTAC
juansal12 0:c792b17d9f78 989 */
juansal12 0:c792b17d9f78 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
juansal12 0:c792b17d9f78 991 // Clear Z bit 11 to disable branch prediction
juansal12 0:c792b17d9f78 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
juansal12 0:c792b17d9f78 993 }
juansal12 0:c792b17d9f78 994
juansal12 0:c792b17d9f78 995
juansal12 0:c792b17d9f78 996 /** \brief Enable MMU
juansal12 0:c792b17d9f78 997
juansal12 0:c792b17d9f78 998 Enable MMU
juansal12 0:c792b17d9f78 999 */
juansal12 0:c792b17d9f78 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
juansal12 0:c792b17d9f78 1001 // Set M bit 0 to enable the MMU
juansal12 0:c792b17d9f78 1002 // Set AFE bit to enable simplified access permissions model
juansal12 0:c792b17d9f78 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
juansal12 0:c792b17d9f78 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
juansal12 0:c792b17d9f78 1005 __ISB();
juansal12 0:c792b17d9f78 1006 }
juansal12 0:c792b17d9f78 1007
juansal12 0:c792b17d9f78 1008 /** \brief Enable MMU
juansal12 0:c792b17d9f78 1009
juansal12 0:c792b17d9f78 1010 Enable MMU
juansal12 0:c792b17d9f78 1011 */
juansal12 0:c792b17d9f78 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
juansal12 0:c792b17d9f78 1013 // Clear M bit 0 to disable the MMU
juansal12 0:c792b17d9f78 1014 __set_SCTLR( __get_SCTLR() & ~1);
juansal12 0:c792b17d9f78 1015 __ISB();
juansal12 0:c792b17d9f78 1016 }
juansal12 0:c792b17d9f78 1017
juansal12 0:c792b17d9f78 1018 /******************************** TLB maintenance operations ************************************************/
juansal12 0:c792b17d9f78 1019 /** \brief Invalidate the whole tlb
juansal12 0:c792b17d9f78 1020
juansal12 0:c792b17d9f78 1021 TLBIALL. Invalidate the whole tlb
juansal12 0:c792b17d9f78 1022 */
juansal12 0:c792b17d9f78 1023
juansal12 0:c792b17d9f78 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
juansal12 0:c792b17d9f78 1025 #if 1
juansal12 0:c792b17d9f78 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
juansal12 0:c792b17d9f78 1027 #else
juansal12 0:c792b17d9f78 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
juansal12 0:c792b17d9f78 1029 __TLBIALL = 0;
juansal12 0:c792b17d9f78 1030 #endif
juansal12 0:c792b17d9f78 1031 __DSB();
juansal12 0:c792b17d9f78 1032 __ISB();
juansal12 0:c792b17d9f78 1033 }
juansal12 0:c792b17d9f78 1034
juansal12 0:c792b17d9f78 1035 /******************************** BTB maintenance operations ************************************************/
juansal12 0:c792b17d9f78 1036 /** \brief Invalidate entire branch predictor array
juansal12 0:c792b17d9f78 1037
juansal12 0:c792b17d9f78 1038 BPIALL. Branch Predictor Invalidate All.
juansal12 0:c792b17d9f78 1039 */
juansal12 0:c792b17d9f78 1040
juansal12 0:c792b17d9f78 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
juansal12 0:c792b17d9f78 1042 #if 1
juansal12 0:c792b17d9f78 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
juansal12 0:c792b17d9f78 1044 #else
juansal12 0:c792b17d9f78 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
juansal12 0:c792b17d9f78 1046 __BPIALL = 0;
juansal12 0:c792b17d9f78 1047 #endif
juansal12 0:c792b17d9f78 1048 __DSB(); //ensure completion of the invalidation
juansal12 0:c792b17d9f78 1049 __ISB(); //ensure instruction fetch path sees new state
juansal12 0:c792b17d9f78 1050 }
juansal12 0:c792b17d9f78 1051
juansal12 0:c792b17d9f78 1052
juansal12 0:c792b17d9f78 1053 /******************************** L1 cache operations ******************************************************/
juansal12 0:c792b17d9f78 1054
juansal12 0:c792b17d9f78 1055 /** \brief Invalidate the whole I$
juansal12 0:c792b17d9f78 1056
juansal12 0:c792b17d9f78 1057 ICIALLU. Instruction Cache Invalidate All to PoU
juansal12 0:c792b17d9f78 1058 */
juansal12 0:c792b17d9f78 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
juansal12 0:c792b17d9f78 1060 #if 1
juansal12 0:c792b17d9f78 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
juansal12 0:c792b17d9f78 1062 #else
juansal12 0:c792b17d9f78 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
juansal12 0:c792b17d9f78 1064 __ICIALLU = 0;
juansal12 0:c792b17d9f78 1065 #endif
juansal12 0:c792b17d9f78 1066 __DSB(); //ensure completion of the invalidation
juansal12 0:c792b17d9f78 1067 __ISB(); //ensure instruction fetch path sees new I cache state
juansal12 0:c792b17d9f78 1068 }
juansal12 0:c792b17d9f78 1069
juansal12 0:c792b17d9f78 1070 /** \brief Clean D$ by MVA
juansal12 0:c792b17d9f78 1071
juansal12 0:c792b17d9f78 1072 DCCMVAC. Data cache clean by MVA to PoC
juansal12 0:c792b17d9f78 1073 */
juansal12 0:c792b17d9f78 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
juansal12 0:c792b17d9f78 1075 #if 1
juansal12 0:c792b17d9f78 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
juansal12 0:c792b17d9f78 1077 #else
juansal12 0:c792b17d9f78 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
juansal12 0:c792b17d9f78 1079 __DCCMVAC = (uint32_t)va;
juansal12 0:c792b17d9f78 1080 #endif
juansal12 0:c792b17d9f78 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
juansal12 0:c792b17d9f78 1082 }
juansal12 0:c792b17d9f78 1083
juansal12 0:c792b17d9f78 1084 /** \brief Invalidate D$ by MVA
juansal12 0:c792b17d9f78 1085
juansal12 0:c792b17d9f78 1086 DCIMVAC. Data cache invalidate by MVA to PoC
juansal12 0:c792b17d9f78 1087 */
juansal12 0:c792b17d9f78 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
juansal12 0:c792b17d9f78 1089 #if 1
juansal12 0:c792b17d9f78 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
juansal12 0:c792b17d9f78 1091 #else
juansal12 0:c792b17d9f78 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
juansal12 0:c792b17d9f78 1093 __DCIMVAC = (uint32_t)va;
juansal12 0:c792b17d9f78 1094 #endif
juansal12 0:c792b17d9f78 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
juansal12 0:c792b17d9f78 1096 }
juansal12 0:c792b17d9f78 1097
juansal12 0:c792b17d9f78 1098 /** \brief Clean and Invalidate D$ by MVA
juansal12 0:c792b17d9f78 1099
juansal12 0:c792b17d9f78 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
juansal12 0:c792b17d9f78 1101 */
juansal12 0:c792b17d9f78 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
juansal12 0:c792b17d9f78 1103 #if 1
juansal12 0:c792b17d9f78 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
juansal12 0:c792b17d9f78 1105 #else
juansal12 0:c792b17d9f78 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
juansal12 0:c792b17d9f78 1107 __DCCIMVAC = (uint32_t)va;
juansal12 0:c792b17d9f78 1108 #endif
juansal12 0:c792b17d9f78 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
juansal12 0:c792b17d9f78 1110 }
juansal12 0:c792b17d9f78 1111
juansal12 0:c792b17d9f78 1112 /** \brief
juansal12 0:c792b17d9f78 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
juansal12 0:c792b17d9f78 1114 */
juansal12 0:c792b17d9f78 1115
juansal12 0:c792b17d9f78 1116 /** \brief __v7_all_cache - helper function
juansal12 0:c792b17d9f78 1117
juansal12 0:c792b17d9f78 1118 */
juansal12 0:c792b17d9f78 1119
juansal12 0:c792b17d9f78 1120 extern void __v7_all_cache(uint32_t op);
juansal12 0:c792b17d9f78 1121
juansal12 0:c792b17d9f78 1122
juansal12 0:c792b17d9f78 1123 /** \brief Invalidate the whole D$
juansal12 0:c792b17d9f78 1124
juansal12 0:c792b17d9f78 1125 DCISW. Invalidate by Set/Way
juansal12 0:c792b17d9f78 1126 */
juansal12 0:c792b17d9f78 1127
juansal12 0:c792b17d9f78 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
juansal12 0:c792b17d9f78 1129 __v7_all_cache(0);
juansal12 0:c792b17d9f78 1130 }
juansal12 0:c792b17d9f78 1131
juansal12 0:c792b17d9f78 1132 /** \brief Clean the whole D$
juansal12 0:c792b17d9f78 1133
juansal12 0:c792b17d9f78 1134 DCCSW. Clean by Set/Way
juansal12 0:c792b17d9f78 1135 */
juansal12 0:c792b17d9f78 1136
juansal12 0:c792b17d9f78 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
juansal12 0:c792b17d9f78 1138 __v7_all_cache(1);
juansal12 0:c792b17d9f78 1139 }
juansal12 0:c792b17d9f78 1140
juansal12 0:c792b17d9f78 1141 /** \brief Clean and invalidate the whole D$
juansal12 0:c792b17d9f78 1142
juansal12 0:c792b17d9f78 1143 DCCISW. Clean and Invalidate by Set/Way
juansal12 0:c792b17d9f78 1144 */
juansal12 0:c792b17d9f78 1145
juansal12 0:c792b17d9f78 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
juansal12 0:c792b17d9f78 1147 __v7_all_cache(2);
juansal12 0:c792b17d9f78 1148 }
juansal12 0:c792b17d9f78 1149
juansal12 0:c792b17d9f78 1150 #include "core_ca_mmu.h"
juansal12 0:c792b17d9f78 1151
juansal12 0:c792b17d9f78 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
juansal12 0:c792b17d9f78 1153
juansal12 0:c792b17d9f78 1154 #error TASKING Compiler support not implemented for Cortex-A
juansal12 0:c792b17d9f78 1155
juansal12 0:c792b17d9f78 1156 #endif
juansal12 0:c792b17d9f78 1157
juansal12 0:c792b17d9f78 1158 /*@} end of CMSIS_Core_RegAccFunctions */
juansal12 0:c792b17d9f78 1159
juansal12 0:c792b17d9f78 1160
juansal12 0:c792b17d9f78 1161 #endif /* __CORE_CAFUNC_H__ */