Juan Salazar / sofi7

test

Dependents:   robotic_fish_6

TARGET_LPC1768/LPC17xx.h@0:c792b17d9f78, 2021-12-03 (annotated)

Committer:
juansal12
Date:
Fri Dec 03 23:00:34 2021 +0000
Revision:
0:c792b17d9f78
uploaded sofi code ;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
juansal12 0:c792b17d9f78 1 /**************************************************************************//**
juansal12 0:c792b17d9f78 2 * @file LPC17xx.h
juansal12 0:c792b17d9f78 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
juansal12 0:c792b17d9f78 4 * NXP LPC17xx Device Series
juansal12 0:c792b17d9f78 5 * @version: V1.09
juansal12 0:c792b17d9f78 6 * @date: 17. March 2010
juansal12 0:c792b17d9f78 7
juansal12 0:c792b17d9f78 8 *
juansal12 0:c792b17d9f78 9 * @note
juansal12 0:c792b17d9f78 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
juansal12 0:c792b17d9f78 11 *
juansal12 0:c792b17d9f78 12 * @par
juansal12 0:c792b17d9f78 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
juansal12 0:c792b17d9f78 14 * processor based microcontrollers. This file can be freely distributed
juansal12 0:c792b17d9f78 15 * within development tools that are supporting such ARM based processors.
juansal12 0:c792b17d9f78 16 *
juansal12 0:c792b17d9f78 17 * @par
juansal12 0:c792b17d9f78 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
juansal12 0:c792b17d9f78 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
juansal12 0:c792b17d9f78 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
juansal12 0:c792b17d9f78 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
juansal12 0:c792b17d9f78 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
juansal12 0:c792b17d9f78 23 *
juansal12 0:c792b17d9f78 24 ******************************************************************************/
juansal12 0:c792b17d9f78 25
juansal12 0:c792b17d9f78 26
juansal12 0:c792b17d9f78 27 #ifndef __LPC17xx_H__
juansal12 0:c792b17d9f78 28 #define __LPC17xx_H__
juansal12 0:c792b17d9f78 29
juansal12 0:c792b17d9f78 30 /*
juansal12 0:c792b17d9f78 31 * ==========================================================================
juansal12 0:c792b17d9f78 32 * ---------- Interrupt Number Definition -----------------------------------
juansal12 0:c792b17d9f78 33 * ==========================================================================
juansal12 0:c792b17d9f78 34 */
juansal12 0:c792b17d9f78 35
juansal12 0:c792b17d9f78 36 typedef enum IRQn
juansal12 0:c792b17d9f78 37 {
juansal12 0:c792b17d9f78 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
juansal12 0:c792b17d9f78 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
juansal12 0:c792b17d9f78 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
juansal12 0:c792b17d9f78 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
juansal12 0:c792b17d9f78 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
juansal12 0:c792b17d9f78 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
juansal12 0:c792b17d9f78 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
juansal12 0:c792b17d9f78 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
juansal12 0:c792b17d9f78 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
juansal12 0:c792b17d9f78 47
juansal12 0:c792b17d9f78 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
juansal12 0:c792b17d9f78 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
juansal12 0:c792b17d9f78 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
juansal12 0:c792b17d9f78 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
juansal12 0:c792b17d9f78 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
juansal12 0:c792b17d9f78 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
juansal12 0:c792b17d9f78 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
juansal12 0:c792b17d9f78 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
juansal12 0:c792b17d9f78 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
juansal12 0:c792b17d9f78 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
juansal12 0:c792b17d9f78 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
juansal12 0:c792b17d9f78 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
juansal12 0:c792b17d9f78 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
juansal12 0:c792b17d9f78 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
juansal12 0:c792b17d9f78 62 SPI_IRQn = 13, /*!< SPI Interrupt */
juansal12 0:c792b17d9f78 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
juansal12 0:c792b17d9f78 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
juansal12 0:c792b17d9f78 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
juansal12 0:c792b17d9f78 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
juansal12 0:c792b17d9f78 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
juansal12 0:c792b17d9f78 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
juansal12 0:c792b17d9f78 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
juansal12 0:c792b17d9f78 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
juansal12 0:c792b17d9f78 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
juansal12 0:c792b17d9f78 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
juansal12 0:c792b17d9f78 73 USB_IRQn = 24, /*!< USB Interrupt */
juansal12 0:c792b17d9f78 74 CAN_IRQn = 25, /*!< CAN Interrupt */
juansal12 0:c792b17d9f78 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
juansal12 0:c792b17d9f78 76 I2S_IRQn = 27, /*!< I2S Interrupt */
juansal12 0:c792b17d9f78 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
juansal12 0:c792b17d9f78 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
juansal12 0:c792b17d9f78 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
juansal12 0:c792b17d9f78 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
juansal12 0:c792b17d9f78 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
juansal12 0:c792b17d9f78 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
juansal12 0:c792b17d9f78 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
juansal12 0:c792b17d9f78 84 } IRQn_Type;
juansal12 0:c792b17d9f78 85
juansal12 0:c792b17d9f78 86
juansal12 0:c792b17d9f78 87 /*
juansal12 0:c792b17d9f78 88 * ==========================================================================
juansal12 0:c792b17d9f78 89 * ----------- Processor and Core Peripheral Section ------------------------
juansal12 0:c792b17d9f78 90 * ==========================================================================
juansal12 0:c792b17d9f78 91 */
juansal12 0:c792b17d9f78 92
juansal12 0:c792b17d9f78 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
juansal12 0:c792b17d9f78 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
juansal12 0:c792b17d9f78 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
juansal12 0:c792b17d9f78 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
juansal12 0:c792b17d9f78 97
juansal12 0:c792b17d9f78 98
juansal12 0:c792b17d9f78 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
juansal12 0:c792b17d9f78 100 #include "system_LPC17xx.h" /* System Header */
juansal12 0:c792b17d9f78 101
juansal12 0:c792b17d9f78 102
juansal12 0:c792b17d9f78 103 /******************************************************************************/
juansal12 0:c792b17d9f78 104 /* Device Specific Peripheral registers structures */
juansal12 0:c792b17d9f78 105 /******************************************************************************/
juansal12 0:c792b17d9f78 106
juansal12 0:c792b17d9f78 107 #if defined ( __CC_ARM )
juansal12 0:c792b17d9f78 108 #pragma anon_unions
juansal12 0:c792b17d9f78 109 #endif
juansal12 0:c792b17d9f78 110
juansal12 0:c792b17d9f78 111 /*------------- System Control (SC) ------------------------------------------*/
juansal12 0:c792b17d9f78 112 typedef struct
juansal12 0:c792b17d9f78 113 {
juansal12 0:c792b17d9f78 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
juansal12 0:c792b17d9f78 115 uint32_t RESERVED0[31];
juansal12 0:c792b17d9f78 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
juansal12 0:c792b17d9f78 117 __IO uint32_t PLL0CFG;
juansal12 0:c792b17d9f78 118 __I uint32_t PLL0STAT;
juansal12 0:c792b17d9f78 119 __O uint32_t PLL0FEED;
juansal12 0:c792b17d9f78 120 uint32_t RESERVED1[4];
juansal12 0:c792b17d9f78 121 __IO uint32_t PLL1CON;
juansal12 0:c792b17d9f78 122 __IO uint32_t PLL1CFG;
juansal12 0:c792b17d9f78 123 __I uint32_t PLL1STAT;
juansal12 0:c792b17d9f78 124 __O uint32_t PLL1FEED;
juansal12 0:c792b17d9f78 125 uint32_t RESERVED2[4];
juansal12 0:c792b17d9f78 126 __IO uint32_t PCON;
juansal12 0:c792b17d9f78 127 __IO uint32_t PCONP;
juansal12 0:c792b17d9f78 128 uint32_t RESERVED3[15];
juansal12 0:c792b17d9f78 129 __IO uint32_t CCLKCFG;
juansal12 0:c792b17d9f78 130 __IO uint32_t USBCLKCFG;
juansal12 0:c792b17d9f78 131 __IO uint32_t CLKSRCSEL;
juansal12 0:c792b17d9f78 132 __IO uint32_t CANSLEEPCLR;
juansal12 0:c792b17d9f78 133 __IO uint32_t CANWAKEFLAGS;
juansal12 0:c792b17d9f78 134 uint32_t RESERVED4[10];
juansal12 0:c792b17d9f78 135 __IO uint32_t EXTINT; /* External Interrupts */
juansal12 0:c792b17d9f78 136 uint32_t RESERVED5;
juansal12 0:c792b17d9f78 137 __IO uint32_t EXTMODE;
juansal12 0:c792b17d9f78 138 __IO uint32_t EXTPOLAR;
juansal12 0:c792b17d9f78 139 uint32_t RESERVED6[12];
juansal12 0:c792b17d9f78 140 __IO uint32_t RSID; /* Reset */
juansal12 0:c792b17d9f78 141 uint32_t RESERVED7[7];
juansal12 0:c792b17d9f78 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
juansal12 0:c792b17d9f78 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
juansal12 0:c792b17d9f78 144 __IO uint32_t PCLKSEL0;
juansal12 0:c792b17d9f78 145 __IO uint32_t PCLKSEL1;
juansal12 0:c792b17d9f78 146 uint32_t RESERVED8[4];
juansal12 0:c792b17d9f78 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
juansal12 0:c792b17d9f78 148 __IO uint32_t DMAREQSEL;
juansal12 0:c792b17d9f78 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
juansal12 0:c792b17d9f78 150 } LPC_SC_TypeDef;
juansal12 0:c792b17d9f78 151
juansal12 0:c792b17d9f78 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
juansal12 0:c792b17d9f78 153 typedef struct
juansal12 0:c792b17d9f78 154 {
juansal12 0:c792b17d9f78 155 __IO uint32_t PINSEL0;
juansal12 0:c792b17d9f78 156 __IO uint32_t PINSEL1;
juansal12 0:c792b17d9f78 157 __IO uint32_t PINSEL2;
juansal12 0:c792b17d9f78 158 __IO uint32_t PINSEL3;
juansal12 0:c792b17d9f78 159 __IO uint32_t PINSEL4;
juansal12 0:c792b17d9f78 160 __IO uint32_t PINSEL5;
juansal12 0:c792b17d9f78 161 __IO uint32_t PINSEL6;
juansal12 0:c792b17d9f78 162 __IO uint32_t PINSEL7;
juansal12 0:c792b17d9f78 163 __IO uint32_t PINSEL8;
juansal12 0:c792b17d9f78 164 __IO uint32_t PINSEL9;
juansal12 0:c792b17d9f78 165 __IO uint32_t PINSEL10;
juansal12 0:c792b17d9f78 166 uint32_t RESERVED0[5];
juansal12 0:c792b17d9f78 167 __IO uint32_t PINMODE0;
juansal12 0:c792b17d9f78 168 __IO uint32_t PINMODE1;
juansal12 0:c792b17d9f78 169 __IO uint32_t PINMODE2;
juansal12 0:c792b17d9f78 170 __IO uint32_t PINMODE3;
juansal12 0:c792b17d9f78 171 __IO uint32_t PINMODE4;
juansal12 0:c792b17d9f78 172 __IO uint32_t PINMODE5;
juansal12 0:c792b17d9f78 173 __IO uint32_t PINMODE6;
juansal12 0:c792b17d9f78 174 __IO uint32_t PINMODE7;
juansal12 0:c792b17d9f78 175 __IO uint32_t PINMODE8;
juansal12 0:c792b17d9f78 176 __IO uint32_t PINMODE9;
juansal12 0:c792b17d9f78 177 __IO uint32_t PINMODE_OD0;
juansal12 0:c792b17d9f78 178 __IO uint32_t PINMODE_OD1;
juansal12 0:c792b17d9f78 179 __IO uint32_t PINMODE_OD2;
juansal12 0:c792b17d9f78 180 __IO uint32_t PINMODE_OD3;
juansal12 0:c792b17d9f78 181 __IO uint32_t PINMODE_OD4;
juansal12 0:c792b17d9f78 182 __IO uint32_t I2CPADCFG;
juansal12 0:c792b17d9f78 183 } LPC_PINCON_TypeDef;
juansal12 0:c792b17d9f78 184
juansal12 0:c792b17d9f78 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
juansal12 0:c792b17d9f78 186 typedef struct
juansal12 0:c792b17d9f78 187 {
juansal12 0:c792b17d9f78 188 union {
juansal12 0:c792b17d9f78 189 __IO uint32_t FIODIR;
juansal12 0:c792b17d9f78 190 struct {
juansal12 0:c792b17d9f78 191 __IO uint16_t FIODIRL;
juansal12 0:c792b17d9f78 192 __IO uint16_t FIODIRH;
juansal12 0:c792b17d9f78 193 };
juansal12 0:c792b17d9f78 194 struct {
juansal12 0:c792b17d9f78 195 __IO uint8_t FIODIR0;
juansal12 0:c792b17d9f78 196 __IO uint8_t FIODIR1;
juansal12 0:c792b17d9f78 197 __IO uint8_t FIODIR2;
juansal12 0:c792b17d9f78 198 __IO uint8_t FIODIR3;
juansal12 0:c792b17d9f78 199 };
juansal12 0:c792b17d9f78 200 };
juansal12 0:c792b17d9f78 201 uint32_t RESERVED0[3];
juansal12 0:c792b17d9f78 202 union {
juansal12 0:c792b17d9f78 203 __IO uint32_t FIOMASK;
juansal12 0:c792b17d9f78 204 struct {
juansal12 0:c792b17d9f78 205 __IO uint16_t FIOMASKL;
juansal12 0:c792b17d9f78 206 __IO uint16_t FIOMASKH;
juansal12 0:c792b17d9f78 207 };
juansal12 0:c792b17d9f78 208 struct {
juansal12 0:c792b17d9f78 209 __IO uint8_t FIOMASK0;
juansal12 0:c792b17d9f78 210 __IO uint8_t FIOMASK1;
juansal12 0:c792b17d9f78 211 __IO uint8_t FIOMASK2;
juansal12 0:c792b17d9f78 212 __IO uint8_t FIOMASK3;
juansal12 0:c792b17d9f78 213 };
juansal12 0:c792b17d9f78 214 };
juansal12 0:c792b17d9f78 215 union {
juansal12 0:c792b17d9f78 216 __IO uint32_t FIOPIN;
juansal12 0:c792b17d9f78 217 struct {
juansal12 0:c792b17d9f78 218 __IO uint16_t FIOPINL;
juansal12 0:c792b17d9f78 219 __IO uint16_t FIOPINH;
juansal12 0:c792b17d9f78 220 };
juansal12 0:c792b17d9f78 221 struct {
juansal12 0:c792b17d9f78 222 __IO uint8_t FIOPIN0;
juansal12 0:c792b17d9f78 223 __IO uint8_t FIOPIN1;
juansal12 0:c792b17d9f78 224 __IO uint8_t FIOPIN2;
juansal12 0:c792b17d9f78 225 __IO uint8_t FIOPIN3;
juansal12 0:c792b17d9f78 226 };
juansal12 0:c792b17d9f78 227 };
juansal12 0:c792b17d9f78 228 union {
juansal12 0:c792b17d9f78 229 __IO uint32_t FIOSET;
juansal12 0:c792b17d9f78 230 struct {
juansal12 0:c792b17d9f78 231 __IO uint16_t FIOSETL;
juansal12 0:c792b17d9f78 232 __IO uint16_t FIOSETH;
juansal12 0:c792b17d9f78 233 };
juansal12 0:c792b17d9f78 234 struct {
juansal12 0:c792b17d9f78 235 __IO uint8_t FIOSET0;
juansal12 0:c792b17d9f78 236 __IO uint8_t FIOSET1;
juansal12 0:c792b17d9f78 237 __IO uint8_t FIOSET2;
juansal12 0:c792b17d9f78 238 __IO uint8_t FIOSET3;
juansal12 0:c792b17d9f78 239 };
juansal12 0:c792b17d9f78 240 };
juansal12 0:c792b17d9f78 241 union {
juansal12 0:c792b17d9f78 242 __O uint32_t FIOCLR;
juansal12 0:c792b17d9f78 243 struct {
juansal12 0:c792b17d9f78 244 __O uint16_t FIOCLRL;
juansal12 0:c792b17d9f78 245 __O uint16_t FIOCLRH;
juansal12 0:c792b17d9f78 246 };
juansal12 0:c792b17d9f78 247 struct {
juansal12 0:c792b17d9f78 248 __O uint8_t FIOCLR0;
juansal12 0:c792b17d9f78 249 __O uint8_t FIOCLR1;
juansal12 0:c792b17d9f78 250 __O uint8_t FIOCLR2;
juansal12 0:c792b17d9f78 251 __O uint8_t FIOCLR3;
juansal12 0:c792b17d9f78 252 };
juansal12 0:c792b17d9f78 253 };
juansal12 0:c792b17d9f78 254 } LPC_GPIO_TypeDef;
juansal12 0:c792b17d9f78 255
juansal12 0:c792b17d9f78 256 typedef struct
juansal12 0:c792b17d9f78 257 {
juansal12 0:c792b17d9f78 258 __I uint32_t IntStatus;
juansal12 0:c792b17d9f78 259 __I uint32_t IO0IntStatR;
juansal12 0:c792b17d9f78 260 __I uint32_t IO0IntStatF;
juansal12 0:c792b17d9f78 261 __O uint32_t IO0IntClr;
juansal12 0:c792b17d9f78 262 __IO uint32_t IO0IntEnR;
juansal12 0:c792b17d9f78 263 __IO uint32_t IO0IntEnF;
juansal12 0:c792b17d9f78 264 uint32_t RESERVED0[3];
juansal12 0:c792b17d9f78 265 __I uint32_t IO2IntStatR;
juansal12 0:c792b17d9f78 266 __I uint32_t IO2IntStatF;
juansal12 0:c792b17d9f78 267 __O uint32_t IO2IntClr;
juansal12 0:c792b17d9f78 268 __IO uint32_t IO2IntEnR;
juansal12 0:c792b17d9f78 269 __IO uint32_t IO2IntEnF;
juansal12 0:c792b17d9f78 270 } LPC_GPIOINT_TypeDef;
juansal12 0:c792b17d9f78 271
juansal12 0:c792b17d9f78 272 /*------------- Timer (TIM) --------------------------------------------------*/
juansal12 0:c792b17d9f78 273 typedef struct
juansal12 0:c792b17d9f78 274 {
juansal12 0:c792b17d9f78 275 __IO uint32_t IR;
juansal12 0:c792b17d9f78 276 __IO uint32_t TCR;
juansal12 0:c792b17d9f78 277 __IO uint32_t TC;
juansal12 0:c792b17d9f78 278 __IO uint32_t PR;
juansal12 0:c792b17d9f78 279 __IO uint32_t PC;
juansal12 0:c792b17d9f78 280 __IO uint32_t MCR;
juansal12 0:c792b17d9f78 281 __IO uint32_t MR0;
juansal12 0:c792b17d9f78 282 __IO uint32_t MR1;
juansal12 0:c792b17d9f78 283 __IO uint32_t MR2;
juansal12 0:c792b17d9f78 284 __IO uint32_t MR3;
juansal12 0:c792b17d9f78 285 __IO uint32_t CCR;
juansal12 0:c792b17d9f78 286 __I uint32_t CR0;
juansal12 0:c792b17d9f78 287 __I uint32_t CR1;
juansal12 0:c792b17d9f78 288 uint32_t RESERVED0[2];
juansal12 0:c792b17d9f78 289 __IO uint32_t EMR;
juansal12 0:c792b17d9f78 290 uint32_t RESERVED1[12];
juansal12 0:c792b17d9f78 291 __IO uint32_t CTCR;
juansal12 0:c792b17d9f78 292 } LPC_TIM_TypeDef;
juansal12 0:c792b17d9f78 293
juansal12 0:c792b17d9f78 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
juansal12 0:c792b17d9f78 295 typedef struct
juansal12 0:c792b17d9f78 296 {
juansal12 0:c792b17d9f78 297 __IO uint32_t IR;
juansal12 0:c792b17d9f78 298 __IO uint32_t TCR;
juansal12 0:c792b17d9f78 299 __IO uint32_t TC;
juansal12 0:c792b17d9f78 300 __IO uint32_t PR;
juansal12 0:c792b17d9f78 301 __IO uint32_t PC;
juansal12 0:c792b17d9f78 302 __IO uint32_t MCR;
juansal12 0:c792b17d9f78 303 __IO uint32_t MR0;
juansal12 0:c792b17d9f78 304 __IO uint32_t MR1;
juansal12 0:c792b17d9f78 305 __IO uint32_t MR2;
juansal12 0:c792b17d9f78 306 __IO uint32_t MR3;
juansal12 0:c792b17d9f78 307 __IO uint32_t CCR;
juansal12 0:c792b17d9f78 308 __I uint32_t CR0;
juansal12 0:c792b17d9f78 309 __I uint32_t CR1;
juansal12 0:c792b17d9f78 310 __I uint32_t CR2;
juansal12 0:c792b17d9f78 311 __I uint32_t CR3;
juansal12 0:c792b17d9f78 312 uint32_t RESERVED0;
juansal12 0:c792b17d9f78 313 __IO uint32_t MR4;
juansal12 0:c792b17d9f78 314 __IO uint32_t MR5;
juansal12 0:c792b17d9f78 315 __IO uint32_t MR6;
juansal12 0:c792b17d9f78 316 __IO uint32_t PCR;
juansal12 0:c792b17d9f78 317 __IO uint32_t LER;
juansal12 0:c792b17d9f78 318 uint32_t RESERVED1[7];
juansal12 0:c792b17d9f78 319 __IO uint32_t CTCR;
juansal12 0:c792b17d9f78 320 } LPC_PWM_TypeDef;
juansal12 0:c792b17d9f78 321
juansal12 0:c792b17d9f78 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
juansal12 0:c792b17d9f78 323 typedef struct
juansal12 0:c792b17d9f78 324 {
juansal12 0:c792b17d9f78 325 union {
juansal12 0:c792b17d9f78 326 __I uint8_t RBR;
juansal12 0:c792b17d9f78 327 __O uint8_t THR;
juansal12 0:c792b17d9f78 328 __IO uint8_t DLL;
juansal12 0:c792b17d9f78 329 uint32_t RESERVED0;
juansal12 0:c792b17d9f78 330 };
juansal12 0:c792b17d9f78 331 union {
juansal12 0:c792b17d9f78 332 __IO uint8_t DLM;
juansal12 0:c792b17d9f78 333 __IO uint32_t IER;
juansal12 0:c792b17d9f78 334 };
juansal12 0:c792b17d9f78 335 union {
juansal12 0:c792b17d9f78 336 __I uint32_t IIR;
juansal12 0:c792b17d9f78 337 __O uint8_t FCR;
juansal12 0:c792b17d9f78 338 };
juansal12 0:c792b17d9f78 339 __IO uint8_t LCR;
juansal12 0:c792b17d9f78 340 uint8_t RESERVED1[7];
juansal12 0:c792b17d9f78 341 __I uint8_t LSR;
juansal12 0:c792b17d9f78 342 uint8_t RESERVED2[7];
juansal12 0:c792b17d9f78 343 __IO uint8_t SCR;
juansal12 0:c792b17d9f78 344 uint8_t RESERVED3[3];
juansal12 0:c792b17d9f78 345 __IO uint32_t ACR;
juansal12 0:c792b17d9f78 346 __IO uint8_t ICR;
juansal12 0:c792b17d9f78 347 uint8_t RESERVED4[3];
juansal12 0:c792b17d9f78 348 __IO uint8_t FDR;
juansal12 0:c792b17d9f78 349 uint8_t RESERVED5[7];
juansal12 0:c792b17d9f78 350 __IO uint8_t TER;
juansal12 0:c792b17d9f78 351 uint8_t RESERVED6[39];
juansal12 0:c792b17d9f78 352 __IO uint32_t FIFOLVL;
juansal12 0:c792b17d9f78 353 } LPC_UART_TypeDef;
juansal12 0:c792b17d9f78 354
juansal12 0:c792b17d9f78 355 typedef struct
juansal12 0:c792b17d9f78 356 {
juansal12 0:c792b17d9f78 357 union {
juansal12 0:c792b17d9f78 358 __I uint8_t RBR;
juansal12 0:c792b17d9f78 359 __O uint8_t THR;
juansal12 0:c792b17d9f78 360 __IO uint8_t DLL;
juansal12 0:c792b17d9f78 361 uint32_t RESERVED0;
juansal12 0:c792b17d9f78 362 };
juansal12 0:c792b17d9f78 363 union {
juansal12 0:c792b17d9f78 364 __IO uint8_t DLM;
juansal12 0:c792b17d9f78 365 __IO uint32_t IER;
juansal12 0:c792b17d9f78 366 };
juansal12 0:c792b17d9f78 367 union {
juansal12 0:c792b17d9f78 368 __I uint32_t IIR;
juansal12 0:c792b17d9f78 369 __O uint8_t FCR;
juansal12 0:c792b17d9f78 370 };
juansal12 0:c792b17d9f78 371 __IO uint8_t LCR;
juansal12 0:c792b17d9f78 372 uint8_t RESERVED1[7];
juansal12 0:c792b17d9f78 373 __I uint8_t LSR;
juansal12 0:c792b17d9f78 374 uint8_t RESERVED2[7];
juansal12 0:c792b17d9f78 375 __IO uint8_t SCR;
juansal12 0:c792b17d9f78 376 uint8_t RESERVED3[3];
juansal12 0:c792b17d9f78 377 __IO uint32_t ACR;
juansal12 0:c792b17d9f78 378 __IO uint8_t ICR;
juansal12 0:c792b17d9f78 379 uint8_t RESERVED4[3];
juansal12 0:c792b17d9f78 380 __IO uint8_t FDR;
juansal12 0:c792b17d9f78 381 uint8_t RESERVED5[7];
juansal12 0:c792b17d9f78 382 __IO uint8_t TER;
juansal12 0:c792b17d9f78 383 uint8_t RESERVED6[39];
juansal12 0:c792b17d9f78 384 __IO uint32_t FIFOLVL;
juansal12 0:c792b17d9f78 385 } LPC_UART0_TypeDef;
juansal12 0:c792b17d9f78 386
juansal12 0:c792b17d9f78 387 typedef struct
juansal12 0:c792b17d9f78 388 {
juansal12 0:c792b17d9f78 389 union {
juansal12 0:c792b17d9f78 390 __I uint8_t RBR;
juansal12 0:c792b17d9f78 391 __O uint8_t THR;
juansal12 0:c792b17d9f78 392 __IO uint8_t DLL;
juansal12 0:c792b17d9f78 393 uint32_t RESERVED0;
juansal12 0:c792b17d9f78 394 };
juansal12 0:c792b17d9f78 395 union {
juansal12 0:c792b17d9f78 396 __IO uint8_t DLM;
juansal12 0:c792b17d9f78 397 __IO uint32_t IER;
juansal12 0:c792b17d9f78 398 };
juansal12 0:c792b17d9f78 399 union {
juansal12 0:c792b17d9f78 400 __I uint32_t IIR;
juansal12 0:c792b17d9f78 401 __O uint8_t FCR;
juansal12 0:c792b17d9f78 402 };
juansal12 0:c792b17d9f78 403 __IO uint8_t LCR;
juansal12 0:c792b17d9f78 404 uint8_t RESERVED1[3];
juansal12 0:c792b17d9f78 405 __IO uint8_t MCR;
juansal12 0:c792b17d9f78 406 uint8_t RESERVED2[3];
juansal12 0:c792b17d9f78 407 __I uint8_t LSR;
juansal12 0:c792b17d9f78 408 uint8_t RESERVED3[3];
juansal12 0:c792b17d9f78 409 __I uint8_t MSR;
juansal12 0:c792b17d9f78 410 uint8_t RESERVED4[3];
juansal12 0:c792b17d9f78 411 __IO uint8_t SCR;
juansal12 0:c792b17d9f78 412 uint8_t RESERVED5[3];
juansal12 0:c792b17d9f78 413 __IO uint32_t ACR;
juansal12 0:c792b17d9f78 414 uint32_t RESERVED6;
juansal12 0:c792b17d9f78 415 __IO uint32_t FDR;
juansal12 0:c792b17d9f78 416 uint32_t RESERVED7;
juansal12 0:c792b17d9f78 417 __IO uint8_t TER;
juansal12 0:c792b17d9f78 418 uint8_t RESERVED8[27];
juansal12 0:c792b17d9f78 419 __IO uint8_t RS485CTRL;
juansal12 0:c792b17d9f78 420 uint8_t RESERVED9[3];
juansal12 0:c792b17d9f78 421 __IO uint8_t ADRMATCH;
juansal12 0:c792b17d9f78 422 uint8_t RESERVED10[3];
juansal12 0:c792b17d9f78 423 __IO uint8_t RS485DLY;
juansal12 0:c792b17d9f78 424 uint8_t RESERVED11[3];
juansal12 0:c792b17d9f78 425 __IO uint32_t FIFOLVL;
juansal12 0:c792b17d9f78 426 } LPC_UART1_TypeDef;
juansal12 0:c792b17d9f78 427
juansal12 0:c792b17d9f78 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
juansal12 0:c792b17d9f78 429 typedef struct
juansal12 0:c792b17d9f78 430 {
juansal12 0:c792b17d9f78 431 __IO uint32_t SPCR;
juansal12 0:c792b17d9f78 432 __I uint32_t SPSR;
juansal12 0:c792b17d9f78 433 __IO uint32_t SPDR;
juansal12 0:c792b17d9f78 434 __IO uint32_t SPCCR;
juansal12 0:c792b17d9f78 435 uint32_t RESERVED0[3];
juansal12 0:c792b17d9f78 436 __IO uint32_t SPINT;
juansal12 0:c792b17d9f78 437 } LPC_SPI_TypeDef;
juansal12 0:c792b17d9f78 438
juansal12 0:c792b17d9f78 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
juansal12 0:c792b17d9f78 440 typedef struct
juansal12 0:c792b17d9f78 441 {
juansal12 0:c792b17d9f78 442 __IO uint32_t CR0;
juansal12 0:c792b17d9f78 443 __IO uint32_t CR1;
juansal12 0:c792b17d9f78 444 __IO uint32_t DR;
juansal12 0:c792b17d9f78 445 __I uint32_t SR;
juansal12 0:c792b17d9f78 446 __IO uint32_t CPSR;
juansal12 0:c792b17d9f78 447 __IO uint32_t IMSC;
juansal12 0:c792b17d9f78 448 __IO uint32_t RIS;
juansal12 0:c792b17d9f78 449 __IO uint32_t MIS;
juansal12 0:c792b17d9f78 450 __IO uint32_t ICR;
juansal12 0:c792b17d9f78 451 __IO uint32_t DMACR;
juansal12 0:c792b17d9f78 452 } LPC_SSP_TypeDef;
juansal12 0:c792b17d9f78 453
juansal12 0:c792b17d9f78 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
juansal12 0:c792b17d9f78 455 typedef struct
juansal12 0:c792b17d9f78 456 {
juansal12 0:c792b17d9f78 457 __IO uint32_t I2CONSET;
juansal12 0:c792b17d9f78 458 __I uint32_t I2STAT;
juansal12 0:c792b17d9f78 459 __IO uint32_t I2DAT;
juansal12 0:c792b17d9f78 460 __IO uint32_t I2ADR0;
juansal12 0:c792b17d9f78 461 __IO uint32_t I2SCLH;
juansal12 0:c792b17d9f78 462 __IO uint32_t I2SCLL;
juansal12 0:c792b17d9f78 463 __O uint32_t I2CONCLR;
juansal12 0:c792b17d9f78 464 __IO uint32_t MMCTRL;
juansal12 0:c792b17d9f78 465 __IO uint32_t I2ADR1;
juansal12 0:c792b17d9f78 466 __IO uint32_t I2ADR2;
juansal12 0:c792b17d9f78 467 __IO uint32_t I2ADR3;
juansal12 0:c792b17d9f78 468 __I uint32_t I2DATA_BUFFER;
juansal12 0:c792b17d9f78 469 __IO uint32_t I2MASK0;
juansal12 0:c792b17d9f78 470 __IO uint32_t I2MASK1;
juansal12 0:c792b17d9f78 471 __IO uint32_t I2MASK2;
juansal12 0:c792b17d9f78 472 __IO uint32_t I2MASK3;
juansal12 0:c792b17d9f78 473 } LPC_I2C_TypeDef;
juansal12 0:c792b17d9f78 474
juansal12 0:c792b17d9f78 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
juansal12 0:c792b17d9f78 476 typedef struct
juansal12 0:c792b17d9f78 477 {
juansal12 0:c792b17d9f78 478 __IO uint32_t I2SDAO;
juansal12 0:c792b17d9f78 479 __IO uint32_t I2SDAI;
juansal12 0:c792b17d9f78 480 __O uint32_t I2STXFIFO;
juansal12 0:c792b17d9f78 481 __I uint32_t I2SRXFIFO;
juansal12 0:c792b17d9f78 482 __I uint32_t I2SSTATE;
juansal12 0:c792b17d9f78 483 __IO uint32_t I2SDMA1;
juansal12 0:c792b17d9f78 484 __IO uint32_t I2SDMA2;
juansal12 0:c792b17d9f78 485 __IO uint32_t I2SIRQ;
juansal12 0:c792b17d9f78 486 __IO uint32_t I2STXRATE;
juansal12 0:c792b17d9f78 487 __IO uint32_t I2SRXRATE;
juansal12 0:c792b17d9f78 488 __IO uint32_t I2STXBITRATE;
juansal12 0:c792b17d9f78 489 __IO uint32_t I2SRXBITRATE;
juansal12 0:c792b17d9f78 490 __IO uint32_t I2STXMODE;
juansal12 0:c792b17d9f78 491 __IO uint32_t I2SRXMODE;
juansal12 0:c792b17d9f78 492 } LPC_I2S_TypeDef;
juansal12 0:c792b17d9f78 493
juansal12 0:c792b17d9f78 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
juansal12 0:c792b17d9f78 495 typedef struct
juansal12 0:c792b17d9f78 496 {
juansal12 0:c792b17d9f78 497 __IO uint32_t RICOMPVAL;
juansal12 0:c792b17d9f78 498 __IO uint32_t RIMASK;
juansal12 0:c792b17d9f78 499 __IO uint8_t RICTRL;
juansal12 0:c792b17d9f78 500 uint8_t RESERVED0[3];
juansal12 0:c792b17d9f78 501 __IO uint32_t RICOUNTER;
juansal12 0:c792b17d9f78 502 } LPC_RIT_TypeDef;
juansal12 0:c792b17d9f78 503
juansal12 0:c792b17d9f78 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
juansal12 0:c792b17d9f78 505 typedef struct
juansal12 0:c792b17d9f78 506 {
juansal12 0:c792b17d9f78 507 __IO uint8_t ILR;
juansal12 0:c792b17d9f78 508 uint8_t RESERVED0[7];
juansal12 0:c792b17d9f78 509 __IO uint8_t CCR;
juansal12 0:c792b17d9f78 510 uint8_t RESERVED1[3];
juansal12 0:c792b17d9f78 511 __IO uint8_t CIIR;
juansal12 0:c792b17d9f78 512 uint8_t RESERVED2[3];
juansal12 0:c792b17d9f78 513 __IO uint8_t AMR;
juansal12 0:c792b17d9f78 514 uint8_t RESERVED3[3];
juansal12 0:c792b17d9f78 515 __I uint32_t CTIME0;
juansal12 0:c792b17d9f78 516 __I uint32_t CTIME1;
juansal12 0:c792b17d9f78 517 __I uint32_t CTIME2;
juansal12 0:c792b17d9f78 518 __IO uint8_t SEC;
juansal12 0:c792b17d9f78 519 uint8_t RESERVED4[3];
juansal12 0:c792b17d9f78 520 __IO uint8_t MIN;
juansal12 0:c792b17d9f78 521 uint8_t RESERVED5[3];
juansal12 0:c792b17d9f78 522 __IO uint8_t HOUR;
juansal12 0:c792b17d9f78 523 uint8_t RESERVED6[3];
juansal12 0:c792b17d9f78 524 __IO uint8_t DOM;
juansal12 0:c792b17d9f78 525 uint8_t RESERVED7[3];
juansal12 0:c792b17d9f78 526 __IO uint8_t DOW;
juansal12 0:c792b17d9f78 527 uint8_t RESERVED8[3];
juansal12 0:c792b17d9f78 528 __IO uint16_t DOY;
juansal12 0:c792b17d9f78 529 uint16_t RESERVED9;
juansal12 0:c792b17d9f78 530 __IO uint8_t MONTH;
juansal12 0:c792b17d9f78 531 uint8_t RESERVED10[3];
juansal12 0:c792b17d9f78 532 __IO uint16_t YEAR;
juansal12 0:c792b17d9f78 533 uint16_t RESERVED11;
juansal12 0:c792b17d9f78 534 __IO uint32_t CALIBRATION;
juansal12 0:c792b17d9f78 535 __IO uint32_t GPREG0;
juansal12 0:c792b17d9f78 536 __IO uint32_t GPREG1;
juansal12 0:c792b17d9f78 537 __IO uint32_t GPREG2;
juansal12 0:c792b17d9f78 538 __IO uint32_t GPREG3;
juansal12 0:c792b17d9f78 539 __IO uint32_t GPREG4;
juansal12 0:c792b17d9f78 540 __IO uint8_t RTC_AUXEN;
juansal12 0:c792b17d9f78 541 uint8_t RESERVED12[3];
juansal12 0:c792b17d9f78 542 __IO uint8_t RTC_AUX;
juansal12 0:c792b17d9f78 543 uint8_t RESERVED13[3];
juansal12 0:c792b17d9f78 544 __IO uint8_t ALSEC;
juansal12 0:c792b17d9f78 545 uint8_t RESERVED14[3];
juansal12 0:c792b17d9f78 546 __IO uint8_t ALMIN;
juansal12 0:c792b17d9f78 547 uint8_t RESERVED15[3];
juansal12 0:c792b17d9f78 548 __IO uint8_t ALHOUR;
juansal12 0:c792b17d9f78 549 uint8_t RESERVED16[3];
juansal12 0:c792b17d9f78 550 __IO uint8_t ALDOM;
juansal12 0:c792b17d9f78 551 uint8_t RESERVED17[3];
juansal12 0:c792b17d9f78 552 __IO uint8_t ALDOW;
juansal12 0:c792b17d9f78 553 uint8_t RESERVED18[3];
juansal12 0:c792b17d9f78 554 __IO uint16_t ALDOY;
juansal12 0:c792b17d9f78 555 uint16_t RESERVED19;
juansal12 0:c792b17d9f78 556 __IO uint8_t ALMON;
juansal12 0:c792b17d9f78 557 uint8_t RESERVED20[3];
juansal12 0:c792b17d9f78 558 __IO uint16_t ALYEAR;
juansal12 0:c792b17d9f78 559 uint16_t RESERVED21;
juansal12 0:c792b17d9f78 560 } LPC_RTC_TypeDef;
juansal12 0:c792b17d9f78 561
juansal12 0:c792b17d9f78 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
juansal12 0:c792b17d9f78 563 typedef struct
juansal12 0:c792b17d9f78 564 {
juansal12 0:c792b17d9f78 565 __IO uint8_t WDMOD;
juansal12 0:c792b17d9f78 566 uint8_t RESERVED0[3];
juansal12 0:c792b17d9f78 567 __IO uint32_t WDTC;
juansal12 0:c792b17d9f78 568 __O uint8_t WDFEED;
juansal12 0:c792b17d9f78 569 uint8_t RESERVED1[3];
juansal12 0:c792b17d9f78 570 __I uint32_t WDTV;
juansal12 0:c792b17d9f78 571 __IO uint32_t WDCLKSEL;
juansal12 0:c792b17d9f78 572 } LPC_WDT_TypeDef;
juansal12 0:c792b17d9f78 573
juansal12 0:c792b17d9f78 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
juansal12 0:c792b17d9f78 575 typedef struct
juansal12 0:c792b17d9f78 576 {
juansal12 0:c792b17d9f78 577 __IO uint32_t ADCR;
juansal12 0:c792b17d9f78 578 __IO uint32_t ADGDR;
juansal12 0:c792b17d9f78 579 uint32_t RESERVED0;
juansal12 0:c792b17d9f78 580 __IO uint32_t ADINTEN;
juansal12 0:c792b17d9f78 581 __I uint32_t ADDR0;
juansal12 0:c792b17d9f78 582 __I uint32_t ADDR1;
juansal12 0:c792b17d9f78 583 __I uint32_t ADDR2;
juansal12 0:c792b17d9f78 584 __I uint32_t ADDR3;
juansal12 0:c792b17d9f78 585 __I uint32_t ADDR4;
juansal12 0:c792b17d9f78 586 __I uint32_t ADDR5;
juansal12 0:c792b17d9f78 587 __I uint32_t ADDR6;
juansal12 0:c792b17d9f78 588 __I uint32_t ADDR7;
juansal12 0:c792b17d9f78 589 __I uint32_t ADSTAT;
juansal12 0:c792b17d9f78 590 __IO uint32_t ADTRM;
juansal12 0:c792b17d9f78 591 } LPC_ADC_TypeDef;
juansal12 0:c792b17d9f78 592
juansal12 0:c792b17d9f78 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
juansal12 0:c792b17d9f78 594 typedef struct
juansal12 0:c792b17d9f78 595 {
juansal12 0:c792b17d9f78 596 __IO uint32_t DACR;
juansal12 0:c792b17d9f78 597 __IO uint32_t DACCTRL;
juansal12 0:c792b17d9f78 598 __IO uint16_t DACCNTVAL;
juansal12 0:c792b17d9f78 599 } LPC_DAC_TypeDef;
juansal12 0:c792b17d9f78 600
juansal12 0:c792b17d9f78 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
juansal12 0:c792b17d9f78 602 typedef struct
juansal12 0:c792b17d9f78 603 {
juansal12 0:c792b17d9f78 604 __I uint32_t MCCON;
juansal12 0:c792b17d9f78 605 __O uint32_t MCCON_SET;
juansal12 0:c792b17d9f78 606 __O uint32_t MCCON_CLR;
juansal12 0:c792b17d9f78 607 __I uint32_t MCCAPCON;
juansal12 0:c792b17d9f78 608 __O uint32_t MCCAPCON_SET;
juansal12 0:c792b17d9f78 609 __O uint32_t MCCAPCON_CLR;
juansal12 0:c792b17d9f78 610 __IO uint32_t MCTIM0;
juansal12 0:c792b17d9f78 611 __IO uint32_t MCTIM1;
juansal12 0:c792b17d9f78 612 __IO uint32_t MCTIM2;
juansal12 0:c792b17d9f78 613 __IO uint32_t MCPER0;
juansal12 0:c792b17d9f78 614 __IO uint32_t MCPER1;
juansal12 0:c792b17d9f78 615 __IO uint32_t MCPER2;
juansal12 0:c792b17d9f78 616 __IO uint32_t MCPW0;
juansal12 0:c792b17d9f78 617 __IO uint32_t MCPW1;
juansal12 0:c792b17d9f78 618 __IO uint32_t MCPW2;
juansal12 0:c792b17d9f78 619 __IO uint32_t MCDEADTIME;
juansal12 0:c792b17d9f78 620 __IO uint32_t MCCCP;
juansal12 0:c792b17d9f78 621 __IO uint32_t MCCR0;
juansal12 0:c792b17d9f78 622 __IO uint32_t MCCR1;
juansal12 0:c792b17d9f78 623 __IO uint32_t MCCR2;
juansal12 0:c792b17d9f78 624 __I uint32_t MCINTEN;
juansal12 0:c792b17d9f78 625 __O uint32_t MCINTEN_SET;
juansal12 0:c792b17d9f78 626 __O uint32_t MCINTEN_CLR;
juansal12 0:c792b17d9f78 627 __I uint32_t MCCNTCON;
juansal12 0:c792b17d9f78 628 __O uint32_t MCCNTCON_SET;
juansal12 0:c792b17d9f78 629 __O uint32_t MCCNTCON_CLR;
juansal12 0:c792b17d9f78 630 __I uint32_t MCINTFLAG;
juansal12 0:c792b17d9f78 631 __O uint32_t MCINTFLAG_SET;
juansal12 0:c792b17d9f78 632 __O uint32_t MCINTFLAG_CLR;
juansal12 0:c792b17d9f78 633 __O uint32_t MCCAP_CLR;
juansal12 0:c792b17d9f78 634 } LPC_MCPWM_TypeDef;
juansal12 0:c792b17d9f78 635
juansal12 0:c792b17d9f78 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
juansal12 0:c792b17d9f78 637 typedef struct
juansal12 0:c792b17d9f78 638 {
juansal12 0:c792b17d9f78 639 __O uint32_t QEICON;
juansal12 0:c792b17d9f78 640 __I uint32_t QEISTAT;
juansal12 0:c792b17d9f78 641 __IO uint32_t QEICONF;
juansal12 0:c792b17d9f78 642 __I uint32_t QEIPOS;
juansal12 0:c792b17d9f78 643 __IO uint32_t QEIMAXPOS;
juansal12 0:c792b17d9f78 644 __IO uint32_t CMPOS0;
juansal12 0:c792b17d9f78 645 __IO uint32_t CMPOS1;
juansal12 0:c792b17d9f78 646 __IO uint32_t CMPOS2;
juansal12 0:c792b17d9f78 647 __I uint32_t INXCNT;
juansal12 0:c792b17d9f78 648 __IO uint32_t INXCMP;
juansal12 0:c792b17d9f78 649 __IO uint32_t QEILOAD;
juansal12 0:c792b17d9f78 650 __I uint32_t QEITIME;
juansal12 0:c792b17d9f78 651 __I uint32_t QEIVEL;
juansal12 0:c792b17d9f78 652 __I uint32_t QEICAP;
juansal12 0:c792b17d9f78 653 __IO uint32_t VELCOMP;
juansal12 0:c792b17d9f78 654 __IO uint32_t FILTER;
juansal12 0:c792b17d9f78 655 uint32_t RESERVED0[998];
juansal12 0:c792b17d9f78 656 __O uint32_t QEIIEC;
juansal12 0:c792b17d9f78 657 __O uint32_t QEIIES;
juansal12 0:c792b17d9f78 658 __I uint32_t QEIINTSTAT;
juansal12 0:c792b17d9f78 659 __I uint32_t QEIIE;
juansal12 0:c792b17d9f78 660 __O uint32_t QEICLR;
juansal12 0:c792b17d9f78 661 __O uint32_t QEISET;
juansal12 0:c792b17d9f78 662 } LPC_QEI_TypeDef;
juansal12 0:c792b17d9f78 663
juansal12 0:c792b17d9f78 664 /*------------- Controller Area Network (CAN) --------------------------------*/
juansal12 0:c792b17d9f78 665 typedef struct
juansal12 0:c792b17d9f78 666 {
juansal12 0:c792b17d9f78 667 __IO uint32_t mask[512]; /* ID Masks */
juansal12 0:c792b17d9f78 668 } LPC_CANAF_RAM_TypeDef;
juansal12 0:c792b17d9f78 669
juansal12 0:c792b17d9f78 670 typedef struct /* Acceptance Filter Registers */
juansal12 0:c792b17d9f78 671 {
juansal12 0:c792b17d9f78 672 __IO uint32_t AFMR;
juansal12 0:c792b17d9f78 673 __IO uint32_t SFF_sa;
juansal12 0:c792b17d9f78 674 __IO uint32_t SFF_GRP_sa;
juansal12 0:c792b17d9f78 675 __IO uint32_t EFF_sa;
juansal12 0:c792b17d9f78 676 __IO uint32_t EFF_GRP_sa;
juansal12 0:c792b17d9f78 677 __IO uint32_t ENDofTable;
juansal12 0:c792b17d9f78 678 __I uint32_t LUTerrAd;
juansal12 0:c792b17d9f78 679 __I uint32_t LUTerr;
juansal12 0:c792b17d9f78 680 __IO uint32_t FCANIE;
juansal12 0:c792b17d9f78 681 __IO uint32_t FCANIC0;
juansal12 0:c792b17d9f78 682 __IO uint32_t FCANIC1;
juansal12 0:c792b17d9f78 683 } LPC_CANAF_TypeDef;
juansal12 0:c792b17d9f78 684
juansal12 0:c792b17d9f78 685 typedef struct /* Central Registers */
juansal12 0:c792b17d9f78 686 {
juansal12 0:c792b17d9f78 687 __I uint32_t CANTxSR;
juansal12 0:c792b17d9f78 688 __I uint32_t CANRxSR;
juansal12 0:c792b17d9f78 689 __I uint32_t CANMSR;
juansal12 0:c792b17d9f78 690 } LPC_CANCR_TypeDef;
juansal12 0:c792b17d9f78 691
juansal12 0:c792b17d9f78 692 typedef struct /* Controller Registers */
juansal12 0:c792b17d9f78 693 {
juansal12 0:c792b17d9f78 694 __IO uint32_t MOD;
juansal12 0:c792b17d9f78 695 __O uint32_t CMR;
juansal12 0:c792b17d9f78 696 __IO uint32_t GSR;
juansal12 0:c792b17d9f78 697 __I uint32_t ICR;
juansal12 0:c792b17d9f78 698 __IO uint32_t IER;
juansal12 0:c792b17d9f78 699 __IO uint32_t BTR;
juansal12 0:c792b17d9f78 700 __IO uint32_t EWL;
juansal12 0:c792b17d9f78 701 __I uint32_t SR;
juansal12 0:c792b17d9f78 702 __IO uint32_t RFS;
juansal12 0:c792b17d9f78 703 __IO uint32_t RID;
juansal12 0:c792b17d9f78 704 __IO uint32_t RDA;
juansal12 0:c792b17d9f78 705 __IO uint32_t RDB;
juansal12 0:c792b17d9f78 706 __IO uint32_t TFI1;
juansal12 0:c792b17d9f78 707 __IO uint32_t TID1;
juansal12 0:c792b17d9f78 708 __IO uint32_t TDA1;
juansal12 0:c792b17d9f78 709 __IO uint32_t TDB1;
juansal12 0:c792b17d9f78 710 __IO uint32_t TFI2;
juansal12 0:c792b17d9f78 711 __IO uint32_t TID2;
juansal12 0:c792b17d9f78 712 __IO uint32_t TDA2;
juansal12 0:c792b17d9f78 713 __IO uint32_t TDB2;
juansal12 0:c792b17d9f78 714 __IO uint32_t TFI3;
juansal12 0:c792b17d9f78 715 __IO uint32_t TID3;
juansal12 0:c792b17d9f78 716 __IO uint32_t TDA3;
juansal12 0:c792b17d9f78 717 __IO uint32_t TDB3;
juansal12 0:c792b17d9f78 718 } LPC_CAN_TypeDef;
juansal12 0:c792b17d9f78 719
juansal12 0:c792b17d9f78 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
juansal12 0:c792b17d9f78 721 typedef struct /* Common Registers */
juansal12 0:c792b17d9f78 722 {
juansal12 0:c792b17d9f78 723 __I uint32_t DMACIntStat;
juansal12 0:c792b17d9f78 724 __I uint32_t DMACIntTCStat;
juansal12 0:c792b17d9f78 725 __O uint32_t DMACIntTCClear;
juansal12 0:c792b17d9f78 726 __I uint32_t DMACIntErrStat;
juansal12 0:c792b17d9f78 727 __O uint32_t DMACIntErrClr;
juansal12 0:c792b17d9f78 728 __I uint32_t DMACRawIntTCStat;
juansal12 0:c792b17d9f78 729 __I uint32_t DMACRawIntErrStat;
juansal12 0:c792b17d9f78 730 __I uint32_t DMACEnbldChns;
juansal12 0:c792b17d9f78 731 __IO uint32_t DMACSoftBReq;
juansal12 0:c792b17d9f78 732 __IO uint32_t DMACSoftSReq;
juansal12 0:c792b17d9f78 733 __IO uint32_t DMACSoftLBReq;
juansal12 0:c792b17d9f78 734 __IO uint32_t DMACSoftLSReq;
juansal12 0:c792b17d9f78 735 __IO uint32_t DMACConfig;
juansal12 0:c792b17d9f78 736 __IO uint32_t DMACSync;
juansal12 0:c792b17d9f78 737 } LPC_GPDMA_TypeDef;
juansal12 0:c792b17d9f78 738
juansal12 0:c792b17d9f78 739 typedef struct /* Channel Registers */
juansal12 0:c792b17d9f78 740 {
juansal12 0:c792b17d9f78 741 __IO uint32_t DMACCSrcAddr;
juansal12 0:c792b17d9f78 742 __IO uint32_t DMACCDestAddr;
juansal12 0:c792b17d9f78 743 __IO uint32_t DMACCLLI;
juansal12 0:c792b17d9f78 744 __IO uint32_t DMACCControl;
juansal12 0:c792b17d9f78 745 __IO uint32_t DMACCConfig;
juansal12 0:c792b17d9f78 746 } LPC_GPDMACH_TypeDef;
juansal12 0:c792b17d9f78 747
juansal12 0:c792b17d9f78 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
juansal12 0:c792b17d9f78 749 typedef struct
juansal12 0:c792b17d9f78 750 {
juansal12 0:c792b17d9f78 751 __I uint32_t HcRevision; /* USB Host Registers */
juansal12 0:c792b17d9f78 752 __IO uint32_t HcControl;
juansal12 0:c792b17d9f78 753 __IO uint32_t HcCommandStatus;
juansal12 0:c792b17d9f78 754 __IO uint32_t HcInterruptStatus;
juansal12 0:c792b17d9f78 755 __IO uint32_t HcInterruptEnable;
juansal12 0:c792b17d9f78 756 __IO uint32_t HcInterruptDisable;
juansal12 0:c792b17d9f78 757 __IO uint32_t HcHCCA;
juansal12 0:c792b17d9f78 758 __I uint32_t HcPeriodCurrentED;
juansal12 0:c792b17d9f78 759 __IO uint32_t HcControlHeadED;
juansal12 0:c792b17d9f78 760 __IO uint32_t HcControlCurrentED;
juansal12 0:c792b17d9f78 761 __IO uint32_t HcBulkHeadED;
juansal12 0:c792b17d9f78 762 __IO uint32_t HcBulkCurrentED;
juansal12 0:c792b17d9f78 763 __I uint32_t HcDoneHead;
juansal12 0:c792b17d9f78 764 __IO uint32_t HcFmInterval;
juansal12 0:c792b17d9f78 765 __I uint32_t HcFmRemaining;
juansal12 0:c792b17d9f78 766 __I uint32_t HcFmNumber;
juansal12 0:c792b17d9f78 767 __IO uint32_t HcPeriodicStart;
juansal12 0:c792b17d9f78 768 __IO uint32_t HcLSTreshold;
juansal12 0:c792b17d9f78 769 __IO uint32_t HcRhDescriptorA;
juansal12 0:c792b17d9f78 770 __IO uint32_t HcRhDescriptorB;
juansal12 0:c792b17d9f78 771 __IO uint32_t HcRhStatus;
juansal12 0:c792b17d9f78 772 __IO uint32_t HcRhPortStatus1;
juansal12 0:c792b17d9f78 773 __IO uint32_t HcRhPortStatus2;
juansal12 0:c792b17d9f78 774 uint32_t RESERVED0[40];
juansal12 0:c792b17d9f78 775 __I uint32_t Module_ID;
juansal12 0:c792b17d9f78 776
juansal12 0:c792b17d9f78 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
juansal12 0:c792b17d9f78 778 __IO uint32_t OTGIntEn;
juansal12 0:c792b17d9f78 779 __O uint32_t OTGIntSet;
juansal12 0:c792b17d9f78 780 __O uint32_t OTGIntClr;
juansal12 0:c792b17d9f78 781 __IO uint32_t OTGStCtrl;
juansal12 0:c792b17d9f78 782 __IO uint32_t OTGTmr;
juansal12 0:c792b17d9f78 783 uint32_t RESERVED1[58];
juansal12 0:c792b17d9f78 784
juansal12 0:c792b17d9f78 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
juansal12 0:c792b17d9f78 786 __IO uint32_t USBDevIntEn;
juansal12 0:c792b17d9f78 787 __O uint32_t USBDevIntClr;
juansal12 0:c792b17d9f78 788 __O uint32_t USBDevIntSet;
juansal12 0:c792b17d9f78 789
juansal12 0:c792b17d9f78 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
juansal12 0:c792b17d9f78 791 __I uint32_t USBCmdData;
juansal12 0:c792b17d9f78 792
juansal12 0:c792b17d9f78 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
juansal12 0:c792b17d9f78 794 __O uint32_t USBTxData;
juansal12 0:c792b17d9f78 795 __I uint32_t USBRxPLen;
juansal12 0:c792b17d9f78 796 __O uint32_t USBTxPLen;
juansal12 0:c792b17d9f78 797 __IO uint32_t USBCtrl;
juansal12 0:c792b17d9f78 798 __O uint32_t USBDevIntPri;
juansal12 0:c792b17d9f78 799
juansal12 0:c792b17d9f78 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
juansal12 0:c792b17d9f78 801 __IO uint32_t USBEpIntEn;
juansal12 0:c792b17d9f78 802 __O uint32_t USBEpIntClr;
juansal12 0:c792b17d9f78 803 __O uint32_t USBEpIntSet;
juansal12 0:c792b17d9f78 804 __O uint32_t USBEpIntPri;
juansal12 0:c792b17d9f78 805
juansal12 0:c792b17d9f78 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
juansal12 0:c792b17d9f78 807 __O uint32_t USBEpInd;
juansal12 0:c792b17d9f78 808 __IO uint32_t USBMaxPSize;
juansal12 0:c792b17d9f78 809
juansal12 0:c792b17d9f78 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
juansal12 0:c792b17d9f78 811 __O uint32_t USBDMARClr;
juansal12 0:c792b17d9f78 812 __O uint32_t USBDMARSet;
juansal12 0:c792b17d9f78 813 uint32_t RESERVED2[9];
juansal12 0:c792b17d9f78 814 __IO uint32_t USBUDCAH;
juansal12 0:c792b17d9f78 815 __I uint32_t USBEpDMASt;
juansal12 0:c792b17d9f78 816 __O uint32_t USBEpDMAEn;
juansal12 0:c792b17d9f78 817 __O uint32_t USBEpDMADis;
juansal12 0:c792b17d9f78 818 __I uint32_t USBDMAIntSt;
juansal12 0:c792b17d9f78 819 __IO uint32_t USBDMAIntEn;
juansal12 0:c792b17d9f78 820 uint32_t RESERVED3[2];
juansal12 0:c792b17d9f78 821 __I uint32_t USBEoTIntSt;
juansal12 0:c792b17d9f78 822 __O uint32_t USBEoTIntClr;
juansal12 0:c792b17d9f78 823 __O uint32_t USBEoTIntSet;
juansal12 0:c792b17d9f78 824 __I uint32_t USBNDDRIntSt;
juansal12 0:c792b17d9f78 825 __O uint32_t USBNDDRIntClr;
juansal12 0:c792b17d9f78 826 __O uint32_t USBNDDRIntSet;
juansal12 0:c792b17d9f78 827 __I uint32_t USBSysErrIntSt;
juansal12 0:c792b17d9f78 828 __O uint32_t USBSysErrIntClr;
juansal12 0:c792b17d9f78 829 __O uint32_t USBSysErrIntSet;
juansal12 0:c792b17d9f78 830 uint32_t RESERVED4[15];
juansal12 0:c792b17d9f78 831
juansal12 0:c792b17d9f78 832 union {
juansal12 0:c792b17d9f78 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
juansal12 0:c792b17d9f78 834 __O uint32_t I2C_TX;
juansal12 0:c792b17d9f78 835 };
juansal12 0:c792b17d9f78 836 __I uint32_t I2C_STS;
juansal12 0:c792b17d9f78 837 __IO uint32_t I2C_CTL;
juansal12 0:c792b17d9f78 838 __IO uint32_t I2C_CLKHI;
juansal12 0:c792b17d9f78 839 __O uint32_t I2C_CLKLO;
juansal12 0:c792b17d9f78 840 uint32_t RESERVED5[824];
juansal12 0:c792b17d9f78 841
juansal12 0:c792b17d9f78 842 union {
juansal12 0:c792b17d9f78 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
juansal12 0:c792b17d9f78 844 __IO uint32_t OTGClkCtrl;
juansal12 0:c792b17d9f78 845 };
juansal12 0:c792b17d9f78 846 union {
juansal12 0:c792b17d9f78 847 __I uint32_t USBClkSt;
juansal12 0:c792b17d9f78 848 __I uint32_t OTGClkSt;
juansal12 0:c792b17d9f78 849 };
juansal12 0:c792b17d9f78 850 } LPC_USB_TypeDef;
juansal12 0:c792b17d9f78 851
juansal12 0:c792b17d9f78 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
juansal12 0:c792b17d9f78 853 typedef struct
juansal12 0:c792b17d9f78 854 {
juansal12 0:c792b17d9f78 855 __IO uint32_t MAC1; /* MAC Registers */
juansal12 0:c792b17d9f78 856 __IO uint32_t MAC2;
juansal12 0:c792b17d9f78 857 __IO uint32_t IPGT;
juansal12 0:c792b17d9f78 858 __IO uint32_t IPGR;
juansal12 0:c792b17d9f78 859 __IO uint32_t CLRT;
juansal12 0:c792b17d9f78 860 __IO uint32_t MAXF;
juansal12 0:c792b17d9f78 861 __IO uint32_t SUPP;
juansal12 0:c792b17d9f78 862 __IO uint32_t TEST;
juansal12 0:c792b17d9f78 863 __IO uint32_t MCFG;
juansal12 0:c792b17d9f78 864 __IO uint32_t MCMD;
juansal12 0:c792b17d9f78 865 __IO uint32_t MADR;
juansal12 0:c792b17d9f78 866 __O uint32_t MWTD;
juansal12 0:c792b17d9f78 867 __I uint32_t MRDD;
juansal12 0:c792b17d9f78 868 __I uint32_t MIND;
juansal12 0:c792b17d9f78 869 uint32_t RESERVED0[2];
juansal12 0:c792b17d9f78 870 __IO uint32_t SA0;
juansal12 0:c792b17d9f78 871 __IO uint32_t SA1;
juansal12 0:c792b17d9f78 872 __IO uint32_t SA2;
juansal12 0:c792b17d9f78 873 uint32_t RESERVED1[45];
juansal12 0:c792b17d9f78 874 __IO uint32_t Command; /* Control Registers */
juansal12 0:c792b17d9f78 875 __I uint32_t Status;
juansal12 0:c792b17d9f78 876 __IO uint32_t RxDescriptor;
juansal12 0:c792b17d9f78 877 __IO uint32_t RxStatus;
juansal12 0:c792b17d9f78 878 __IO uint32_t RxDescriptorNumber;
juansal12 0:c792b17d9f78 879 __I uint32_t RxProduceIndex;
juansal12 0:c792b17d9f78 880 __IO uint32_t RxConsumeIndex;
juansal12 0:c792b17d9f78 881 __IO uint32_t TxDescriptor;
juansal12 0:c792b17d9f78 882 __IO uint32_t TxStatus;
juansal12 0:c792b17d9f78 883 __IO uint32_t TxDescriptorNumber;
juansal12 0:c792b17d9f78 884 __IO uint32_t TxProduceIndex;
juansal12 0:c792b17d9f78 885 __I uint32_t TxConsumeIndex;
juansal12 0:c792b17d9f78 886 uint32_t RESERVED2[10];
juansal12 0:c792b17d9f78 887 __I uint32_t TSV0;
juansal12 0:c792b17d9f78 888 __I uint32_t TSV1;
juansal12 0:c792b17d9f78 889 __I uint32_t RSV;
juansal12 0:c792b17d9f78 890 uint32_t RESERVED3[3];
juansal12 0:c792b17d9f78 891 __IO uint32_t FlowControlCounter;
juansal12 0:c792b17d9f78 892 __I uint32_t FlowControlStatus;
juansal12 0:c792b17d9f78 893 uint32_t RESERVED4[34];
juansal12 0:c792b17d9f78 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
juansal12 0:c792b17d9f78 895 __IO uint32_t RxFilterWoLStatus;
juansal12 0:c792b17d9f78 896 __IO uint32_t RxFilterWoLClear;
juansal12 0:c792b17d9f78 897 uint32_t RESERVED5;
juansal12 0:c792b17d9f78 898 __IO uint32_t HashFilterL;
juansal12 0:c792b17d9f78 899 __IO uint32_t HashFilterH;
juansal12 0:c792b17d9f78 900 uint32_t RESERVED6[882];
juansal12 0:c792b17d9f78 901 __I uint32_t IntStatus; /* Module Control Registers */
juansal12 0:c792b17d9f78 902 __IO uint32_t IntEnable;
juansal12 0:c792b17d9f78 903 __O uint32_t IntClear;
juansal12 0:c792b17d9f78 904 __O uint32_t IntSet;
juansal12 0:c792b17d9f78 905 uint32_t RESERVED7;
juansal12 0:c792b17d9f78 906 __IO uint32_t PowerDown;
juansal12 0:c792b17d9f78 907 uint32_t RESERVED8;
juansal12 0:c792b17d9f78 908 __IO uint32_t Module_ID;
juansal12 0:c792b17d9f78 909 } LPC_EMAC_TypeDef;
juansal12 0:c792b17d9f78 910
juansal12 0:c792b17d9f78 911 #if defined ( __CC_ARM )
juansal12 0:c792b17d9f78 912 #pragma no_anon_unions
juansal12 0:c792b17d9f78 913 #endif
juansal12 0:c792b17d9f78 914
juansal12 0:c792b17d9f78 915
juansal12 0:c792b17d9f78 916 /******************************************************************************/
juansal12 0:c792b17d9f78 917 /* Peripheral memory map */
juansal12 0:c792b17d9f78 918 /******************************************************************************/
juansal12 0:c792b17d9f78 919 /* Base addresses */
juansal12 0:c792b17d9f78 920 #define LPC_FLASH_BASE (0x00000000UL)
juansal12 0:c792b17d9f78 921 #define LPC_RAM_BASE (0x10000000UL)
juansal12 0:c792b17d9f78 922 #define LPC_GPIO_BASE (0x2009C000UL)
juansal12 0:c792b17d9f78 923 #define LPC_APB0_BASE (0x40000000UL)
juansal12 0:c792b17d9f78 924 #define LPC_APB1_BASE (0x40080000UL)
juansal12 0:c792b17d9f78 925 #define LPC_AHB_BASE (0x50000000UL)
juansal12 0:c792b17d9f78 926 #define LPC_CM3_BASE (0xE0000000UL)
juansal12 0:c792b17d9f78 927
juansal12 0:c792b17d9f78 928 /* APB0 peripherals */
juansal12 0:c792b17d9f78 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
juansal12 0:c792b17d9f78 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
juansal12 0:c792b17d9f78 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
juansal12 0:c792b17d9f78 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
juansal12 0:c792b17d9f78 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
juansal12 0:c792b17d9f78 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
juansal12 0:c792b17d9f78 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
juansal12 0:c792b17d9f78 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
juansal12 0:c792b17d9f78 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
juansal12 0:c792b17d9f78 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
juansal12 0:c792b17d9f78 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
juansal12 0:c792b17d9f78 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
juansal12 0:c792b17d9f78 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
juansal12 0:c792b17d9f78 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
juansal12 0:c792b17d9f78 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
juansal12 0:c792b17d9f78 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
juansal12 0:c792b17d9f78 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
juansal12 0:c792b17d9f78 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
juansal12 0:c792b17d9f78 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
juansal12 0:c792b17d9f78 948
juansal12 0:c792b17d9f78 949 /* APB1 peripherals */
juansal12 0:c792b17d9f78 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
juansal12 0:c792b17d9f78 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
juansal12 0:c792b17d9f78 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
juansal12 0:c792b17d9f78 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
juansal12 0:c792b17d9f78 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
juansal12 0:c792b17d9f78 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
juansal12 0:c792b17d9f78 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
juansal12 0:c792b17d9f78 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
juansal12 0:c792b17d9f78 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
juansal12 0:c792b17d9f78 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
juansal12 0:c792b17d9f78 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
juansal12 0:c792b17d9f78 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
juansal12 0:c792b17d9f78 962
juansal12 0:c792b17d9f78 963 /* AHB peripherals */
juansal12 0:c792b17d9f78 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
juansal12 0:c792b17d9f78 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
juansal12 0:c792b17d9f78 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
juansal12 0:c792b17d9f78 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
juansal12 0:c792b17d9f78 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
juansal12 0:c792b17d9f78 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
juansal12 0:c792b17d9f78 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
juansal12 0:c792b17d9f78 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
juansal12 0:c792b17d9f78 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
juansal12 0:c792b17d9f78 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
juansal12 0:c792b17d9f78 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
juansal12 0:c792b17d9f78 975
juansal12 0:c792b17d9f78 976 /* GPIOs */
juansal12 0:c792b17d9f78 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
juansal12 0:c792b17d9f78 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
juansal12 0:c792b17d9f78 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
juansal12 0:c792b17d9f78 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
juansal12 0:c792b17d9f78 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
juansal12 0:c792b17d9f78 982
juansal12 0:c792b17d9f78 983
juansal12 0:c792b17d9f78 984 /******************************************************************************/
juansal12 0:c792b17d9f78 985 /* Peripheral declaration */
juansal12 0:c792b17d9f78 986 /******************************************************************************/
juansal12 0:c792b17d9f78 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
juansal12 0:c792b17d9f78 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
juansal12 0:c792b17d9f78 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
juansal12 0:c792b17d9f78 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
juansal12 0:c792b17d9f78 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
juansal12 0:c792b17d9f78 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
juansal12 0:c792b17d9f78 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
juansal12 0:c792b17d9f78 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
juansal12 0:c792b17d9f78 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
juansal12 0:c792b17d9f78 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
juansal12 0:c792b17d9f78 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
juansal12 0:c792b17d9f78 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
juansal12 0:c792b17d9f78 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
juansal12 0:c792b17d9f78 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
juansal12 0:c792b17d9f78 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
juansal12 0:c792b17d9f78 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
juansal12 0:c792b17d9f78 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
juansal12 0:c792b17d9f78 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
juansal12 0:c792b17d9f78 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
juansal12 0:c792b17d9f78 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
juansal12 0:c792b17d9f78 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
juansal12 0:c792b17d9f78 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
juansal12 0:c792b17d9f78 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
juansal12 0:c792b17d9f78 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
juansal12 0:c792b17d9f78 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
juansal12 0:c792b17d9f78 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
juansal12 0:c792b17d9f78 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
juansal12 0:c792b17d9f78 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
juansal12 0:c792b17d9f78 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
juansal12 0:c792b17d9f78 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
juansal12 0:c792b17d9f78 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
juansal12 0:c792b17d9f78 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
juansal12 0:c792b17d9f78 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
juansal12 0:c792b17d9f78 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
juansal12 0:c792b17d9f78 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
juansal12 0:c792b17d9f78 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
juansal12 0:c792b17d9f78 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
juansal12 0:c792b17d9f78 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
juansal12 0:c792b17d9f78 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
juansal12 0:c792b17d9f78 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
juansal12 0:c792b17d9f78 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
juansal12 0:c792b17d9f78 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
juansal12 0:c792b17d9f78 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
juansal12 0:c792b17d9f78 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
juansal12 0:c792b17d9f78 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
juansal12 0:c792b17d9f78 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
juansal12 0:c792b17d9f78 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
juansal12 0:c792b17d9f78 1034
juansal12 0:c792b17d9f78 1035 #endif // __LPC17xx_H__