mbed - test

Users » juansal12 » Code » mbed

test

TARGET_LPC1768/core_cm4.h@0:44931ff4a3ed, 2020-01-14 (annotated)

Committer:: juansal12
Date:: Tue Jan 14 19:14:29 2020 +0000
Revision:: 0:44931ff4a3ed

Sofi 7 code;

Who changed what in which revision?

User	Revision	Line number	New contents of line
juansal12	0:44931ff4a3ed	1	/************************************************************************//
juansal12	0:44931ff4a3ed	2	* @file core_cm4.h
juansal12	0:44931ff4a3ed	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
juansal12	0:44931ff4a3ed	4	* @version V3.20
juansal12	0:44931ff4a3ed	5	* @date 25. February 2013
juansal12	0:44931ff4a3ed	6	*
juansal12	0:44931ff4a3ed	7	* @note
juansal12	0:44931ff4a3ed	8	*
juansal12	0:44931ff4a3ed	9	******************************************************************************/
juansal12	0:44931ff4a3ed	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
juansal12	0:44931ff4a3ed	11
juansal12	0:44931ff4a3ed	12	All rights reserved.
juansal12	0:44931ff4a3ed	13	Redistribution and use in source and binary forms, with or without
juansal12	0:44931ff4a3ed	14	modification, are permitted provided that the following conditions are met:
juansal12	0:44931ff4a3ed	15	- Redistributions of source code must retain the above copyright
juansal12	0:44931ff4a3ed	16	notice, this list of conditions and the following disclaimer.
juansal12	0:44931ff4a3ed	17	- Redistributions in binary form must reproduce the above copyright
juansal12	0:44931ff4a3ed	18	notice, this list of conditions and the following disclaimer in the
juansal12	0:44931ff4a3ed	19	documentation and/or other materials provided with the distribution.
juansal12	0:44931ff4a3ed	20	- Neither the name of ARM nor the names of its contributors may be used
juansal12	0:44931ff4a3ed	21	to endorse or promote products derived from this software without
juansal12	0:44931ff4a3ed	22	specific prior written permission.
juansal12	0:44931ff4a3ed	23	*
juansal12	0:44931ff4a3ed	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
juansal12	0:44931ff4a3ed	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
juansal12	0:44931ff4a3ed	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
juansal12	0:44931ff4a3ed	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
juansal12	0:44931ff4a3ed	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
juansal12	0:44931ff4a3ed	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
juansal12	0:44931ff4a3ed	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
juansal12	0:44931ff4a3ed	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
juansal12	0:44931ff4a3ed	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
juansal12	0:44931ff4a3ed	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
juansal12	0:44931ff4a3ed	34	POSSIBILITY OF SUCH DAMAGE.
juansal12	0:44931ff4a3ed	35	---------------------------------------------------------------------------*/
juansal12	0:44931ff4a3ed	36
juansal12	0:44931ff4a3ed	37
juansal12	0:44931ff4a3ed	38	#if defined ( __ICCARM__ )
juansal12	0:44931ff4a3ed	39	#pragma system_include /* treat file as system include file for MISRA check */
juansal12	0:44931ff4a3ed	40	#endif
juansal12	0:44931ff4a3ed	41
juansal12	0:44931ff4a3ed	42	#ifdef __cplusplus
juansal12	0:44931ff4a3ed	43	extern "C" {
juansal12	0:44931ff4a3ed	44	#endif
juansal12	0:44931ff4a3ed	45
juansal12	0:44931ff4a3ed	46	#ifndef __CORE_CM4_H_GENERIC
juansal12	0:44931ff4a3ed	47	#define __CORE_CM4_H_GENERIC
juansal12	0:44931ff4a3ed	48
juansal12	0:44931ff4a3ed	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
juansal12	0:44931ff4a3ed	50	CMSIS violates the following MISRA-C:2004 rules:
juansal12	0:44931ff4a3ed	51
juansal12	0:44931ff4a3ed	52	\li Required Rule 8.5, object/function definition in header file.<br>
juansal12	0:44931ff4a3ed	53	Function definitions in header files are used to allow 'inlining'.
juansal12	0:44931ff4a3ed	54
juansal12	0:44931ff4a3ed	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
juansal12	0:44931ff4a3ed	56	Unions are used for effective representation of core registers.
juansal12	0:44931ff4a3ed	57
juansal12	0:44931ff4a3ed	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
juansal12	0:44931ff4a3ed	59	Function-like macros are used to allow more efficient code.
juansal12	0:44931ff4a3ed	60	*/
juansal12	0:44931ff4a3ed	61
juansal12	0:44931ff4a3ed	62
juansal12	0:44931ff4a3ed	63	/*******************************************************************************
juansal12	0:44931ff4a3ed	64	* CMSIS definitions
juansal12	0:44931ff4a3ed	65	******************************************************************************/
juansal12	0:44931ff4a3ed	66	/** \ingroup Cortex_M4
juansal12	0:44931ff4a3ed	67	@{
juansal12	0:44931ff4a3ed	68	*/
juansal12	0:44931ff4a3ed	69
juansal12	0:44931ff4a3ed	70	/* CMSIS CM4 definitions */
juansal12	0:44931ff4a3ed	71	#define __CM4_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
juansal12	0:44931ff4a3ed	72	#define __CM4_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
juansal12	0:44931ff4a3ed	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
juansal12	0:44931ff4a3ed	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
juansal12	0:44931ff4a3ed	75
juansal12	0:44931ff4a3ed	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
juansal12	0:44931ff4a3ed	77
juansal12	0:44931ff4a3ed	78
juansal12	0:44931ff4a3ed	79	#if defined ( __CC_ARM )
juansal12	0:44931ff4a3ed	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
juansal12	0:44931ff4a3ed	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
juansal12	0:44931ff4a3ed	82	#define __STATIC_INLINE static __inline
juansal12	0:44931ff4a3ed	83
juansal12	0:44931ff4a3ed	84	#elif defined ( __ICCARM__ )
juansal12	0:44931ff4a3ed	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
juansal12	0:44931ff4a3ed	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
juansal12	0:44931ff4a3ed	87	#define __STATIC_INLINE static inline
juansal12	0:44931ff4a3ed	88
juansal12	0:44931ff4a3ed	89	#elif defined ( __TMS470__ )
juansal12	0:44931ff4a3ed	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
juansal12	0:44931ff4a3ed	91	#define __STATIC_INLINE static inline
juansal12	0:44931ff4a3ed	92
juansal12	0:44931ff4a3ed	93	#elif defined ( __GNUC__ )
juansal12	0:44931ff4a3ed	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
juansal12	0:44931ff4a3ed	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
juansal12	0:44931ff4a3ed	96	#define __STATIC_INLINE static inline
juansal12	0:44931ff4a3ed	97
juansal12	0:44931ff4a3ed	98	#elif defined ( __TASKING__ )
juansal12	0:44931ff4a3ed	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
juansal12	0:44931ff4a3ed	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
juansal12	0:44931ff4a3ed	101	#define __STATIC_INLINE static inline
juansal12	0:44931ff4a3ed	102
juansal12	0:44931ff4a3ed	103	#endif
juansal12	0:44931ff4a3ed	104
juansal12	0:44931ff4a3ed	105	/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
juansal12	0:44931ff4a3ed	106	*/
juansal12	0:44931ff4a3ed	107	#if defined ( __CC_ARM )
juansal12	0:44931ff4a3ed	108	#if defined __TARGET_FPU_VFP
juansal12	0:44931ff4a3ed	109	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	110	#define __FPU_USED 1
juansal12	0:44931ff4a3ed	111	#else
juansal12	0:44931ff4a3ed	112	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12	0:44931ff4a3ed	113	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	114	#endif
juansal12	0:44931ff4a3ed	115	#else
juansal12	0:44931ff4a3ed	116	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	117	#endif
juansal12	0:44931ff4a3ed	118
juansal12	0:44931ff4a3ed	119	#elif defined ( __ICCARM__ )
juansal12	0:44931ff4a3ed	120	#if defined __ARMVFP__
juansal12	0:44931ff4a3ed	121	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	122	#define __FPU_USED 1
juansal12	0:44931ff4a3ed	123	#else
juansal12	0:44931ff4a3ed	124	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12	0:44931ff4a3ed	125	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	126	#endif
juansal12	0:44931ff4a3ed	127	#else
juansal12	0:44931ff4a3ed	128	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	129	#endif
juansal12	0:44931ff4a3ed	130
juansal12	0:44931ff4a3ed	131	#elif defined ( __TMS470__ )
juansal12	0:44931ff4a3ed	132	#if defined __TI_VFP_SUPPORT__
juansal12	0:44931ff4a3ed	133	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	134	#define __FPU_USED 1
juansal12	0:44931ff4a3ed	135	#else
juansal12	0:44931ff4a3ed	136	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12	0:44931ff4a3ed	137	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	138	#endif
juansal12	0:44931ff4a3ed	139	#else
juansal12	0:44931ff4a3ed	140	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	141	#endif
juansal12	0:44931ff4a3ed	142
juansal12	0:44931ff4a3ed	143	#elif defined ( __GNUC__ )
juansal12	0:44931ff4a3ed	144	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
juansal12	0:44931ff4a3ed	145	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	146	#define __FPU_USED 1
juansal12	0:44931ff4a3ed	147	#else
juansal12	0:44931ff4a3ed	148	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12	0:44931ff4a3ed	149	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	150	#endif
juansal12	0:44931ff4a3ed	151	#else
juansal12	0:44931ff4a3ed	152	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	153	#endif
juansal12	0:44931ff4a3ed	154
juansal12	0:44931ff4a3ed	155	#elif defined ( __TASKING__ )
juansal12	0:44931ff4a3ed	156	#if defined __FPU_VFP__
juansal12	0:44931ff4a3ed	157	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	158	#define __FPU_USED 1
juansal12	0:44931ff4a3ed	159	#else
juansal12	0:44931ff4a3ed	160	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
juansal12	0:44931ff4a3ed	161	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	162	#endif
juansal12	0:44931ff4a3ed	163	#else
juansal12	0:44931ff4a3ed	164	#define __FPU_USED 0
juansal12	0:44931ff4a3ed	165	#endif
juansal12	0:44931ff4a3ed	166	#endif
juansal12	0:44931ff4a3ed	167
juansal12	0:44931ff4a3ed	168	#include <stdint.h> /* standard types definitions */
juansal12	0:44931ff4a3ed	169	#include <core_cmInstr.h> /* Core Instruction Access */
juansal12	0:44931ff4a3ed	170	#include <core_cmFunc.h> /* Core Function Access */
juansal12	0:44931ff4a3ed	171	#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
juansal12	0:44931ff4a3ed	172
juansal12	0:44931ff4a3ed	173	#endif /* __CORE_CM4_H_GENERIC */
juansal12	0:44931ff4a3ed	174
juansal12	0:44931ff4a3ed	175	#ifndef __CMSIS_GENERIC
juansal12	0:44931ff4a3ed	176
juansal12	0:44931ff4a3ed	177	#ifndef __CORE_CM4_H_DEPENDANT
juansal12	0:44931ff4a3ed	178	#define __CORE_CM4_H_DEPENDANT
juansal12	0:44931ff4a3ed	179
juansal12	0:44931ff4a3ed	180	/* check device defines and use defaults */
juansal12	0:44931ff4a3ed	181	#if defined __CHECK_DEVICE_DEFINES
juansal12	0:44931ff4a3ed	182	#ifndef __CM4_REV
juansal12	0:44931ff4a3ed	183	#define __CM4_REV 0x0000
juansal12	0:44931ff4a3ed	184	#warning "__CM4_REV not defined in device header file; using default!"
juansal12	0:44931ff4a3ed	185	#endif
juansal12	0:44931ff4a3ed	186
juansal12	0:44931ff4a3ed	187	#ifndef __FPU_PRESENT
juansal12	0:44931ff4a3ed	188	#define __FPU_PRESENT 0
juansal12	0:44931ff4a3ed	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
juansal12	0:44931ff4a3ed	190	#endif
juansal12	0:44931ff4a3ed	191
juansal12	0:44931ff4a3ed	192	#ifndef __MPU_PRESENT
juansal12	0:44931ff4a3ed	193	#define __MPU_PRESENT 0
juansal12	0:44931ff4a3ed	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
juansal12	0:44931ff4a3ed	195	#endif
juansal12	0:44931ff4a3ed	196
juansal12	0:44931ff4a3ed	197	#ifndef __NVIC_PRIO_BITS
juansal12	0:44931ff4a3ed	198	#define __NVIC_PRIO_BITS 4
juansal12	0:44931ff4a3ed	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
juansal12	0:44931ff4a3ed	200	#endif
juansal12	0:44931ff4a3ed	201
juansal12	0:44931ff4a3ed	202	#ifndef __Vendor_SysTickConfig
juansal12	0:44931ff4a3ed	203	#define __Vendor_SysTickConfig 0
juansal12	0:44931ff4a3ed	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
juansal12	0:44931ff4a3ed	205	#endif
juansal12	0:44931ff4a3ed	206	#endif
juansal12	0:44931ff4a3ed	207
juansal12	0:44931ff4a3ed	208	/* IO definitions (access restrictions to peripheral registers) */
juansal12	0:44931ff4a3ed	209	/**
juansal12	0:44931ff4a3ed	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
juansal12	0:44931ff4a3ed	211
juansal12	0:44931ff4a3ed	212	<strong>IO Type Qualifiers</strong> are used
juansal12	0:44931ff4a3ed	213	\li to specify the access to peripheral variables.
juansal12	0:44931ff4a3ed	214	\li for automatic generation of peripheral register debug information.
juansal12	0:44931ff4a3ed	215	*/
juansal12	0:44931ff4a3ed	216	#ifdef __cplusplus
juansal12	0:44931ff4a3ed	217	#define __I volatile /!< Defines 'read only' permissions /
juansal12	0:44931ff4a3ed	218	#else
juansal12	0:44931ff4a3ed	219	#define __I volatile const /!< Defines 'read only' permissions /
juansal12	0:44931ff4a3ed	220	#endif
juansal12	0:44931ff4a3ed	221	#define __O volatile /!< Defines 'write only' permissions /
juansal12	0:44931ff4a3ed	222	#define __IO volatile /!< Defines 'read / write' permissions /
juansal12	0:44931ff4a3ed	223
juansal12	0:44931ff4a3ed	224	/@} end of group Cortex_M4 /
juansal12	0:44931ff4a3ed	225
juansal12	0:44931ff4a3ed	226
juansal12	0:44931ff4a3ed	227
juansal12	0:44931ff4a3ed	228	/*******************************************************************************
juansal12	0:44931ff4a3ed	229	* Register Abstraction
juansal12	0:44931ff4a3ed	230	Core Register contain:
juansal12	0:44931ff4a3ed	231	- Core Register
juansal12	0:44931ff4a3ed	232	- Core NVIC Register
juansal12	0:44931ff4a3ed	233	- Core SCB Register
juansal12	0:44931ff4a3ed	234	- Core SysTick Register
juansal12	0:44931ff4a3ed	235	- Core Debug Register
juansal12	0:44931ff4a3ed	236	- Core MPU Register
juansal12	0:44931ff4a3ed	237	- Core FPU Register
juansal12	0:44931ff4a3ed	238	******************************************************************************/
juansal12	0:44931ff4a3ed	239	/** \defgroup CMSIS_core_register Defines and Type Definitions
juansal12	0:44931ff4a3ed	240	\brief Type definitions and defines for Cortex-M processor based devices.
juansal12	0:44931ff4a3ed	241	*/
juansal12	0:44931ff4a3ed	242
juansal12	0:44931ff4a3ed	243	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	244	\defgroup CMSIS_CORE Status and Control Registers
juansal12	0:44931ff4a3ed	245	\brief Core Register type definitions.
juansal12	0:44931ff4a3ed	246	@{
juansal12	0:44931ff4a3ed	247	*/
juansal12	0:44931ff4a3ed	248
juansal12	0:44931ff4a3ed	249	/** \brief Union type to access the Application Program Status Register (APSR).
juansal12	0:44931ff4a3ed	250	*/
juansal12	0:44931ff4a3ed	251	typedef union
juansal12	0:44931ff4a3ed	252	{
juansal12	0:44931ff4a3ed	253	struct
juansal12	0:44931ff4a3ed	254	{
juansal12	0:44931ff4a3ed	255	#if (__CORTEX_M != 0x04)
juansal12	0:44931ff4a3ed	256	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
juansal12	0:44931ff4a3ed	257	#else
juansal12	0:44931ff4a3ed	258	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
juansal12	0:44931ff4a3ed	259	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
juansal12	0:44931ff4a3ed	260	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
juansal12	0:44931ff4a3ed	261	#endif
juansal12	0:44931ff4a3ed	262	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
juansal12	0:44931ff4a3ed	263	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
juansal12	0:44931ff4a3ed	264	uint32_t C:1; /!< bit: 29 Carry condition code flag /
juansal12	0:44931ff4a3ed	265	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
juansal12	0:44931ff4a3ed	266	uint32_t N:1; /!< bit: 31 Negative condition code flag /
juansal12	0:44931ff4a3ed	267	} b; /!< Structure used for bit access /
juansal12	0:44931ff4a3ed	268	uint32_t w; /!< Type used for word access /
juansal12	0:44931ff4a3ed	269	} APSR_Type;
juansal12	0:44931ff4a3ed	270
juansal12	0:44931ff4a3ed	271
juansal12	0:44931ff4a3ed	272	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
juansal12	0:44931ff4a3ed	273	*/
juansal12	0:44931ff4a3ed	274	typedef union
juansal12	0:44931ff4a3ed	275	{
juansal12	0:44931ff4a3ed	276	struct
juansal12	0:44931ff4a3ed	277	{
juansal12	0:44931ff4a3ed	278	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
juansal12	0:44931ff4a3ed	279	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
juansal12	0:44931ff4a3ed	280	} b; /!< Structure used for bit access /
juansal12	0:44931ff4a3ed	281	uint32_t w; /!< Type used for word access /
juansal12	0:44931ff4a3ed	282	} IPSR_Type;
juansal12	0:44931ff4a3ed	283
juansal12	0:44931ff4a3ed	284
juansal12	0:44931ff4a3ed	285	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
juansal12	0:44931ff4a3ed	286	*/
juansal12	0:44931ff4a3ed	287	typedef union
juansal12	0:44931ff4a3ed	288	{
juansal12	0:44931ff4a3ed	289	struct
juansal12	0:44931ff4a3ed	290	{
juansal12	0:44931ff4a3ed	291	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
juansal12	0:44931ff4a3ed	292	#if (__CORTEX_M != 0x04)
juansal12	0:44931ff4a3ed	293	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
juansal12	0:44931ff4a3ed	294	#else
juansal12	0:44931ff4a3ed	295	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
juansal12	0:44931ff4a3ed	296	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
juansal12	0:44931ff4a3ed	297	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
juansal12	0:44931ff4a3ed	298	#endif
juansal12	0:44931ff4a3ed	299	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
juansal12	0:44931ff4a3ed	300	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
juansal12	0:44931ff4a3ed	301	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
juansal12	0:44931ff4a3ed	302	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
juansal12	0:44931ff4a3ed	303	uint32_t C:1; /!< bit: 29 Carry condition code flag /
juansal12	0:44931ff4a3ed	304	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
juansal12	0:44931ff4a3ed	305	uint32_t N:1; /!< bit: 31 Negative condition code flag /
juansal12	0:44931ff4a3ed	306	} b; /!< Structure used for bit access /
juansal12	0:44931ff4a3ed	307	uint32_t w; /!< Type used for word access /
juansal12	0:44931ff4a3ed	308	} xPSR_Type;
juansal12	0:44931ff4a3ed	309
juansal12	0:44931ff4a3ed	310
juansal12	0:44931ff4a3ed	311	/** \brief Union type to access the Control Registers (CONTROL).
juansal12	0:44931ff4a3ed	312	*/
juansal12	0:44931ff4a3ed	313	typedef union
juansal12	0:44931ff4a3ed	314	{
juansal12	0:44931ff4a3ed	315	struct
juansal12	0:44931ff4a3ed	316	{
juansal12	0:44931ff4a3ed	317	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
juansal12	0:44931ff4a3ed	318	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
juansal12	0:44931ff4a3ed	319	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
juansal12	0:44931ff4a3ed	320	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
juansal12	0:44931ff4a3ed	321	} b; /!< Structure used for bit access /
juansal12	0:44931ff4a3ed	322	uint32_t w; /!< Type used for word access /
juansal12	0:44931ff4a3ed	323	} CONTROL_Type;
juansal12	0:44931ff4a3ed	324
juansal12	0:44931ff4a3ed	325	/@} end of group CMSIS_CORE /
juansal12	0:44931ff4a3ed	326
juansal12	0:44931ff4a3ed	327
juansal12	0:44931ff4a3ed	328	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	329	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
juansal12	0:44931ff4a3ed	330	\brief Type definitions for the NVIC Registers
juansal12	0:44931ff4a3ed	331	@{
juansal12	0:44931ff4a3ed	332	*/
juansal12	0:44931ff4a3ed	333
juansal12	0:44931ff4a3ed	334	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
juansal12	0:44931ff4a3ed	335	*/
juansal12	0:44931ff4a3ed	336	typedef struct
juansal12	0:44931ff4a3ed	337	{
juansal12	0:44931ff4a3ed	338	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
juansal12	0:44931ff4a3ed	339	uint32_t RESERVED0[24];
juansal12	0:44931ff4a3ed	340	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
juansal12	0:44931ff4a3ed	341	uint32_t RSERVED1[24];
juansal12	0:44931ff4a3ed	342	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
juansal12	0:44931ff4a3ed	343	uint32_t RESERVED2[24];
juansal12	0:44931ff4a3ed	344	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
juansal12	0:44931ff4a3ed	345	uint32_t RESERVED3[24];
juansal12	0:44931ff4a3ed	346	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
juansal12	0:44931ff4a3ed	347	uint32_t RESERVED4[56];
juansal12	0:44931ff4a3ed	348	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
juansal12	0:44931ff4a3ed	349	uint32_t RESERVED5[644];
juansal12	0:44931ff4a3ed	350	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
juansal12	0:44931ff4a3ed	351	} NVIC_Type;
juansal12	0:44931ff4a3ed	352
juansal12	0:44931ff4a3ed	353	/* Software Triggered Interrupt Register Definitions */
juansal12	0:44931ff4a3ed	354	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
juansal12	0:44931ff4a3ed	355	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
juansal12	0:44931ff4a3ed	356
juansal12	0:44931ff4a3ed	357	/@} end of group CMSIS_NVIC /
juansal12	0:44931ff4a3ed	358
juansal12	0:44931ff4a3ed	359
juansal12	0:44931ff4a3ed	360	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	361	\defgroup CMSIS_SCB System Control Block (SCB)
juansal12	0:44931ff4a3ed	362	\brief Type definitions for the System Control Block Registers
juansal12	0:44931ff4a3ed	363	@{
juansal12	0:44931ff4a3ed	364	*/
juansal12	0:44931ff4a3ed	365
juansal12	0:44931ff4a3ed	366	/** \brief Structure type to access the System Control Block (SCB).
juansal12	0:44931ff4a3ed	367	*/
juansal12	0:44931ff4a3ed	368	typedef struct
juansal12	0:44931ff4a3ed	369	{
juansal12	0:44931ff4a3ed	370	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
juansal12	0:44931ff4a3ed	371	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
juansal12	0:44931ff4a3ed	372	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
juansal12	0:44931ff4a3ed	373	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
juansal12	0:44931ff4a3ed	374	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
juansal12	0:44931ff4a3ed	375	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
juansal12	0:44931ff4a3ed	376	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
juansal12	0:44931ff4a3ed	377	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
juansal12	0:44931ff4a3ed	378	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
juansal12	0:44931ff4a3ed	379	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
juansal12	0:44931ff4a3ed	380	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
juansal12	0:44931ff4a3ed	381	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
juansal12	0:44931ff4a3ed	382	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
juansal12	0:44931ff4a3ed	383	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
juansal12	0:44931ff4a3ed	384	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
juansal12	0:44931ff4a3ed	385	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
juansal12	0:44931ff4a3ed	386	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
juansal12	0:44931ff4a3ed	387	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
juansal12	0:44931ff4a3ed	388	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
juansal12	0:44931ff4a3ed	389	uint32_t RESERVED0[5];
juansal12	0:44931ff4a3ed	390	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
juansal12	0:44931ff4a3ed	391	} SCB_Type;
juansal12	0:44931ff4a3ed	392
juansal12	0:44931ff4a3ed	393	/* SCB CPUID Register Definitions */
juansal12	0:44931ff4a3ed	394	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
juansal12	0:44931ff4a3ed	395	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
juansal12	0:44931ff4a3ed	396
juansal12	0:44931ff4a3ed	397	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
juansal12	0:44931ff4a3ed	398	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
juansal12	0:44931ff4a3ed	399
juansal12	0:44931ff4a3ed	400	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
juansal12	0:44931ff4a3ed	401	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
juansal12	0:44931ff4a3ed	402
juansal12	0:44931ff4a3ed	403	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
juansal12	0:44931ff4a3ed	404	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
juansal12	0:44931ff4a3ed	405
juansal12	0:44931ff4a3ed	406	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
juansal12	0:44931ff4a3ed	407	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
juansal12	0:44931ff4a3ed	408
juansal12	0:44931ff4a3ed	409	/* SCB Interrupt Control State Register Definitions */
juansal12	0:44931ff4a3ed	410	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
juansal12	0:44931ff4a3ed	411	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
juansal12	0:44931ff4a3ed	412
juansal12	0:44931ff4a3ed	413	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
juansal12	0:44931ff4a3ed	414	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
juansal12	0:44931ff4a3ed	415
juansal12	0:44931ff4a3ed	416	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
juansal12	0:44931ff4a3ed	417	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
juansal12	0:44931ff4a3ed	418
juansal12	0:44931ff4a3ed	419	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
juansal12	0:44931ff4a3ed	420	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
juansal12	0:44931ff4a3ed	421
juansal12	0:44931ff4a3ed	422	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
juansal12	0:44931ff4a3ed	423	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
juansal12	0:44931ff4a3ed	424
juansal12	0:44931ff4a3ed	425	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
juansal12	0:44931ff4a3ed	426	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
juansal12	0:44931ff4a3ed	427
juansal12	0:44931ff4a3ed	428	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
juansal12	0:44931ff4a3ed	429	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
juansal12	0:44931ff4a3ed	430
juansal12	0:44931ff4a3ed	431	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
juansal12	0:44931ff4a3ed	432	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
juansal12	0:44931ff4a3ed	433
juansal12	0:44931ff4a3ed	434	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
juansal12	0:44931ff4a3ed	435	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
juansal12	0:44931ff4a3ed	436
juansal12	0:44931ff4a3ed	437	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
juansal12	0:44931ff4a3ed	438	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
juansal12	0:44931ff4a3ed	439
juansal12	0:44931ff4a3ed	440	/* SCB Vector Table Offset Register Definitions */
juansal12	0:44931ff4a3ed	441	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
juansal12	0:44931ff4a3ed	442	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
juansal12	0:44931ff4a3ed	443
juansal12	0:44931ff4a3ed	444	/* SCB Application Interrupt and Reset Control Register Definitions */
juansal12	0:44931ff4a3ed	445	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
juansal12	0:44931ff4a3ed	446	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
juansal12	0:44931ff4a3ed	447
juansal12	0:44931ff4a3ed	448	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
juansal12	0:44931ff4a3ed	449	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
juansal12	0:44931ff4a3ed	450
juansal12	0:44931ff4a3ed	451	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
juansal12	0:44931ff4a3ed	452	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
juansal12	0:44931ff4a3ed	453
juansal12	0:44931ff4a3ed	454	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
juansal12	0:44931ff4a3ed	455	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
juansal12	0:44931ff4a3ed	456
juansal12	0:44931ff4a3ed	457	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
juansal12	0:44931ff4a3ed	458	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
juansal12	0:44931ff4a3ed	459
juansal12	0:44931ff4a3ed	460	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
juansal12	0:44931ff4a3ed	461	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
juansal12	0:44931ff4a3ed	462
juansal12	0:44931ff4a3ed	463	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
juansal12	0:44931ff4a3ed	464	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
juansal12	0:44931ff4a3ed	465
juansal12	0:44931ff4a3ed	466	/* SCB System Control Register Definitions */
juansal12	0:44931ff4a3ed	467	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
juansal12	0:44931ff4a3ed	468	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
juansal12	0:44931ff4a3ed	469
juansal12	0:44931ff4a3ed	470	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
juansal12	0:44931ff4a3ed	471	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
juansal12	0:44931ff4a3ed	472
juansal12	0:44931ff4a3ed	473	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
juansal12	0:44931ff4a3ed	474	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
juansal12	0:44931ff4a3ed	475
juansal12	0:44931ff4a3ed	476	/* SCB Configuration Control Register Definitions */
juansal12	0:44931ff4a3ed	477	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
juansal12	0:44931ff4a3ed	478	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
juansal12	0:44931ff4a3ed	479
juansal12	0:44931ff4a3ed	480	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
juansal12	0:44931ff4a3ed	481	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
juansal12	0:44931ff4a3ed	482
juansal12	0:44931ff4a3ed	483	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
juansal12	0:44931ff4a3ed	484	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
juansal12	0:44931ff4a3ed	485
juansal12	0:44931ff4a3ed	486	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
juansal12	0:44931ff4a3ed	487	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
juansal12	0:44931ff4a3ed	488
juansal12	0:44931ff4a3ed	489	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
juansal12	0:44931ff4a3ed	490	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
juansal12	0:44931ff4a3ed	491
juansal12	0:44931ff4a3ed	492	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
juansal12	0:44931ff4a3ed	493	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
juansal12	0:44931ff4a3ed	494
juansal12	0:44931ff4a3ed	495	/* SCB System Handler Control and State Register Definitions */
juansal12	0:44931ff4a3ed	496	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
juansal12	0:44931ff4a3ed	497	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
juansal12	0:44931ff4a3ed	498
juansal12	0:44931ff4a3ed	499	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
juansal12	0:44931ff4a3ed	500	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
juansal12	0:44931ff4a3ed	501
juansal12	0:44931ff4a3ed	502	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
juansal12	0:44931ff4a3ed	503	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
juansal12	0:44931ff4a3ed	504
juansal12	0:44931ff4a3ed	505	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
juansal12	0:44931ff4a3ed	506	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
juansal12	0:44931ff4a3ed	507
juansal12	0:44931ff4a3ed	508	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
juansal12	0:44931ff4a3ed	509	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
juansal12	0:44931ff4a3ed	510
juansal12	0:44931ff4a3ed	511	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
juansal12	0:44931ff4a3ed	512	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
juansal12	0:44931ff4a3ed	513
juansal12	0:44931ff4a3ed	514	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
juansal12	0:44931ff4a3ed	515	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
juansal12	0:44931ff4a3ed	516
juansal12	0:44931ff4a3ed	517	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
juansal12	0:44931ff4a3ed	518	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
juansal12	0:44931ff4a3ed	519
juansal12	0:44931ff4a3ed	520	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
juansal12	0:44931ff4a3ed	521	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
juansal12	0:44931ff4a3ed	522
juansal12	0:44931ff4a3ed	523	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
juansal12	0:44931ff4a3ed	524	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
juansal12	0:44931ff4a3ed	525
juansal12	0:44931ff4a3ed	526	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
juansal12	0:44931ff4a3ed	527	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
juansal12	0:44931ff4a3ed	528
juansal12	0:44931ff4a3ed	529	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
juansal12	0:44931ff4a3ed	530	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
juansal12	0:44931ff4a3ed	531
juansal12	0:44931ff4a3ed	532	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
juansal12	0:44931ff4a3ed	533	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
juansal12	0:44931ff4a3ed	534
juansal12	0:44931ff4a3ed	535	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
juansal12	0:44931ff4a3ed	536	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
juansal12	0:44931ff4a3ed	537
juansal12	0:44931ff4a3ed	538	/* SCB Configurable Fault Status Registers Definitions */
juansal12	0:44931ff4a3ed	539	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
juansal12	0:44931ff4a3ed	540	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
juansal12	0:44931ff4a3ed	541
juansal12	0:44931ff4a3ed	542	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
juansal12	0:44931ff4a3ed	543	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
juansal12	0:44931ff4a3ed	544
juansal12	0:44931ff4a3ed	545	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
juansal12	0:44931ff4a3ed	546	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
juansal12	0:44931ff4a3ed	547
juansal12	0:44931ff4a3ed	548	/* SCB Hard Fault Status Registers Definitions */
juansal12	0:44931ff4a3ed	549	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
juansal12	0:44931ff4a3ed	550	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
juansal12	0:44931ff4a3ed	551
juansal12	0:44931ff4a3ed	552	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
juansal12	0:44931ff4a3ed	553	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
juansal12	0:44931ff4a3ed	554
juansal12	0:44931ff4a3ed	555	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
juansal12	0:44931ff4a3ed	556	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
juansal12	0:44931ff4a3ed	557
juansal12	0:44931ff4a3ed	558	/* SCB Debug Fault Status Register Definitions */
juansal12	0:44931ff4a3ed	559	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
juansal12	0:44931ff4a3ed	560	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
juansal12	0:44931ff4a3ed	561
juansal12	0:44931ff4a3ed	562	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
juansal12	0:44931ff4a3ed	563	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
juansal12	0:44931ff4a3ed	564
juansal12	0:44931ff4a3ed	565	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
juansal12	0:44931ff4a3ed	566	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
juansal12	0:44931ff4a3ed	567
juansal12	0:44931ff4a3ed	568	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
juansal12	0:44931ff4a3ed	569	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
juansal12	0:44931ff4a3ed	570
juansal12	0:44931ff4a3ed	571	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
juansal12	0:44931ff4a3ed	572	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
juansal12	0:44931ff4a3ed	573
juansal12	0:44931ff4a3ed	574	/@} end of group CMSIS_SCB /
juansal12	0:44931ff4a3ed	575
juansal12	0:44931ff4a3ed	576
juansal12	0:44931ff4a3ed	577	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	578	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
juansal12	0:44931ff4a3ed	579	\brief Type definitions for the System Control and ID Register not in the SCB
juansal12	0:44931ff4a3ed	580	@{
juansal12	0:44931ff4a3ed	581	*/
juansal12	0:44931ff4a3ed	582
juansal12	0:44931ff4a3ed	583	/** \brief Structure type to access the System Control and ID Register not in the SCB.
juansal12	0:44931ff4a3ed	584	*/
juansal12	0:44931ff4a3ed	585	typedef struct
juansal12	0:44931ff4a3ed	586	{
juansal12	0:44931ff4a3ed	587	uint32_t RESERVED0[1];
juansal12	0:44931ff4a3ed	588	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
juansal12	0:44931ff4a3ed	589	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
juansal12	0:44931ff4a3ed	590	} SCnSCB_Type;
juansal12	0:44931ff4a3ed	591
juansal12	0:44931ff4a3ed	592	/* Interrupt Controller Type Register Definitions */
juansal12	0:44931ff4a3ed	593	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
juansal12	0:44931ff4a3ed	594	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
juansal12	0:44931ff4a3ed	595
juansal12	0:44931ff4a3ed	596	/* Auxiliary Control Register Definitions */
juansal12	0:44931ff4a3ed	597	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
juansal12	0:44931ff4a3ed	598	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
juansal12	0:44931ff4a3ed	599
juansal12	0:44931ff4a3ed	600	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
juansal12	0:44931ff4a3ed	601	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
juansal12	0:44931ff4a3ed	602
juansal12	0:44931ff4a3ed	603	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
juansal12	0:44931ff4a3ed	604	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
juansal12	0:44931ff4a3ed	605
juansal12	0:44931ff4a3ed	606	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
juansal12	0:44931ff4a3ed	607	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
juansal12	0:44931ff4a3ed	608
juansal12	0:44931ff4a3ed	609	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
juansal12	0:44931ff4a3ed	610	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
juansal12	0:44931ff4a3ed	611
juansal12	0:44931ff4a3ed	612	/@} end of group CMSIS_SCnotSCB /
juansal12	0:44931ff4a3ed	613
juansal12	0:44931ff4a3ed	614
juansal12	0:44931ff4a3ed	615	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	616	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
juansal12	0:44931ff4a3ed	617	\brief Type definitions for the System Timer Registers.
juansal12	0:44931ff4a3ed	618	@{
juansal12	0:44931ff4a3ed	619	*/
juansal12	0:44931ff4a3ed	620
juansal12	0:44931ff4a3ed	621	/** \brief Structure type to access the System Timer (SysTick).
juansal12	0:44931ff4a3ed	622	*/
juansal12	0:44931ff4a3ed	623	typedef struct
juansal12	0:44931ff4a3ed	624	{
juansal12	0:44931ff4a3ed	625	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
juansal12	0:44931ff4a3ed	626	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
juansal12	0:44931ff4a3ed	627	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
juansal12	0:44931ff4a3ed	628	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
juansal12	0:44931ff4a3ed	629	} SysTick_Type;
juansal12	0:44931ff4a3ed	630
juansal12	0:44931ff4a3ed	631	/* SysTick Control / Status Register Definitions */
juansal12	0:44931ff4a3ed	632	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
juansal12	0:44931ff4a3ed	633	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
juansal12	0:44931ff4a3ed	634
juansal12	0:44931ff4a3ed	635	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
juansal12	0:44931ff4a3ed	636	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
juansal12	0:44931ff4a3ed	637
juansal12	0:44931ff4a3ed	638	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
juansal12	0:44931ff4a3ed	639	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
juansal12	0:44931ff4a3ed	640
juansal12	0:44931ff4a3ed	641	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
juansal12	0:44931ff4a3ed	642	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
juansal12	0:44931ff4a3ed	643
juansal12	0:44931ff4a3ed	644	/* SysTick Reload Register Definitions */
juansal12	0:44931ff4a3ed	645	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
juansal12	0:44931ff4a3ed	646	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
juansal12	0:44931ff4a3ed	647
juansal12	0:44931ff4a3ed	648	/* SysTick Current Register Definitions */
juansal12	0:44931ff4a3ed	649	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
juansal12	0:44931ff4a3ed	650	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
juansal12	0:44931ff4a3ed	651
juansal12	0:44931ff4a3ed	652	/* SysTick Calibration Register Definitions */
juansal12	0:44931ff4a3ed	653	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
juansal12	0:44931ff4a3ed	654	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
juansal12	0:44931ff4a3ed	655
juansal12	0:44931ff4a3ed	656	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
juansal12	0:44931ff4a3ed	657	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
juansal12	0:44931ff4a3ed	658
juansal12	0:44931ff4a3ed	659	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
juansal12	0:44931ff4a3ed	660	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
juansal12	0:44931ff4a3ed	661
juansal12	0:44931ff4a3ed	662	/@} end of group CMSIS_SysTick /
juansal12	0:44931ff4a3ed	663
juansal12	0:44931ff4a3ed	664
juansal12	0:44931ff4a3ed	665	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	666	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
juansal12	0:44931ff4a3ed	667	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
juansal12	0:44931ff4a3ed	668	@{
juansal12	0:44931ff4a3ed	669	*/
juansal12	0:44931ff4a3ed	670
juansal12	0:44931ff4a3ed	671	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
juansal12	0:44931ff4a3ed	672	*/
juansal12	0:44931ff4a3ed	673	typedef struct
juansal12	0:44931ff4a3ed	674	{
juansal12	0:44931ff4a3ed	675	__O union
juansal12	0:44931ff4a3ed	676	{
juansal12	0:44931ff4a3ed	677	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
juansal12	0:44931ff4a3ed	678	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
juansal12	0:44931ff4a3ed	679	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
juansal12	0:44931ff4a3ed	680	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
juansal12	0:44931ff4a3ed	681	uint32_t RESERVED0[864];
juansal12	0:44931ff4a3ed	682	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
juansal12	0:44931ff4a3ed	683	uint32_t RESERVED1[15];
juansal12	0:44931ff4a3ed	684	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
juansal12	0:44931ff4a3ed	685	uint32_t RESERVED2[15];
juansal12	0:44931ff4a3ed	686	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
juansal12	0:44931ff4a3ed	687	uint32_t RESERVED3[29];
juansal12	0:44931ff4a3ed	688	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
juansal12	0:44931ff4a3ed	689	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
juansal12	0:44931ff4a3ed	690	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
juansal12	0:44931ff4a3ed	691	uint32_t RESERVED4[43];
juansal12	0:44931ff4a3ed	692	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
juansal12	0:44931ff4a3ed	693	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
juansal12	0:44931ff4a3ed	694	uint32_t RESERVED5[6];
juansal12	0:44931ff4a3ed	695	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
juansal12	0:44931ff4a3ed	696	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
juansal12	0:44931ff4a3ed	697	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
juansal12	0:44931ff4a3ed	698	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
juansal12	0:44931ff4a3ed	699	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
juansal12	0:44931ff4a3ed	700	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
juansal12	0:44931ff4a3ed	701	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
juansal12	0:44931ff4a3ed	702	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
juansal12	0:44931ff4a3ed	703	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
juansal12	0:44931ff4a3ed	704	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
juansal12	0:44931ff4a3ed	705	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
juansal12	0:44931ff4a3ed	706	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
juansal12	0:44931ff4a3ed	707	} ITM_Type;
juansal12	0:44931ff4a3ed	708
juansal12	0:44931ff4a3ed	709	/* ITM Trace Privilege Register Definitions */
juansal12	0:44931ff4a3ed	710	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
juansal12	0:44931ff4a3ed	711	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
juansal12	0:44931ff4a3ed	712
juansal12	0:44931ff4a3ed	713	/* ITM Trace Control Register Definitions */
juansal12	0:44931ff4a3ed	714	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
juansal12	0:44931ff4a3ed	715	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
juansal12	0:44931ff4a3ed	716
juansal12	0:44931ff4a3ed	717	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
juansal12	0:44931ff4a3ed	718	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
juansal12	0:44931ff4a3ed	719
juansal12	0:44931ff4a3ed	720	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
juansal12	0:44931ff4a3ed	721	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
juansal12	0:44931ff4a3ed	722
juansal12	0:44931ff4a3ed	723	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
juansal12	0:44931ff4a3ed	724	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
juansal12	0:44931ff4a3ed	725
juansal12	0:44931ff4a3ed	726	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
juansal12	0:44931ff4a3ed	727	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
juansal12	0:44931ff4a3ed	728
juansal12	0:44931ff4a3ed	729	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
juansal12	0:44931ff4a3ed	730	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
juansal12	0:44931ff4a3ed	731
juansal12	0:44931ff4a3ed	732	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
juansal12	0:44931ff4a3ed	733	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
juansal12	0:44931ff4a3ed	734
juansal12	0:44931ff4a3ed	735	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
juansal12	0:44931ff4a3ed	736	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
juansal12	0:44931ff4a3ed	737
juansal12	0:44931ff4a3ed	738	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
juansal12	0:44931ff4a3ed	739	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
juansal12	0:44931ff4a3ed	740
juansal12	0:44931ff4a3ed	741	/* ITM Integration Write Register Definitions */
juansal12	0:44931ff4a3ed	742	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
juansal12	0:44931ff4a3ed	743	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
juansal12	0:44931ff4a3ed	744
juansal12	0:44931ff4a3ed	745	/* ITM Integration Read Register Definitions */
juansal12	0:44931ff4a3ed	746	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
juansal12	0:44931ff4a3ed	747	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
juansal12	0:44931ff4a3ed	748
juansal12	0:44931ff4a3ed	749	/* ITM Integration Mode Control Register Definitions */
juansal12	0:44931ff4a3ed	750	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
juansal12	0:44931ff4a3ed	751	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
juansal12	0:44931ff4a3ed	752
juansal12	0:44931ff4a3ed	753	/* ITM Lock Status Register Definitions */
juansal12	0:44931ff4a3ed	754	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
juansal12	0:44931ff4a3ed	755	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
juansal12	0:44931ff4a3ed	756
juansal12	0:44931ff4a3ed	757	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
juansal12	0:44931ff4a3ed	758	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
juansal12	0:44931ff4a3ed	759
juansal12	0:44931ff4a3ed	760	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
juansal12	0:44931ff4a3ed	761	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
juansal12	0:44931ff4a3ed	762
juansal12	0:44931ff4a3ed	763	/@}/ /* end of group CMSIS_ITM */
juansal12	0:44931ff4a3ed	764
juansal12	0:44931ff4a3ed	765
juansal12	0:44931ff4a3ed	766	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	767	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
juansal12	0:44931ff4a3ed	768	\brief Type definitions for the Data Watchpoint and Trace (DWT)
juansal12	0:44931ff4a3ed	769	@{
juansal12	0:44931ff4a3ed	770	*/
juansal12	0:44931ff4a3ed	771
juansal12	0:44931ff4a3ed	772	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
juansal12	0:44931ff4a3ed	773	*/
juansal12	0:44931ff4a3ed	774	typedef struct
juansal12	0:44931ff4a3ed	775	{
juansal12	0:44931ff4a3ed	776	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
juansal12	0:44931ff4a3ed	777	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
juansal12	0:44931ff4a3ed	778	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
juansal12	0:44931ff4a3ed	779	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
juansal12	0:44931ff4a3ed	780	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
juansal12	0:44931ff4a3ed	781	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
juansal12	0:44931ff4a3ed	782	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
juansal12	0:44931ff4a3ed	783	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
juansal12	0:44931ff4a3ed	784	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
juansal12	0:44931ff4a3ed	785	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
juansal12	0:44931ff4a3ed	786	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
juansal12	0:44931ff4a3ed	787	uint32_t RESERVED0[1];
juansal12	0:44931ff4a3ed	788	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
juansal12	0:44931ff4a3ed	789	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
juansal12	0:44931ff4a3ed	790	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
juansal12	0:44931ff4a3ed	791	uint32_t RESERVED1[1];
juansal12	0:44931ff4a3ed	792	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
juansal12	0:44931ff4a3ed	793	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
juansal12	0:44931ff4a3ed	794	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
juansal12	0:44931ff4a3ed	795	uint32_t RESERVED2[1];
juansal12	0:44931ff4a3ed	796	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
juansal12	0:44931ff4a3ed	797	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
juansal12	0:44931ff4a3ed	798	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
juansal12	0:44931ff4a3ed	799	} DWT_Type;
juansal12	0:44931ff4a3ed	800
juansal12	0:44931ff4a3ed	801	/* DWT Control Register Definitions */
juansal12	0:44931ff4a3ed	802	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
juansal12	0:44931ff4a3ed	803	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
juansal12	0:44931ff4a3ed	804
juansal12	0:44931ff4a3ed	805	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
juansal12	0:44931ff4a3ed	806	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
juansal12	0:44931ff4a3ed	807
juansal12	0:44931ff4a3ed	808	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
juansal12	0:44931ff4a3ed	809	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
juansal12	0:44931ff4a3ed	810
juansal12	0:44931ff4a3ed	811	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
juansal12	0:44931ff4a3ed	812	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
juansal12	0:44931ff4a3ed	813
juansal12	0:44931ff4a3ed	814	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
juansal12	0:44931ff4a3ed	815	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
juansal12	0:44931ff4a3ed	816
juansal12	0:44931ff4a3ed	817	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
juansal12	0:44931ff4a3ed	818	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
juansal12	0:44931ff4a3ed	819
juansal12	0:44931ff4a3ed	820	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
juansal12	0:44931ff4a3ed	821	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
juansal12	0:44931ff4a3ed	822
juansal12	0:44931ff4a3ed	823	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
juansal12	0:44931ff4a3ed	824	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
juansal12	0:44931ff4a3ed	825
juansal12	0:44931ff4a3ed	826	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
juansal12	0:44931ff4a3ed	827	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
juansal12	0:44931ff4a3ed	828
juansal12	0:44931ff4a3ed	829	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
juansal12	0:44931ff4a3ed	830	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
juansal12	0:44931ff4a3ed	831
juansal12	0:44931ff4a3ed	832	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
juansal12	0:44931ff4a3ed	833	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
juansal12	0:44931ff4a3ed	834
juansal12	0:44931ff4a3ed	835	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
juansal12	0:44931ff4a3ed	836	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
juansal12	0:44931ff4a3ed	837
juansal12	0:44931ff4a3ed	838	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
juansal12	0:44931ff4a3ed	839	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
juansal12	0:44931ff4a3ed	840
juansal12	0:44931ff4a3ed	841	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
juansal12	0:44931ff4a3ed	842	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
juansal12	0:44931ff4a3ed	843
juansal12	0:44931ff4a3ed	844	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
juansal12	0:44931ff4a3ed	845	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
juansal12	0:44931ff4a3ed	846
juansal12	0:44931ff4a3ed	847	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
juansal12	0:44931ff4a3ed	848	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
juansal12	0:44931ff4a3ed	849
juansal12	0:44931ff4a3ed	850	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
juansal12	0:44931ff4a3ed	851	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
juansal12	0:44931ff4a3ed	852
juansal12	0:44931ff4a3ed	853	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
juansal12	0:44931ff4a3ed	854	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
juansal12	0:44931ff4a3ed	855
juansal12	0:44931ff4a3ed	856	/* DWT CPI Count Register Definitions */
juansal12	0:44931ff4a3ed	857	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
juansal12	0:44931ff4a3ed	858	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
juansal12	0:44931ff4a3ed	859
juansal12	0:44931ff4a3ed	860	/* DWT Exception Overhead Count Register Definitions */
juansal12	0:44931ff4a3ed	861	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
juansal12	0:44931ff4a3ed	862	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
juansal12	0:44931ff4a3ed	863
juansal12	0:44931ff4a3ed	864	/* DWT Sleep Count Register Definitions */
juansal12	0:44931ff4a3ed	865	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
juansal12	0:44931ff4a3ed	866	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
juansal12	0:44931ff4a3ed	867
juansal12	0:44931ff4a3ed	868	/* DWT LSU Count Register Definitions */
juansal12	0:44931ff4a3ed	869	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
juansal12	0:44931ff4a3ed	870	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
juansal12	0:44931ff4a3ed	871
juansal12	0:44931ff4a3ed	872	/* DWT Folded-instruction Count Register Definitions */
juansal12	0:44931ff4a3ed	873	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
juansal12	0:44931ff4a3ed	874	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
juansal12	0:44931ff4a3ed	875
juansal12	0:44931ff4a3ed	876	/* DWT Comparator Mask Register Definitions */
juansal12	0:44931ff4a3ed	877	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
juansal12	0:44931ff4a3ed	878	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
juansal12	0:44931ff4a3ed	879
juansal12	0:44931ff4a3ed	880	/* DWT Comparator Function Register Definitions */
juansal12	0:44931ff4a3ed	881	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
juansal12	0:44931ff4a3ed	882	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
juansal12	0:44931ff4a3ed	883
juansal12	0:44931ff4a3ed	884	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
juansal12	0:44931ff4a3ed	885	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
juansal12	0:44931ff4a3ed	886
juansal12	0:44931ff4a3ed	887	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
juansal12	0:44931ff4a3ed	888	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
juansal12	0:44931ff4a3ed	889
juansal12	0:44931ff4a3ed	890	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
juansal12	0:44931ff4a3ed	891	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
juansal12	0:44931ff4a3ed	892
juansal12	0:44931ff4a3ed	893	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
juansal12	0:44931ff4a3ed	894	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
juansal12	0:44931ff4a3ed	895
juansal12	0:44931ff4a3ed	896	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
juansal12	0:44931ff4a3ed	897	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
juansal12	0:44931ff4a3ed	898
juansal12	0:44931ff4a3ed	899	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
juansal12	0:44931ff4a3ed	900	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
juansal12	0:44931ff4a3ed	901
juansal12	0:44931ff4a3ed	902	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
juansal12	0:44931ff4a3ed	903	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
juansal12	0:44931ff4a3ed	904
juansal12	0:44931ff4a3ed	905	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
juansal12	0:44931ff4a3ed	906	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
juansal12	0:44931ff4a3ed	907
juansal12	0:44931ff4a3ed	908	/@}/ /* end of group CMSIS_DWT */
juansal12	0:44931ff4a3ed	909
juansal12	0:44931ff4a3ed	910
juansal12	0:44931ff4a3ed	911	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	912	\defgroup CMSIS_TPI Trace Port Interface (TPI)
juansal12	0:44931ff4a3ed	913	\brief Type definitions for the Trace Port Interface (TPI)
juansal12	0:44931ff4a3ed	914	@{
juansal12	0:44931ff4a3ed	915	*/
juansal12	0:44931ff4a3ed	916
juansal12	0:44931ff4a3ed	917	/** \brief Structure type to access the Trace Port Interface Register (TPI).
juansal12	0:44931ff4a3ed	918	*/
juansal12	0:44931ff4a3ed	919	typedef struct
juansal12	0:44931ff4a3ed	920	{
juansal12	0:44931ff4a3ed	921	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
juansal12	0:44931ff4a3ed	922	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
juansal12	0:44931ff4a3ed	923	uint32_t RESERVED0[2];
juansal12	0:44931ff4a3ed	924	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
juansal12	0:44931ff4a3ed	925	uint32_t RESERVED1[55];
juansal12	0:44931ff4a3ed	926	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
juansal12	0:44931ff4a3ed	927	uint32_t RESERVED2[131];
juansal12	0:44931ff4a3ed	928	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
juansal12	0:44931ff4a3ed	929	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
juansal12	0:44931ff4a3ed	930	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
juansal12	0:44931ff4a3ed	931	uint32_t RESERVED3[759];
juansal12	0:44931ff4a3ed	932	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
juansal12	0:44931ff4a3ed	933	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
juansal12	0:44931ff4a3ed	934	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
juansal12	0:44931ff4a3ed	935	uint32_t RESERVED4[1];
juansal12	0:44931ff4a3ed	936	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
juansal12	0:44931ff4a3ed	937	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
juansal12	0:44931ff4a3ed	938	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
juansal12	0:44931ff4a3ed	939	uint32_t RESERVED5[39];
juansal12	0:44931ff4a3ed	940	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
juansal12	0:44931ff4a3ed	941	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
juansal12	0:44931ff4a3ed	942	uint32_t RESERVED7[8];
juansal12	0:44931ff4a3ed	943	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
juansal12	0:44931ff4a3ed	944	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
juansal12	0:44931ff4a3ed	945	} TPI_Type;
juansal12	0:44931ff4a3ed	946
juansal12	0:44931ff4a3ed	947	/* TPI Asynchronous Clock Prescaler Register Definitions */
juansal12	0:44931ff4a3ed	948	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
juansal12	0:44931ff4a3ed	949	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
juansal12	0:44931ff4a3ed	950
juansal12	0:44931ff4a3ed	951	/* TPI Selected Pin Protocol Register Definitions */
juansal12	0:44931ff4a3ed	952	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
juansal12	0:44931ff4a3ed	953	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
juansal12	0:44931ff4a3ed	954
juansal12	0:44931ff4a3ed	955	/* TPI Formatter and Flush Status Register Definitions */
juansal12	0:44931ff4a3ed	956	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
juansal12	0:44931ff4a3ed	957	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
juansal12	0:44931ff4a3ed	958
juansal12	0:44931ff4a3ed	959	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
juansal12	0:44931ff4a3ed	960	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
juansal12	0:44931ff4a3ed	961
juansal12	0:44931ff4a3ed	962	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
juansal12	0:44931ff4a3ed	963	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
juansal12	0:44931ff4a3ed	964
juansal12	0:44931ff4a3ed	965	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
juansal12	0:44931ff4a3ed	966	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
juansal12	0:44931ff4a3ed	967
juansal12	0:44931ff4a3ed	968	/* TPI Formatter and Flush Control Register Definitions */
juansal12	0:44931ff4a3ed	969	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
juansal12	0:44931ff4a3ed	970	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
juansal12	0:44931ff4a3ed	971
juansal12	0:44931ff4a3ed	972	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
juansal12	0:44931ff4a3ed	973	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
juansal12	0:44931ff4a3ed	974
juansal12	0:44931ff4a3ed	975	/* TPI TRIGGER Register Definitions */
juansal12	0:44931ff4a3ed	976	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
juansal12	0:44931ff4a3ed	977	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
juansal12	0:44931ff4a3ed	978
juansal12	0:44931ff4a3ed	979	/* TPI Integration ETM Data Register Definitions (FIFO0) */
juansal12	0:44931ff4a3ed	980	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
juansal12	0:44931ff4a3ed	981	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
juansal12	0:44931ff4a3ed	982
juansal12	0:44931ff4a3ed	983	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
juansal12	0:44931ff4a3ed	984	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
juansal12	0:44931ff4a3ed	985
juansal12	0:44931ff4a3ed	986	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
juansal12	0:44931ff4a3ed	987	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
juansal12	0:44931ff4a3ed	988
juansal12	0:44931ff4a3ed	989	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
juansal12	0:44931ff4a3ed	990	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
juansal12	0:44931ff4a3ed	991
juansal12	0:44931ff4a3ed	992	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
juansal12	0:44931ff4a3ed	993	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
juansal12	0:44931ff4a3ed	994
juansal12	0:44931ff4a3ed	995	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
juansal12	0:44931ff4a3ed	996	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
juansal12	0:44931ff4a3ed	997
juansal12	0:44931ff4a3ed	998	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
juansal12	0:44931ff4a3ed	999	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
juansal12	0:44931ff4a3ed	1000
juansal12	0:44931ff4a3ed	1001	/* TPI ITATBCTR2 Register Definitions */
juansal12	0:44931ff4a3ed	1002	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
juansal12	0:44931ff4a3ed	1003	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
juansal12	0:44931ff4a3ed	1004
juansal12	0:44931ff4a3ed	1005	/* TPI Integration ITM Data Register Definitions (FIFO1) */
juansal12	0:44931ff4a3ed	1006	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
juansal12	0:44931ff4a3ed	1007	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
juansal12	0:44931ff4a3ed	1008
juansal12	0:44931ff4a3ed	1009	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
juansal12	0:44931ff4a3ed	1010	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
juansal12	0:44931ff4a3ed	1011
juansal12	0:44931ff4a3ed	1012	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
juansal12	0:44931ff4a3ed	1013	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
juansal12	0:44931ff4a3ed	1014
juansal12	0:44931ff4a3ed	1015	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
juansal12	0:44931ff4a3ed	1016	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
juansal12	0:44931ff4a3ed	1017
juansal12	0:44931ff4a3ed	1018	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
juansal12	0:44931ff4a3ed	1019	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
juansal12	0:44931ff4a3ed	1020
juansal12	0:44931ff4a3ed	1021	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
juansal12	0:44931ff4a3ed	1022	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
juansal12	0:44931ff4a3ed	1023
juansal12	0:44931ff4a3ed	1024	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
juansal12	0:44931ff4a3ed	1025	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
juansal12	0:44931ff4a3ed	1026
juansal12	0:44931ff4a3ed	1027	/* TPI ITATBCTR0 Register Definitions */
juansal12	0:44931ff4a3ed	1028	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
juansal12	0:44931ff4a3ed	1029	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
juansal12	0:44931ff4a3ed	1030
juansal12	0:44931ff4a3ed	1031	/* TPI Integration Mode Control Register Definitions */
juansal12	0:44931ff4a3ed	1032	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
juansal12	0:44931ff4a3ed	1033	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
juansal12	0:44931ff4a3ed	1034
juansal12	0:44931ff4a3ed	1035	/* TPI DEVID Register Definitions */
juansal12	0:44931ff4a3ed	1036	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
juansal12	0:44931ff4a3ed	1037	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
juansal12	0:44931ff4a3ed	1038
juansal12	0:44931ff4a3ed	1039	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
juansal12	0:44931ff4a3ed	1040	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
juansal12	0:44931ff4a3ed	1041
juansal12	0:44931ff4a3ed	1042	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
juansal12	0:44931ff4a3ed	1043	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
juansal12	0:44931ff4a3ed	1044
juansal12	0:44931ff4a3ed	1045	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
juansal12	0:44931ff4a3ed	1046	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
juansal12	0:44931ff4a3ed	1047
juansal12	0:44931ff4a3ed	1048	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
juansal12	0:44931ff4a3ed	1049	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
juansal12	0:44931ff4a3ed	1050
juansal12	0:44931ff4a3ed	1051	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
juansal12	0:44931ff4a3ed	1052	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
juansal12	0:44931ff4a3ed	1053
juansal12	0:44931ff4a3ed	1054	/* TPI DEVTYPE Register Definitions */
juansal12	0:44931ff4a3ed	1055	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
juansal12	0:44931ff4a3ed	1056	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
juansal12	0:44931ff4a3ed	1057
juansal12	0:44931ff4a3ed	1058	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
juansal12	0:44931ff4a3ed	1059	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
juansal12	0:44931ff4a3ed	1060
juansal12	0:44931ff4a3ed	1061	/@}/ /* end of group CMSIS_TPI */
juansal12	0:44931ff4a3ed	1062
juansal12	0:44931ff4a3ed	1063
juansal12	0:44931ff4a3ed	1064	#if (__MPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	1065	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	1066	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
juansal12	0:44931ff4a3ed	1067	\brief Type definitions for the Memory Protection Unit (MPU)
juansal12	0:44931ff4a3ed	1068	@{
juansal12	0:44931ff4a3ed	1069	*/
juansal12	0:44931ff4a3ed	1070
juansal12	0:44931ff4a3ed	1071	/** \brief Structure type to access the Memory Protection Unit (MPU).
juansal12	0:44931ff4a3ed	1072	*/
juansal12	0:44931ff4a3ed	1073	typedef struct
juansal12	0:44931ff4a3ed	1074	{
juansal12	0:44931ff4a3ed	1075	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
juansal12	0:44931ff4a3ed	1076	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
juansal12	0:44931ff4a3ed	1077	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
juansal12	0:44931ff4a3ed	1078	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
juansal12	0:44931ff4a3ed	1079	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
juansal12	0:44931ff4a3ed	1080	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
juansal12	0:44931ff4a3ed	1081	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
juansal12	0:44931ff4a3ed	1082	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
juansal12	0:44931ff4a3ed	1083	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
juansal12	0:44931ff4a3ed	1084	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
juansal12	0:44931ff4a3ed	1085	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
juansal12	0:44931ff4a3ed	1086	} MPU_Type;
juansal12	0:44931ff4a3ed	1087
juansal12	0:44931ff4a3ed	1088	/* MPU Type Register */
juansal12	0:44931ff4a3ed	1089	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
juansal12	0:44931ff4a3ed	1090	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
juansal12	0:44931ff4a3ed	1091
juansal12	0:44931ff4a3ed	1092	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
juansal12	0:44931ff4a3ed	1093	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
juansal12	0:44931ff4a3ed	1094
juansal12	0:44931ff4a3ed	1095	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
juansal12	0:44931ff4a3ed	1096	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
juansal12	0:44931ff4a3ed	1097
juansal12	0:44931ff4a3ed	1098	/* MPU Control Register */
juansal12	0:44931ff4a3ed	1099	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
juansal12	0:44931ff4a3ed	1100	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
juansal12	0:44931ff4a3ed	1101
juansal12	0:44931ff4a3ed	1102	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
juansal12	0:44931ff4a3ed	1103	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
juansal12	0:44931ff4a3ed	1104
juansal12	0:44931ff4a3ed	1105	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
juansal12	0:44931ff4a3ed	1106	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
juansal12	0:44931ff4a3ed	1107
juansal12	0:44931ff4a3ed	1108	/* MPU Region Number Register */
juansal12	0:44931ff4a3ed	1109	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
juansal12	0:44931ff4a3ed	1110	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
juansal12	0:44931ff4a3ed	1111
juansal12	0:44931ff4a3ed	1112	/* MPU Region Base Address Register */
juansal12	0:44931ff4a3ed	1113	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
juansal12	0:44931ff4a3ed	1114	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
juansal12	0:44931ff4a3ed	1115
juansal12	0:44931ff4a3ed	1116	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
juansal12	0:44931ff4a3ed	1117	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
juansal12	0:44931ff4a3ed	1118
juansal12	0:44931ff4a3ed	1119	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
juansal12	0:44931ff4a3ed	1120	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
juansal12	0:44931ff4a3ed	1121
juansal12	0:44931ff4a3ed	1122	/* MPU Region Attribute and Size Register */
juansal12	0:44931ff4a3ed	1123	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
juansal12	0:44931ff4a3ed	1124	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
juansal12	0:44931ff4a3ed	1125
juansal12	0:44931ff4a3ed	1126	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
juansal12	0:44931ff4a3ed	1127	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
juansal12	0:44931ff4a3ed	1128
juansal12	0:44931ff4a3ed	1129	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
juansal12	0:44931ff4a3ed	1130	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
juansal12	0:44931ff4a3ed	1131
juansal12	0:44931ff4a3ed	1132	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
juansal12	0:44931ff4a3ed	1133	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
juansal12	0:44931ff4a3ed	1134
juansal12	0:44931ff4a3ed	1135	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
juansal12	0:44931ff4a3ed	1136	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
juansal12	0:44931ff4a3ed	1137
juansal12	0:44931ff4a3ed	1138	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
juansal12	0:44931ff4a3ed	1139	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
juansal12	0:44931ff4a3ed	1140
juansal12	0:44931ff4a3ed	1141	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
juansal12	0:44931ff4a3ed	1142	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
juansal12	0:44931ff4a3ed	1143
juansal12	0:44931ff4a3ed	1144	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
juansal12	0:44931ff4a3ed	1145	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
juansal12	0:44931ff4a3ed	1146
juansal12	0:44931ff4a3ed	1147	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
juansal12	0:44931ff4a3ed	1148	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
juansal12	0:44931ff4a3ed	1149
juansal12	0:44931ff4a3ed	1150	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
juansal12	0:44931ff4a3ed	1151	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
juansal12	0:44931ff4a3ed	1152
juansal12	0:44931ff4a3ed	1153	/@} end of group CMSIS_MPU /
juansal12	0:44931ff4a3ed	1154	#endif
juansal12	0:44931ff4a3ed	1155
juansal12	0:44931ff4a3ed	1156
juansal12	0:44931ff4a3ed	1157	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	1158	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	1159	\defgroup CMSIS_FPU Floating Point Unit (FPU)
juansal12	0:44931ff4a3ed	1160	\brief Type definitions for the Floating Point Unit (FPU)
juansal12	0:44931ff4a3ed	1161	@{
juansal12	0:44931ff4a3ed	1162	*/
juansal12	0:44931ff4a3ed	1163
juansal12	0:44931ff4a3ed	1164	/** \brief Structure type to access the Floating Point Unit (FPU).
juansal12	0:44931ff4a3ed	1165	*/
juansal12	0:44931ff4a3ed	1166	typedef struct
juansal12	0:44931ff4a3ed	1167	{
juansal12	0:44931ff4a3ed	1168	uint32_t RESERVED0[1];
juansal12	0:44931ff4a3ed	1169	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
juansal12	0:44931ff4a3ed	1170	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
juansal12	0:44931ff4a3ed	1171	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
juansal12	0:44931ff4a3ed	1172	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
juansal12	0:44931ff4a3ed	1173	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
juansal12	0:44931ff4a3ed	1174	} FPU_Type;
juansal12	0:44931ff4a3ed	1175
juansal12	0:44931ff4a3ed	1176	/* Floating-Point Context Control Register */
juansal12	0:44931ff4a3ed	1177	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
juansal12	0:44931ff4a3ed	1178	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
juansal12	0:44931ff4a3ed	1179
juansal12	0:44931ff4a3ed	1180	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
juansal12	0:44931ff4a3ed	1181	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
juansal12	0:44931ff4a3ed	1182
juansal12	0:44931ff4a3ed	1183	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
juansal12	0:44931ff4a3ed	1184	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
juansal12	0:44931ff4a3ed	1185
juansal12	0:44931ff4a3ed	1186	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
juansal12	0:44931ff4a3ed	1187	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
juansal12	0:44931ff4a3ed	1188
juansal12	0:44931ff4a3ed	1189	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
juansal12	0:44931ff4a3ed	1190	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
juansal12	0:44931ff4a3ed	1191
juansal12	0:44931ff4a3ed	1192	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
juansal12	0:44931ff4a3ed	1193	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
juansal12	0:44931ff4a3ed	1194
juansal12	0:44931ff4a3ed	1195	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
juansal12	0:44931ff4a3ed	1196	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
juansal12	0:44931ff4a3ed	1197
juansal12	0:44931ff4a3ed	1198	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
juansal12	0:44931ff4a3ed	1199	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
juansal12	0:44931ff4a3ed	1200
juansal12	0:44931ff4a3ed	1201	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
juansal12	0:44931ff4a3ed	1202	#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /!< FPCCR: Lazy state preservation active bit Mask /
juansal12	0:44931ff4a3ed	1203
juansal12	0:44931ff4a3ed	1204	/* Floating-Point Context Address Register */
juansal12	0:44931ff4a3ed	1205	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
juansal12	0:44931ff4a3ed	1206	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
juansal12	0:44931ff4a3ed	1207
juansal12	0:44931ff4a3ed	1208	/* Floating-Point Default Status Control Register */
juansal12	0:44931ff4a3ed	1209	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
juansal12	0:44931ff4a3ed	1210	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
juansal12	0:44931ff4a3ed	1211
juansal12	0:44931ff4a3ed	1212	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
juansal12	0:44931ff4a3ed	1213	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
juansal12	0:44931ff4a3ed	1214
juansal12	0:44931ff4a3ed	1215	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
juansal12	0:44931ff4a3ed	1216	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
juansal12	0:44931ff4a3ed	1217
juansal12	0:44931ff4a3ed	1218	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
juansal12	0:44931ff4a3ed	1219	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
juansal12	0:44931ff4a3ed	1220
juansal12	0:44931ff4a3ed	1221	/* Media and FP Feature Register 0 */
juansal12	0:44931ff4a3ed	1222	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
juansal12	0:44931ff4a3ed	1223	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
juansal12	0:44931ff4a3ed	1224
juansal12	0:44931ff4a3ed	1225	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
juansal12	0:44931ff4a3ed	1226	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
juansal12	0:44931ff4a3ed	1227
juansal12	0:44931ff4a3ed	1228	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
juansal12	0:44931ff4a3ed	1229	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
juansal12	0:44931ff4a3ed	1230
juansal12	0:44931ff4a3ed	1231	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
juansal12	0:44931ff4a3ed	1232	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
juansal12	0:44931ff4a3ed	1233
juansal12	0:44931ff4a3ed	1234	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
juansal12	0:44931ff4a3ed	1235	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
juansal12	0:44931ff4a3ed	1236
juansal12	0:44931ff4a3ed	1237	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
juansal12	0:44931ff4a3ed	1238	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
juansal12	0:44931ff4a3ed	1239
juansal12	0:44931ff4a3ed	1240	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
juansal12	0:44931ff4a3ed	1241	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
juansal12	0:44931ff4a3ed	1242
juansal12	0:44931ff4a3ed	1243	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
juansal12	0:44931ff4a3ed	1244	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /!< MVFR0: A_SIMD registers bits Mask /
juansal12	0:44931ff4a3ed	1245
juansal12	0:44931ff4a3ed	1246	/* Media and FP Feature Register 1 */
juansal12	0:44931ff4a3ed	1247	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
juansal12	0:44931ff4a3ed	1248	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
juansal12	0:44931ff4a3ed	1249
juansal12	0:44931ff4a3ed	1250	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
juansal12	0:44931ff4a3ed	1251	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
juansal12	0:44931ff4a3ed	1252
juansal12	0:44931ff4a3ed	1253	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
juansal12	0:44931ff4a3ed	1254	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
juansal12	0:44931ff4a3ed	1255
juansal12	0:44931ff4a3ed	1256	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
juansal12	0:44931ff4a3ed	1257	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /!< MVFR1: FtZ mode bits Mask /
juansal12	0:44931ff4a3ed	1258
juansal12	0:44931ff4a3ed	1259	/@} end of group CMSIS_FPU /
juansal12	0:44931ff4a3ed	1260	#endif
juansal12	0:44931ff4a3ed	1261
juansal12	0:44931ff4a3ed	1262
juansal12	0:44931ff4a3ed	1263	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	1264	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
juansal12	0:44931ff4a3ed	1265	\brief Type definitions for the Core Debug Registers
juansal12	0:44931ff4a3ed	1266	@{
juansal12	0:44931ff4a3ed	1267	*/
juansal12	0:44931ff4a3ed	1268
juansal12	0:44931ff4a3ed	1269	/** \brief Structure type to access the Core Debug Register (CoreDebug).
juansal12	0:44931ff4a3ed	1270	*/
juansal12	0:44931ff4a3ed	1271	typedef struct
juansal12	0:44931ff4a3ed	1272	{
juansal12	0:44931ff4a3ed	1273	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
juansal12	0:44931ff4a3ed	1274	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
juansal12	0:44931ff4a3ed	1275	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
juansal12	0:44931ff4a3ed	1276	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
juansal12	0:44931ff4a3ed	1277	} CoreDebug_Type;
juansal12	0:44931ff4a3ed	1278
juansal12	0:44931ff4a3ed	1279	/* Debug Halting Control and Status Register */
juansal12	0:44931ff4a3ed	1280	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
juansal12	0:44931ff4a3ed	1281	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
juansal12	0:44931ff4a3ed	1282
juansal12	0:44931ff4a3ed	1283	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
juansal12	0:44931ff4a3ed	1284	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
juansal12	0:44931ff4a3ed	1285
juansal12	0:44931ff4a3ed	1286	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
juansal12	0:44931ff4a3ed	1287	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
juansal12	0:44931ff4a3ed	1288
juansal12	0:44931ff4a3ed	1289	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
juansal12	0:44931ff4a3ed	1290	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
juansal12	0:44931ff4a3ed	1291
juansal12	0:44931ff4a3ed	1292	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
juansal12	0:44931ff4a3ed	1293	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
juansal12	0:44931ff4a3ed	1294
juansal12	0:44931ff4a3ed	1295	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
juansal12	0:44931ff4a3ed	1296	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
juansal12	0:44931ff4a3ed	1297
juansal12	0:44931ff4a3ed	1298	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
juansal12	0:44931ff4a3ed	1299	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
juansal12	0:44931ff4a3ed	1300
juansal12	0:44931ff4a3ed	1301	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
juansal12	0:44931ff4a3ed	1302	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
juansal12	0:44931ff4a3ed	1303
juansal12	0:44931ff4a3ed	1304	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
juansal12	0:44931ff4a3ed	1305	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
juansal12	0:44931ff4a3ed	1306
juansal12	0:44931ff4a3ed	1307	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
juansal12	0:44931ff4a3ed	1308	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
juansal12	0:44931ff4a3ed	1309
juansal12	0:44931ff4a3ed	1310	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
juansal12	0:44931ff4a3ed	1311	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
juansal12	0:44931ff4a3ed	1312
juansal12	0:44931ff4a3ed	1313	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
juansal12	0:44931ff4a3ed	1314	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
juansal12	0:44931ff4a3ed	1315
juansal12	0:44931ff4a3ed	1316	/* Debug Core Register Selector Register */
juansal12	0:44931ff4a3ed	1317	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
juansal12	0:44931ff4a3ed	1318	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
juansal12	0:44931ff4a3ed	1319
juansal12	0:44931ff4a3ed	1320	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
juansal12	0:44931ff4a3ed	1321	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
juansal12	0:44931ff4a3ed	1322
juansal12	0:44931ff4a3ed	1323	/* Debug Exception and Monitor Control Register */
juansal12	0:44931ff4a3ed	1324	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
juansal12	0:44931ff4a3ed	1325	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
juansal12	0:44931ff4a3ed	1326
juansal12	0:44931ff4a3ed	1327	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
juansal12	0:44931ff4a3ed	1328	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
juansal12	0:44931ff4a3ed	1329
juansal12	0:44931ff4a3ed	1330	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
juansal12	0:44931ff4a3ed	1331	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
juansal12	0:44931ff4a3ed	1332
juansal12	0:44931ff4a3ed	1333	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
juansal12	0:44931ff4a3ed	1334	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
juansal12	0:44931ff4a3ed	1335
juansal12	0:44931ff4a3ed	1336	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
juansal12	0:44931ff4a3ed	1337	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
juansal12	0:44931ff4a3ed	1338
juansal12	0:44931ff4a3ed	1339	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
juansal12	0:44931ff4a3ed	1340	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
juansal12	0:44931ff4a3ed	1341
juansal12	0:44931ff4a3ed	1342	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
juansal12	0:44931ff4a3ed	1343	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
juansal12	0:44931ff4a3ed	1344
juansal12	0:44931ff4a3ed	1345	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
juansal12	0:44931ff4a3ed	1346	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
juansal12	0:44931ff4a3ed	1347
juansal12	0:44931ff4a3ed	1348	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
juansal12	0:44931ff4a3ed	1349	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
juansal12	0:44931ff4a3ed	1350
juansal12	0:44931ff4a3ed	1351	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
juansal12	0:44931ff4a3ed	1352	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
juansal12	0:44931ff4a3ed	1353
juansal12	0:44931ff4a3ed	1354	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
juansal12	0:44931ff4a3ed	1355	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
juansal12	0:44931ff4a3ed	1356
juansal12	0:44931ff4a3ed	1357	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
juansal12	0:44931ff4a3ed	1358	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
juansal12	0:44931ff4a3ed	1359
juansal12	0:44931ff4a3ed	1360	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
juansal12	0:44931ff4a3ed	1361	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
juansal12	0:44931ff4a3ed	1362
juansal12	0:44931ff4a3ed	1363	/@} end of group CMSIS_CoreDebug /
juansal12	0:44931ff4a3ed	1364
juansal12	0:44931ff4a3ed	1365
juansal12	0:44931ff4a3ed	1366	/** \ingroup CMSIS_core_register
juansal12	0:44931ff4a3ed	1367	\defgroup CMSIS_core_base Core Definitions
juansal12	0:44931ff4a3ed	1368	\brief Definitions for base addresses, unions, and structures.
juansal12	0:44931ff4a3ed	1369	@{
juansal12	0:44931ff4a3ed	1370	*/
juansal12	0:44931ff4a3ed	1371
juansal12	0:44931ff4a3ed	1372	/* Memory mapping of Cortex-M4 Hardware */
juansal12	0:44931ff4a3ed	1373	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
juansal12	0:44931ff4a3ed	1374	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
juansal12	0:44931ff4a3ed	1375	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
juansal12	0:44931ff4a3ed	1376	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
juansal12	0:44931ff4a3ed	1377	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
juansal12	0:44931ff4a3ed	1378	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
juansal12	0:44931ff4a3ed	1379	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
juansal12	0:44931ff4a3ed	1380	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
juansal12	0:44931ff4a3ed	1381
juansal12	0:44931ff4a3ed	1382	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
juansal12	0:44931ff4a3ed	1383	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
juansal12	0:44931ff4a3ed	1384	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
juansal12	0:44931ff4a3ed	1385	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
juansal12	0:44931ff4a3ed	1386	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
juansal12	0:44931ff4a3ed	1387	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
juansal12	0:44931ff4a3ed	1388	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
juansal12	0:44931ff4a3ed	1389	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
juansal12	0:44931ff4a3ed	1390
juansal12	0:44931ff4a3ed	1391	#if (__MPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	1392	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
juansal12	0:44931ff4a3ed	1393	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
juansal12	0:44931ff4a3ed	1394	#endif
juansal12	0:44931ff4a3ed	1395
juansal12	0:44931ff4a3ed	1396	#if (__FPU_PRESENT == 1)
juansal12	0:44931ff4a3ed	1397	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
juansal12	0:44931ff4a3ed	1398	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
juansal12	0:44931ff4a3ed	1399	#endif
juansal12	0:44931ff4a3ed	1400
juansal12	0:44931ff4a3ed	1401	/@} /
juansal12	0:44931ff4a3ed	1402
juansal12	0:44931ff4a3ed	1403
juansal12	0:44931ff4a3ed	1404
juansal12	0:44931ff4a3ed	1405	/*******************************************************************************
juansal12	0:44931ff4a3ed	1406	* Hardware Abstraction Layer
juansal12	0:44931ff4a3ed	1407	Core Function Interface contains:
juansal12	0:44931ff4a3ed	1408	- Core NVIC Functions
juansal12	0:44931ff4a3ed	1409	- Core SysTick Functions
juansal12	0:44931ff4a3ed	1410	- Core Debug Functions
juansal12	0:44931ff4a3ed	1411	- Core Register Access Functions
juansal12	0:44931ff4a3ed	1412	******************************************************************************/
juansal12	0:44931ff4a3ed	1413	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
juansal12	0:44931ff4a3ed	1414	*/
juansal12	0:44931ff4a3ed	1415
juansal12	0:44931ff4a3ed	1416
juansal12	0:44931ff4a3ed	1417
juansal12	0:44931ff4a3ed	1418	/* ########################## NVIC functions #################################### */
juansal12	0:44931ff4a3ed	1419	/** \ingroup CMSIS_Core_FunctionInterface
juansal12	0:44931ff4a3ed	1420	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
juansal12	0:44931ff4a3ed	1421	\brief Functions that manage interrupts and exceptions via the NVIC.
juansal12	0:44931ff4a3ed	1422	@{
juansal12	0:44931ff4a3ed	1423	*/
juansal12	0:44931ff4a3ed	1424
juansal12	0:44931ff4a3ed	1425	/** \brief Set Priority Grouping
juansal12	0:44931ff4a3ed	1426
juansal12	0:44931ff4a3ed	1427	The function sets the priority grouping field using the required unlock sequence.
juansal12	0:44931ff4a3ed	1428	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
juansal12	0:44931ff4a3ed	1429	Only values from 0..7 are used.
juansal12	0:44931ff4a3ed	1430	In case of a conflict between priority grouping and available
juansal12	0:44931ff4a3ed	1431	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
juansal12	0:44931ff4a3ed	1432
juansal12	0:44931ff4a3ed	1433	\param [in] PriorityGroup Priority grouping field.
juansal12	0:44931ff4a3ed	1434	*/
juansal12	0:44931ff4a3ed	1435	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
juansal12	0:44931ff4a3ed	1436	{
juansal12	0:44931ff4a3ed	1437	uint32_t reg_value;
juansal12	0:44931ff4a3ed	1438	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
juansal12	0:44931ff4a3ed	1439
juansal12	0:44931ff4a3ed	1440	reg_value = SCB->AIRCR; /* read old register configuration */
juansal12	0:44931ff4a3ed	1441	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
juansal12	0:44931ff4a3ed	1442	reg_value = (reg_value \|
juansal12	0:44931ff4a3ed	1443	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
juansal12	0:44931ff4a3ed	1444	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
juansal12	0:44931ff4a3ed	1445	SCB->AIRCR = reg_value;
juansal12	0:44931ff4a3ed	1446	}
juansal12	0:44931ff4a3ed	1447
juansal12	0:44931ff4a3ed	1448
juansal12	0:44931ff4a3ed	1449	/** \brief Get Priority Grouping
juansal12	0:44931ff4a3ed	1450
juansal12	0:44931ff4a3ed	1451	The function reads the priority grouping field from the NVIC Interrupt Controller.
juansal12	0:44931ff4a3ed	1452
juansal12	0:44931ff4a3ed	1453	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
juansal12	0:44931ff4a3ed	1454	*/
juansal12	0:44931ff4a3ed	1455	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
juansal12	0:44931ff4a3ed	1456	{
juansal12	0:44931ff4a3ed	1457	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
juansal12	0:44931ff4a3ed	1458	}
juansal12	0:44931ff4a3ed	1459
juansal12	0:44931ff4a3ed	1460
juansal12	0:44931ff4a3ed	1461	/** \brief Enable External Interrupt
juansal12	0:44931ff4a3ed	1462
juansal12	0:44931ff4a3ed	1463	The function enables a device-specific interrupt in the NVIC interrupt controller.
juansal12	0:44931ff4a3ed	1464
juansal12	0:44931ff4a3ed	1465	\param [in] IRQn External interrupt number. Value cannot be negative.
juansal12	0:44931ff4a3ed	1466	*/
juansal12	0:44931ff4a3ed	1467	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1468	{
juansal12	0:44931ff4a3ed	1469	/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
juansal12	0:44931ff4a3ed	1470	NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
juansal12	0:44931ff4a3ed	1471	}
juansal12	0:44931ff4a3ed	1472
juansal12	0:44931ff4a3ed	1473
juansal12	0:44931ff4a3ed	1474	/** \brief Disable External Interrupt
juansal12	0:44931ff4a3ed	1475
juansal12	0:44931ff4a3ed	1476	The function disables a device-specific interrupt in the NVIC interrupt controller.
juansal12	0:44931ff4a3ed	1477
juansal12	0:44931ff4a3ed	1478	\param [in] IRQn External interrupt number. Value cannot be negative.
juansal12	0:44931ff4a3ed	1479	*/
juansal12	0:44931ff4a3ed	1480	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1481	{
juansal12	0:44931ff4a3ed	1482	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
juansal12	0:44931ff4a3ed	1483	}
juansal12	0:44931ff4a3ed	1484
juansal12	0:44931ff4a3ed	1485
juansal12	0:44931ff4a3ed	1486	/** \brief Get Pending Interrupt
juansal12	0:44931ff4a3ed	1487
juansal12	0:44931ff4a3ed	1488	The function reads the pending register in the NVIC and returns the pending bit
juansal12	0:44931ff4a3ed	1489	for the specified interrupt.
juansal12	0:44931ff4a3ed	1490
juansal12	0:44931ff4a3ed	1491	\param [in] IRQn Interrupt number.
juansal12	0:44931ff4a3ed	1492
juansal12	0:44931ff4a3ed	1493	\return 0 Interrupt status is not pending.
juansal12	0:44931ff4a3ed	1494	\return 1 Interrupt status is pending.
juansal12	0:44931ff4a3ed	1495	*/
juansal12	0:44931ff4a3ed	1496	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1497	{
juansal12	0:44931ff4a3ed	1498	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
juansal12	0:44931ff4a3ed	1499	}
juansal12	0:44931ff4a3ed	1500
juansal12	0:44931ff4a3ed	1501
juansal12	0:44931ff4a3ed	1502	/** \brief Set Pending Interrupt
juansal12	0:44931ff4a3ed	1503
juansal12	0:44931ff4a3ed	1504	The function sets the pending bit of an external interrupt.
juansal12	0:44931ff4a3ed	1505
juansal12	0:44931ff4a3ed	1506	\param [in] IRQn Interrupt number. Value cannot be negative.
juansal12	0:44931ff4a3ed	1507	*/
juansal12	0:44931ff4a3ed	1508	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1509	{
juansal12	0:44931ff4a3ed	1510	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
juansal12	0:44931ff4a3ed	1511	}
juansal12	0:44931ff4a3ed	1512
juansal12	0:44931ff4a3ed	1513
juansal12	0:44931ff4a3ed	1514	/** \brief Clear Pending Interrupt
juansal12	0:44931ff4a3ed	1515
juansal12	0:44931ff4a3ed	1516	The function clears the pending bit of an external interrupt.
juansal12	0:44931ff4a3ed	1517
juansal12	0:44931ff4a3ed	1518	\param [in] IRQn External interrupt number. Value cannot be negative.
juansal12	0:44931ff4a3ed	1519	*/
juansal12	0:44931ff4a3ed	1520	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1521	{
juansal12	0:44931ff4a3ed	1522	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
juansal12	0:44931ff4a3ed	1523	}
juansal12	0:44931ff4a3ed	1524
juansal12	0:44931ff4a3ed	1525
juansal12	0:44931ff4a3ed	1526	/** \brief Get Active Interrupt
juansal12	0:44931ff4a3ed	1527
juansal12	0:44931ff4a3ed	1528	The function reads the active register in NVIC and returns the active bit.
juansal12	0:44931ff4a3ed	1529
juansal12	0:44931ff4a3ed	1530	\param [in] IRQn Interrupt number.
juansal12	0:44931ff4a3ed	1531
juansal12	0:44931ff4a3ed	1532	\return 0 Interrupt status is not active.
juansal12	0:44931ff4a3ed	1533	\return 1 Interrupt status is active.
juansal12	0:44931ff4a3ed	1534	*/
juansal12	0:44931ff4a3ed	1535	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1536	{
juansal12	0:44931ff4a3ed	1537	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
juansal12	0:44931ff4a3ed	1538	}
juansal12	0:44931ff4a3ed	1539
juansal12	0:44931ff4a3ed	1540
juansal12	0:44931ff4a3ed	1541	/** \brief Set Interrupt Priority
juansal12	0:44931ff4a3ed	1542
juansal12	0:44931ff4a3ed	1543	The function sets the priority of an interrupt.
juansal12	0:44931ff4a3ed	1544
juansal12	0:44931ff4a3ed	1545	\note The priority cannot be set for every core interrupt.
juansal12	0:44931ff4a3ed	1546
juansal12	0:44931ff4a3ed	1547	\param [in] IRQn Interrupt number.
juansal12	0:44931ff4a3ed	1548	\param [in] priority Priority to set.
juansal12	0:44931ff4a3ed	1549	*/
juansal12	0:44931ff4a3ed	1550	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
juansal12	0:44931ff4a3ed	1551	{
juansal12	0:44931ff4a3ed	1552	if(IRQn < 0) {
juansal12	0:44931ff4a3ed	1553	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
juansal12	0:44931ff4a3ed	1554	else {
juansal12	0:44931ff4a3ed	1555	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
juansal12	0:44931ff4a3ed	1556	}
juansal12	0:44931ff4a3ed	1557
juansal12	0:44931ff4a3ed	1558
juansal12	0:44931ff4a3ed	1559	/** \brief Get Interrupt Priority
juansal12	0:44931ff4a3ed	1560
juansal12	0:44931ff4a3ed	1561	The function reads the priority of an interrupt. The interrupt
juansal12	0:44931ff4a3ed	1562	number can be positive to specify an external (device specific)
juansal12	0:44931ff4a3ed	1563	interrupt, or negative to specify an internal (core) interrupt.
juansal12	0:44931ff4a3ed	1564
juansal12	0:44931ff4a3ed	1565
juansal12	0:44931ff4a3ed	1566	\param [in] IRQn Interrupt number.
juansal12	0:44931ff4a3ed	1567	\return Interrupt Priority. Value is aligned automatically to the implemented
juansal12	0:44931ff4a3ed	1568	priority bits of the microcontroller.
juansal12	0:44931ff4a3ed	1569	*/
juansal12	0:44931ff4a3ed	1570	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
juansal12	0:44931ff4a3ed	1571	{
juansal12	0:44931ff4a3ed	1572
juansal12	0:44931ff4a3ed	1573	if(IRQn < 0) {
juansal12	0:44931ff4a3ed	1574	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
juansal12	0:44931ff4a3ed	1575	else {
juansal12	0:44931ff4a3ed	1576	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
juansal12	0:44931ff4a3ed	1577	}
juansal12	0:44931ff4a3ed	1578
juansal12	0:44931ff4a3ed	1579
juansal12	0:44931ff4a3ed	1580	/** \brief Encode Priority
juansal12	0:44931ff4a3ed	1581
juansal12	0:44931ff4a3ed	1582	The function encodes the priority for an interrupt with the given priority group,
juansal12	0:44931ff4a3ed	1583	preemptive priority value, and subpriority value.
juansal12	0:44931ff4a3ed	1584	In case of a conflict between priority grouping and available
juansal12	0:44931ff4a3ed	1585	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
juansal12	0:44931ff4a3ed	1586
juansal12	0:44931ff4a3ed	1587	\param [in] PriorityGroup Used priority group.
juansal12	0:44931ff4a3ed	1588	\param [in] PreemptPriority Preemptive priority value (starting from 0).
juansal12	0:44931ff4a3ed	1589	\param [in] SubPriority Subpriority value (starting from 0).
juansal12	0:44931ff4a3ed	1590	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
juansal12	0:44931ff4a3ed	1591	*/
juansal12	0:44931ff4a3ed	1592	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
juansal12	0:44931ff4a3ed	1593	{
juansal12	0:44931ff4a3ed	1594	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
juansal12	0:44931ff4a3ed	1595	uint32_t PreemptPriorityBits;
juansal12	0:44931ff4a3ed	1596	uint32_t SubPriorityBits;
juansal12	0:44931ff4a3ed	1597
juansal12	0:44931ff4a3ed	1598	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
juansal12	0:44931ff4a3ed	1599	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
juansal12	0:44931ff4a3ed	1600
juansal12	0:44931ff4a3ed	1601	return (
juansal12	0:44931ff4a3ed	1602	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
juansal12	0:44931ff4a3ed	1603	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
juansal12	0:44931ff4a3ed	1604	);
juansal12	0:44931ff4a3ed	1605	}
juansal12	0:44931ff4a3ed	1606
juansal12	0:44931ff4a3ed	1607
juansal12	0:44931ff4a3ed	1608	/** \brief Decode Priority
juansal12	0:44931ff4a3ed	1609
juansal12	0:44931ff4a3ed	1610	The function decodes an interrupt priority value with a given priority group to
juansal12	0:44931ff4a3ed	1611	preemptive priority value and subpriority value.
juansal12	0:44931ff4a3ed	1612	In case of a conflict between priority grouping and available
juansal12	0:44931ff4a3ed	1613	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
juansal12	0:44931ff4a3ed	1614
juansal12	0:44931ff4a3ed	1615	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
juansal12	0:44931ff4a3ed	1616	\param [in] PriorityGroup Used priority group.
juansal12	0:44931ff4a3ed	1617	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
juansal12	0:44931ff4a3ed	1618	\param [out] pSubPriority Subpriority value (starting from 0).
juansal12	0:44931ff4a3ed	1619	*/
juansal12	0:44931ff4a3ed	1620	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
juansal12	0:44931ff4a3ed	1621	{
juansal12	0:44931ff4a3ed	1622	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
juansal12	0:44931ff4a3ed	1623	uint32_t PreemptPriorityBits;
juansal12	0:44931ff4a3ed	1624	uint32_t SubPriorityBits;
juansal12	0:44931ff4a3ed	1625
juansal12	0:44931ff4a3ed	1626	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
juansal12	0:44931ff4a3ed	1627	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
juansal12	0:44931ff4a3ed	1628
juansal12	0:44931ff4a3ed	1629	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
juansal12	0:44931ff4a3ed	1630	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
juansal12	0:44931ff4a3ed	1631	}
juansal12	0:44931ff4a3ed	1632
juansal12	0:44931ff4a3ed	1633
juansal12	0:44931ff4a3ed	1634	/** \brief System Reset
juansal12	0:44931ff4a3ed	1635
juansal12	0:44931ff4a3ed	1636	The function initiates a system reset request to reset the MCU.
juansal12	0:44931ff4a3ed	1637	*/
juansal12	0:44931ff4a3ed	1638	__STATIC_INLINE void NVIC_SystemReset(void)
juansal12	0:44931ff4a3ed	1639	{
juansal12	0:44931ff4a3ed	1640	__DSB(); /* Ensure all outstanding memory accesses included
juansal12	0:44931ff4a3ed	1641	buffered write are completed before reset */
juansal12	0:44931ff4a3ed	1642	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
juansal12	0:44931ff4a3ed	1643	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
juansal12	0:44931ff4a3ed	1644	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
juansal12	0:44931ff4a3ed	1645	__DSB(); /* Ensure completion of memory access */
juansal12	0:44931ff4a3ed	1646	while(1); /* wait until reset */
juansal12	0:44931ff4a3ed	1647	}
juansal12	0:44931ff4a3ed	1648
juansal12	0:44931ff4a3ed	1649	/@} end of CMSIS_Core_NVICFunctions /
juansal12	0:44931ff4a3ed	1650
juansal12	0:44931ff4a3ed	1651
juansal12	0:44931ff4a3ed	1652
juansal12	0:44931ff4a3ed	1653	/* ################################## SysTick function ############################################ */
juansal12	0:44931ff4a3ed	1654	/** \ingroup CMSIS_Core_FunctionInterface
juansal12	0:44931ff4a3ed	1655	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
juansal12	0:44931ff4a3ed	1656	\brief Functions that configure the System.
juansal12	0:44931ff4a3ed	1657	@{
juansal12	0:44931ff4a3ed	1658	*/
juansal12	0:44931ff4a3ed	1659
juansal12	0:44931ff4a3ed	1660	#if (__Vendor_SysTickConfig == 0)
juansal12	0:44931ff4a3ed	1661
juansal12	0:44931ff4a3ed	1662	/** \brief System Tick Configuration
juansal12	0:44931ff4a3ed	1663
juansal12	0:44931ff4a3ed	1664	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
juansal12	0:44931ff4a3ed	1665	Counter is in free running mode to generate periodic interrupts.
juansal12	0:44931ff4a3ed	1666
juansal12	0:44931ff4a3ed	1667	\param [in] ticks Number of ticks between two interrupts.
juansal12	0:44931ff4a3ed	1668
juansal12	0:44931ff4a3ed	1669	\return 0 Function succeeded.
juansal12	0:44931ff4a3ed	1670	\return 1 Function failed.
juansal12	0:44931ff4a3ed	1671
juansal12	0:44931ff4a3ed	1672	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
juansal12	0:44931ff4a3ed	1673	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
juansal12	0:44931ff4a3ed	1674	must contain a vendor-specific implementation of this function.
juansal12	0:44931ff4a3ed	1675
juansal12	0:44931ff4a3ed	1676	*/
juansal12	0:44931ff4a3ed	1677	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
juansal12	0:44931ff4a3ed	1678	{
juansal12	0:44931ff4a3ed	1679	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
juansal12	0:44931ff4a3ed	1680
juansal12	0:44931ff4a3ed	1681	SysTick->LOAD = ticks - 1; /* set reload register */
juansal12	0:44931ff4a3ed	1682	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
juansal12	0:44931ff4a3ed	1683	SysTick->VAL = 0; /* Load the SysTick Counter Value */
juansal12	0:44931ff4a3ed	1684	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
juansal12	0:44931ff4a3ed	1685	SysTick_CTRL_TICKINT_Msk \|
juansal12	0:44931ff4a3ed	1686	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
juansal12	0:44931ff4a3ed	1687	return (0); /* Function successful */
juansal12	0:44931ff4a3ed	1688	}
juansal12	0:44931ff4a3ed	1689
juansal12	0:44931ff4a3ed	1690	#endif
juansal12	0:44931ff4a3ed	1691
juansal12	0:44931ff4a3ed	1692	/@} end of CMSIS_Core_SysTickFunctions /
juansal12	0:44931ff4a3ed	1693
juansal12	0:44931ff4a3ed	1694
juansal12	0:44931ff4a3ed	1695
juansal12	0:44931ff4a3ed	1696	/* ##################################### Debug In/Output function ########################################### */
juansal12	0:44931ff4a3ed	1697	/** \ingroup CMSIS_Core_FunctionInterface
juansal12	0:44931ff4a3ed	1698	\defgroup CMSIS_core_DebugFunctions ITM Functions
juansal12	0:44931ff4a3ed	1699	\brief Functions that access the ITM debug interface.
juansal12	0:44931ff4a3ed	1700	@{
juansal12	0:44931ff4a3ed	1701	*/
juansal12	0:44931ff4a3ed	1702
juansal12	0:44931ff4a3ed	1703	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
juansal12	0:44931ff4a3ed	1704	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
juansal12	0:44931ff4a3ed	1705
juansal12	0:44931ff4a3ed	1706
juansal12	0:44931ff4a3ed	1707	/** \brief ITM Send Character
juansal12	0:44931ff4a3ed	1708
juansal12	0:44931ff4a3ed	1709	The function transmits a character via the ITM channel 0, and
juansal12	0:44931ff4a3ed	1710	\li Just returns when no debugger is connected that has booked the output.
juansal12	0:44931ff4a3ed	1711	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
juansal12	0:44931ff4a3ed	1712
juansal12	0:44931ff4a3ed	1713	\param [in] ch Character to transmit.
juansal12	0:44931ff4a3ed	1714
juansal12	0:44931ff4a3ed	1715	\returns Character to transmit.
juansal12	0:44931ff4a3ed	1716	*/
juansal12	0:44931ff4a3ed	1717	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
juansal12	0:44931ff4a3ed	1718	{
juansal12	0:44931ff4a3ed	1719	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
juansal12	0:44931ff4a3ed	1720	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
juansal12	0:44931ff4a3ed	1721	{
juansal12	0:44931ff4a3ed	1722	while (ITM->PORT[0].u32 == 0);
juansal12	0:44931ff4a3ed	1723	ITM->PORT[0].u8 = (uint8_t) ch;
juansal12	0:44931ff4a3ed	1724	}
juansal12	0:44931ff4a3ed	1725	return (ch);
juansal12	0:44931ff4a3ed	1726	}
juansal12	0:44931ff4a3ed	1727
juansal12	0:44931ff4a3ed	1728
juansal12	0:44931ff4a3ed	1729	/** \brief ITM Receive Character
juansal12	0:44931ff4a3ed	1730
juansal12	0:44931ff4a3ed	1731	The function inputs a character via the external variable \ref ITM_RxBuffer.
juansal12	0:44931ff4a3ed	1732
juansal12	0:44931ff4a3ed	1733	\return Received character.
juansal12	0:44931ff4a3ed	1734	\return -1 No character pending.
juansal12	0:44931ff4a3ed	1735	*/
juansal12	0:44931ff4a3ed	1736	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
juansal12	0:44931ff4a3ed	1737	int32_t ch = -1; /* no character available */
juansal12	0:44931ff4a3ed	1738
juansal12	0:44931ff4a3ed	1739	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
juansal12	0:44931ff4a3ed	1740	ch = ITM_RxBuffer;
juansal12	0:44931ff4a3ed	1741	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
juansal12	0:44931ff4a3ed	1742	}
juansal12	0:44931ff4a3ed	1743
juansal12	0:44931ff4a3ed	1744	return (ch);
juansal12	0:44931ff4a3ed	1745	}
juansal12	0:44931ff4a3ed	1746
juansal12	0:44931ff4a3ed	1747
juansal12	0:44931ff4a3ed	1748	/** \brief ITM Check Character
juansal12	0:44931ff4a3ed	1749
juansal12	0:44931ff4a3ed	1750	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
juansal12	0:44931ff4a3ed	1751
juansal12	0:44931ff4a3ed	1752	\return 0 No character available.
juansal12	0:44931ff4a3ed	1753	\return 1 Character available.
juansal12	0:44931ff4a3ed	1754	*/
juansal12	0:44931ff4a3ed	1755	__STATIC_INLINE int32_t ITM_CheckChar (void) {
juansal12	0:44931ff4a3ed	1756
juansal12	0:44931ff4a3ed	1757	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
juansal12	0:44931ff4a3ed	1758	return (0); /* no character available */
juansal12	0:44931ff4a3ed	1759	} else {
juansal12	0:44931ff4a3ed	1760	return (1); /* character available */
juansal12	0:44931ff4a3ed	1761	}
juansal12	0:44931ff4a3ed	1762	}
juansal12	0:44931ff4a3ed	1763
juansal12	0:44931ff4a3ed	1764	/@} end of CMSIS_core_DebugFunctions /
juansal12	0:44931ff4a3ed	1765
juansal12	0:44931ff4a3ed	1766	#endif /* __CORE_CM4_H_DEPENDANT */
juansal12	0:44931ff4a3ed	1767
juansal12	0:44931ff4a3ed	1768	#endif /* __CMSIS_GENERIC */
juansal12	0:44931ff4a3ed	1769
juansal12	0:44931ff4a3ed	1770	#ifdef __cplusplus
juansal12	0:44931ff4a3ed	1771	}
juansal12	0:44931ff4a3ed	1772	#endif

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	14 Jan 2020
Imports:	6
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_LPC1768/core_cm4.h@0:44931ff4a3ed, 2020-01-14 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning