Revision 4:3bad83de58b3, committed 2020-04-29

Comitter:

jtarasidis

Date:

Wed Apr 29 15:01:23 2020 +0000

Parent:

3:c9f3ff8e49c0

Commit message:

newest rev

Changed in this revision

--- a/main.cpp	Sat Apr 25 23:51:58 2020 +0000
+++ b/main.cpp	Wed Apr 29 15:01:23 2020 +0000
@@ -1,13 +1,19 @@
 #include "mbed.h"
-//#include "SDFileSystem"
-//#include "FastIO.h"
-//#include "MODDMA.h"
+
+/////////////////global variables/////////////////////////
+//create frame buffer in peripheral SRAM bank 0 and bank 1
+//unsigned char *framebuffer = (unsigned char *)(0x2007C000);
+
+//volatile unsigned char *pointer = framebuffer;
+
+//static unsigned line_counter;
+/////////////////end global variables/////////////////////
 
 //assert PLL0CFG and PLL0CON regs
 void main_pll_feed() {
     __disable_irq();
-    LPC_SC->PLL0FEED=0x000000aa;
-    LPC_SC->PLL0FEED=0x00000055;
+    LPC_SC -> PLL0FEED = 0x000000aa;
+    LPC_SC -> PLL0FEED = 0x00000055;
     __enable_irq();    
 }
 
@@ -15,29 +21,29 @@
 void init_main_pll() {
     // the MBED crystal oscillator is 12 MHz
     // main oscillator frequency 300 MHz: M = (300 x N) / (2 x 12)
-    int n=2;
-    int m=25;
+    int n = 2;
+    int m = 25;
     // processor clock 100 MHz = 300 MHz / D
-    int d=3;
+    int d = 3;
     // disconnect
-    LPC_SC->PLL0CON=0x00000001; main_pll_feed();
+    LPC_SC -> PLL0CON = 0x00000001; main_pll_feed();
     // disable
-    LPC_SC->PLL0CON=0x00000000; main_pll_feed();
+    LPC_SC -> PLL0CON = 0x00000000; main_pll_feed();
     // set new PLL values
-    LPC_SC->PLL0CFG=((n-1)<<16)|(m-1); main_pll_feed();
+    LPC_SC -> PLL0CFG = ((n-1)<<16)|(m-1); main_pll_feed();
     // enable
-    LPC_SC->PLL0CON=0x00000001; main_pll_feed();
+    LPC_SC -> PLL0CON = 0x00000001; main_pll_feed();
     // set cpu clock divider
-    LPC_SC->CCLKCFG=d-1;
+    LPC_SC -> CCLKCFG = (d-1);
     // wait for lock
-    while (LPC_SC->PLL0STAT&0x04000000==0);
+    while (LPC_SC -> PLL0STAT&0x04000000==0);
     // connect
-    LPC_SC->PLL0CON=0x00000003; main_pll_feed();
+    LPC_SC -> PLL0CON = 0x00000003; main_pll_feed();
 }
 
 
 void init_hsync() {
-    LPC_SC -> PCONP = 0;
+    //LPC_SC -> PCONP = 0;
     //power on pwm
     LPC_SC -> PCONP |= (1<<6);
     //set pwm periph clock
@@ -70,6 +76,35 @@
     LPC_PWM1 -> TCR |= 8;
 }
 
+void init_vysnc() {
+    ///////////////////////////
+    //power timer 3 (0/1 used by DMA)
+    //LPC_SC -> PCONP |= (1<<23);
+    //set timer periph clock - CCLK/4 = 25MHz by default
+    //LPC_SC -> PCLKSEL1 |= (0<<12);
+    //pin select (MAT3.1 on 0.11 -> DIP 27)
+    //LPC_PINCON -> PINSEL0 |= (3<<22);
+    //pin mode
+    //LPC_PINCON -> PINMODE0 |= (1<<23);
+    //set TC reset time
+    //LPC_TIM3 -> MR0 = 359200;
+    //set reset on MR0
+    //LPC_TIM3 -> MCR |= (1<<1);
+    //toggle at 331200
+    //LPC_TIM3 -> MR1 = 331200;
+    //set toggle on match
+    //LPC_TIM3 -> EMR |= (1<<1);
+    //enable toggle on match
+    //LPC_TIM3 -> EMR |= (3<<6);
+    //timer enable
+    //LPC_TIM3 -> TCR |= 1;
+    /////////////////////////////
+    
+}
+DigitalOut vsync(p27);
+//void init_i2s() {
+DigitalOut pixel(p21);
+
 int main() {
     init_main_pll();
     main_pll_feed();
@@ -77,9 +112,9 @@
     init_hsync();
     hsync_enable();
     
-    
+    init_vysnc();
     
-    
+    pixel = 1;
     //char s[] = "I2S CCLK/4 Verification Test";
     
     //turn on i2s periph
@@ -119,7 +154,18 @@
     //dma.Setup(config);
     //dma.Enable(config);
     while(1) {
-        
+        //if (LPC_TIM3 -> TC > 331200) {
+        //    LPC_TIM3 -> MR1 = 329600;
+        //} else {
+        //    LPC_TIM3 -> MR1 = 331200;
+        //}
+        //printf("%x/n/r", LPC_PWM1 -> TC);
+        vsync = 1;
+        wait_us(13400);
+        vsync = 0;
+        wait_us(80);
+        vsync = 1;
+        wait_us(1300);
     }
 }