The first video game for the mbed video game console. The code utilizes the SimpleLib package developed by thomas@soete.org. For more information about the project and if you'd like to download the schematics and PCB design visit http://www.mbedgc.com/
timers.h@0:31cd577d85a4, 2011-07-09 (annotated)
- Committer:
- jp
- Date:
- Sat Jul 09 15:47:27 2011 +0000
- Revision:
- 0:31cd577d85a4
Initial release of Snake for the mbed Game Console.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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jp | 0:31cd577d85a4 | 1 | /* |
jp | 0:31cd577d85a4 | 2 | * Copyright or � or Copr. 2010, Thomas SOETE |
jp | 0:31cd577d85a4 | 3 | * |
jp | 0:31cd577d85a4 | 4 | * Author e-mail: thomas@soete.org |
jp | 0:31cd577d85a4 | 5 | * Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/ |
jp | 0:31cd577d85a4 | 6 | * |
jp | 0:31cd577d85a4 | 7 | * This software is governed by the CeCILL license under French law and |
jp | 0:31cd577d85a4 | 8 | * abiding by the rules of distribution of free software. You can use, |
jp | 0:31cd577d85a4 | 9 | * modify and/ or redistribute the software under the terms of the CeCILL |
jp | 0:31cd577d85a4 | 10 | * license as circulated by CEA, CNRS and INRIA at the following URL |
jp | 0:31cd577d85a4 | 11 | * "http://www.cecill.info". |
jp | 0:31cd577d85a4 | 12 | * |
jp | 0:31cd577d85a4 | 13 | * As a counterpart to the access to the source code and rights to copy, |
jp | 0:31cd577d85a4 | 14 | * modify and redistribute granted by the license, users are provided only |
jp | 0:31cd577d85a4 | 15 | * with a limited warranty and the software's author, the holder of the |
jp | 0:31cd577d85a4 | 16 | * economic rights, and the successive licensors have only limited |
jp | 0:31cd577d85a4 | 17 | * liability. |
jp | 0:31cd577d85a4 | 18 | * |
jp | 0:31cd577d85a4 | 19 | * In this respect, the user's attention is drawn to the risks associated |
jp | 0:31cd577d85a4 | 20 | * with loading, using, modifying and/or developing or reproducing the |
jp | 0:31cd577d85a4 | 21 | * software by the user in light of its specific status of free software, |
jp | 0:31cd577d85a4 | 22 | * that may mean that it is complicated to manipulate, and that also |
jp | 0:31cd577d85a4 | 23 | * therefore means that it is reserved for developers and experienced |
jp | 0:31cd577d85a4 | 24 | * professionals having in-depth computer knowledge. Users are therefore |
jp | 0:31cd577d85a4 | 25 | * encouraged to load and test the software's suitability as regards their |
jp | 0:31cd577d85a4 | 26 | * requirements in conditions enabling the security of their systems and/or |
jp | 0:31cd577d85a4 | 27 | * data to be ensured and, more generally, to use and operate it in the |
jp | 0:31cd577d85a4 | 28 | * same conditions as regards security. |
jp | 0:31cd577d85a4 | 29 | * |
jp | 0:31cd577d85a4 | 30 | * The fact that you are presently reading this means that you have had |
jp | 0:31cd577d85a4 | 31 | * knowledge of the CeCILL license and that you accept its terms. |
jp | 0:31cd577d85a4 | 32 | */ |
jp | 0:31cd577d85a4 | 33 | |
jp | 0:31cd577d85a4 | 34 | #ifndef __SIMPLELIB_TIMERS_H__ |
jp | 0:31cd577d85a4 | 35 | #define __SIMPLELIB_TIMERS_H__ |
jp | 0:31cd577d85a4 | 36 | |
jp | 0:31cd577d85a4 | 37 | #include "mbed_globals.h" |
jp | 0:31cd577d85a4 | 38 | #include "interrupts.h" |
jp | 0:31cd577d85a4 | 39 | |
jp | 0:31cd577d85a4 | 40 | /********************************** |
jp | 0:31cd577d85a4 | 41 | * Simple Timers Managment * |
jp | 0:31cd577d85a4 | 42 | ********************************** |
jp | 0:31cd577d85a4 | 43 | * The interrupt handler is : * |
jp | 0:31cd577d85a4 | 44 | * TIMERn_INTERRUPT_HANDLER(void) * |
jp | 0:31cd577d85a4 | 45 | **********************************/ |
jp | 0:31cd577d85a4 | 46 | |
jp | 0:31cd577d85a4 | 47 | /** Registers **/ |
jp | 0:31cd577d85a4 | 48 | #define TIMER0_BASE (LPC_TIM0) |
jp | 0:31cd577d85a4 | 49 | #define TIMER1_BASE (LPC_TIM1) |
jp | 0:31cd577d85a4 | 50 | #define TIMER2_BASE (LPC_TIM2) |
jp | 0:31cd577d85a4 | 51 | #define TIMER3_BASE (LPC_TIM3) |
jp | 0:31cd577d85a4 | 52 | #define TIMER_BASE(timer) TOKENPASTE2(timer,_BASE) |
jp | 0:31cd577d85a4 | 53 | |
jp | 0:31cd577d85a4 | 54 | // Peripheral Clock Selection registers (See 4.7.3 p56) |
jp | 0:31cd577d85a4 | 55 | #define TIMER0_PCLK_REG (LPC_SC->PCLKSEL0) |
jp | 0:31cd577d85a4 | 56 | #define TIMER1_PCLK_REG (LPC_SC->PCLKSEL0) |
jp | 0:31cd577d85a4 | 57 | #define TIMER2_PCLK_REG (LPC_SC->PCLKSEL1) |
jp | 0:31cd577d85a4 | 58 | #define TIMER3_PCLK_REG (LPC_SC->PCLKSEL1) |
jp | 0:31cd577d85a4 | 59 | #define TIMER_PCLK_REG(timer) TOKENPASTE2(timer,_PCLK_REG) |
jp | 0:31cd577d85a4 | 60 | |
jp | 0:31cd577d85a4 | 61 | #define TIMER0_PCLK_OFFSET 2 |
jp | 0:31cd577d85a4 | 62 | #define TIMER1_PCLK_OFFSET 4 |
jp | 0:31cd577d85a4 | 63 | #define TIMER2_PCLK_OFFSET 12 |
jp | 0:31cd577d85a4 | 64 | #define TIMER3_PCLK_OFFSET 14 |
jp | 0:31cd577d85a4 | 65 | #define TIMER_PCLK_OFFSET(timer) TOKENPASTE2(timer,_PCLK_OFFSET) |
jp | 0:31cd577d85a4 | 66 | |
jp | 0:31cd577d85a4 | 67 | /** Interrupt handlers **/ |
jp | 0:31cd577d85a4 | 68 | #define TIMER0_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER0) |
jp | 0:31cd577d85a4 | 69 | #define TIMER1_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER1) |
jp | 0:31cd577d85a4 | 70 | #define TIMER2_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER2) |
jp | 0:31cd577d85a4 | 71 | #define TIMER3_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER3) |
jp | 0:31cd577d85a4 | 72 | #define TIMER_INTERRUPT_HANDLER(timer) EXTERN_C void __IRQ TOKENPASTE2(timer,_IRQHandler) |
jp | 0:31cd577d85a4 | 73 | |
jp | 0:31cd577d85a4 | 74 | /** Bits **/ |
jp | 0:31cd577d85a4 | 75 | // Power Control for Peripherals (PCONP, 4.8.7.1 p63) |
jp | 0:31cd577d85a4 | 76 | #define TIMER0_PCONP_BIT 1 |
jp | 0:31cd577d85a4 | 77 | #define TIMER1_PCONP_BIT 2 |
jp | 0:31cd577d85a4 | 78 | #define TIMER2_PCONP_BIT 22 |
jp | 0:31cd577d85a4 | 79 | #define TIMER3_PCONP_BIT 23 |
jp | 0:31cd577d85a4 | 80 | |
jp | 0:31cd577d85a4 | 81 | // Match Control Register (TnMCR, 21.6.8 p496) |
jp | 0:31cd577d85a4 | 82 | #define MATCH_INTERRUPT 1 |
jp | 0:31cd577d85a4 | 83 | #define MATCH_RESET 2 |
jp | 0:31cd577d85a4 | 84 | #define MATCH_STOP 4 |
jp | 0:31cd577d85a4 | 85 | #define MR0_OFFSET 0 |
jp | 0:31cd577d85a4 | 86 | #define MR1_OFFSET 3 |
jp | 0:31cd577d85a4 | 87 | #define MR2_OFFSET 6 |
jp | 0:31cd577d85a4 | 88 | #define MR3_OFFSET 9 |
jp | 0:31cd577d85a4 | 89 | |
jp | 0:31cd577d85a4 | 90 | // Interrupt Register (TnIR, 21.6.1, p493) |
jp | 0:31cd577d85a4 | 91 | #define MR0_INT (1U << 0) |
jp | 0:31cd577d85a4 | 92 | #define MR1_INT (1U << 1) |
jp | 0:31cd577d85a4 | 93 | #define MR2_INT (1U << 2) |
jp | 0:31cd577d85a4 | 94 | #define MR3_INT (1U << 3) |
jp | 0:31cd577d85a4 | 95 | #define CR0_INT (1U << 4) |
jp | 0:31cd577d85a4 | 96 | #define CR1_INT (1U << 5) |
jp | 0:31cd577d85a4 | 97 | |
jp | 0:31cd577d85a4 | 98 | /** Macros **/ |
jp | 0:31cd577d85a4 | 99 | // Enable TIMERn |
jp | 0:31cd577d85a4 | 100 | #define TIMER0_INIT() TIMER_INIT(TIMER0) |
jp | 0:31cd577d85a4 | 101 | #define TIMER1_INIT() TIMER_INIT(TIMER1) |
jp | 0:31cd577d85a4 | 102 | #define TIMER2_INIT() TIMER_INIT(TIMER2) |
jp | 0:31cd577d85a4 | 103 | #define TIMER3_INIT() TIMER_INIT(TIMER3) |
jp | 0:31cd577d85a4 | 104 | #define TIMER_INIT(timer) do { \ |
jp | 0:31cd577d85a4 | 105 | SET_BIT_VALUE(LPC_SC->PCONP, TOKENPASTE2(timer,_PCONP_BIT) , 1); /* Enable Timer */ \ |
jp | 0:31cd577d85a4 | 106 | TIMER_BASE(timer)->TCR = 0x2; /* Reset Timer, Table 427 p493 */ \ |
jp | 0:31cd577d85a4 | 107 | } while(0) |
jp | 0:31cd577d85a4 | 108 | |
jp | 0:31cd577d85a4 | 109 | // Set Peripheral Clock |
jp | 0:31cd577d85a4 | 110 | #define TIMER0_SETPCLK(clk) TIMER_SETPCLK(TIMER0, clk) |
jp | 0:31cd577d85a4 | 111 | #define TIMER1_SETPCLK(clk) TIMER_SETPCLK(TIMER1, clk) |
jp | 0:31cd577d85a4 | 112 | #define TIMER2_SETPCLK(clk) TIMER_SETPCLK(TIMER2, clk) |
jp | 0:31cd577d85a4 | 113 | #define TIMER3_SETPCLK(clk) TIMER_SETPCLK(TIMER3, clk) |
jp | 0:31cd577d85a4 | 114 | #define TIMER_SETPCLK(timer, clk) TIMER_PCLK_REG(timer) = ((TIMER_PCLK_REG(timer) & (~(3U << TIMER_PCLK_OFFSET(timer)))) | (clk << TIMER_PCLK_OFFSET(timer))) |
jp | 0:31cd577d85a4 | 115 | |
jp | 0:31cd577d85a4 | 116 | // Set Prescale Register |
jp | 0:31cd577d85a4 | 117 | #define TIMER0_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER0, value) |
jp | 0:31cd577d85a4 | 118 | #define TIMER1_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER1, value) |
jp | 0:31cd577d85a4 | 119 | #define TIMER2_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER2, value) |
jp | 0:31cd577d85a4 | 120 | #define TIMER3_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER3, value) |
jp | 0:31cd577d85a4 | 121 | #define TIMER_SETPRESCALE(timer, value) TIMER_BASE(timer)->PR = (value) |
jp | 0:31cd577d85a4 | 122 | |
jp | 0:31cd577d85a4 | 123 | // Set Match Register (MR0-3, 21.6.7 p496) |
jp | 0:31cd577d85a4 | 124 | #define TIMER0_SETMATCH(id, value) TIMER_SETMATCH(TIMER0, id, value) |
jp | 0:31cd577d85a4 | 125 | #define TIMER1_SETMATCH(id, value) TIMER_SETMATCH(TIMER1, id, value) |
jp | 0:31cd577d85a4 | 126 | #define TIMER2_SETMATCH(id, value) TIMER_SETMATCH(TIMER2, id, value) |
jp | 0:31cd577d85a4 | 127 | #define TIMER3_SETMATCH(id, value) TIMER_SETMATCH(TIMER3, id, value) |
jp | 0:31cd577d85a4 | 128 | #define TIMER_SETMATCH(timer, id, value) TIMER_BASE(timer)->TOKENPASTE2(MR,id) = (value) |
jp | 0:31cd577d85a4 | 129 | |
jp | 0:31cd577d85a4 | 130 | // Set Match Control Register (TnMCR, 21.6.8 p496) |
jp | 0:31cd577d85a4 | 131 | #define TIMER0_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER0, id, value) |
jp | 0:31cd577d85a4 | 132 | #define TIMER1_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER1, id, value) |
jp | 0:31cd577d85a4 | 133 | #define TIMER2_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER2, id, value) |
jp | 0:31cd577d85a4 | 134 | #define TIMER3_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER3, id, value) |
jp | 0:31cd577d85a4 | 135 | #define TIMER_SETMATCHCONTROL(timer, id, value) TIMER_BASE(timer)->MCR = (value) << (MR ## id ## _OFFSET) |
jp | 0:31cd577d85a4 | 136 | |
jp | 0:31cd577d85a4 | 137 | // Enable interrupt for TIMERn |
jp | 0:31cd577d85a4 | 138 | #define TIMER0_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER0) |
jp | 0:31cd577d85a4 | 139 | #define TIMER1_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER1) |
jp | 0:31cd577d85a4 | 140 | #define TIMER2_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER2) |
jp | 0:31cd577d85a4 | 141 | #define TIMER3_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER3) |
jp | 0:31cd577d85a4 | 142 | #define TIMER_ENABLE_INTERRUPT(timer) ENABLE_INTERRUPT(TOKENPASTE2(timer,_IRQn)) |
jp | 0:31cd577d85a4 | 143 | |
jp | 0:31cd577d85a4 | 144 | // Interrut Register (TnIR, 21.6.1, p493) |
jp | 0:31cd577d85a4 | 145 | #define TIMER0_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER0, value) |
jp | 0:31cd577d85a4 | 146 | #define TIMER1_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER1, value) |
jp | 0:31cd577d85a4 | 147 | #define TIMER2_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER2, value) |
jp | 0:31cd577d85a4 | 148 | #define TIMER3_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER3, value) |
jp | 0:31cd577d85a4 | 149 | #define TIMER_CLEAR_INTERRUPT(timer, value) TIMER_BASE(timer)->IR = (value) |
jp | 0:31cd577d85a4 | 150 | |
jp | 0:31cd577d85a4 | 151 | // Start Timer |
jp | 0:31cd577d85a4 | 152 | #define TIMER0_START() TIMER_START(TIMER0) |
jp | 0:31cd577d85a4 | 153 | #define TIMER1_START() TIMER_START(TIMER1) |
jp | 0:31cd577d85a4 | 154 | #define TIMER2_START() TIMER_START(TIMER2) |
jp | 0:31cd577d85a4 | 155 | #define TIMER3_START() TIMER_START(TIMER3) |
jp | 0:31cd577d85a4 | 156 | #define TIMER_START(timer) TIMER_BASE(timer)->TCR = 0x1 /* Counter Enable, Table 427 p493*/ |
jp | 0:31cd577d85a4 | 157 | |
jp | 0:31cd577d85a4 | 158 | // Get Timer Value |
jp | 0:31cd577d85a4 | 159 | #define TIMER0_VALUE() TIMER_VALUE(TIMER0) |
jp | 0:31cd577d85a4 | 160 | #define TIMER1_VALUE() TIMER_VALUE(TIMER1) |
jp | 0:31cd577d85a4 | 161 | #define TIMER2_VALUE() TIMER_VALUE(TIMER2) |
jp | 0:31cd577d85a4 | 162 | #define TIMER3_VALUE() TIMER_VALUE(TIMER3) |
jp | 0:31cd577d85a4 | 163 | #define TIMER_VALUE(timer) (TIMER_BASE(timer)->TC) |
jp | 0:31cd577d85a4 | 164 | |
jp | 0:31cd577d85a4 | 165 | #endif |