Zimin Wang
/
DDRO_Farrari
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Fork of
DDRO_Farrari
by 
Liangzhen Lai
Revision 2:bf2ce6c4e789, committed 2014-01-20
- Comitter:
- josewang
- Date:
- Mon Jan 20 00:20:50 2014 +0000
- Parent:
- 1:6a820a0ca03b
- Child:
- 3:f8f27b0de752
- Commit message:
- Added some comments
Changed in this revision
--- a/jtag.cpp Mon Oct 21 22:36:51 2013 +0000
+++ b/jtag.cpp Mon Jan 20 00:20:50 2014 +0000
@@ -223,6 +223,8 @@
}
}
+// JTAG DP / AP Access Registers (DPACC / APACC)
+// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0413c/Babcdjce.html
void JTAG::writeAPACC(unsigned int data, unsigned char addr, bool set_ir)
{
if(set_ir) {
@@ -247,6 +249,8 @@
shiftData(banksel << 4, DP_SELECT, WRITE);
}
+// DAP: Debug Access Port
+// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Babdadfc.html
void JTAG::DAP_enable(void)
{
setState('r');
@@ -303,6 +307,7 @@
// --------------------------------
// State Manipulation
+// IR: instruction register (IR)
void JTAG::setIR(unsigned char A)
{
setState('i');
@@ -484,6 +489,8 @@
clockLow();
}
+// JTAG: TMS (Test Mode Select)
+// http://en.wikipedia.org/wiki/Joint_Test_Action_Group
void JTAG::TMSHigh(void)
{
wait_us(delay);
--- a/jtag.h Mon Oct 21 22:36:51 2013 +0000 +++ b/jtag.h Mon Jan 20 00:20:50 2014 +0000 @@ -4,7 +4,11 @@ */ // Addresses + +// DHCSR: Debug Halting Control and Status Register. +// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/CEGCJAHJ.html #define DHCSR_ADDR 0xE000EDF0 + #define DCRSR_ADDR 0xE000EDF4 #define DCRDR_ADDR 0xE000EDF8 #define DEMCR_ADDR 0xE000EDFC
--- a/main.cpp Mon Oct 21 22:36:51 2013 +0000
+++ b/main.cpp Mon Jan 20 00:20:50 2014 +0000
@@ -30,6 +30,7 @@
CORERESETn = 1;
JTAG jtag;
+ // We check if JTAG works well by checking idcode returned by issuing a test instruction and read result idcode back.
int idcode = jtag.readID();
if(idcode != 0x4ba00477) {
pc.printf("ERROR: IDCode %X\r\n", idcode);