Zimin Wang / Mbed 2 deprecated DDRO_Farrari

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Dependencies:   mbed-rtos mbed

Fork of DDRO_Farrari by Liangzhen Lai

Diff: mmap.h

Revision:
1:6a820a0ca03b
Parent:
0:84a8bcfbdec9
Child:
10:95e9932f7990
--- a/mmap.h	Mon Oct 07 22:58:19 2013 +0000
+++ b/mmap.h	Mon Oct 21 22:36:51 2013 +0000
@@ -40,6 +40,56 @@
 #define ext_div_by 0x44100018///////////////////////////////////////
 #define extclk_source 0x4410001c
 
+/*
+   always @*
+   begin
+      case (intclk_source)
+      2'b00 : HCLK = HCLK_EXT;
+      2'b01 : HCLK = ring_osc_HCLK;
+      2'b10 : HCLK = PLL_PLLOUTA;
+      2'b11 : HCLK = PLL_PLLOUTB;
+      default : HCLK = HCLK_EXT;
+      endcase
+   end
+
+
+
+   always @*
+   begin
+      case (extclk_source)
+      2'b00 : HCLK_div_down = HCLK_EXT;
+      2'b01 : HCLK_div_down = HCLK_divider;
+      2'b10 : HCLK_div_down = PLL_PLLOUTA;
+      2'b11 : HCLK_div_down = PLL_PLLOUTB;
+      default : HCLK_div_down = HCLK_EXT;
+      endcase
+   end
+   
+      always @*
+   begin
+      case (ext_div_by)
+4'd0 : HCLK_divider = HCLK_div_2;
+4'd1 : HCLK_divider = HCLK_div_2;
+4'd2 : HCLK_divider = HCLK_div_4;
+4'd3 : HCLK_divider = HCLK_div_8;
+4'd4 : HCLK_divider = HCLK_div_16;
+4'd5 : HCLK_divider = HCLK_div_32;
+4'd6 : HCLK_divider = HCLK_div_64;
+4'd7 : HCLK_divider = HCLK_div_128;
+4'd8 : HCLK_divider = HCLK_div_256;
+4'd9 : HCLK_divider = HCLK_div_512;
+4'd10 : HCLK_divider = HCLK_div_1024;
+4'd11 : HCLK_divider = HCLK_div_2048;
+4'd12 : HCLK_divider = HCLK_div_4096;
+4'd13 : HCLK_divider = HCLK_div_8192;
+4'd14 : HCLK_divider = HCLK_div_16384;
+4'd15 : HCLK_divider = HCLK_div_32768;
+      default : HCLK_divider = HCLK_div_2;
+      endcase
+   end
+
+*/
+
 // Resets
 #define reset_reg 0x44000004
 #define RESET_scan 0x44100020
@@ -57,6 +107,42 @@
 #define ddro_done 0x44100060
 #define ddro_count 0x44100064
 
+/*
+ reg          ref_clk;
+   always @*
+   begin
+      case(ref_src)
+      5'h0:  ref_clk = HCLK;
+      5'h1:  ref_clk = ring_osc_HCLK;
+      5'h2:  ref_clk = PLL_REFCLK;
+      5'h3:  ref_clk = syn_out[0];
+      5'h4:  ref_clk = syn_out[1];
+      5'h5:  ref_clk = syn_out[2];
+      5'h6:  ref_clk = syn_out[3];
+      5'h7:  ref_clk = syn_out[4];
+      5'h8:  ref_clk = syn_out[5];
+      5'h9:  ref_clk = syn_out[6];
+      5'ha:  ref_clk = syn_out[7];
+      5'hb:  ref_clk = syn_out[8];
+      5'hc:  ref_clk = inv_out[0];
+      5'hd:  ref_clk = inv_out[1];
+      5'he:  ref_clk = inv_out[2];
+      5'hf:  ref_clk = inv_out[3];
+      5'h10: ref_clk = inv_out[4];
+      5'h11: ref_clk = inv_out[5];
+      5'h12: ref_clk = inv_out[6];
+      5'h13: ref_clk = inv_out[7];
+      5'h14: ref_clk = inv_out[8];
+      5'h15: ref_clk = inv_out[9];
+      5'h16: ref_clk = OXIDE_CLK;
+      5'h17: ref_clk = PMOS_CLK;
+      5'h18: ref_clk = NMOS_CLK;
+      5'h19: ref_clk = TEMP_CLK;
+      default: ref_clk = HCLK;
+      endcase
+   end
+*/
+
 // Sensors
 #define sensor_disable 0x44100048
 #define sensor_oxide_stress 0x4410004c