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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_lptim.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_ll_lptim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of LPTIM LL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_LL_LPTIM_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_LL_LPTIM_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_LL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52	#if defined (LPTIM1) \|\| defined (LPTIM2)
<>	144:ef7eb2e8f9f7	53
<>	144:ef7eb2e8f9f7	54	/** @defgroup LPTIM_LL LPTIM
<>	144:ef7eb2e8f9f7	55	* @{
<>	144:ef7eb2e8f9f7	56	*/
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	59	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	64	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	65	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	66	/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
<>	144:ef7eb2e8f9f7	67	* @{
<>	144:ef7eb2e8f9f7	68	*/
<>	144:ef7eb2e8f9f7	69	/**
<>	144:ef7eb2e8f9f7	70	* @}
<>	144:ef7eb2e8f9f7	71	*/
<>	144:ef7eb2e8f9f7	72	#endif /USE_FULL_LL_DRIVER/
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	75	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	76	/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
<>	144:ef7eb2e8f9f7	77	* @{
<>	144:ef7eb2e8f9f7	78	*/
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	/**
<>	144:ef7eb2e8f9f7	81	* @brief LPTIM Init structure definition
<>	144:ef7eb2e8f9f7	82	*/
<>	144:ef7eb2e8f9f7	83	typedef struct
<>	144:ef7eb2e8f9f7	84	{
<>	144:ef7eb2e8f9f7	85	uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
<>	144:ef7eb2e8f9f7	86	This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
<>	144:ef7eb2e8f9f7	91	This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	uint32_t Waveform; /*!< Specifies the waveform shape.
<>	144:ef7eb2e8f9f7	96	This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	uint32_t Polarity; /*!< Specifies waveform polarity.
<>	144:ef7eb2e8f9f7	101	This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
<>	144:ef7eb2e8f9f7	104	} LL_LPTIM_InitTypeDef;
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	/**
<>	144:ef7eb2e8f9f7	107	* @}
<>	144:ef7eb2e8f9f7	108	*/
<>	144:ef7eb2e8f9f7	109	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	112	/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
<>	144:ef7eb2e8f9f7	113	* @{
<>	144:ef7eb2e8f9f7	114	*/
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
<>	144:ef7eb2e8f9f7	117	* @brief Flags defines which can be used with LL_LPTIM_ReadReg function
<>	144:ef7eb2e8f9f7	118	* @{
<>	144:ef7eb2e8f9f7	119	*/
<>	144:ef7eb2e8f9f7	120	#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /!< Compare match /
<>	144:ef7eb2e8f9f7	121	#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /!< Autoreload match /
<>	144:ef7eb2e8f9f7	122	#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /!< External trigger edge event /
<>	144:ef7eb2e8f9f7	123	#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /!< Compare register update OK /
<>	144:ef7eb2e8f9f7	124	#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /!< Autoreload register update OK /
<>	144:ef7eb2e8f9f7	125	#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /!< Counter direction change down to up /
<>	144:ef7eb2e8f9f7	126	#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /!< Counter direction change up to down /
<>	144:ef7eb2e8f9f7	127	/**
<>	144:ef7eb2e8f9f7	128	* @}
<>	144:ef7eb2e8f9f7	129	*/
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/** @defgroup LPTIM_LL_EC_IT IT Defines
<>	144:ef7eb2e8f9f7	132	* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
<>	144:ef7eb2e8f9f7	133	* @{
<>	144:ef7eb2e8f9f7	134	*/
<>	144:ef7eb2e8f9f7	135	#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /!< Compare match Interrupt Enable /
<>	144:ef7eb2e8f9f7	136	#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /!< Autoreload match Interrupt Enable /
<>	144:ef7eb2e8f9f7	137	#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /!< External trigger valid edge Interrupt Enable /
<>	144:ef7eb2e8f9f7	138	#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /!< Compare register update OK Interrupt Enable /
<>	144:ef7eb2e8f9f7	139	#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /!< Autoreload register update OK Interrupt Enable /
<>	144:ef7eb2e8f9f7	140	#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /!< Direction change to UP Interrupt Enable /
<>	144:ef7eb2e8f9f7	141	#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /!< Direction change to down Interrupt Enable /
<>	144:ef7eb2e8f9f7	142	/**
<>	144:ef7eb2e8f9f7	143	* @}
<>	144:ef7eb2e8f9f7	144	*/
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
<>	144:ef7eb2e8f9f7	147	* @{
<>	144:ef7eb2e8f9f7	148	*/
<>	144:ef7eb2e8f9f7	149	#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /!<LP Timer starts in continuous mode/
<>	144:ef7eb2e8f9f7	150	#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /!<LP Tilmer starts in single mode/
<>	144:ef7eb2e8f9f7	151	/**
<>	144:ef7eb2e8f9f7	152	* @}
<>	144:ef7eb2e8f9f7	153	*/
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
<>	144:ef7eb2e8f9f7	156	* @{
<>	144:ef7eb2e8f9f7	157	*/
<>	144:ef7eb2e8f9f7	158	#define LL_LPTIM_UPDATE_MODE_IMMEDIATE ((uint32_t)0x00000000U) /!<Preload is disabled: registers are updated after each APB bus write access/
<>	144:ef7eb2e8f9f7	159	#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /!<preload is enabled: registers are updated at the end of the current LPTIM period/
<>	144:ef7eb2e8f9f7	160	/**
<>	144:ef7eb2e8f9f7	161	* @}
<>	144:ef7eb2e8f9f7	162	*/
<>	144:ef7eb2e8f9f7	163
<>	144:ef7eb2e8f9f7	164	/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
<>	144:ef7eb2e8f9f7	165	* @{
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167	#define LL_LPTIM_COUNTER_MODE_INTERNAL ((uint32_t)0x00000000U) /!<The counter is incremented following each internal clock pulse/
<>	144:ef7eb2e8f9f7	168	#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /!<The counter is incremented following each valid clock pulse on the LPTIM external Input1/
<>	144:ef7eb2e8f9f7	169	/**
<>	144:ef7eb2e8f9f7	170	* @}
<>	144:ef7eb2e8f9f7	171	*/
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173	/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
<>	144:ef7eb2e8f9f7	174	* @{
<>	144:ef7eb2e8f9f7	175	*/
<>	144:ef7eb2e8f9f7	176	#define LL_LPTIM_OUTPUT_WAVEFORM_PWM ((uint32_t)0x00000000U) /!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE/
<>	144:ef7eb2e8f9f7	177	#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /!<LPTIM generates a Set Once waveform/
<>	144:ef7eb2e8f9f7	178	/**
<>	144:ef7eb2e8f9f7	179	* @}
<>	144:ef7eb2e8f9f7	180	*/
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
<>	144:ef7eb2e8f9f7	183	* @{
<>	144:ef7eb2e8f9f7	184	*/
<>	144:ef7eb2e8f9f7	185	#define LL_LPTIM_OUTPUT_POLARITY_REGULAR ((uint32_t) 0x00000000U) /!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers/
<>	144:ef7eb2e8f9f7	186	#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers/
<>	144:ef7eb2e8f9f7	187	/**
<>	144:ef7eb2e8f9f7	188	* @}
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
<>	144:ef7eb2e8f9f7	192	* @{
<>	144:ef7eb2e8f9f7	193	*/
<>	144:ef7eb2e8f9f7	194	#define LL_LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U) /!<Prescaler division factor is set to 1/
<>	144:ef7eb2e8f9f7	195	#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /!<Prescaler division factor is set to 2/
<>	144:ef7eb2e8f9f7	196	#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /!<Prescaler division factor is set to 4/
<>	144:ef7eb2e8f9f7	197	#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 \| LPTIM_CFGR_PRESC_0) /!<Prescaler division factor is set to 8/
<>	144:ef7eb2e8f9f7	198	#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /!<Prescaler division factor is set to 16/
<>	144:ef7eb2e8f9f7	199	#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 \| LPTIM_CFGR_PRESC_0) /!<Prescaler division factor is set to 32/
<>	144:ef7eb2e8f9f7	200	#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 \| LPTIM_CFGR_PRESC_1) /!<Prescaler division factor is set to 64/
<>	144:ef7eb2e8f9f7	201	#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /!<Prescaler division factor is set to 128/
<>	144:ef7eb2e8f9f7	202	/**
<>	144:ef7eb2e8f9f7	203	* @}
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
<>	144:ef7eb2e8f9f7	207	* @{
<>	144:ef7eb2e8f9f7	208	*/
<>	144:ef7eb2e8f9f7	209	#define LL_LPTIM_TRIG_SOURCE_GPIO ((uint32_t)0x00000000U) /!<External input trigger is connected to TIMx_ETR input/
<>	144:ef7eb2e8f9f7	210	#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /!<External input trigger is connected to RTC Alarm A/
<>	144:ef7eb2e8f9f7	211	#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /!<External input trigger is connected to RTC Alarm B/
<>	144:ef7eb2e8f9f7	212	#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 \| LPTIM_CFGR_TRIGSEL_0) /!<External input trigger is connected to RTC Tamper 1/
<>	144:ef7eb2e8f9f7	213	#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /!<External input trigger is connected to RTC Tamper 2/
<>	144:ef7eb2e8f9f7	214	#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 \| LPTIM_CFGR_TRIGSEL_0) /!<External input trigger is connected to RTC Tamper 3/
<>	144:ef7eb2e8f9f7	215	#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 \| LPTIM_CFGR_TRIGSEL_1) /!<External input trigger is connected to COMP1 output/
<>	144:ef7eb2e8f9f7	216	#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /!<External input trigger is connected to COMP2 output/
<>	144:ef7eb2e8f9f7	217	/**
<>	144:ef7eb2e8f9f7	218	* @}
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
<>	144:ef7eb2e8f9f7	222	* @{
<>	144:ef7eb2e8f9f7	223	*/
<>	144:ef7eb2e8f9f7	224	#define LL_LPTIM_TRIG_FILTER_NONE ((uint32_t)0x00000000U) /!<Any trigger active level change is considered as a valid trigger/
<>	144:ef7eb2e8f9f7	225	#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger/
<>	144:ef7eb2e8f9f7	226	#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger/
<>	144:ef7eb2e8f9f7	227	#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger/
<>	144:ef7eb2e8f9f7	228	/**
<>	144:ef7eb2e8f9f7	229	* @}
<>	144:ef7eb2e8f9f7	230	*/
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
<>	144:ef7eb2e8f9f7	233	* @{
<>	144:ef7eb2e8f9f7	234	*/
<>	144:ef7eb2e8f9f7	235	#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /!<LPTIM counter starts when a rising edge is detected/
<>	144:ef7eb2e8f9f7	236	#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /!<LPTIM counter starts when a falling edge is detected/
<>	144:ef7eb2e8f9f7	237	#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /!<LPTIM counter starts when a rising or a falling edge is detected/
<>	144:ef7eb2e8f9f7	238	/**
<>	144:ef7eb2e8f9f7	239	* @}
<>	144:ef7eb2e8f9f7	240	*/
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
<>	144:ef7eb2e8f9f7	243	* @{
<>	144:ef7eb2e8f9f7	244	*/
<>	144:ef7eb2e8f9f7	245	#define LL_LPTIM_CLK_SOURCE_INTERNAL ((uint32_t)0x00000000U) /!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)/
<>	144:ef7eb2e8f9f7	246	#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /!<LPTIM is clocked by an external clock source through the LPTIM external Input1/
<>	144:ef7eb2e8f9f7	247	/**
<>	144:ef7eb2e8f9f7	248	* @}
<>	144:ef7eb2e8f9f7	249	*/
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
<>	144:ef7eb2e8f9f7	252	* @{
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254	#define LL_LPTIM_CLK_FILTER_NONE ((uint32_t)0x00000000U) /!<Any external clock signal level change is considered as a valid transition/
<>	144:ef7eb2e8f9f7	255	#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition/
<>	144:ef7eb2e8f9f7	256	#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition/
<>	144:ef7eb2e8f9f7	257	#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition/
<>	144:ef7eb2e8f9f7	258	/**
<>	144:ef7eb2e8f9f7	259	* @}
<>	144:ef7eb2e8f9f7	260	*/
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
<>	144:ef7eb2e8f9f7	263	* @{
<>	144:ef7eb2e8f9f7	264	*/
<>	144:ef7eb2e8f9f7	265	#define LL_LPTIM_CLK_POLARITY_RISING ((uint32_t)0x00000000U) /!< The rising edge is the active edge used for counting/
<>	144:ef7eb2e8f9f7	266	#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /!< The falling edge is the active edge used for counting/
<>	144:ef7eb2e8f9f7	267	#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /!< Both edges are active edges/
<>	144:ef7eb2e8f9f7	268	/**
<>	144:ef7eb2e8f9f7	269	* @}
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
<>	144:ef7eb2e8f9f7	273	* @{
<>	144:ef7eb2e8f9f7	274	*/
<>	144:ef7eb2e8f9f7	275	#define LL_LPTIM_ENCODER_MODE_RISING ((uint32_t)0x00000000U) /!< The rising edge is the active edge used for counting/
<>	144:ef7eb2e8f9f7	276	#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /!< The falling edge is the active edge used for counting/
<>	144:ef7eb2e8f9f7	277	#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /!< Both edges are active edges/
<>	144:ef7eb2e8f9f7	278	/**
<>	144:ef7eb2e8f9f7	279	* @}
<>	144:ef7eb2e8f9f7	280	*/
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
<>	144:ef7eb2e8f9f7	283	* @{
<>	144:ef7eb2e8f9f7	284	*/
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	#define LL_LPTIM_INPUT1_SRC_GPIO ((uint32_t)0x00000000U) /!< For LPTIM1 and LPTIM2 /
<>	144:ef7eb2e8f9f7	287	#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0 /!< For LPTIM1 and LPTIM2 /
<>	144:ef7eb2e8f9f7	288	#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1 /!< For LPTIM2 /
<>	144:ef7eb2e8f9f7	289	#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR /!< For LPTIM2 /
<>	144:ef7eb2e8f9f7	290	/**
<>	144:ef7eb2e8f9f7	291	* @}
<>	144:ef7eb2e8f9f7	292	*/
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
<>	144:ef7eb2e8f9f7	295	* @{
<>	144:ef7eb2e8f9f7	296	*/
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	#define LL_LPTIM_INPUT2_SRC_GPIO ((uint32_t)0x00000000U) /!< For LPTIM1 /
<>	144:ef7eb2e8f9f7	299	#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1 /!< For LPTIM1 /
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @}
<>	144:ef7eb2e8f9f7	302	*/
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/**
<>	144:ef7eb2e8f9f7	305	* @}
<>	144:ef7eb2e8f9f7	306	*/
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	309	/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
<>	144:ef7eb2e8f9f7	310	* @{
<>	144:ef7eb2e8f9f7	311	*/
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	144:ef7eb2e8f9f7	314	* @{
<>	144:ef7eb2e8f9f7	315	*/
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/**
<>	144:ef7eb2e8f9f7	318	* @brief Write a value in LPTIM register
<>	144:ef7eb2e8f9f7	319	* @param __INSTANCE__ LPTIM Instance
<>	144:ef7eb2e8f9f7	320	* @param __REG__ Register to be written
<>	144:ef7eb2e8f9f7	321	* @param __VALUE__ Value to be written in the register
<>	144:ef7eb2e8f9f7	322	* @retval None
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324	#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	144:ef7eb2e8f9f7	325
<>	144:ef7eb2e8f9f7	326	/**
<>	144:ef7eb2e8f9f7	327	* @brief Read a value in LPTIM register
<>	144:ef7eb2e8f9f7	328	* @param __INSTANCE__ LPTIM Instance
<>	144:ef7eb2e8f9f7	329	* @param __REG__ Register to be read
<>	144:ef7eb2e8f9f7	330	* @retval Register value
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332	#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	144:ef7eb2e8f9f7	333	/**
<>	144:ef7eb2e8f9f7	334	* @}
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/**
<>	144:ef7eb2e8f9f7	338	* @}
<>	144:ef7eb2e8f9f7	339	*/
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	343	/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
<>	144:ef7eb2e8f9f7	344	* @{
<>	144:ef7eb2e8f9f7	345	*/
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
<>	144:ef7eb2e8f9f7	348	* @{
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/**
<>	144:ef7eb2e8f9f7	352	* @brief Enable the LPTIM instance
<>	144:ef7eb2e8f9f7	353	* @note After setting the ENABLE bit, a delay of two counter clock is needed
<>	144:ef7eb2e8f9f7	354	* before the LPTIM instance is actually enabled.
<>	144:ef7eb2e8f9f7	355	* @rmtoll CR ENABLE LL_LPTIM_Enable
<>	144:ef7eb2e8f9f7	356	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	357	* @retval None
<>	144:ef7eb2e8f9f7	358	*/
<>	144:ef7eb2e8f9f7	359	__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	360	{
<>	144:ef7eb2e8f9f7	361	SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
<>	144:ef7eb2e8f9f7	362	}
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364	/**
<>	144:ef7eb2e8f9f7	365	* @brief Disable the LPTIM instance
<>	144:ef7eb2e8f9f7	366	* @rmtoll CR ENABLE LL_LPTIM_Disable
<>	144:ef7eb2e8f9f7	367	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	368	* @retval None
<>	144:ef7eb2e8f9f7	369	*/
<>	144:ef7eb2e8f9f7	370	__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	371	{
<>	144:ef7eb2e8f9f7	372	CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
<>	144:ef7eb2e8f9f7	373	}
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	/**
<>	144:ef7eb2e8f9f7	376	* @brief Indicates whether the LPTIM instance is enabled.
<>	144:ef7eb2e8f9f7	377	* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
<>	144:ef7eb2e8f9f7	378	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	379	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	380	*/
<>	144:ef7eb2e8f9f7	381	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	382	{
<>	144:ef7eb2e8f9f7	383	return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
<>	144:ef7eb2e8f9f7	384	}
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/**
<>	144:ef7eb2e8f9f7	387	* @brief Starts the LPTIM counter in the desired mode.
<>	144:ef7eb2e8f9f7	388	* @note LPTIM instance must be enabled before starting the counter.
<>	144:ef7eb2e8f9f7	389	* @note It is possible to change on the fly from One Shot mode to
<>	144:ef7eb2e8f9f7	390	* Continuous mode.
<>	144:ef7eb2e8f9f7	391	* @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
<>	144:ef7eb2e8f9f7	392	* CR SNGSTRT LL_LPTIM_StartCounter
<>	144:ef7eb2e8f9f7	393	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	394	* @param OperatingMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	395	* @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
<>	144:ef7eb2e8f9f7	396	* @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
<>	144:ef7eb2e8f9f7	397	* @retval None
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399	__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
<>	144:ef7eb2e8f9f7	400	{
<>	144:ef7eb2e8f9f7	401	MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT \| LPTIM_CR_SNGSTRT, OperatingMode);
<>	144:ef7eb2e8f9f7	402	}
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/**
<>	144:ef7eb2e8f9f7	405	* @brief Set the LPTIM registers update mode (enable/disable register preload)
<>	144:ef7eb2e8f9f7	406	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	407	* @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
<>	144:ef7eb2e8f9f7	408	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	409	* @param UpdateMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	410	* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
<>	144:ef7eb2e8f9f7	411	* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
<>	144:ef7eb2e8f9f7	412	* @retval None
<>	144:ef7eb2e8f9f7	413	*/
<>	144:ef7eb2e8f9f7	414	__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
<>	144:ef7eb2e8f9f7	415	{
<>	144:ef7eb2e8f9f7	416	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
<>	144:ef7eb2e8f9f7	417	}
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	/**
<>	144:ef7eb2e8f9f7	420	* @brief Get the LPTIM registers update mode
<>	144:ef7eb2e8f9f7	421	* @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
<>	144:ef7eb2e8f9f7	422	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	423	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	424	* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
<>	144:ef7eb2e8f9f7	425	* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
<>	144:ef7eb2e8f9f7	426	*/
<>	144:ef7eb2e8f9f7	427	__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	428	{
<>	144:ef7eb2e8f9f7	429	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
<>	144:ef7eb2e8f9f7	430	}
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/**
<>	144:ef7eb2e8f9f7	433	* @brief Set the auto reload value
<>	144:ef7eb2e8f9f7	434	* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
<>	144:ef7eb2e8f9f7	435	* @note After a write to the LPTIMx_ARR register a new write operation to the
<>	144:ef7eb2e8f9f7	436	* same register can only be performed when the previous write operation
<>	144:ef7eb2e8f9f7	437	* is completed. Any successive write before the ARROK flag be set, will
<>	144:ef7eb2e8f9f7	438	* lead to unpredictable results.
<>	144:ef7eb2e8f9f7	439	* @note autoreload value be strictly greater than the compare value.
<>	144:ef7eb2e8f9f7	440	* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
<>	144:ef7eb2e8f9f7	441	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	442	* @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	144:ef7eb2e8f9f7	443	* @retval None
<>	144:ef7eb2e8f9f7	444	*/
<>	144:ef7eb2e8f9f7	445	__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
<>	144:ef7eb2e8f9f7	446	{
<>	144:ef7eb2e8f9f7	447	MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
<>	144:ef7eb2e8f9f7	448	}
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/**
<>	144:ef7eb2e8f9f7	451	* @brief Get actual auto reload value
<>	144:ef7eb2e8f9f7	452	* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
<>	144:ef7eb2e8f9f7	453	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	454	* @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	144:ef7eb2e8f9f7	455	*/
<>	144:ef7eb2e8f9f7	456	__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	457	{
<>	144:ef7eb2e8f9f7	458	return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
<>	144:ef7eb2e8f9f7	459	}
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/**
<>	144:ef7eb2e8f9f7	462	* @brief Set the compare value
<>	144:ef7eb2e8f9f7	463	* @note After a write to the LPTIMx_CMP register a new write operation to the
<>	144:ef7eb2e8f9f7	464	* same register can only be performed when the previous write operation
<>	144:ef7eb2e8f9f7	465	* is completed. Any successive write before the CMPOK flag be set, will
<>	144:ef7eb2e8f9f7	466	* lead to unpredictable results.
<>	144:ef7eb2e8f9f7	467	* @rmtoll CMP CMP LL_LPTIM_SetCompare
<>	144:ef7eb2e8f9f7	468	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	469	* @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	144:ef7eb2e8f9f7	470	* @retval None
<>	144:ef7eb2e8f9f7	471	*/
<>	144:ef7eb2e8f9f7	472	__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	473	{
<>	144:ef7eb2e8f9f7	474	MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
<>	144:ef7eb2e8f9f7	475	}
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/**
<>	144:ef7eb2e8f9f7	478	* @brief Get actual compare value
<>	144:ef7eb2e8f9f7	479	* @rmtoll CMP CMP LL_LPTIM_GetCompare
<>	144:ef7eb2e8f9f7	480	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	481	* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	144:ef7eb2e8f9f7	482	*/
<>	144:ef7eb2e8f9f7	483	__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	484	{
<>	144:ef7eb2e8f9f7	485	return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
<>	144:ef7eb2e8f9f7	486	}
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	/**
<>	144:ef7eb2e8f9f7	489	* @brief Get actual counter value
<>	144:ef7eb2e8f9f7	490	* @note When the LPTIM instance is running with an asynchronous clock, reading
<>	144:ef7eb2e8f9f7	491	* the LPTIMx_CNT register may return unreliable values. So in this case
<>	144:ef7eb2e8f9f7	492	* it is necessary to perform two consecutive read accesses and verify
<>	144:ef7eb2e8f9f7	493	* that the two returned values are identical.
<>	144:ef7eb2e8f9f7	494	* @rmtoll CNT CNT LL_LPTIM_GetCounter
<>	144:ef7eb2e8f9f7	495	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	496	* @retval Counter value
<>	144:ef7eb2e8f9f7	497	*/
<>	144:ef7eb2e8f9f7	498	__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	499	{
<>	144:ef7eb2e8f9f7	500	return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
<>	144:ef7eb2e8f9f7	501	}
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/**
<>	144:ef7eb2e8f9f7	504	* @brief Set the counter mode (selection of the LPTIM counter clock source).
<>	144:ef7eb2e8f9f7	505	* @note The counter mode can be set only when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	506	* @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
<>	144:ef7eb2e8f9f7	507	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	508	* @param CounterMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	509	* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
<>	144:ef7eb2e8f9f7	510	* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
<>	144:ef7eb2e8f9f7	511	* @retval None
<>	144:ef7eb2e8f9f7	512	*/
<>	144:ef7eb2e8f9f7	513	__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
<>	144:ef7eb2e8f9f7	514	{
<>	144:ef7eb2e8f9f7	515	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
<>	144:ef7eb2e8f9f7	516	}
<>	144:ef7eb2e8f9f7	517
<>	144:ef7eb2e8f9f7	518	/**
<>	144:ef7eb2e8f9f7	519	* @brief Get the counter mode
<>	144:ef7eb2e8f9f7	520	* @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
<>	144:ef7eb2e8f9f7	521	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	522	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	523	* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
<>	144:ef7eb2e8f9f7	524	* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
<>	144:ef7eb2e8f9f7	525	*/
<>	144:ef7eb2e8f9f7	526	__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	527	{
<>	144:ef7eb2e8f9f7	528	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
<>	144:ef7eb2e8f9f7	529	}
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/**
<>	144:ef7eb2e8f9f7	532	* @brief Configure the LPTIM instance output (LPTIMx_OUT)
<>	144:ef7eb2e8f9f7	533	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	534	* @note Regarding the LPTIM output polarity the change takes effect
<>	144:ef7eb2e8f9f7	535	* immediately, so the output default value will change immediately after
<>	144:ef7eb2e8f9f7	536	* the polarity is re-configured, even before the timer is enabled.
<>	144:ef7eb2e8f9f7	537	* @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
<>	144:ef7eb2e8f9f7	538	* CFGR WAVPOL LL_LPTIM_ConfigOutput
<>	144:ef7eb2e8f9f7	539	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	540	* @param Waveform This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	541	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
<>	144:ef7eb2e8f9f7	542	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
<>	144:ef7eb2e8f9f7	543	* @param Polarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	544	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
<>	144:ef7eb2e8f9f7	545	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
<>	144:ef7eb2e8f9f7	546	* @retval None
<>	144:ef7eb2e8f9f7	547	*/
<>	144:ef7eb2e8f9f7	548	__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
<>	144:ef7eb2e8f9f7	549	{
<>	144:ef7eb2e8f9f7	550	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE \| LPTIM_CFGR_WAVPOL, Waveform \| Polarity);
<>	144:ef7eb2e8f9f7	551	}
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/**
<>	144:ef7eb2e8f9f7	554	* @brief Set waveform shape
<>	144:ef7eb2e8f9f7	555	* @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
<>	144:ef7eb2e8f9f7	556	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	557	* @param Waveform This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	558	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
<>	144:ef7eb2e8f9f7	559	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
<>	144:ef7eb2e8f9f7	560	* @retval None
<>	144:ef7eb2e8f9f7	561	*/
<>	144:ef7eb2e8f9f7	562	__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
<>	144:ef7eb2e8f9f7	563	{
<>	144:ef7eb2e8f9f7	564	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
<>	144:ef7eb2e8f9f7	565	}
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/**
<>	144:ef7eb2e8f9f7	568	* @brief Get actual waveform shape
<>	144:ef7eb2e8f9f7	569	* @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
<>	144:ef7eb2e8f9f7	570	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	571	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	572	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
<>	144:ef7eb2e8f9f7	573	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
<>	144:ef7eb2e8f9f7	574	*/
<>	144:ef7eb2e8f9f7	575	__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	576	{
<>	144:ef7eb2e8f9f7	577	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
<>	144:ef7eb2e8f9f7	578	}
<>	144:ef7eb2e8f9f7	579
<>	144:ef7eb2e8f9f7	580	/**
<>	144:ef7eb2e8f9f7	581	* @brief Set output polarity
<>	144:ef7eb2e8f9f7	582	* @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
<>	144:ef7eb2e8f9f7	583	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	584	* @param Polarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	585	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
<>	144:ef7eb2e8f9f7	586	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
<>	144:ef7eb2e8f9f7	587	* @retval None
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589	__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
<>	144:ef7eb2e8f9f7	592	}
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	/**
<>	144:ef7eb2e8f9f7	595	* @brief Get actual output polarity
<>	144:ef7eb2e8f9f7	596	* @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
<>	144:ef7eb2e8f9f7	597	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	598	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	599	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
<>	144:ef7eb2e8f9f7	600	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
<>	144:ef7eb2e8f9f7	601	*/
<>	144:ef7eb2e8f9f7	602	__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	603	{
<>	144:ef7eb2e8f9f7	604	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
<>	144:ef7eb2e8f9f7	605	}
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	/**
<>	144:ef7eb2e8f9f7	608	* @brief Set actual prescaler division ratio.
<>	144:ef7eb2e8f9f7	609	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	610	* @note When the LPTIM is configured to be clocked by an internal clock source
<>	144:ef7eb2e8f9f7	611	* and the LPTIM counter is configured to be updated by active edges
<>	144:ef7eb2e8f9f7	612	* detected on the LPTIM external Input1, the internal clock provided to
<>	144:ef7eb2e8f9f7	613	* the LPTIM must be not be prescaled.
<>	144:ef7eb2e8f9f7	614	* @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
<>	144:ef7eb2e8f9f7	615	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	616	* @param Prescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	617	* @arg @ref LL_LPTIM_PRESCALER_DIV1
<>	144:ef7eb2e8f9f7	618	* @arg @ref LL_LPTIM_PRESCALER_DIV2
<>	144:ef7eb2e8f9f7	619	* @arg @ref LL_LPTIM_PRESCALER_DIV4
<>	144:ef7eb2e8f9f7	620	* @arg @ref LL_LPTIM_PRESCALER_DIV8
<>	144:ef7eb2e8f9f7	621	* @arg @ref LL_LPTIM_PRESCALER_DIV16
<>	144:ef7eb2e8f9f7	622	* @arg @ref LL_LPTIM_PRESCALER_DIV32
<>	144:ef7eb2e8f9f7	623	* @arg @ref LL_LPTIM_PRESCALER_DIV64
<>	144:ef7eb2e8f9f7	624	* @arg @ref LL_LPTIM_PRESCALER_DIV128
<>	144:ef7eb2e8f9f7	625	* @retval None
<>	144:ef7eb2e8f9f7	626	*/
<>	144:ef7eb2e8f9f7	627	__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
<>	144:ef7eb2e8f9f7	628	{
<>	144:ef7eb2e8f9f7	629	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
<>	144:ef7eb2e8f9f7	630	}
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/**
<>	144:ef7eb2e8f9f7	633	* @brief Get actual prescaler division ratio.
<>	144:ef7eb2e8f9f7	634	* @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
<>	144:ef7eb2e8f9f7	635	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	636	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	637	* @arg @ref LL_LPTIM_PRESCALER_DIV1
<>	144:ef7eb2e8f9f7	638	* @arg @ref LL_LPTIM_PRESCALER_DIV2
<>	144:ef7eb2e8f9f7	639	* @arg @ref LL_LPTIM_PRESCALER_DIV4
<>	144:ef7eb2e8f9f7	640	* @arg @ref LL_LPTIM_PRESCALER_DIV8
<>	144:ef7eb2e8f9f7	641	* @arg @ref LL_LPTIM_PRESCALER_DIV16
<>	144:ef7eb2e8f9f7	642	* @arg @ref LL_LPTIM_PRESCALER_DIV32
<>	144:ef7eb2e8f9f7	643	* @arg @ref LL_LPTIM_PRESCALER_DIV64
<>	144:ef7eb2e8f9f7	644	* @arg @ref LL_LPTIM_PRESCALER_DIV128
<>	144:ef7eb2e8f9f7	645	*/
<>	144:ef7eb2e8f9f7	646	__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	647	{
<>	144:ef7eb2e8f9f7	648	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
<>	144:ef7eb2e8f9f7	649	}
<>	144:ef7eb2e8f9f7	650
<>	144:ef7eb2e8f9f7	651	/**
<>	144:ef7eb2e8f9f7	652	* @brief Set LPTIM input 1 source (default GPIO).
<>	144:ef7eb2e8f9f7	653	* @rmtoll OR OR_0 LL_LPTIM_SetInput1Src
<>	144:ef7eb2e8f9f7	654	* @rmtoll OR OR_1 LL_LPTIM_SetInput1Src
<>	144:ef7eb2e8f9f7	655	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	656	* @param Src This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	657	* @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
<>	144:ef7eb2e8f9f7	658	* @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
<>	144:ef7eb2e8f9f7	659	* @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
<>	144:ef7eb2e8f9f7	660	* @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
<>	144:ef7eb2e8f9f7	661	* @retval None
<>	144:ef7eb2e8f9f7	662	*/
<>	144:ef7eb2e8f9f7	663	__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
<>	144:ef7eb2e8f9f7	664	{
<>	144:ef7eb2e8f9f7	665	WRITE_REG(LPTIMx->OR, Src);
<>	144:ef7eb2e8f9f7	666	}
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	/**
<>	144:ef7eb2e8f9f7	669	* @brief Set LPTIM input 2 source (default GPIO).
<>	144:ef7eb2e8f9f7	670	* @rmtoll OR OR_0 LL_LPTIM_SetInput2Src
<>	144:ef7eb2e8f9f7	671	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	672	* @param Src This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	673	* @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
<>	144:ef7eb2e8f9f7	674	* @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
<>	144:ef7eb2e8f9f7	675	* @retval None
<>	144:ef7eb2e8f9f7	676	*/
<>	144:ef7eb2e8f9f7	677	__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
<>	144:ef7eb2e8f9f7	678	{
<>	144:ef7eb2e8f9f7	679	WRITE_REG(LPTIMx->OR, Src);
<>	144:ef7eb2e8f9f7	680	}
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/**
<>	144:ef7eb2e8f9f7	683	* @}
<>	144:ef7eb2e8f9f7	684	*/
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
<>	144:ef7eb2e8f9f7	687	* @{
<>	144:ef7eb2e8f9f7	688	*/
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/**
<>	144:ef7eb2e8f9f7	691	* @brief Enable the timeout function
<>	144:ef7eb2e8f9f7	692	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	693	* @note The first trigger event will start the timer, any successive trigger
<>	144:ef7eb2e8f9f7	694	* event will reset the counter and the timer will restart.
<>	144:ef7eb2e8f9f7	695	* @note The timeout value corresponds to the compare value; if no trigger
<>	144:ef7eb2e8f9f7	696	* occurs within the expected time frame, the MCU is waked-up by the
<>	144:ef7eb2e8f9f7	697	* compare match event.
<>	144:ef7eb2e8f9f7	698	* @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
<>	144:ef7eb2e8f9f7	699	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	700	* @retval None
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702	__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	703	{
<>	144:ef7eb2e8f9f7	704	SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
<>	144:ef7eb2e8f9f7	705	}
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/**
<>	144:ef7eb2e8f9f7	708	* @brief Disable the timeout function
<>	144:ef7eb2e8f9f7	709	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	710	* @note A trigger event arriving when the timer is already started will be
<>	144:ef7eb2e8f9f7	711	* ignored.
<>	144:ef7eb2e8f9f7	712	* @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
<>	144:ef7eb2e8f9f7	713	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	714	* @retval None
<>	144:ef7eb2e8f9f7	715	*/
<>	144:ef7eb2e8f9f7	716	__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
<>	144:ef7eb2e8f9f7	719	}
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	/**
<>	144:ef7eb2e8f9f7	722	* @brief Indicate whether the timeout function is enabled.
<>	144:ef7eb2e8f9f7	723	* @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
<>	144:ef7eb2e8f9f7	724	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	725	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	726	*/
<>	144:ef7eb2e8f9f7	727	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	728	{
<>	144:ef7eb2e8f9f7	729	return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
<>	144:ef7eb2e8f9f7	730	}
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/**
<>	144:ef7eb2e8f9f7	733	* @brief Start the LPTIM counter
<>	144:ef7eb2e8f9f7	734	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	735	* @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
<>	144:ef7eb2e8f9f7	736	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	737	* @retval None
<>	144:ef7eb2e8f9f7	738	*/
<>	144:ef7eb2e8f9f7	739	__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	740	{
<>	144:ef7eb2e8f9f7	741	CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
<>	144:ef7eb2e8f9f7	742	}
<>	144:ef7eb2e8f9f7	743
<>	144:ef7eb2e8f9f7	744	/**
<>	144:ef7eb2e8f9f7	745	* @brief Configure the external trigger used as a trigger event for the LPTIM.
<>	144:ef7eb2e8f9f7	746	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	747	* @note An internal clock source must be present when a digital filter is
<>	144:ef7eb2e8f9f7	748	* required for the trigger.
<>	144:ef7eb2e8f9f7	749	* @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
<>	144:ef7eb2e8f9f7	750	* CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
<>	144:ef7eb2e8f9f7	751	* CFGR TRIGEN LL_LPTIM_ConfigTrigger
<>	144:ef7eb2e8f9f7	752	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	753	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	754	* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
<>	144:ef7eb2e8f9f7	755	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
<>	144:ef7eb2e8f9f7	756	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
<>	144:ef7eb2e8f9f7	757	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
<>	144:ef7eb2e8f9f7	758	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
<>	144:ef7eb2e8f9f7	759	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
<>	144:ef7eb2e8f9f7	760	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
<>	144:ef7eb2e8f9f7	761	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
<>	144:ef7eb2e8f9f7	762	* @param Filter This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	763	* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
<>	144:ef7eb2e8f9f7	764	* @arg @ref LL_LPTIM_TRIG_FILTER_2
<>	144:ef7eb2e8f9f7	765	* @arg @ref LL_LPTIM_TRIG_FILTER_4
<>	144:ef7eb2e8f9f7	766	* @arg @ref LL_LPTIM_TRIG_FILTER_8
<>	144:ef7eb2e8f9f7	767	* @param Polarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	768	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
<>	144:ef7eb2e8f9f7	769	* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	770	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
<>	144:ef7eb2e8f9f7	771	* @retval None
<>	144:ef7eb2e8f9f7	772	*/
<>	144:ef7eb2e8f9f7	773	__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
<>	144:ef7eb2e8f9f7	774	{
<>	144:ef7eb2e8f9f7	775	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL \| LPTIM_CFGR_TRGFLT \| LPTIM_CFGR_TRIGEN, Source \| Filter \| Polarity);
<>	144:ef7eb2e8f9f7	776	}
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	/**
<>	144:ef7eb2e8f9f7	779	* @brief Get actual external trigger source.
<>	144:ef7eb2e8f9f7	780	* @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
<>	144:ef7eb2e8f9f7	781	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	782	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	783	* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
<>	144:ef7eb2e8f9f7	784	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
<>	144:ef7eb2e8f9f7	785	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
<>	144:ef7eb2e8f9f7	786	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
<>	144:ef7eb2e8f9f7	787	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
<>	144:ef7eb2e8f9f7	788	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
<>	144:ef7eb2e8f9f7	789	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
<>	144:ef7eb2e8f9f7	790	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
<>	144:ef7eb2e8f9f7	791	*/
<>	144:ef7eb2e8f9f7	792	__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	793	{
<>	144:ef7eb2e8f9f7	794	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
<>	144:ef7eb2e8f9f7	795	}
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	/**
<>	144:ef7eb2e8f9f7	798	* @brief Get actual external trigger filter.
<>	144:ef7eb2e8f9f7	799	* @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
<>	144:ef7eb2e8f9f7	800	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	801	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	802	* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
<>	144:ef7eb2e8f9f7	803	* @arg @ref LL_LPTIM_TRIG_FILTER_2
<>	144:ef7eb2e8f9f7	804	* @arg @ref LL_LPTIM_TRIG_FILTER_4
<>	144:ef7eb2e8f9f7	805	* @arg @ref LL_LPTIM_TRIG_FILTER_8
<>	144:ef7eb2e8f9f7	806	*/
<>	144:ef7eb2e8f9f7	807	__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	808	{
<>	144:ef7eb2e8f9f7	809	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
<>	144:ef7eb2e8f9f7	810	}
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/**
<>	144:ef7eb2e8f9f7	813	* @brief Get actual external trigger polarity.
<>	144:ef7eb2e8f9f7	814	* @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
<>	144:ef7eb2e8f9f7	815	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	816	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	817	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
<>	144:ef7eb2e8f9f7	818	* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	819	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
<>	144:ef7eb2e8f9f7	820	*/
<>	144:ef7eb2e8f9f7	821	__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	822	{
<>	144:ef7eb2e8f9f7	823	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
<>	144:ef7eb2e8f9f7	824	}
<>	144:ef7eb2e8f9f7	825
<>	144:ef7eb2e8f9f7	826	/**
<>	144:ef7eb2e8f9f7	827	* @}
<>	144:ef7eb2e8f9f7	828	*/
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
<>	144:ef7eb2e8f9f7	831	* @{
<>	144:ef7eb2e8f9f7	832	*/
<>	144:ef7eb2e8f9f7	833
<>	144:ef7eb2e8f9f7	834	/**
<>	144:ef7eb2e8f9f7	835	* @brief Set the source of the clock used by the LPTIM instance.
<>	144:ef7eb2e8f9f7	836	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	837	* @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
<>	144:ef7eb2e8f9f7	838	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	839	* @param ClockSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	840	* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
<>	144:ef7eb2e8f9f7	841	* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
<>	144:ef7eb2e8f9f7	842	* @retval None
<>	144:ef7eb2e8f9f7	843	*/
<>	144:ef7eb2e8f9f7	844	__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
<>	144:ef7eb2e8f9f7	845	{
<>	144:ef7eb2e8f9f7	846	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
<>	144:ef7eb2e8f9f7	847	}
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	/**
<>	144:ef7eb2e8f9f7	850	* @brief Get actual LPTIM instance clock source.
<>	144:ef7eb2e8f9f7	851	* @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
<>	144:ef7eb2e8f9f7	852	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	853	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	854	* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
<>	144:ef7eb2e8f9f7	855	* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
<>	144:ef7eb2e8f9f7	856	*/
<>	144:ef7eb2e8f9f7	857	__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	858	{
<>	144:ef7eb2e8f9f7	859	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
<>	144:ef7eb2e8f9f7	860	}
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/**
<>	144:ef7eb2e8f9f7	863	* @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
<>	144:ef7eb2e8f9f7	864	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	865	* @note When both external clock signal edges are considered active ones,
<>	144:ef7eb2e8f9f7	866	* the LPTIM must also be clocked by an internal clock source with a
<>	144:ef7eb2e8f9f7	867	* frequency equal to at least four times the external clock frequency.
<>	144:ef7eb2e8f9f7	868	* @note An internal clock source must be present when a digital filter is
<>	144:ef7eb2e8f9f7	869	* required for external clock.
<>	144:ef7eb2e8f9f7	870	* @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
<>	144:ef7eb2e8f9f7	871	* CFGR CKPOL LL_LPTIM_ConfigClock
<>	144:ef7eb2e8f9f7	872	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	873	* @param ClockFilter This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	874	* @arg @ref LL_LPTIM_CLK_FILTER_NONE
<>	144:ef7eb2e8f9f7	875	* @arg @ref LL_LPTIM_CLK_FILTER_2
<>	144:ef7eb2e8f9f7	876	* @arg @ref LL_LPTIM_CLK_FILTER_4
<>	144:ef7eb2e8f9f7	877	* @arg @ref LL_LPTIM_CLK_FILTER_8
<>	144:ef7eb2e8f9f7	878	* @param ClockPolarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	879	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
<>	144:ef7eb2e8f9f7	880	* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	881	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
<>	144:ef7eb2e8f9f7	882	* @retval None
<>	144:ef7eb2e8f9f7	883	*/
<>	144:ef7eb2e8f9f7	884	__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
<>	144:ef7eb2e8f9f7	885	{
<>	144:ef7eb2e8f9f7	886	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT \| LPTIM_CFGR_CKPOL, ClockFilter \| ClockPolarity);
<>	144:ef7eb2e8f9f7	887	}
<>	144:ef7eb2e8f9f7	888
<>	144:ef7eb2e8f9f7	889	/**
<>	144:ef7eb2e8f9f7	890	* @brief Get actual clock polarity
<>	144:ef7eb2e8f9f7	891	* @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
<>	144:ef7eb2e8f9f7	892	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	893	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	894	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
<>	144:ef7eb2e8f9f7	895	* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	896	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
<>	144:ef7eb2e8f9f7	897	*/
<>	144:ef7eb2e8f9f7	898	__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	899	{
<>	144:ef7eb2e8f9f7	900	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
<>	144:ef7eb2e8f9f7	901	}
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903	/**
<>	144:ef7eb2e8f9f7	904	* @brief Get actual clock digital filter
<>	144:ef7eb2e8f9f7	905	* @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
<>	144:ef7eb2e8f9f7	906	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	907	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	908	* @arg @ref LL_LPTIM_CLK_FILTER_NONE
<>	144:ef7eb2e8f9f7	909	* @arg @ref LL_LPTIM_CLK_FILTER_2
<>	144:ef7eb2e8f9f7	910	* @arg @ref LL_LPTIM_CLK_FILTER_4
<>	144:ef7eb2e8f9f7	911	* @arg @ref LL_LPTIM_CLK_FILTER_8
<>	144:ef7eb2e8f9f7	912	*/
<>	144:ef7eb2e8f9f7	913	__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	914	{
<>	144:ef7eb2e8f9f7	915	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
<>	144:ef7eb2e8f9f7	916	}
<>	144:ef7eb2e8f9f7	917
<>	144:ef7eb2e8f9f7	918	/**
<>	144:ef7eb2e8f9f7	919	* @}
<>	144:ef7eb2e8f9f7	920	*/
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
<>	144:ef7eb2e8f9f7	923	* @{
<>	144:ef7eb2e8f9f7	924	*/
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/**
<>	144:ef7eb2e8f9f7	927	* @brief Configure the encoder mode.
<>	144:ef7eb2e8f9f7	928	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	929	* @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
<>	144:ef7eb2e8f9f7	930	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	931	* @param EncoderMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	932	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
<>	144:ef7eb2e8f9f7	933	* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
<>	144:ef7eb2e8f9f7	934	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
<>	144:ef7eb2e8f9f7	935	* @retval None
<>	144:ef7eb2e8f9f7	936	*/
<>	144:ef7eb2e8f9f7	937	__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
<>	144:ef7eb2e8f9f7	938	{
<>	144:ef7eb2e8f9f7	939	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
<>	144:ef7eb2e8f9f7	940	}
<>	144:ef7eb2e8f9f7	941
<>	144:ef7eb2e8f9f7	942	/**
<>	144:ef7eb2e8f9f7	943	* @brief Get actual encoder mode.
<>	144:ef7eb2e8f9f7	944	* @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
<>	144:ef7eb2e8f9f7	945	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	946	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	947	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
<>	144:ef7eb2e8f9f7	948	* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
<>	144:ef7eb2e8f9f7	949	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
<>	144:ef7eb2e8f9f7	950	*/
<>	144:ef7eb2e8f9f7	951	__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	952	{
<>	144:ef7eb2e8f9f7	953	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
<>	144:ef7eb2e8f9f7	954	}
<>	144:ef7eb2e8f9f7	955
<>	144:ef7eb2e8f9f7	956	/**
<>	144:ef7eb2e8f9f7	957	* @brief Enable the encoder mode
<>	144:ef7eb2e8f9f7	958	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	959	* @note In this mode the LPTIM instance must be clocked by an internal clock
<>	144:ef7eb2e8f9f7	960	* source. Also, the prescaler division ratio must be equal to 1.
<>	144:ef7eb2e8f9f7	961	* @note LPTIM instance must be configured in continuous mode prior enabling
<>	144:ef7eb2e8f9f7	962	* the encoder mode.
<>	144:ef7eb2e8f9f7	963	* @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
<>	144:ef7eb2e8f9f7	964	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	965	* @retval None
<>	144:ef7eb2e8f9f7	966	*/
<>	144:ef7eb2e8f9f7	967	__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	968	{
<>	144:ef7eb2e8f9f7	969	SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
<>	144:ef7eb2e8f9f7	970	}
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/**
<>	144:ef7eb2e8f9f7	973	* @brief Disable the encoder mode
<>	144:ef7eb2e8f9f7	974	* @note This function must be called when the LPTIM instance is disabled.
<>	144:ef7eb2e8f9f7	975	* @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
<>	144:ef7eb2e8f9f7	976	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	977	* @retval None
<>	144:ef7eb2e8f9f7	978	*/
<>	144:ef7eb2e8f9f7	979	__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	980	{
<>	144:ef7eb2e8f9f7	981	CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
<>	144:ef7eb2e8f9f7	982	}
<>	144:ef7eb2e8f9f7	983
<>	144:ef7eb2e8f9f7	984	/**
<>	144:ef7eb2e8f9f7	985	* @brief Indicates whether the LPTIM operates in encoder mode.
<>	144:ef7eb2e8f9f7	986	* @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
<>	144:ef7eb2e8f9f7	987	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	988	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	989	*/
<>	144:ef7eb2e8f9f7	990	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	991	{
<>	144:ef7eb2e8f9f7	992	return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
<>	144:ef7eb2e8f9f7	993	}
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	/**
<>	144:ef7eb2e8f9f7	996	* @}
<>	144:ef7eb2e8f9f7	997	*/
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
<>	144:ef7eb2e8f9f7	1000	* @{
<>	144:ef7eb2e8f9f7	1001	*/
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/**
<>	144:ef7eb2e8f9f7	1004	* @brief Clear the compare match flag (CMPMCF)
<>	144:ef7eb2e8f9f7	1005	* @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
<>	144:ef7eb2e8f9f7	1006	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1007	* @retval None
<>	144:ef7eb2e8f9f7	1008	*/
<>	144:ef7eb2e8f9f7	1009	__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1010	{
<>	144:ef7eb2e8f9f7	1011	SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
<>	144:ef7eb2e8f9f7	1012	}
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	/**
<>	144:ef7eb2e8f9f7	1015	* @brief Inform application whether a compare match interrupt has occurred.
<>	144:ef7eb2e8f9f7	1016	* @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
<>	144:ef7eb2e8f9f7	1017	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1018	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1019	*/
<>	144:ef7eb2e8f9f7	1020	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1021	{
<>	144:ef7eb2e8f9f7	1022	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
<>	144:ef7eb2e8f9f7	1023	}
<>	144:ef7eb2e8f9f7	1024
<>	144:ef7eb2e8f9f7	1025	/**
<>	144:ef7eb2e8f9f7	1026	* @brief Clear the autoreload match flag (ARRMCF)
<>	144:ef7eb2e8f9f7	1027	* @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
<>	144:ef7eb2e8f9f7	1028	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1029	* @retval None
<>	144:ef7eb2e8f9f7	1030	*/
<>	144:ef7eb2e8f9f7	1031	__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1032	{
<>	144:ef7eb2e8f9f7	1033	SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
<>	144:ef7eb2e8f9f7	1034	}
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	/**
<>	144:ef7eb2e8f9f7	1037	* @brief Inform application whether a autoreload match interrupt has occured.
<>	144:ef7eb2e8f9f7	1038	* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
<>	144:ef7eb2e8f9f7	1039	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1040	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1041	*/
<>	144:ef7eb2e8f9f7	1042	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1043	{
<>	144:ef7eb2e8f9f7	1044	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
<>	144:ef7eb2e8f9f7	1045	}
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/**
<>	144:ef7eb2e8f9f7	1048	* @brief Clear the external trigger valid edge flag(EXTTRIGCF).
<>	144:ef7eb2e8f9f7	1049	* @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
<>	144:ef7eb2e8f9f7	1050	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1051	* @retval None
<>	144:ef7eb2e8f9f7	1052	*/
<>	144:ef7eb2e8f9f7	1053	__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1054	{
<>	144:ef7eb2e8f9f7	1055	SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
<>	144:ef7eb2e8f9f7	1056	}
<>	144:ef7eb2e8f9f7	1057
<>	144:ef7eb2e8f9f7	1058	/**
<>	144:ef7eb2e8f9f7	1059	* @brief Inform application whether a valid edge on the selected external trigger input has occurred.
<>	144:ef7eb2e8f9f7	1060	* @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
<>	144:ef7eb2e8f9f7	1061	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1062	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1063	*/
<>	144:ef7eb2e8f9f7	1064	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1065	{
<>	144:ef7eb2e8f9f7	1066	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
<>	144:ef7eb2e8f9f7	1067	}
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	/**
<>	144:ef7eb2e8f9f7	1070	* @brief Clear the compare register update interrupt flag (CMPOKCF).
<>	144:ef7eb2e8f9f7	1071	* @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
<>	144:ef7eb2e8f9f7	1072	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1073	* @retval None
<>	144:ef7eb2e8f9f7	1074	*/
<>	144:ef7eb2e8f9f7	1075	__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1076	{
<>	144:ef7eb2e8f9f7	1077	SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
<>	144:ef7eb2e8f9f7	1078	}
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/**
<>	144:ef7eb2e8f9f7	1081	* @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
<>	144:ef7eb2e8f9f7	1082	* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
<>	144:ef7eb2e8f9f7	1083	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1084	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1085	*/
<>	144:ef7eb2e8f9f7	1086	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1087	{
<>	144:ef7eb2e8f9f7	1088	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
<>	144:ef7eb2e8f9f7	1089	}
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	/**
<>	144:ef7eb2e8f9f7	1092	* @brief Clear the autoreload register update interrupt flag (ARROKCF).
<>	144:ef7eb2e8f9f7	1093	* @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
<>	144:ef7eb2e8f9f7	1094	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1095	* @retval None
<>	144:ef7eb2e8f9f7	1096	*/
<>	144:ef7eb2e8f9f7	1097	__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1098	{
<>	144:ef7eb2e8f9f7	1099	SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
<>	144:ef7eb2e8f9f7	1100	}
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/**
<>	144:ef7eb2e8f9f7	1103	* @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
<>	144:ef7eb2e8f9f7	1104	* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
<>	144:ef7eb2e8f9f7	1105	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1106	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1107	*/
<>	144:ef7eb2e8f9f7	1108	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1109	{
<>	144:ef7eb2e8f9f7	1110	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
<>	144:ef7eb2e8f9f7	1111	}
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/**
<>	144:ef7eb2e8f9f7	1114	* @brief Clear the counter direction change to up interrupt flag (UPCF).
<>	144:ef7eb2e8f9f7	1115	* @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
<>	144:ef7eb2e8f9f7	1116	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1117	* @retval None
<>	144:ef7eb2e8f9f7	1118	*/
<>	144:ef7eb2e8f9f7	1119	__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1120	{
<>	144:ef7eb2e8f9f7	1121	SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
<>	144:ef7eb2e8f9f7	1122	}
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	/**
<>	144:ef7eb2e8f9f7	1125	* @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
<>	144:ef7eb2e8f9f7	1126	* @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
<>	144:ef7eb2e8f9f7	1127	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1128	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1129	*/
<>	144:ef7eb2e8f9f7	1130	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1131	{
<>	144:ef7eb2e8f9f7	1132	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
<>	144:ef7eb2e8f9f7	1133	}
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/**
<>	144:ef7eb2e8f9f7	1136	* @brief Clear the counter direction change to down interrupt flag (DOWNCF).
<>	144:ef7eb2e8f9f7	1137	* @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
<>	144:ef7eb2e8f9f7	1138	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1139	* @retval None
<>	144:ef7eb2e8f9f7	1140	*/
<>	144:ef7eb2e8f9f7	1141	__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
<>	144:ef7eb2e8f9f7	1144	}
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	/**
<>	144:ef7eb2e8f9f7	1147	* @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
<>	144:ef7eb2e8f9f7	1148	* @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
<>	144:ef7eb2e8f9f7	1149	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1150	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1151	*/
<>	144:ef7eb2e8f9f7	1152	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1153	{
<>	144:ef7eb2e8f9f7	1154	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
<>	144:ef7eb2e8f9f7	1155	}
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/**
<>	144:ef7eb2e8f9f7	1158	* @}
<>	144:ef7eb2e8f9f7	1159	*/
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
<>	144:ef7eb2e8f9f7	1162	* @{
<>	144:ef7eb2e8f9f7	1163	*/
<>	144:ef7eb2e8f9f7	1164
<>	144:ef7eb2e8f9f7	1165	/**
<>	144:ef7eb2e8f9f7	1166	* @brief Enable compare match interrupt (CMPMIE).
<>	144:ef7eb2e8f9f7	1167	* @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
<>	144:ef7eb2e8f9f7	1168	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1169	* @retval None
<>	144:ef7eb2e8f9f7	1170	*/
<>	144:ef7eb2e8f9f7	1171	__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1172	{
<>	144:ef7eb2e8f9f7	1173	SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
<>	144:ef7eb2e8f9f7	1174	}
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	/**
<>	144:ef7eb2e8f9f7	1177	* @brief Disable compare match interrupt (CMPMIE).
<>	144:ef7eb2e8f9f7	1178	* @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
<>	144:ef7eb2e8f9f7	1179	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1180	* @retval None
<>	144:ef7eb2e8f9f7	1181	*/
<>	144:ef7eb2e8f9f7	1182	__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1183	{
<>	144:ef7eb2e8f9f7	1184	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
<>	144:ef7eb2e8f9f7	1185	}
<>	144:ef7eb2e8f9f7	1186
<>	144:ef7eb2e8f9f7	1187	/**
<>	144:ef7eb2e8f9f7	1188	* @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
<>	144:ef7eb2e8f9f7	1189	* @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
<>	144:ef7eb2e8f9f7	1190	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1191	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1192	*/
<>	144:ef7eb2e8f9f7	1193	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1194	{
<>	144:ef7eb2e8f9f7	1195	return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
<>	144:ef7eb2e8f9f7	1196	}
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/**
<>	144:ef7eb2e8f9f7	1199	* @brief Enable autoreload match interrupt (ARRMIE).
<>	144:ef7eb2e8f9f7	1200	* @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
<>	144:ef7eb2e8f9f7	1201	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1202	* @retval None
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204	__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1205	{
<>	144:ef7eb2e8f9f7	1206	SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
<>	144:ef7eb2e8f9f7	1207	}
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	/**
<>	144:ef7eb2e8f9f7	1210	* @brief Disable autoreload match interrupt (ARRMIE).
<>	144:ef7eb2e8f9f7	1211	* @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
<>	144:ef7eb2e8f9f7	1212	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1213	* @retval None
<>	144:ef7eb2e8f9f7	1214	*/
<>	144:ef7eb2e8f9f7	1215	__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1216	{
<>	144:ef7eb2e8f9f7	1217	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
<>	144:ef7eb2e8f9f7	1218	}
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/**
<>	144:ef7eb2e8f9f7	1221	* @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
<>	144:ef7eb2e8f9f7	1222	* @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
<>	144:ef7eb2e8f9f7	1223	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1224	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1225	*/
<>	144:ef7eb2e8f9f7	1226	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1227	{
<>	144:ef7eb2e8f9f7	1228	return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
<>	144:ef7eb2e8f9f7	1229	}
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	/**
<>	144:ef7eb2e8f9f7	1232	* @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
<>	144:ef7eb2e8f9f7	1233	* @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
<>	144:ef7eb2e8f9f7	1234	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1235	* @retval None
<>	144:ef7eb2e8f9f7	1236	*/
<>	144:ef7eb2e8f9f7	1237	__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1238	{
<>	144:ef7eb2e8f9f7	1239	SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
<>	144:ef7eb2e8f9f7	1240	}
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	/**
<>	144:ef7eb2e8f9f7	1243	* @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
<>	144:ef7eb2e8f9f7	1244	* @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
<>	144:ef7eb2e8f9f7	1245	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1246	* @retval None
<>	144:ef7eb2e8f9f7	1247	*/
<>	144:ef7eb2e8f9f7	1248	__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1249	{
<>	144:ef7eb2e8f9f7	1250	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
<>	144:ef7eb2e8f9f7	1251	}
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/**
<>	144:ef7eb2e8f9f7	1254	* @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
<>	144:ef7eb2e8f9f7	1255	* @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
<>	144:ef7eb2e8f9f7	1256	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1257	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1258	*/
<>	144:ef7eb2e8f9f7	1259	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1260	{
<>	144:ef7eb2e8f9f7	1261	return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
<>	144:ef7eb2e8f9f7	1262	}
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264	/**
<>	144:ef7eb2e8f9f7	1265	* @brief Enable compare register write completed interrupt (CMPOKIE).
<>	144:ef7eb2e8f9f7	1266	* @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
<>	144:ef7eb2e8f9f7	1267	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1268	* @retval None
<>	144:ef7eb2e8f9f7	1269	*/
<>	144:ef7eb2e8f9f7	1270	__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1271	{
<>	144:ef7eb2e8f9f7	1272	SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
<>	144:ef7eb2e8f9f7	1273	}
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/**
<>	144:ef7eb2e8f9f7	1276	* @brief Disable compare register write completed interrupt (CMPOKIE).
<>	144:ef7eb2e8f9f7	1277	* @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
<>	144:ef7eb2e8f9f7	1278	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1279	* @retval None
<>	144:ef7eb2e8f9f7	1280	*/
<>	144:ef7eb2e8f9f7	1281	__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1282	{
<>	144:ef7eb2e8f9f7	1283	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
<>	144:ef7eb2e8f9f7	1284	}
<>	144:ef7eb2e8f9f7	1285
<>	144:ef7eb2e8f9f7	1286	/**
<>	144:ef7eb2e8f9f7	1287	* @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
<>	144:ef7eb2e8f9f7	1288	* @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
<>	144:ef7eb2e8f9f7	1289	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1290	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1291	*/
<>	144:ef7eb2e8f9f7	1292	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1293	{
<>	144:ef7eb2e8f9f7	1294	return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
<>	144:ef7eb2e8f9f7	1295	}
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	/**
<>	144:ef7eb2e8f9f7	1298	* @brief Enable autoreload register write completed interrupt (ARROKIE).
<>	144:ef7eb2e8f9f7	1299	* @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
<>	144:ef7eb2e8f9f7	1300	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1301	* @retval None
<>	144:ef7eb2e8f9f7	1302	*/
<>	144:ef7eb2e8f9f7	1303	__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1304	{
<>	144:ef7eb2e8f9f7	1305	SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
<>	144:ef7eb2e8f9f7	1306	}
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	/**
<>	144:ef7eb2e8f9f7	1309	* @brief Disable autoreload register write completed interrupt (ARROKIE).
<>	144:ef7eb2e8f9f7	1310	* @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
<>	144:ef7eb2e8f9f7	1311	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1312	* @retval None
<>	144:ef7eb2e8f9f7	1313	*/
<>	144:ef7eb2e8f9f7	1314	__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1315	{
<>	144:ef7eb2e8f9f7	1316	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
<>	144:ef7eb2e8f9f7	1317	}
<>	144:ef7eb2e8f9f7	1318
<>	144:ef7eb2e8f9f7	1319	/**
<>	144:ef7eb2e8f9f7	1320	* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
<>	144:ef7eb2e8f9f7	1321	* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
<>	144:ef7eb2e8f9f7	1322	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1323	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1324	*/
<>	144:ef7eb2e8f9f7	1325	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1326	{
<>	144:ef7eb2e8f9f7	1327	return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
<>	144:ef7eb2e8f9f7	1328	}
<>	144:ef7eb2e8f9f7	1329
<>	144:ef7eb2e8f9f7	1330	/**
<>	144:ef7eb2e8f9f7	1331	* @brief Enable direction change to up interrupt (UPIE).
<>	144:ef7eb2e8f9f7	1332	* @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
<>	144:ef7eb2e8f9f7	1333	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1334	* @retval None
<>	144:ef7eb2e8f9f7	1335	*/
<>	144:ef7eb2e8f9f7	1336	__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1337	{
<>	144:ef7eb2e8f9f7	1338	SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
<>	144:ef7eb2e8f9f7	1339	}
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	/**
<>	144:ef7eb2e8f9f7	1342	* @brief Disable direction change to up interrupt (UPIE).
<>	144:ef7eb2e8f9f7	1343	* @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
<>	144:ef7eb2e8f9f7	1344	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1345	* @retval None
<>	144:ef7eb2e8f9f7	1346	*/
<>	144:ef7eb2e8f9f7	1347	__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1348	{
<>	144:ef7eb2e8f9f7	1349	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
<>	144:ef7eb2e8f9f7	1350	}
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	/**
<>	144:ef7eb2e8f9f7	1353	* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
<>	144:ef7eb2e8f9f7	1354	* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
<>	144:ef7eb2e8f9f7	1355	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1356	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1357	*/
<>	144:ef7eb2e8f9f7	1358	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1359	{
<>	144:ef7eb2e8f9f7	1360	return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
<>	144:ef7eb2e8f9f7	1361	}
<>	144:ef7eb2e8f9f7	1362
<>	144:ef7eb2e8f9f7	1363	/**
<>	144:ef7eb2e8f9f7	1364	* @brief Enable direction change to down interrupt (DOWNIE).
<>	144:ef7eb2e8f9f7	1365	* @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
<>	144:ef7eb2e8f9f7	1366	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1367	* @retval None
<>	144:ef7eb2e8f9f7	1368	*/
<>	144:ef7eb2e8f9f7	1369	__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1370	{
<>	144:ef7eb2e8f9f7	1371	SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
<>	144:ef7eb2e8f9f7	1372	}
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	/**
<>	144:ef7eb2e8f9f7	1375	* @brief Disable direction change to down interrupt (DOWNIE).
<>	144:ef7eb2e8f9f7	1376	* @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
<>	144:ef7eb2e8f9f7	1377	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1378	* @retval None
<>	144:ef7eb2e8f9f7	1379	*/
<>	144:ef7eb2e8f9f7	1380	__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1381	{
<>	144:ef7eb2e8f9f7	1382	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
<>	144:ef7eb2e8f9f7	1383	}
<>	144:ef7eb2e8f9f7	1384
<>	144:ef7eb2e8f9f7	1385	/**
<>	144:ef7eb2e8f9f7	1386	* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
<>	144:ef7eb2e8f9f7	1387	* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
<>	144:ef7eb2e8f9f7	1388	* @param LPTIMx Low-Power Timer instance
<>	144:ef7eb2e8f9f7	1389	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1390	*/
<>	144:ef7eb2e8f9f7	1391	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
<>	144:ef7eb2e8f9f7	1392	{
<>	144:ef7eb2e8f9f7	1393	return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
<>	144:ef7eb2e8f9f7	1394	}
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/**
<>	144:ef7eb2e8f9f7	1397	* @}
<>	144:ef7eb2e8f9f7	1398	*/
<>	144:ef7eb2e8f9f7	1399
<>	144:ef7eb2e8f9f7	1400	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	1401	/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
<>	144:ef7eb2e8f9f7	1402	* @{
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
<>	144:ef7eb2e8f9f7	1406	void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
<>	144:ef7eb2e8f9f7	1407	ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef LPTIMx, LL_LPTIM_InitTypeDef LPTIM_InitStruct);
<>	144:ef7eb2e8f9f7	1408	/**
<>	144:ef7eb2e8f9f7	1409	* @}
<>	144:ef7eb2e8f9f7	1410	*/
<>	144:ef7eb2e8f9f7	1411	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	/**
<>	144:ef7eb2e8f9f7	1414	* @}
<>	144:ef7eb2e8f9f7	1415	*/
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/**
<>	144:ef7eb2e8f9f7	1418	* @}
<>	144:ef7eb2e8f9f7	1419	*/
<>	144:ef7eb2e8f9f7	1420
<>	144:ef7eb2e8f9f7	1421	#endif /* LPTIM1 \|\| LPTIM2 */
<>	144:ef7eb2e8f9f7	1422
<>	144:ef7eb2e8f9f7	1423	/**
<>	144:ef7eb2e8f9f7	1424	* @}
<>	144:ef7eb2e8f9f7	1425	*/
<>	144:ef7eb2e8f9f7	1426
<>	144:ef7eb2e8f9f7	1427	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1428	}
<>	144:ef7eb2e8f9f7	1429	#endif
<>	144:ef7eb2e8f9f7	1430
<>	144:ef7eb2e8f9f7	1431	#endif /* __STM32L4xx_LL_LPTIM_H */
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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