Jolyon Hill / mbed-dev

Changes to support running on smaller memory LPC device LPC1764

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Child:
147:30b64687e01f
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************/
<> 144:ef7eb2e8f9f7 2 /**
<> 144:ef7eb2e8f9f7 3 * @file ARMCM3.h
<> 144:ef7eb2e8f9f7 4 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
<> 144:ef7eb2e8f9f7 5 * for CM3 Device Series
<> 144:ef7eb2e8f9f7 6 * @version V1.05
<> 144:ef7eb2e8f9f7 7 * @date 26. July 2011
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * @note
<> 144:ef7eb2e8f9f7 10 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * @par
<> 144:ef7eb2e8f9f7 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 144:ef7eb2e8f9f7 14 * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 15 * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * @par
<> 144:ef7eb2e8f9f7 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 ******************************************************************************/
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #ifndef ARMCM3_H
<> 144:ef7eb2e8f9f7 27 #define ARMCM3_H
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /**
<> 144:ef7eb2e8f9f7 30 * ==========================================================================
<> 144:ef7eb2e8f9f7 31 * ---------- Interrupt Number Definition -----------------------------------
<> 144:ef7eb2e8f9f7 32 * ==========================================================================
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34 typedef enum IRQn
<> 144:ef7eb2e8f9f7 35 {
<> 144:ef7eb2e8f9f7 36 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
<> 144:ef7eb2e8f9f7 37 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 38 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
<> 144:ef7eb2e8f9f7 39 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 40 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 41 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 42 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 43 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 44 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 45 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /****** ARMCM3 specific Interrupt Numbers ********************************************************/
<> 144:ef7eb2e8f9f7 48 Tim0_IRQn = 0,
<> 144:ef7eb2e8f9f7 49 Tim1_IRQn = 1,
<> 144:ef7eb2e8f9f7 50 Tim2_IRQn = 2,
<> 144:ef7eb2e8f9f7 51 Uart1_IRQn = 3,
<> 144:ef7eb2e8f9f7 52 Spi_IRQn = 4,
<> 144:ef7eb2e8f9f7 53 I2C_IRQn = 5,
<> 144:ef7eb2e8f9f7 54 Gpio_IRQn = 6,
<> 144:ef7eb2e8f9f7 55 Rtc_IRQn = 7,
<> 144:ef7eb2e8f9f7 56 Flash_IRQn = 8,
<> 144:ef7eb2e8f9f7 57 MacHw_IRQn = 9,
<> 144:ef7eb2e8f9f7 58 Aes_IRQn = 10,
<> 144:ef7eb2e8f9f7 59 Adc_IRQn = 11,
<> 144:ef7eb2e8f9f7 60 ClockCal_IRQn = 12,
<> 144:ef7eb2e8f9f7 61 Uart2_IRQn = 13,
<> 144:ef7eb2e8f9f7 62 Uvi_IRQn = 14,
<> 144:ef7eb2e8f9f7 63 Dma_IRQn = 15,
<> 144:ef7eb2e8f9f7 64 DbgPwrUp_IRQn = 16,
<> 144:ef7eb2e8f9f7 65 Spi2_IRQn = 17,
<> 144:ef7eb2e8f9f7 66 I2C2_IRQn = 18,
<> 144:ef7eb2e8f9f7 67 FVDDHComp_IRQn = 19
<> 144:ef7eb2e8f9f7 68 } IRQn_Type;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /**
<> 144:ef7eb2e8f9f7 71 * ==========================================================================
<> 144:ef7eb2e8f9f7 72 * ----------- Processor and Core Peripheral Section ------------------------
<> 144:ef7eb2e8f9f7 73 * ==========================================================================
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /** Configuration of the Cortex-M3 Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 77 #define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
<> 144:ef7eb2e8f9f7 78 #define __MPU_PRESENT 1 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 79 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 80 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
<> 144:ef7eb2e8f9f7 83 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
<> 144:ef7eb2e8f9f7 84 //#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 //#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
<> 144:ef7eb2e8f9f7 87 //#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
<> 144:ef7eb2e8f9f7 90 #include "system_NCS36510.h" /* System Header */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #endif /* ARMCM3_H */