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targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/cmsis_nvic.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #ifndef MBED_CMSIS_NVIC_H
<> 144:ef7eb2e8f9f7 18 #define MBED_CMSIS_NVIC_H
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #define NVIC_USER_IRQ_OFFSET 16
<> 144:ef7eb2e8f9f7 23 #define NVIC_USER_IRQ_NUMBER 142
<> 144:ef7eb2e8f9f7 24 #define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 27 # define NVIC_RAM_VECTOR_ADDRESS &Image$$ER_IRAMVEC$$ZI$$Base
<> 144:ef7eb2e8f9f7 28 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 29 # pragma section = "IRAMVEC"
<> 144:ef7eb2e8f9f7 30 # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
<> 144:ef7eb2e8f9f7 31 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 32 # define NVIC_RAM_VECTOR_ADDRESS &__start_vector_table__
<> 144:ef7eb2e8f9f7 33 #endif
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #define NVIC_FLASH_VECTOR_ADDRESS 0
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 39 extern "C" {
<> 144:ef7eb2e8f9f7 40 #endif
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /** Set the ISR for IRQn
<> 144:ef7eb2e8f9f7 43 *
<> 144:ef7eb2e8f9f7 44 * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
<> 144:ef7eb2e8f9f7 45 * the first time this function is called
<> 144:ef7eb2e8f9f7 46 * @param[in] IRQn The Interrupt Request number for which a vector will be registered
<> 144:ef7eb2e8f9f7 47 * @param[in] vector The ISR vector to register for IRQn
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** Get the ISR registered for IRQn
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * Reads the Interrupt Service Routine currently registered for IRQn
<> 144:ef7eb2e8f9f7 54 * @param[in] IRQn The Interrupt Request number the vector of which will be read
<> 144:ef7eb2e8f9f7 55 * @return Returns the ISR registered for IRQn
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57 uint32_t NVIC_GetVector(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 60 }
<> 144:ef7eb2e8f9f7 61 #endif
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #endif