Jolyon Hill / mbed-dev

Changes to support running on smaller memory LPC device LPC1764

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC13XX/pinmap.c@149:6f3fb14e6942, 2016-10-10 (annotated)

Committer:
jolyon
Date:
Mon Oct 10 14:36:54 2016 +0000
Revision:
149:6f3fb14e6942
Parent:
144:ef7eb2e8f9f7 
Working with LPC1764 & inverted LEDS

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 18 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 #define LPC_IOCON0_BASE (LPC_IOCON_BASE)
<> 144:ef7eb2e8f9f7 21 #define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 void pin_function(PinName pin, int function) {
<> 144:ef7eb2e8f9f7 24 MBED_ASSERT(pin != (PinName)NC);
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 uint32_t pin_number = (uint32_t)pin;
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 __IO uint32_t *reg = (pin_number < 32) ?
<> 144:ef7eb2e8f9f7 29 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
<> 144:ef7eb2e8f9f7 30 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 // pin function bits: [2:0] -> 111 = (0x7)
<> 144:ef7eb2e8f9f7 33 *reg = (*reg & ~0x7) | (function & 0x7);
<> 144:ef7eb2e8f9f7 34 }
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 void pin_mode(PinName pin, PinMode mode) {
<> 144:ef7eb2e8f9f7 37 MBED_ASSERT(pin != (PinName)NC);
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 uint32_t pin_number = (uint32_t)pin;
<> 144:ef7eb2e8f9f7 40 uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 __IO uint32_t *reg = (pin_number < 32) ?
<> 144:ef7eb2e8f9f7 43 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
<> 144:ef7eb2e8f9f7 44 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
<> 144:ef7eb2e8f9f7 45 uint32_t tmp = *reg;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
<> 144:ef7eb2e8f9f7 48 tmp &= ~(0x3 << 3);
<> 144:ef7eb2e8f9f7 49 tmp |= (mode & 0x3) << 3;
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 // drain
<> 144:ef7eb2e8f9f7 52 tmp &= ~(0x1 << 10);
<> 144:ef7eb2e8f9f7 53 tmp |= drain << 10;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 *reg = tmp;
<> 144:ef7eb2e8f9f7 56 }