VL53L3_Lib - Fork Charles's library

Users » johnAlexander » Code » VL53L3_Lib

Fork Charles's library

Dependencies: X_NUCLEO_COMMON ST_INTERFACES

vl53lx_def.h@3:316175f392f7, 2020-11-03 (annotated)

Committer:: johnAlexander
Date:: Tue Nov 03 15:16:36 2020 +0000
Revision:: 3:316175f392f7
Parent:: vl53l3inc/vl53lx_def.h@0:0be0bd219e72

Add ST common libs

Who changed what in which revision?

User	Revision	Line number	New contents of line
charlesmn	0:0be0bd219e72	1
charlesmn	0:0be0bd219e72	2	#ifndef __VL53LX_DEF_H
charlesmn	0:0be0bd219e72	3	#define __VL53LX_DEF_H
charlesmn	0:0be0bd219e72	4
charlesmn	0:0be0bd219e72	5	#include <stdint.h>
charlesmn	0:0be0bd219e72	6	#include <stdint.h>
charlesmn	0:0be0bd219e72	7	#include <stddef.h>
charlesmn	0:0be0bd219e72	8	#include <string.h>
charlesmn	0:0be0bd219e72	9	#include <stdio.h>
charlesmn	0:0be0bd219e72	10	#include <stdlib.h>
charlesmn	0:0be0bd219e72	11
charlesmn	0:0be0bd219e72	12	#include "vl53L3_I2c.h"
charlesmn	0:0be0bd219e72	13
charlesmn	0:0be0bd219e72	14	#ifdef __cplusplus
charlesmn	0:0be0bd219e72	15	extern "C"
charlesmn	0:0be0bd219e72	16	{
charlesmn	0:0be0bd219e72	17	#endif
charlesmn	0:0be0bd219e72	18
charlesmn	0:0be0bd219e72	19	//define from vl53lx_register_map.h
charlesmn	0:0be0bd219e72	20
charlesmn	0:0be0bd219e72	21	#define VL53LX_SOFT_RESET 0x0000
charlesmn	0:0be0bd219e72	22
charlesmn	0:0be0bd219e72	23	#define VL53LX_I2C_SLAVE__DEVICE_ADDRESS 0x0001
charlesmn	0:0be0bd219e72	24
charlesmn	0:0be0bd219e72	25	#define VL53LX_ANA_CONFIG__VHV_REF_SEL_VDDPIX 0x0002
charlesmn	0:0be0bd219e72	26
charlesmn	0:0be0bd219e72	27	#define VL53LX_ANA_CONFIG__VHV_REF_SEL_VQUENCH 0x0003
charlesmn	0:0be0bd219e72	28
charlesmn	0:0be0bd219e72	29	#define VL53LX_ANA_CONFIG__REG_AVDD1V2_SEL 0x0004
charlesmn	0:0be0bd219e72	30
charlesmn	0:0be0bd219e72	31	#define VL53LX_ANA_CONFIG__FAST_OSC__TRIM 0x0005
charlesmn	0:0be0bd219e72	32
charlesmn	0:0be0bd219e72	33	#define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY 0x0006
charlesmn	0:0be0bd219e72	34
charlesmn	0:0be0bd219e72	35	#define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY_HI 0x0006
charlesmn	0:0be0bd219e72	36
charlesmn	0:0be0bd219e72	37	#define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY_LO 0x0007
charlesmn	0:0be0bd219e72	38
charlesmn	0:0be0bd219e72	39	#define VL53LX_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008
charlesmn	0:0be0bd219e72	40
charlesmn	0:0be0bd219e72	41	#define VL53LX_VHV_CONFIG__COUNT_THRESH 0x0009
charlesmn	0:0be0bd219e72	42
charlesmn	0:0be0bd219e72	43	#define VL53LX_VHV_CONFIG__OFFSET 0x000A
charlesmn	0:0be0bd219e72	44
charlesmn	0:0be0bd219e72	45	#define VL53LX_VHV_CONFIG__INIT 0x000B
charlesmn	0:0be0bd219e72	46
charlesmn	0:0be0bd219e72	47	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D
charlesmn	0:0be0bd219e72	48
charlesmn	0:0be0bd219e72	49	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_1 0x000E
charlesmn	0:0be0bd219e72	50
charlesmn	0:0be0bd219e72	51	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_2 0x000F
charlesmn	0:0be0bd219e72	52
charlesmn	0:0be0bd219e72	53	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_3 0x0010
charlesmn	0:0be0bd219e72	54
charlesmn	0:0be0bd219e72	55	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_4 0x0011
charlesmn	0:0be0bd219e72	56
charlesmn	0:0be0bd219e72	57	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_5 0x0012
charlesmn	0:0be0bd219e72	58
charlesmn	0:0be0bd219e72	59	#define VL53LX_GLOBAL_CONFIG__REF_EN_START_SELECT 0x0013
charlesmn	0:0be0bd219e72	60
charlesmn	0:0be0bd219e72	61	#define VL53LX_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS 0x0014
charlesmn	0:0be0bd219e72	62
charlesmn	0:0be0bd219e72	63	#define VL53LX_REF_SPAD_MAN__REF_LOCATION 0x0015
charlesmn	0:0be0bd219e72	64
charlesmn	0:0be0bd219e72	65	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x0016
charlesmn	0:0be0bd219e72	66
charlesmn	0:0be0bd219e72	67	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI 0x0016
charlesmn	0:0be0bd219e72	68
charlesmn	0:0be0bd219e72	69	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO 0x0017
charlesmn	0:0be0bd219e72	70
charlesmn	0:0be0bd219e72	71	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x0018
charlesmn	0:0be0bd219e72	72
charlesmn	0:0be0bd219e72	73	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI 0x0018
charlesmn	0:0be0bd219e72	74
charlesmn	0:0be0bd219e72	75	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO 0x0019
charlesmn	0:0be0bd219e72	76
charlesmn	0:0be0bd219e72	77	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x001A
charlesmn	0:0be0bd219e72	78
charlesmn	0:0be0bd219e72	79	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI 0x001A
charlesmn	0:0be0bd219e72	80
charlesmn	0:0be0bd219e72	81	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO 0x001B
charlesmn	0:0be0bd219e72	82
charlesmn	0:0be0bd219e72	83	#define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS 0x001C
charlesmn	0:0be0bd219e72	84
charlesmn	0:0be0bd219e72	85	#define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI 0x001C
charlesmn	0:0be0bd219e72	86
charlesmn	0:0be0bd219e72	87	#define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO 0x001D
charlesmn	0:0be0bd219e72	88
charlesmn	0:0be0bd219e72	89	#define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x001E
charlesmn	0:0be0bd219e72	90
charlesmn	0:0be0bd219e72	91	#define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI 0x001E
charlesmn	0:0be0bd219e72	92
charlesmn	0:0be0bd219e72	93	#define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO 0x001F
charlesmn	0:0be0bd219e72	94
charlesmn	0:0be0bd219e72	95	#define VL53LX_MM_CONFIG__INNER_OFFSET_MM 0x0020
charlesmn	0:0be0bd219e72	96
charlesmn	0:0be0bd219e72	97	#define VL53LX_MM_CONFIG__INNER_OFFSET_MM_HI 0x0020
charlesmn	0:0be0bd219e72	98
charlesmn	0:0be0bd219e72	99	#define VL53LX_MM_CONFIG__INNER_OFFSET_MM_LO 0x0021
charlesmn	0:0be0bd219e72	100
charlesmn	0:0be0bd219e72	101	#define VL53LX_MM_CONFIG__OUTER_OFFSET_MM 0x0022
charlesmn	0:0be0bd219e72	102
charlesmn	0:0be0bd219e72	103	#define VL53LX_MM_CONFIG__OUTER_OFFSET_MM_HI 0x0022
charlesmn	0:0be0bd219e72	104
charlesmn	0:0be0bd219e72	105	#define VL53LX_MM_CONFIG__OUTER_OFFSET_MM_LO 0x0023
charlesmn	0:0be0bd219e72	106
charlesmn	0:0be0bd219e72	107	#define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 0x0024
charlesmn	0:0be0bd219e72	108
charlesmn	0:0be0bd219e72	109	#define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI 0x0024
charlesmn	0:0be0bd219e72	110
charlesmn	0:0be0bd219e72	111	#define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO 0x0025
charlesmn	0:0be0bd219e72	112
charlesmn	0:0be0bd219e72	113	#define VL53LX_DEBUG__CTRL 0x0026
charlesmn	0:0be0bd219e72	114
charlesmn	0:0be0bd219e72	115	#define VL53LX_TEST_MODE__CTRL 0x0027
charlesmn	0:0be0bd219e72	116
charlesmn	0:0be0bd219e72	117	#define VL53LX_CLK_GATING__CTRL 0x0028
charlesmn	0:0be0bd219e72	118
charlesmn	0:0be0bd219e72	119	#define VL53LX_NVM_BIST__CTRL 0x0029
charlesmn	0:0be0bd219e72	120
charlesmn	0:0be0bd219e72	121	#define VL53LX_NVM_BIST__NUM_NVM_WORDS 0x002A
charlesmn	0:0be0bd219e72	122
charlesmn	0:0be0bd219e72	123	#define VL53LX_NVM_BIST__START_ADDRESS 0x002B
charlesmn	0:0be0bd219e72	124
charlesmn	0:0be0bd219e72	125	#define VL53LX_HOST_IF__STATUS 0x002C
charlesmn	0:0be0bd219e72	126
charlesmn	0:0be0bd219e72	127	#define VL53LX_PAD_I2C_HV__CONFIG 0x002D
charlesmn	0:0be0bd219e72	128
charlesmn	0:0be0bd219e72	129	#define VL53LX_PAD_I2C_HV__EXTSUP_CONFIG 0x002E
charlesmn	0:0be0bd219e72	130
charlesmn	0:0be0bd219e72	131	#define VL53LX_GPIO_HV_PAD__CTRL 0x002F
charlesmn	0:0be0bd219e72	132
charlesmn	0:0be0bd219e72	133	#define VL53LX_GPIO_HV_MUX__CTRL 0x0030
charlesmn	0:0be0bd219e72	134
charlesmn	0:0be0bd219e72	135	#define VL53LX_GPIO__TIO_HV_STATUS 0x0031
charlesmn	0:0be0bd219e72	136
charlesmn	0:0be0bd219e72	137	#define VL53LX_GPIO__FIO_HV_STATUS 0x0032
charlesmn	0:0be0bd219e72	138
charlesmn	0:0be0bd219e72	139	#define VL53LX_ANA_CONFIG__SPAD_SEL_PSWIDTH 0x0033
charlesmn	0:0be0bd219e72	140
charlesmn	0:0be0bd219e72	141	#define VL53LX_ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET 0x0034
charlesmn	0:0be0bd219e72	142
charlesmn	0:0be0bd219e72	143	#define VL53LX_ANA_CONFIG__FAST_OSC__CONFIG_CTRL 0x0035
charlesmn	0:0be0bd219e72	144
charlesmn	0:0be0bd219e72	145	#define VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 0x0036
charlesmn	0:0be0bd219e72	146
charlesmn	0:0be0bd219e72	147	#define VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 0x0037
charlesmn	0:0be0bd219e72	148
charlesmn	0:0be0bd219e72	149	#define VL53LX_SIGMA_ESTIMATOR__SIGMA_REF_MM 0x0038
charlesmn	0:0be0bd219e72	150
charlesmn	0:0be0bd219e72	151	#define VL53LX_ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM 0x0039
charlesmn	0:0be0bd219e72	152
charlesmn	0:0be0bd219e72	153	#define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 0x003A
charlesmn	0:0be0bd219e72	154
charlesmn	0:0be0bd219e72	155	#define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 0x003B
charlesmn	0:0be0bd219e72	156
charlesmn	0:0be0bd219e72	157	#define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 0x003C
charlesmn	0:0be0bd219e72	158
charlesmn	0:0be0bd219e72	159	#define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI 0x003C
charlesmn	0:0be0bd219e72	160
charlesmn	0:0be0bd219e72	161	#define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO 0x003D
charlesmn	0:0be0bd219e72	162
charlesmn	0:0be0bd219e72	163	#define VL53LX_ALGO__RANGE_IGNORE_VALID_HEIGHT_MM 0x003E
charlesmn	0:0be0bd219e72	164
charlesmn	0:0be0bd219e72	165	#define VL53LX_ALGO__RANGE_MIN_CLIP 0x003F
charlesmn	0:0be0bd219e72	166
charlesmn	0:0be0bd219e72	167	#define VL53LX_ALGO__CONSISTENCY_CHECK__TOLERANCE 0x0040
charlesmn	0:0be0bd219e72	168
charlesmn	0:0be0bd219e72	169	#define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 0x0041
charlesmn	0:0be0bd219e72	170
charlesmn	0:0be0bd219e72	171	#define VL53LX_SD_CONFIG__RESET_STAGES_MSB 0x0042
charlesmn	0:0be0bd219e72	172
charlesmn	0:0be0bd219e72	173	#define VL53LX_SD_CONFIG__RESET_STAGES_LSB 0x0043
charlesmn	0:0be0bd219e72	174
charlesmn	0:0be0bd219e72	175	#define VL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 0x0044
charlesmn	0:0be0bd219e72	176
charlesmn	0:0be0bd219e72	177	#define VL53LX_GLOBAL_CONFIG__STREAM_DIVIDER 0x0045
charlesmn	0:0be0bd219e72	178
charlesmn	0:0be0bd219e72	179	#define VL53LX_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046
charlesmn	0:0be0bd219e72	180
charlesmn	0:0be0bd219e72	181	#define VL53LX_CAL_CONFIG__VCSEL_START 0x0047
charlesmn	0:0be0bd219e72	182
charlesmn	0:0be0bd219e72	183	#define VL53LX_CAL_CONFIG__REPEAT_RATE 0x0048
charlesmn	0:0be0bd219e72	184
charlesmn	0:0be0bd219e72	185	#define VL53LX_CAL_CONFIG__REPEAT_RATE_HI 0x0048
charlesmn	0:0be0bd219e72	186
charlesmn	0:0be0bd219e72	187	#define VL53LX_CAL_CONFIG__REPEAT_RATE_LO 0x0049
charlesmn	0:0be0bd219e72	188
charlesmn	0:0be0bd219e72	189	#define VL53LX_GLOBAL_CONFIG__VCSEL_WIDTH 0x004A
charlesmn	0:0be0bd219e72	190
charlesmn	0:0be0bd219e72	191	#define VL53LX_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B
charlesmn	0:0be0bd219e72	192
charlesmn	0:0be0bd219e72	193	#define VL53LX_PHASECAL_CONFIG__TARGET 0x004C
charlesmn	0:0be0bd219e72	194
charlesmn	0:0be0bd219e72	195	#define VL53LX_PHASECAL_CONFIG__OVERRIDE 0x004D
charlesmn	0:0be0bd219e72	196
charlesmn	0:0be0bd219e72	197	#define VL53LX_DSS_CONFIG__ROI_MODE_CONTROL 0x004F
charlesmn	0:0be0bd219e72	198
charlesmn	0:0be0bd219e72	199	#define VL53LX_SYSTEM__THRESH_RATE_HIGH 0x0050
charlesmn	0:0be0bd219e72	200
charlesmn	0:0be0bd219e72	201	#define VL53LX_SYSTEM__THRESH_RATE_HIGH_HI 0x0050
charlesmn	0:0be0bd219e72	202
charlesmn	0:0be0bd219e72	203	#define VL53LX_SYSTEM__THRESH_RATE_HIGH_LO 0x0051
charlesmn	0:0be0bd219e72	204
charlesmn	0:0be0bd219e72	205	#define VL53LX_SYSTEM__THRESH_RATE_LOW 0x0052
charlesmn	0:0be0bd219e72	206
charlesmn	0:0be0bd219e72	207	#define VL53LX_SYSTEM__THRESH_RATE_LOW_HI 0x0052
charlesmn	0:0be0bd219e72	208
charlesmn	0:0be0bd219e72	209	#define VL53LX_SYSTEM__THRESH_RATE_LOW_LO 0x0053
charlesmn	0:0be0bd219e72	210
charlesmn	0:0be0bd219e72	211	#define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0054
charlesmn	0:0be0bd219e72	212
charlesmn	0:0be0bd219e72	213	#define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0054
charlesmn	0:0be0bd219e72	214
charlesmn	0:0be0bd219e72	215	#define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0055
charlesmn	0:0be0bd219e72	216
charlesmn	0:0be0bd219e72	217	#define VL53LX_DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0056
charlesmn	0:0be0bd219e72	218
charlesmn	0:0be0bd219e72	219	#define VL53LX_DSS_CONFIG__APERTURE_ATTENUATION 0x0057
charlesmn	0:0be0bd219e72	220
charlesmn	0:0be0bd219e72	221	#define VL53LX_DSS_CONFIG__MAX_SPADS_LIMIT 0x0058
charlesmn	0:0be0bd219e72	222
charlesmn	0:0be0bd219e72	223	#define VL53LX_DSS_CONFIG__MIN_SPADS_LIMIT 0x0059
charlesmn	0:0be0bd219e72	224
charlesmn	0:0be0bd219e72	225	#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI 0x005A
charlesmn	0:0be0bd219e72	226
charlesmn	0:0be0bd219e72	227	#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_LO 0x005B
charlesmn	0:0be0bd219e72	228
charlesmn	0:0be0bd219e72	229	#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_B_HI 0x005C
charlesmn	0:0be0bd219e72	230
charlesmn	0:0be0bd219e72	231	#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_B_LO 0x005D
charlesmn	0:0be0bd219e72	232
charlesmn	0:0be0bd219e72	233	#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x005E
charlesmn	0:0be0bd219e72	234
charlesmn	0:0be0bd219e72	235	#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x005F
charlesmn	0:0be0bd219e72	236
charlesmn	0:0be0bd219e72	237	#define VL53LX_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060
charlesmn	0:0be0bd219e72	238
charlesmn	0:0be0bd219e72	239	#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0061
charlesmn	0:0be0bd219e72	240
charlesmn	0:0be0bd219e72	241	#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0062
charlesmn	0:0be0bd219e72	242
charlesmn	0:0be0bd219e72	243	#define VL53LX_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063
charlesmn	0:0be0bd219e72	244
charlesmn	0:0be0bd219e72	245	#define VL53LX_RANGE_CONFIG__SIGMA_THRESH 0x0064
charlesmn	0:0be0bd219e72	246
charlesmn	0:0be0bd219e72	247	#define VL53LX_RANGE_CONFIG__SIGMA_THRESH_HI 0x0064
charlesmn	0:0be0bd219e72	248
charlesmn	0:0be0bd219e72	249	#define VL53LX_RANGE_CONFIG__SIGMA_THRESH_LO 0x0065
charlesmn	0:0be0bd219e72	250
charlesmn	0:0be0bd219e72	251	#define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0066
charlesmn	0:0be0bd219e72	252
charlesmn	0:0be0bd219e72	253	#define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0066
charlesmn	0:0be0bd219e72	254
charlesmn	0:0be0bd219e72	255	#define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0067
charlesmn	0:0be0bd219e72	256
charlesmn	0:0be0bd219e72	257	#define VL53LX_RANGE_CONFIG__VALID_PHASE_LOW 0x0068
charlesmn	0:0be0bd219e72	258
charlesmn	0:0be0bd219e72	259	#define VL53LX_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069
charlesmn	0:0be0bd219e72	260
charlesmn	0:0be0bd219e72	261	#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C
charlesmn	0:0be0bd219e72	262
charlesmn	0:0be0bd219e72	263	#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_3 0x006C
charlesmn	0:0be0bd219e72	264
charlesmn	0:0be0bd219e72	265	#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_2 0x006D
charlesmn	0:0be0bd219e72	266
charlesmn	0:0be0bd219e72	267	#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_1 0x006E
charlesmn	0:0be0bd219e72	268
charlesmn	0:0be0bd219e72	269	#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_0 0x006F
charlesmn	0:0be0bd219e72	270
charlesmn	0:0be0bd219e72	271	#define VL53LX_SYSTEM__FRACTIONAL_ENABLE 0x0070
charlesmn	0:0be0bd219e72	272
charlesmn	0:0be0bd219e72	273	#define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0 0x0071
charlesmn	0:0be0bd219e72	274
charlesmn	0:0be0bd219e72	275	#define VL53LX_SYSTEM__THRESH_HIGH 0x0072
charlesmn	0:0be0bd219e72	276
charlesmn	0:0be0bd219e72	277	#define VL53LX_SYSTEM__THRESH_HIGH_HI 0x0072
charlesmn	0:0be0bd219e72	278
charlesmn	0:0be0bd219e72	279	#define VL53LX_SYSTEM__THRESH_HIGH_LO 0x0073
charlesmn	0:0be0bd219e72	280
charlesmn	0:0be0bd219e72	281	#define VL53LX_SYSTEM__THRESH_LOW 0x0074
charlesmn	0:0be0bd219e72	282
charlesmn	0:0be0bd219e72	283	#define VL53LX_SYSTEM__THRESH_LOW_HI 0x0074
charlesmn	0:0be0bd219e72	284
charlesmn	0:0be0bd219e72	285	#define VL53LX_SYSTEM__THRESH_LOW_LO 0x0075
charlesmn	0:0be0bd219e72	286
charlesmn	0:0be0bd219e72	287	#define VL53LX_SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x0076
charlesmn	0:0be0bd219e72	288
charlesmn	0:0be0bd219e72	289	#define VL53LX_SYSTEM__SEED_CONFIG 0x0077
charlesmn	0:0be0bd219e72	290
charlesmn	0:0be0bd219e72	291	#define VL53LX_SD_CONFIG__WOI_SD0 0x0078
charlesmn	0:0be0bd219e72	292
charlesmn	0:0be0bd219e72	293	#define VL53LX_SD_CONFIG__WOI_SD1 0x0079
charlesmn	0:0be0bd219e72	294
charlesmn	0:0be0bd219e72	295	#define VL53LX_SD_CONFIG__INITIAL_PHASE_SD0 0x007A
charlesmn	0:0be0bd219e72	296
charlesmn	0:0be0bd219e72	297	#define VL53LX_SD_CONFIG__INITIAL_PHASE_SD1 0x007B
charlesmn	0:0be0bd219e72	298
charlesmn	0:0be0bd219e72	299	#define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_1 0x007C
charlesmn	0:0be0bd219e72	300
charlesmn	0:0be0bd219e72	301	#define VL53LX_SD_CONFIG__FIRST_ORDER_SELECT 0x007D
charlesmn	0:0be0bd219e72	302
charlesmn	0:0be0bd219e72	303	#define VL53LX_SD_CONFIG__QUANTIFIER 0x007E
charlesmn	0:0be0bd219e72	304
charlesmn	0:0be0bd219e72	305	#define VL53LX_ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x007F
charlesmn	0:0be0bd219e72	306
charlesmn	0:0be0bd219e72	307	#define VL53LX_ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x0080
charlesmn	0:0be0bd219e72	308
charlesmn	0:0be0bd219e72	309	#define VL53LX_SYSTEM__SEQUENCE_CONFIG 0x0081
charlesmn	0:0be0bd219e72	310
charlesmn	0:0be0bd219e72	311	#define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD 0x0082
charlesmn	0:0be0bd219e72	312
charlesmn	0:0be0bd219e72	313	#define VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083
charlesmn	0:0be0bd219e72	314
charlesmn	0:0be0bd219e72	315	#define VL53LX_SYSTEM__STREAM_COUNT_CTRL 0x0084
charlesmn	0:0be0bd219e72	316
charlesmn	0:0be0bd219e72	317	#define VL53LX_FIRMWARE__ENABLE 0x0085
charlesmn	0:0be0bd219e72	318
charlesmn	0:0be0bd219e72	319	#define VL53LX_SYSTEM__INTERRUPT_CLEAR 0x0086
charlesmn	0:0be0bd219e72	320
charlesmn	0:0be0bd219e72	321	#define VL53LX_SYSTEM__MODE_START 0x0087
charlesmn	0:0be0bd219e72	322
charlesmn	0:0be0bd219e72	323	#define VL53LX_RESULT__INTERRUPT_STATUS 0x0088
charlesmn	0:0be0bd219e72	324
charlesmn	0:0be0bd219e72	325	#define VL53LX_RESULT__RANGE_STATUS 0x0089
charlesmn	0:0be0bd219e72	326
charlesmn	0:0be0bd219e72	327	#define VL53LX_RESULT__REPORT_STATUS 0x008A
charlesmn	0:0be0bd219e72	328
charlesmn	0:0be0bd219e72	329	#define VL53LX_RESULT__STREAM_COUNT 0x008B
charlesmn	0:0be0bd219e72	330
charlesmn	0:0be0bd219e72	331	#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x008C
charlesmn	0:0be0bd219e72	332
charlesmn	0:0be0bd219e72	333	#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x008C
charlesmn	0:0be0bd219e72	334
charlesmn	0:0be0bd219e72	335	#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x008D
charlesmn	0:0be0bd219e72	336
charlesmn	0:0be0bd219e72	337	#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x008E
charlesmn	0:0be0bd219e72	338
charlesmn	0:0be0bd219e72	339	#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x008E
charlesmn	0:0be0bd219e72	340
charlesmn	0:0be0bd219e72	341	#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x008F
charlesmn	0:0be0bd219e72	342
charlesmn	0:0be0bd219e72	343	#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0090
charlesmn	0:0be0bd219e72	344
charlesmn	0:0be0bd219e72	345	#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0090
charlesmn	0:0be0bd219e72	346
charlesmn	0:0be0bd219e72	347	#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0091
charlesmn	0:0be0bd219e72	348
charlesmn	0:0be0bd219e72	349	#define VL53LX_RESULT__SIGMA_SD0 0x0092
charlesmn	0:0be0bd219e72	350
charlesmn	0:0be0bd219e72	351	#define VL53LX_RESULT__SIGMA_SD0_HI 0x0092
charlesmn	0:0be0bd219e72	352
charlesmn	0:0be0bd219e72	353	#define VL53LX_RESULT__SIGMA_SD0_LO 0x0093
charlesmn	0:0be0bd219e72	354
charlesmn	0:0be0bd219e72	355	#define VL53LX_RESULT__PHASE_SD0 0x0094
charlesmn	0:0be0bd219e72	356
charlesmn	0:0be0bd219e72	357	#define VL53LX_RESULT__PHASE_SD0_HI 0x0094
charlesmn	0:0be0bd219e72	358
charlesmn	0:0be0bd219e72	359	#define VL53LX_RESULT__PHASE_SD0_LO 0x0095
charlesmn	0:0be0bd219e72	360
charlesmn	0:0be0bd219e72	361	#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096
charlesmn	0:0be0bd219e72	362
charlesmn	0:0be0bd219e72	363	#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0096
charlesmn	0:0be0bd219e72	364
charlesmn	0:0be0bd219e72	365	#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0097
charlesmn	0:0be0bd219e72	366
charlesmn	0:0be0bd219e72	367	#define VL53LX_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0098
charlesmn	0:0be0bd219e72	368
charlesmn	0:0be0bd219e72	369	#define VL53LX__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0098
charlesmn	0:0be0bd219e72	370
charlesmn	0:0be0bd219e72	371	#define VL53LX___PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0099
charlesmn	0:0be0bd219e72	372
charlesmn	0:0be0bd219e72	373	#define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009A
charlesmn	0:0be0bd219e72	374
charlesmn	0:0be0bd219e72	375	#define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009A
charlesmn	0:0be0bd219e72	376
charlesmn	0:0be0bd219e72	377	#define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009B
charlesmn	0:0be0bd219e72	378
charlesmn	0:0be0bd219e72	379	#define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009C
charlesmn	0:0be0bd219e72	380
charlesmn	0:0be0bd219e72	381	#define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009C
charlesmn	0:0be0bd219e72	382
charlesmn	0:0be0bd219e72	383	#define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009D
charlesmn	0:0be0bd219e72	384
charlesmn	0:0be0bd219e72	385	#define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x009E
charlesmn	0:0be0bd219e72	386
charlesmn	0:0be0bd219e72	387	#define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x009E
charlesmn	0:0be0bd219e72	388
charlesmn	0:0be0bd219e72	389	#define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x009F
charlesmn	0:0be0bd219e72	390
charlesmn	0:0be0bd219e72	391	#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x00A0
charlesmn	0:0be0bd219e72	392
charlesmn	0:0be0bd219e72	393	#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x00A0
charlesmn	0:0be0bd219e72	394
charlesmn	0:0be0bd219e72	395	#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x00A1
charlesmn	0:0be0bd219e72	396
charlesmn	0:0be0bd219e72	397	#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x00A2
charlesmn	0:0be0bd219e72	398
charlesmn	0:0be0bd219e72	399	#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x00A2
charlesmn	0:0be0bd219e72	400
charlesmn	0:0be0bd219e72	401	#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x00A3
charlesmn	0:0be0bd219e72	402
charlesmn	0:0be0bd219e72	403	#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x00A4
charlesmn	0:0be0bd219e72	404
charlesmn	0:0be0bd219e72	405	#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x00A4
charlesmn	0:0be0bd219e72	406
charlesmn	0:0be0bd219e72	407	#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x00A5
charlesmn	0:0be0bd219e72	408
charlesmn	0:0be0bd219e72	409	#define VL53LX_RESULT__SIGMA_SD1 0x00A6
charlesmn	0:0be0bd219e72	410
charlesmn	0:0be0bd219e72	411	#define VL53LX_RESULT__SIGMA_SD1_HI 0x00A6
charlesmn	0:0be0bd219e72	412
charlesmn	0:0be0bd219e72	413	#define VL53LX_RESULT__SIGMA_SD1_LO 0x00A7
charlesmn	0:0be0bd219e72	414
charlesmn	0:0be0bd219e72	415	#define VL53LX_RESULT__PHASE_SD1 0x00A8
charlesmn	0:0be0bd219e72	416
charlesmn	0:0be0bd219e72	417	#define VL53LX_RESULT__PHASE_SD1_HI 0x00A8
charlesmn	0:0be0bd219e72	418
charlesmn	0:0be0bd219e72	419	#define VL53LX_RESULT__PHASE_SD1_LO 0x00A9
charlesmn	0:0be0bd219e72	420
charlesmn	0:0be0bd219e72	421	#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x00AA
charlesmn	0:0be0bd219e72	422
charlesmn	0:0be0bd219e72	423	#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x00AA
charlesmn	0:0be0bd219e72	424
charlesmn	0:0be0bd219e72	425	#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x00AB
charlesmn	0:0be0bd219e72	426
charlesmn	0:0be0bd219e72	427	#define VL53LX_RESULT__SPARE_0_SD1 0x00AC
charlesmn	0:0be0bd219e72	428
charlesmn	0:0be0bd219e72	429	#define VL53LX_RESULT__SPARE_0_SD1_HI 0x00AC
charlesmn	0:0be0bd219e72	430
charlesmn	0:0be0bd219e72	431	#define VL53LX_RESULT__SPARE_0_SD1_LO 0x00AD
charlesmn	0:0be0bd219e72	432
charlesmn	0:0be0bd219e72	433	#define VL53LX_RESULT__SPARE_1_SD1 0x00AE
charlesmn	0:0be0bd219e72	434
charlesmn	0:0be0bd219e72	435	#define VL53LX_RESULT__SPARE_1_SD1_HI 0x00AE
charlesmn	0:0be0bd219e72	436
charlesmn	0:0be0bd219e72	437	#define VL53LX_RESULT__SPARE_1_SD1_LO 0x00AF
charlesmn	0:0be0bd219e72	438
charlesmn	0:0be0bd219e72	439	#define VL53LX_RESULT__SPARE_2_SD1 0x00B0
charlesmn	0:0be0bd219e72	440
charlesmn	0:0be0bd219e72	441	#define VL53LX_RESULT__SPARE_2_SD1_HI 0x00B0
charlesmn	0:0be0bd219e72	442
charlesmn	0:0be0bd219e72	443	#define VL53LX_RESULT__SPARE_2_SD1_LO 0x00B1
charlesmn	0:0be0bd219e72	444
charlesmn	0:0be0bd219e72	445	#define VL53LX_RESULT__SPARE_3_SD1 0x00B2
charlesmn	0:0be0bd219e72	446
charlesmn	0:0be0bd219e72	447	#define VL53LX_RESULT__THRESH_INFO 0x00B3
charlesmn	0:0be0bd219e72	448
charlesmn	0:0be0bd219e72	449	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x00B4
charlesmn	0:0be0bd219e72	450
charlesmn	0:0be0bd219e72	451	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x00B4
charlesmn	0:0be0bd219e72	452
charlesmn	0:0be0bd219e72	453	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x00B5
charlesmn	0:0be0bd219e72	454
charlesmn	0:0be0bd219e72	455	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x00B6
charlesmn	0:0be0bd219e72	456
charlesmn	0:0be0bd219e72	457	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x00B7
charlesmn	0:0be0bd219e72	458
charlesmn	0:0be0bd219e72	459	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x00B8
charlesmn	0:0be0bd219e72	460
charlesmn	0:0be0bd219e72	461	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x00B8
charlesmn	0:0be0bd219e72	462
charlesmn	0:0be0bd219e72	463	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x00B9
charlesmn	0:0be0bd219e72	464
charlesmn	0:0be0bd219e72	465	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x00BA
charlesmn	0:0be0bd219e72	466
charlesmn	0:0be0bd219e72	467	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x00BB
charlesmn	0:0be0bd219e72	468
charlesmn	0:0be0bd219e72	469	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x00BC
charlesmn	0:0be0bd219e72	470
charlesmn	0:0be0bd219e72	471	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x00BC
charlesmn	0:0be0bd219e72	472
charlesmn	0:0be0bd219e72	473	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x00BD
charlesmn	0:0be0bd219e72	474
charlesmn	0:0be0bd219e72	475	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x00BE
charlesmn	0:0be0bd219e72	476
charlesmn	0:0be0bd219e72	477	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x00BF
charlesmn	0:0be0bd219e72	478
charlesmn	0:0be0bd219e72	479	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x00C0
charlesmn	0:0be0bd219e72	480
charlesmn	0:0be0bd219e72	481	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x00C0
charlesmn	0:0be0bd219e72	482
charlesmn	0:0be0bd219e72	483	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x00C1
charlesmn	0:0be0bd219e72	484
charlesmn	0:0be0bd219e72	485	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x00C2
charlesmn	0:0be0bd219e72	486
charlesmn	0:0be0bd219e72	487	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x00C3
charlesmn	0:0be0bd219e72	488
charlesmn	0:0be0bd219e72	489	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x00C4
charlesmn	0:0be0bd219e72	490
charlesmn	0:0be0bd219e72	491	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x00C4
charlesmn	0:0be0bd219e72	492
charlesmn	0:0be0bd219e72	493	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x00C5
charlesmn	0:0be0bd219e72	494
charlesmn	0:0be0bd219e72	495	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x00C6
charlesmn	0:0be0bd219e72	496
charlesmn	0:0be0bd219e72	497	#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x00C7
charlesmn	0:0be0bd219e72	498
charlesmn	0:0be0bd219e72	499	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x00C8
charlesmn	0:0be0bd219e72	500
charlesmn	0:0be0bd219e72	501	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x00C8
charlesmn	0:0be0bd219e72	502
charlesmn	0:0be0bd219e72	503	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x00C9
charlesmn	0:0be0bd219e72	504
charlesmn	0:0be0bd219e72	505	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x00CA
charlesmn	0:0be0bd219e72	506
charlesmn	0:0be0bd219e72	507	#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x00CB
charlesmn	0:0be0bd219e72	508
charlesmn	0:0be0bd219e72	509	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x00CC
charlesmn	0:0be0bd219e72	510
charlesmn	0:0be0bd219e72	511	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x00CC
charlesmn	0:0be0bd219e72	512
charlesmn	0:0be0bd219e72	513	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x00CD
charlesmn	0:0be0bd219e72	514
charlesmn	0:0be0bd219e72	515	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x00CE
charlesmn	0:0be0bd219e72	516
charlesmn	0:0be0bd219e72	517	#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x00CF
charlesmn	0:0be0bd219e72	518
charlesmn	0:0be0bd219e72	519	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x00D0
charlesmn	0:0be0bd219e72	520
charlesmn	0:0be0bd219e72	521	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x00D0
charlesmn	0:0be0bd219e72	522
charlesmn	0:0be0bd219e72	523	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x00D1
charlesmn	0:0be0bd219e72	524
charlesmn	0:0be0bd219e72	525	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x00D2
charlesmn	0:0be0bd219e72	526
charlesmn	0:0be0bd219e72	527	#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x00D3
charlesmn	0:0be0bd219e72	528
charlesmn	0:0be0bd219e72	529	#define VL53LX_RESULT_CORE__SPARE_0 0x00D4
charlesmn	0:0be0bd219e72	530
charlesmn	0:0be0bd219e72	531	#define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE 0x00D6
charlesmn	0:0be0bd219e72	532
charlesmn	0:0be0bd219e72	533	#define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x00D6
charlesmn	0:0be0bd219e72	534
charlesmn	0:0be0bd219e72	535	#define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x00D7
charlesmn	0:0be0bd219e72	536
charlesmn	0:0be0bd219e72	537	#define VL53LX_PHASECAL_RESULT__VCSEL_START 0x00D8
charlesmn	0:0be0bd219e72	538
charlesmn	0:0be0bd219e72	539	#define VL53LX_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS 0x00D9
charlesmn	0:0be0bd219e72	540
charlesmn	0:0be0bd219e72	541	#define VL53LX_REF_SPAD_CHAR_RESULT__REF_LOCATION 0x00DA
charlesmn	0:0be0bd219e72	542
charlesmn	0:0be0bd219e72	543	#define VL53LX_VHV_RESULT__COLDBOOT_STATUS 0x00DB
charlesmn	0:0be0bd219e72	544
charlesmn	0:0be0bd219e72	545	#define VL53LX_VHV_RESULT__SEARCH_RESULT 0x00DC
charlesmn	0:0be0bd219e72	546
charlesmn	0:0be0bd219e72	547	#define VL53LX_VHV_RESULT__LATEST_SETTING 0x00DD
charlesmn	0:0be0bd219e72	548
charlesmn	0:0be0bd219e72	549	#define VL53LX_RESULT__OSC_CALIBRATE_VAL 0x00DE
charlesmn	0:0be0bd219e72	550
charlesmn	0:0be0bd219e72	551	#define VL53LX_RESULT__OSC_CALIBRATE_VAL_HI 0x00DE
charlesmn	0:0be0bd219e72	552
charlesmn	0:0be0bd219e72	553	#define VL53LX_RESULT__OSC_CALIBRATE_VAL_LO 0x00DF
charlesmn	0:0be0bd219e72	554
charlesmn	0:0be0bd219e72	555	#define VL53LX_ANA_CONFIG__POWERDOWN_GO1 0x00E0
charlesmn	0:0be0bd219e72	556
charlesmn	0:0be0bd219e72	557	#define VL53LX_ANA_CONFIG__REF_BG_CTRL 0x00E1
charlesmn	0:0be0bd219e72	558
charlesmn	0:0be0bd219e72	559	#define VL53LX_ANA_CONFIG__REGDVDD1V2_CTRL 0x00E2
charlesmn	0:0be0bd219e72	560
charlesmn	0:0be0bd219e72	561	#define VL53LX_ANA_CONFIG__OSC_SLOW_CTRL 0x00E3
charlesmn	0:0be0bd219e72	562
charlesmn	0:0be0bd219e72	563	#define VL53LX_TEST_MODE__STATUS 0x00E4
charlesmn	0:0be0bd219e72	564
charlesmn	0:0be0bd219e72	565	#define VL53LX_FIRMWARE__SYSTEM_STATUS 0x00E5
charlesmn	0:0be0bd219e72	566
charlesmn	0:0be0bd219e72	567	#define VL53LX_FIRMWARE__MODE_STATUS 0x00E6
charlesmn	0:0be0bd219e72	568
charlesmn	0:0be0bd219e72	569	#define VL53LX_FIRMWARE__SECONDARY_MODE_STATUS 0x00E7
charlesmn	0:0be0bd219e72	570
charlesmn	0:0be0bd219e72	571	#define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER 0x00E8
charlesmn	0:0be0bd219e72	572
charlesmn	0:0be0bd219e72	573	#define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI 0x00E8
charlesmn	0:0be0bd219e72	574
charlesmn	0:0be0bd219e72	575	#define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO 0x00E9
charlesmn	0:0be0bd219e72	576
charlesmn	0:0be0bd219e72	577	#define VL53LX_FIRMWARE__HISTOGRAM_BIN 0x00EA
charlesmn	0:0be0bd219e72	578
charlesmn	0:0be0bd219e72	579	#define VL53LX_GPH__SYSTEM__THRESH_HIGH 0x00EC
charlesmn	0:0be0bd219e72	580
charlesmn	0:0be0bd219e72	581	#define VL53LX_GPH__SYSTEM__THRESH_HIGH_HI 0x00EC
charlesmn	0:0be0bd219e72	582
charlesmn	0:0be0bd219e72	583	#define VL53LX_GPH__SYSTEM__THRESH_HIGH_LO 0x00ED
charlesmn	0:0be0bd219e72	584
charlesmn	0:0be0bd219e72	585	#define VL53LX_GPH__SYSTEM__THRESH_LOW 0x00EE
charlesmn	0:0be0bd219e72	586
charlesmn	0:0be0bd219e72	587	#define VL53LX_GPH__SYSTEM__THRESH_LOW_HI 0x00EE
charlesmn	0:0be0bd219e72	588
charlesmn	0:0be0bd219e72	589	#define VL53LX_GPH__SYSTEM__THRESH_LOW_LO 0x00EF
charlesmn	0:0be0bd219e72	590
charlesmn	0:0be0bd219e72	591	#define VL53LX_GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x00F0
charlesmn	0:0be0bd219e72	592
charlesmn	0:0be0bd219e72	593	#define VL53LX_GPH__SPARE_0 0x00F1
charlesmn	0:0be0bd219e72	594
charlesmn	0:0be0bd219e72	595	#define VL53LX_GPH__SD_CONFIG__WOI_SD0 0x00F2
charlesmn	0:0be0bd219e72	596
charlesmn	0:0be0bd219e72	597	#define VL53LX_GPH__SD_CONFIG__WOI_SD1 0x00F3
charlesmn	0:0be0bd219e72	598
charlesmn	0:0be0bd219e72	599	#define VL53LX_GPH__SD_CONFIG__INITIAL_PHASE_SD0 0x00F4
charlesmn	0:0be0bd219e72	600
charlesmn	0:0be0bd219e72	601	#define VL53LX_GPH__SD_CONFIG__INITIAL_PHASE_SD1 0x00F5
charlesmn	0:0be0bd219e72	602
charlesmn	0:0be0bd219e72	603	#define VL53LX_GPH__SD_CONFIG__FIRST_ORDER_SELECT 0x00F6
charlesmn	0:0be0bd219e72	604
charlesmn	0:0be0bd219e72	605	#define VL53LX_GPH__SD_CONFIG__QUANTIFIER 0x00F7
charlesmn	0:0be0bd219e72	606
charlesmn	0:0be0bd219e72	607	#define VL53LX_GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x00F8
charlesmn	0:0be0bd219e72	608
charlesmn	0:0be0bd219e72	609	#define VL53LX_GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9
charlesmn	0:0be0bd219e72	610
charlesmn	0:0be0bd219e72	611	#define VL53LX_GPH__SYSTEM__SEQUENCE_CONFIG 0x00FA
charlesmn	0:0be0bd219e72	612
charlesmn	0:0be0bd219e72	613	#define VL53LX_GPH__GPH_ID 0x00FB
charlesmn	0:0be0bd219e72	614
charlesmn	0:0be0bd219e72	615	#define VL53LX_SYSTEM__INTERRUPT_SET 0x00FC
charlesmn	0:0be0bd219e72	616
charlesmn	0:0be0bd219e72	617	#define VL53LX_INTERRUPT_MANAGER__ENABLES 0x00FD
charlesmn	0:0be0bd219e72	618
charlesmn	0:0be0bd219e72	619	#define VL53LX_INTERRUPT_MANAGER__CLEAR 0x00FE
charlesmn	0:0be0bd219e72	620
charlesmn	0:0be0bd219e72	621	#define VL53LX_INTERRUPT_MANAGER__STATUS 0x00FF
charlesmn	0:0be0bd219e72	622
charlesmn	0:0be0bd219e72	623	#define VL53LX_MCU_TO_HOST_BANK__WR_ACCESS_EN 0x0100
charlesmn	0:0be0bd219e72	624
charlesmn	0:0be0bd219e72	625	#define VL53LX_POWER_MANAGEMENT__GO1_RESET_STATUS 0x0101
charlesmn	0:0be0bd219e72	626
charlesmn	0:0be0bd219e72	627	#define VL53LX_PAD_STARTUP_MODE__VALUE_RO 0x0102
charlesmn	0:0be0bd219e72	628
charlesmn	0:0be0bd219e72	629	#define VL53LX_PAD_STARTUP_MODE__VALUE_CTRL 0x0103
charlesmn	0:0be0bd219e72	630
charlesmn	0:0be0bd219e72	631	#define VL53LX_PLL_PERIOD_US 0x0104
charlesmn	0:0be0bd219e72	632
charlesmn	0:0be0bd219e72	633	#define VL53LX_PLL_PERIOD_US_3 0x0104
charlesmn	0:0be0bd219e72	634
charlesmn	0:0be0bd219e72	635	#define VL53LX_PLL_PERIOD_US_2 0x0105
charlesmn	0:0be0bd219e72	636
charlesmn	0:0be0bd219e72	637	#define VL53LX_PLL_PERIOD_US_1 0x0106
charlesmn	0:0be0bd219e72	638
charlesmn	0:0be0bd219e72	639	#define VL53LX_PLL_PERIOD_US_0 0x0107
charlesmn	0:0be0bd219e72	640
charlesmn	0:0be0bd219e72	641	#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT 0x0108
charlesmn	0:0be0bd219e72	642
charlesmn	0:0be0bd219e72	643	#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_3 0x0108
charlesmn	0:0be0bd219e72	644
charlesmn	0:0be0bd219e72	645	#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_2 0x0109
charlesmn	0:0be0bd219e72	646
charlesmn	0:0be0bd219e72	647	#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_1 0x010A
charlesmn	0:0be0bd219e72	648
charlesmn	0:0be0bd219e72	649	#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_0 0x010B
charlesmn	0:0be0bd219e72	650
charlesmn	0:0be0bd219e72	651	#define VL53LX_NVM_BIST__COMPLETE 0x010C
charlesmn	0:0be0bd219e72	652
charlesmn	0:0be0bd219e72	653	#define VL53LX_NVM_BIST__STATUS 0x010D
charlesmn	0:0be0bd219e72	654
charlesmn	0:0be0bd219e72	655	#define VL53LX_IDENTIFICATION__MODEL_ID 0x010F
charlesmn	0:0be0bd219e72	656
charlesmn	0:0be0bd219e72	657	#define VL53LX_IDENTIFICATION__MODULE_TYPE 0x0110
charlesmn	0:0be0bd219e72	658
charlesmn	0:0be0bd219e72	659	#define VL53LX_IDENTIFICATION__REVISION_ID 0x0111
charlesmn	0:0be0bd219e72	660
charlesmn	0:0be0bd219e72	661	#define VL53LX_IDENTIFICATION__MODULE_ID 0x0112
charlesmn	0:0be0bd219e72	662
charlesmn	0:0be0bd219e72	663	#define VL53LX_IDENTIFICATION__MODULE_ID_HI 0x0112
charlesmn	0:0be0bd219e72	664
charlesmn	0:0be0bd219e72	665	#define VL53LX_IDENTIFICATION__MODULE_ID_LO 0x0113
charlesmn	0:0be0bd219e72	666
charlesmn	0:0be0bd219e72	667	#define VL53LX_ANA_CONFIG__FAST_OSC__TRIM_MAX 0x0114
charlesmn	0:0be0bd219e72	668
charlesmn	0:0be0bd219e72	669	#define VL53LX_ANA_CONFIG__FAST_OSC__FREQ_SET 0x0115
charlesmn	0:0be0bd219e72	670
charlesmn	0:0be0bd219e72	671	#define VL53LX_ANA_CONFIG__VCSEL_TRIM 0x0116
charlesmn	0:0be0bd219e72	672
charlesmn	0:0be0bd219e72	673	#define VL53LX_ANA_CONFIG__VCSEL_SELION 0x0117
charlesmn	0:0be0bd219e72	674
charlesmn	0:0be0bd219e72	675	#define VL53LX_ANA_CONFIG__VCSEL_SELION_MAX 0x0118
charlesmn	0:0be0bd219e72	676
charlesmn	0:0be0bd219e72	677	#define VL53LX_PROTECTED_LASER_SAFETY__LOCK_BIT 0x0119
charlesmn	0:0be0bd219e72	678
charlesmn	0:0be0bd219e72	679	#define VL53LX_LASER_SAFETY__KEY 0x011A
charlesmn	0:0be0bd219e72	680
charlesmn	0:0be0bd219e72	681	#define VL53LX_LASER_SAFETY__KEY_RO 0x011B
charlesmn	0:0be0bd219e72	682
charlesmn	0:0be0bd219e72	683	#define VL53LX_LASER_SAFETY__CLIP 0x011C
charlesmn	0:0be0bd219e72	684
charlesmn	0:0be0bd219e72	685	#define VL53LX_LASER_SAFETY__MULT 0x011D
charlesmn	0:0be0bd219e72	686
charlesmn	0:0be0bd219e72	687	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 0x011E
charlesmn	0:0be0bd219e72	688
charlesmn	0:0be0bd219e72	689	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 0x011F
charlesmn	0:0be0bd219e72	690
charlesmn	0:0be0bd219e72	691	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 0x0120
charlesmn	0:0be0bd219e72	692
charlesmn	0:0be0bd219e72	693	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 0x0121
charlesmn	0:0be0bd219e72	694
charlesmn	0:0be0bd219e72	695	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 0x0122
charlesmn	0:0be0bd219e72	696
charlesmn	0:0be0bd219e72	697	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 0x0123
charlesmn	0:0be0bd219e72	698
charlesmn	0:0be0bd219e72	699	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 0x0124
charlesmn	0:0be0bd219e72	700
charlesmn	0:0be0bd219e72	701	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 0x0125
charlesmn	0:0be0bd219e72	702
charlesmn	0:0be0bd219e72	703	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 0x0126
charlesmn	0:0be0bd219e72	704
charlesmn	0:0be0bd219e72	705	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 0x0127
charlesmn	0:0be0bd219e72	706
charlesmn	0:0be0bd219e72	707	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 0x0128
charlesmn	0:0be0bd219e72	708
charlesmn	0:0be0bd219e72	709	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 0x0129
charlesmn	0:0be0bd219e72	710
charlesmn	0:0be0bd219e72	711	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 0x012A
charlesmn	0:0be0bd219e72	712
charlesmn	0:0be0bd219e72	713	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 0x012B
charlesmn	0:0be0bd219e72	714
charlesmn	0:0be0bd219e72	715	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 0x012C
charlesmn	0:0be0bd219e72	716
charlesmn	0:0be0bd219e72	717	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 0x012D
charlesmn	0:0be0bd219e72	718
charlesmn	0:0be0bd219e72	719	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 0x012E
charlesmn	0:0be0bd219e72	720
charlesmn	0:0be0bd219e72	721	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 0x012F
charlesmn	0:0be0bd219e72	722
charlesmn	0:0be0bd219e72	723	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 0x0130
charlesmn	0:0be0bd219e72	724
charlesmn	0:0be0bd219e72	725	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 0x0131
charlesmn	0:0be0bd219e72	726
charlesmn	0:0be0bd219e72	727	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 0x0132
charlesmn	0:0be0bd219e72	728
charlesmn	0:0be0bd219e72	729	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 0x0133
charlesmn	0:0be0bd219e72	730
charlesmn	0:0be0bd219e72	731	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 0x0134
charlesmn	0:0be0bd219e72	732
charlesmn	0:0be0bd219e72	733	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 0x0135
charlesmn	0:0be0bd219e72	734
charlesmn	0:0be0bd219e72	735	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 0x0136
charlesmn	0:0be0bd219e72	736
charlesmn	0:0be0bd219e72	737	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 0x0137
charlesmn	0:0be0bd219e72	738
charlesmn	0:0be0bd219e72	739	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 0x0138
charlesmn	0:0be0bd219e72	740
charlesmn	0:0be0bd219e72	741	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 0x0139
charlesmn	0:0be0bd219e72	742
charlesmn	0:0be0bd219e72	743	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 0x013A
charlesmn	0:0be0bd219e72	744
charlesmn	0:0be0bd219e72	745	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 0x013B
charlesmn	0:0be0bd219e72	746
charlesmn	0:0be0bd219e72	747	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 0x013C
charlesmn	0:0be0bd219e72	748
charlesmn	0:0be0bd219e72	749	#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 0x013D
charlesmn	0:0be0bd219e72	750
charlesmn	0:0be0bd219e72	751	#define VL53LX_ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x013E
charlesmn	0:0be0bd219e72	752
charlesmn	0:0be0bd219e72	753	#define VL53LX_ROI_CONFIG__MODE_ROI_XY_SIZE 0x013F
charlesmn	0:0be0bd219e72	754
charlesmn	0:0be0bd219e72	755	#define VL53LX_GO2_HOST_BANK_ACCESS__OVERRIDE 0x0300
charlesmn	0:0be0bd219e72	756
charlesmn	0:0be0bd219e72	757	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND 0x0400
charlesmn	0:0be0bd219e72	758
charlesmn	0:0be0bd219e72	759	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 0x0400
charlesmn	0:0be0bd219e72	760
charlesmn	0:0be0bd219e72	761	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 0x0401
charlesmn	0:0be0bd219e72	762
charlesmn	0:0be0bd219e72	763	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 0x0402
charlesmn	0:0be0bd219e72	764
charlesmn	0:0be0bd219e72	765	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 0x0403
charlesmn	0:0be0bd219e72	766
charlesmn	0:0be0bd219e72	767	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER 0x0404
charlesmn	0:0be0bd219e72	768
charlesmn	0:0be0bd219e72	769	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_3 0x0404
charlesmn	0:0be0bd219e72	770
charlesmn	0:0be0bd219e72	771	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_2 0x0405
charlesmn	0:0be0bd219e72	772
charlesmn	0:0be0bd219e72	773	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_1 0x0406
charlesmn	0:0be0bd219e72	774
charlesmn	0:0be0bd219e72	775	#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_0 0x0407
charlesmn	0:0be0bd219e72	776
charlesmn	0:0be0bd219e72	777	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI 0x0408
charlesmn	0:0be0bd219e72	778
charlesmn	0:0be0bd219e72	779	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 0x0408
charlesmn	0:0be0bd219e72	780
charlesmn	0:0be0bd219e72	781	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 0x0409
charlesmn	0:0be0bd219e72	782
charlesmn	0:0be0bd219e72	783	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 0x040A
charlesmn	0:0be0bd219e72	784
charlesmn	0:0be0bd219e72	785	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 0x040B
charlesmn	0:0be0bd219e72	786
charlesmn	0:0be0bd219e72	787	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO 0x040C
charlesmn	0:0be0bd219e72	788
charlesmn	0:0be0bd219e72	789	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 0x040C
charlesmn	0:0be0bd219e72	790
charlesmn	0:0be0bd219e72	791	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 0x040D
charlesmn	0:0be0bd219e72	792
charlesmn	0:0be0bd219e72	793	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 0x040E
charlesmn	0:0be0bd219e72	794
charlesmn	0:0be0bd219e72	795	#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 0x040F
charlesmn	0:0be0bd219e72	796
charlesmn	0:0be0bd219e72	797	#define VL53LX_MCU_UTIL_MULTIPLIER__START 0x0410
charlesmn	0:0be0bd219e72	798
charlesmn	0:0be0bd219e72	799	#define VL53LX_MCU_UTIL_MULTIPLIER__STATUS 0x0411
charlesmn	0:0be0bd219e72	800
charlesmn	0:0be0bd219e72	801	#define VL53LX_MCU_UTIL_DIVIDER__START 0x0412
charlesmn	0:0be0bd219e72	802
charlesmn	0:0be0bd219e72	803	#define VL53LX_MCU_UTIL_DIVIDER__STATUS 0x0413
charlesmn	0:0be0bd219e72	804
charlesmn	0:0be0bd219e72	805	#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND 0x0414
charlesmn	0:0be0bd219e72	806
charlesmn	0:0be0bd219e72	807	#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_3 0x0414
charlesmn	0:0be0bd219e72	808
charlesmn	0:0be0bd219e72	809	#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_2 0x0415
charlesmn	0:0be0bd219e72	810
charlesmn	0:0be0bd219e72	811	#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_1 0x0416
charlesmn	0:0be0bd219e72	812
charlesmn	0:0be0bd219e72	813	#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_0 0x0417
charlesmn	0:0be0bd219e72	814
charlesmn	0:0be0bd219e72	815	#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR 0x0418
charlesmn	0:0be0bd219e72	816
charlesmn	0:0be0bd219e72	817	#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_3 0x0418
charlesmn	0:0be0bd219e72	818
charlesmn	0:0be0bd219e72	819	#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_2 0x0419
charlesmn	0:0be0bd219e72	820
charlesmn	0:0be0bd219e72	821	#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_1 0x041A
charlesmn	0:0be0bd219e72	822
charlesmn	0:0be0bd219e72	823	#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_0 0x041B
charlesmn	0:0be0bd219e72	824
charlesmn	0:0be0bd219e72	825	#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT 0x041C
charlesmn	0:0be0bd219e72	826
charlesmn	0:0be0bd219e72	827	#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_3 0x041C
charlesmn	0:0be0bd219e72	828
charlesmn	0:0be0bd219e72	829	#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_2 0x041D
charlesmn	0:0be0bd219e72	830
charlesmn	0:0be0bd219e72	831	#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_1 0x041E
charlesmn	0:0be0bd219e72	832
charlesmn	0:0be0bd219e72	833	#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_0 0x041F
charlesmn	0:0be0bd219e72	834
charlesmn	0:0be0bd219e72	835	#define VL53LX_TIMER0__VALUE_IN 0x0420
charlesmn	0:0be0bd219e72	836
charlesmn	0:0be0bd219e72	837	#define VL53LX_TIMER0__VALUE_IN_3 0x0420
charlesmn	0:0be0bd219e72	838
charlesmn	0:0be0bd219e72	839	#define VL53LX_TIMER0__VALUE_IN_2 0x0421
charlesmn	0:0be0bd219e72	840
charlesmn	0:0be0bd219e72	841	#define VL53LX_TIMER0__VALUE_IN_1 0x0422
charlesmn	0:0be0bd219e72	842
charlesmn	0:0be0bd219e72	843	#define VL53LX_TIMER0__VALUE_IN_0 0x0423
charlesmn	0:0be0bd219e72	844
charlesmn	0:0be0bd219e72	845	#define VL53LX_TIMER1__VALUE_IN 0x0424
charlesmn	0:0be0bd219e72	846
charlesmn	0:0be0bd219e72	847	#define VL53LX_TIMER1__VALUE_IN_3 0x0424
charlesmn	0:0be0bd219e72	848
charlesmn	0:0be0bd219e72	849	#define VL53LX_TIMER1__VALUE_IN_2 0x0425
charlesmn	0:0be0bd219e72	850
charlesmn	0:0be0bd219e72	851	#define VL53LX_TIMER1__VALUE_IN_1 0x0426
charlesmn	0:0be0bd219e72	852
charlesmn	0:0be0bd219e72	853	#define VL53LX_TIMER1__VALUE_IN_0 0x0427
charlesmn	0:0be0bd219e72	854
charlesmn	0:0be0bd219e72	855	#define VL53LX_TIMER0__CTRL 0x0428
charlesmn	0:0be0bd219e72	856
charlesmn	0:0be0bd219e72	857	#define VL53LX_TIMER1__CTRL 0x0429
charlesmn	0:0be0bd219e72	858
charlesmn	0:0be0bd219e72	859	#define VL53LX_MCU_GENERAL_PURPOSE__GP_0 0x042C
charlesmn	0:0be0bd219e72	860
charlesmn	0:0be0bd219e72	861	#define VL53LX_MCU_GENERAL_PURPOSE__GP_1 0x042D
charlesmn	0:0be0bd219e72	862
charlesmn	0:0be0bd219e72	863	#define VL53LX_MCU_GENERAL_PURPOSE__GP_2 0x042E
charlesmn	0:0be0bd219e72	864
charlesmn	0:0be0bd219e72	865	#define VL53LX_MCU_GENERAL_PURPOSE__GP_3 0x042F
charlesmn	0:0be0bd219e72	866
charlesmn	0:0be0bd219e72	867	#define VL53LX_MCU_RANGE_CALC__CONFIG 0x0430
charlesmn	0:0be0bd219e72	868
charlesmn	0:0be0bd219e72	869	#define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE 0x0432
charlesmn	0:0be0bd219e72	870
charlesmn	0:0be0bd219e72	871	#define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI 0x0432
charlesmn	0:0be0bd219e72	872
charlesmn	0:0be0bd219e72	873	#define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO 0x0433
charlesmn	0:0be0bd219e72	874
charlesmn	0:0be0bd219e72	875	#define VL53LX_MCU_RANGE_CALC__SPARE_4 0x0434
charlesmn	0:0be0bd219e72	876
charlesmn	0:0be0bd219e72	877	#define VL53LX_MCU_RANGE_CALC__SPARE_4_3 0x0434
charlesmn	0:0be0bd219e72	878
charlesmn	0:0be0bd219e72	879	#define VL53LX_MCU_RANGE_CALC__SPARE_4_2 0x0435
charlesmn	0:0be0bd219e72	880
charlesmn	0:0be0bd219e72	881	#define VL53LX_MCU_RANGE_CALC__SPARE_4_1 0x0436
charlesmn	0:0be0bd219e72	882
charlesmn	0:0be0bd219e72	883	#define VL53LX_MCU_RANGE_CALC__SPARE_4_0 0x0437
charlesmn	0:0be0bd219e72	884
charlesmn	0:0be0bd219e72	885	#define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC 0x0438
charlesmn	0:0be0bd219e72	886
charlesmn	0:0be0bd219e72	887	#define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI 0x0438
charlesmn	0:0be0bd219e72	888
charlesmn	0:0be0bd219e72	889	#define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO 0x0439
charlesmn	0:0be0bd219e72	890
charlesmn	0:0be0bd219e72	891	#define VL53LX_MCU_RANGE_CALC__ALGO_VCSEL_PERIOD 0x043C
charlesmn	0:0be0bd219e72	892
charlesmn	0:0be0bd219e72	893	#define VL53LX_MCU_RANGE_CALC__SPARE_5 0x043D
charlesmn	0:0be0bd219e72	894
charlesmn	0:0be0bd219e72	895	#define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS 0x043E
charlesmn	0:0be0bd219e72	896
charlesmn	0:0be0bd219e72	897	#define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI 0x043E
charlesmn	0:0be0bd219e72	898
charlesmn	0:0be0bd219e72	899	#define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO 0x043F
charlesmn	0:0be0bd219e72	900
charlesmn	0:0be0bd219e72	901	#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE 0x0440
charlesmn	0:0be0bd219e72	902
charlesmn	0:0be0bd219e72	903	#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 0x0440
charlesmn	0:0be0bd219e72	904
charlesmn	0:0be0bd219e72	905	#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 0x0441
charlesmn	0:0be0bd219e72	906
charlesmn	0:0be0bd219e72	907	#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 0x0442
charlesmn	0:0be0bd219e72	908
charlesmn	0:0be0bd219e72	909	#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 0x0443
charlesmn	0:0be0bd219e72	910
charlesmn	0:0be0bd219e72	911	#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS 0x0444
charlesmn	0:0be0bd219e72	912
charlesmn	0:0be0bd219e72	913	#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 0x0444
charlesmn	0:0be0bd219e72	914
charlesmn	0:0be0bd219e72	915	#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 0x0445
charlesmn	0:0be0bd219e72	916
charlesmn	0:0be0bd219e72	917	#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 0x0446
charlesmn	0:0be0bd219e72	918
charlesmn	0:0be0bd219e72	919	#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 0x0447
charlesmn	0:0be0bd219e72	920
charlesmn	0:0be0bd219e72	921	#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS 0x0448
charlesmn	0:0be0bd219e72	922
charlesmn	0:0be0bd219e72	923	#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 0x0448
charlesmn	0:0be0bd219e72	924
charlesmn	0:0be0bd219e72	925	#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 0x0449
charlesmn	0:0be0bd219e72	926
charlesmn	0:0be0bd219e72	927	#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 0x044A
charlesmn	0:0be0bd219e72	928
charlesmn	0:0be0bd219e72	929	#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 0x044B
charlesmn	0:0be0bd219e72	930
charlesmn	0:0be0bd219e72	931	#define VL53LX_MCU_RANGE_CALC__SPARE_6 0x044C
charlesmn	0:0be0bd219e72	932
charlesmn	0:0be0bd219e72	933	#define VL53LX_MCU_RANGE_CALC__SPARE_6_HI 0x044C
charlesmn	0:0be0bd219e72	934
charlesmn	0:0be0bd219e72	935	#define VL53LX_MCU_RANGE_CALC__SPARE_6_LO 0x044D
charlesmn	0:0be0bd219e72	936
charlesmn	0:0be0bd219e72	937	#define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD 0x044E
charlesmn	0:0be0bd219e72	938
charlesmn	0:0be0bd219e72	939	#define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI 0x044E
charlesmn	0:0be0bd219e72	940
charlesmn	0:0be0bd219e72	941	#define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO 0x044F
charlesmn	0:0be0bd219e72	942
charlesmn	0:0be0bd219e72	943	#define VL53LX_MCU_RANGE_CALC__NUM_SPADS 0x0450
charlesmn	0:0be0bd219e72	944
charlesmn	0:0be0bd219e72	945	#define VL53LX_MCU_RANGE_CALC__NUM_SPADS_HI 0x0450
charlesmn	0:0be0bd219e72	946
charlesmn	0:0be0bd219e72	947	#define VL53LX_MCU_RANGE_CALC__NUM_SPADS_LO 0x0451
charlesmn	0:0be0bd219e72	948
charlesmn	0:0be0bd219e72	949	#define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT 0x0452
charlesmn	0:0be0bd219e72	950
charlesmn	0:0be0bd219e72	951	#define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT_HI 0x0452
charlesmn	0:0be0bd219e72	952
charlesmn	0:0be0bd219e72	953	#define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT_LO 0x0453
charlesmn	0:0be0bd219e72	954
charlesmn	0:0be0bd219e72	955	#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS 0x0454
charlesmn	0:0be0bd219e72	956
charlesmn	0:0be0bd219e72	957	#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 0x0454
charlesmn	0:0be0bd219e72	958
charlesmn	0:0be0bd219e72	959	#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 0x0455
charlesmn	0:0be0bd219e72	960
charlesmn	0:0be0bd219e72	961	#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 0x0456
charlesmn	0:0be0bd219e72	962
charlesmn	0:0be0bd219e72	963	#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 0x0457
charlesmn	0:0be0bd219e72	964
charlesmn	0:0be0bd219e72	965	#define VL53LX_MCU_RANGE_CALC__SPARE_7 0x0458
charlesmn	0:0be0bd219e72	966
charlesmn	0:0be0bd219e72	967	#define VL53LX_MCU_RANGE_CALC__SPARE_8 0x0459
charlesmn	0:0be0bd219e72	968
charlesmn	0:0be0bd219e72	969	#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS 0x045A
charlesmn	0:0be0bd219e72	970
charlesmn	0:0be0bd219e72	971	#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI 0x045A
charlesmn	0:0be0bd219e72	972
charlesmn	0:0be0bd219e72	973	#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO 0x045B
charlesmn	0:0be0bd219e72	974
charlesmn	0:0be0bd219e72	975	#define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS 0x045C
charlesmn	0:0be0bd219e72	976
charlesmn	0:0be0bd219e72	977	#define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI 0x045C
charlesmn	0:0be0bd219e72	978
charlesmn	0:0be0bd219e72	979	#define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO 0x045D
charlesmn	0:0be0bd219e72	980
charlesmn	0:0be0bd219e72	981	#define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS 0x045E
charlesmn	0:0be0bd219e72	982
charlesmn	0:0be0bd219e72	983	#define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI 0x045E
charlesmn	0:0be0bd219e72	984
charlesmn	0:0be0bd219e72	985	#define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO 0x045F
charlesmn	0:0be0bd219e72	986
charlesmn	0:0be0bd219e72	987	#define VL53LX_MCU_RANGE_CALC__XTALK 0x0460
charlesmn	0:0be0bd219e72	988
charlesmn	0:0be0bd219e72	989	#define VL53LX_MCU_RANGE_CALC__XTALK_HI 0x0460
charlesmn	0:0be0bd219e72	990
charlesmn	0:0be0bd219e72	991	#define VL53LX_MCU_RANGE_CALC__XTALK_LO 0x0461
charlesmn	0:0be0bd219e72	992
charlesmn	0:0be0bd219e72	993	#define VL53LX_MCU_RANGE_CALC__CALC_STATUS 0x0462
charlesmn	0:0be0bd219e72	994
charlesmn	0:0be0bd219e72	995	#define VL53LX_MCU_RANGE_CALC__DEBUG 0x0463
charlesmn	0:0be0bd219e72	996
charlesmn	0:0be0bd219e72	997	#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS 0x0464
charlesmn	0:0be0bd219e72	998
charlesmn	0:0be0bd219e72	999	#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI 0x0464
charlesmn	0:0be0bd219e72	1000
charlesmn	0:0be0bd219e72	1001	#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO 0x0465
charlesmn	0:0be0bd219e72	1002
charlesmn	0:0be0bd219e72	1003	#define VL53LX_MCU_RANGE_CALC__SPARE_0 0x0468
charlesmn	0:0be0bd219e72	1004
charlesmn	0:0be0bd219e72	1005	#define VL53LX_MCU_RANGE_CALC__SPARE_1 0x0469
charlesmn	0:0be0bd219e72	1006
charlesmn	0:0be0bd219e72	1007	#define VL53LX_MCU_RANGE_CALC__SPARE_2 0x046A
charlesmn	0:0be0bd219e72	1008
charlesmn	0:0be0bd219e72	1009	#define VL53LX_MCU_RANGE_CALC__SPARE_3 0x046B
charlesmn	0:0be0bd219e72	1010
charlesmn	0:0be0bd219e72	1011	#define VL53LX_PATCH__CTRL 0x0470
charlesmn	0:0be0bd219e72	1012
charlesmn	0:0be0bd219e72	1013	#define VL53LX_PATCH__JMP_ENABLES 0x0472
charlesmn	0:0be0bd219e72	1014
charlesmn	0:0be0bd219e72	1015	#define VL53LX_PATCH__JMP_ENABLES_HI 0x0472
charlesmn	0:0be0bd219e72	1016
charlesmn	0:0be0bd219e72	1017	#define VL53LX_PATCH__JMP_ENABLES_LO 0x0473
charlesmn	0:0be0bd219e72	1018
charlesmn	0:0be0bd219e72	1019	#define VL53LX_PATCH__DATA_ENABLES 0x0474
charlesmn	0:0be0bd219e72	1020
charlesmn	0:0be0bd219e72	1021	#define VL53LX_PATCH__DATA_ENABLES_HI 0x0474
charlesmn	0:0be0bd219e72	1022
charlesmn	0:0be0bd219e72	1023	#define VL53LX_PATCH__DATA_ENABLES_LO 0x0475
charlesmn	0:0be0bd219e72	1024
charlesmn	0:0be0bd219e72	1025	#define VL53LX_PATCH__OFFSET_0 0x0476
charlesmn	0:0be0bd219e72	1026
charlesmn	0:0be0bd219e72	1027	#define VL53LX_PATCH__OFFSET_0_HI 0x0476
charlesmn	0:0be0bd219e72	1028
charlesmn	0:0be0bd219e72	1029	#define VL53LX_PATCH__OFFSET_0_LO 0x0477
charlesmn	0:0be0bd219e72	1030
charlesmn	0:0be0bd219e72	1031	#define VL53LX_PATCH__OFFSET_1 0x0478
charlesmn	0:0be0bd219e72	1032
charlesmn	0:0be0bd219e72	1033	#define VL53LX_PATCH__OFFSET_1_HI 0x0478
charlesmn	0:0be0bd219e72	1034
charlesmn	0:0be0bd219e72	1035	#define VL53LX_PATCH__OFFSET_1_LO 0x0479
charlesmn	0:0be0bd219e72	1036
charlesmn	0:0be0bd219e72	1037	#define VL53LX_PATCH__OFFSET_2 0x047A
charlesmn	0:0be0bd219e72	1038
charlesmn	0:0be0bd219e72	1039	#define VL53LX_PATCH__OFFSET_2_HI 0x047A
charlesmn	0:0be0bd219e72	1040
charlesmn	0:0be0bd219e72	1041	#define VL53LX_PATCH__OFFSET_2_LO 0x047B
charlesmn	0:0be0bd219e72	1042
charlesmn	0:0be0bd219e72	1043	#define VL53LX_PATCH__OFFSET_3 0x047C
charlesmn	0:0be0bd219e72	1044
charlesmn	0:0be0bd219e72	1045	#define VL53LX_PATCH__OFFSET_3_HI 0x047C
charlesmn	0:0be0bd219e72	1046
charlesmn	0:0be0bd219e72	1047	#define VL53LX_PATCH__OFFSET_3_LO 0x047D
charlesmn	0:0be0bd219e72	1048
charlesmn	0:0be0bd219e72	1049	#define VL53LX_PATCH__OFFSET_4 0x047E
charlesmn	0:0be0bd219e72	1050
charlesmn	0:0be0bd219e72	1051	#define VL53LX_PATCH__OFFSET_4_HI 0x047E
charlesmn	0:0be0bd219e72	1052
charlesmn	0:0be0bd219e72	1053	#define VL53LX_PATCH__OFFSET_4_LO 0x047F
charlesmn	0:0be0bd219e72	1054
charlesmn	0:0be0bd219e72	1055	#define VL53LX_PATCH__OFFSET_5 0x0480
charlesmn	0:0be0bd219e72	1056
charlesmn	0:0be0bd219e72	1057	#define VL53LX_PATCH__OFFSET_5_HI 0x0480
charlesmn	0:0be0bd219e72	1058
charlesmn	0:0be0bd219e72	1059	#define VL53LX_PATCH__OFFSET_5_LO 0x0481
charlesmn	0:0be0bd219e72	1060
charlesmn	0:0be0bd219e72	1061	#define VL53LX_PATCH__OFFSET_6 0x0482
charlesmn	0:0be0bd219e72	1062
charlesmn	0:0be0bd219e72	1063	#define VL53LX_PATCH__OFFSET_6_HI 0x0482
charlesmn	0:0be0bd219e72	1064
charlesmn	0:0be0bd219e72	1065	#define VL53LX_PATCH__OFFSET_6_LO 0x0483
charlesmn	0:0be0bd219e72	1066
charlesmn	0:0be0bd219e72	1067	#define VL53LX_PATCH__OFFSET_7 0x0484
charlesmn	0:0be0bd219e72	1068
charlesmn	0:0be0bd219e72	1069	#define VL53LX_PATCH__OFFSET_7_HI 0x0484
charlesmn	0:0be0bd219e72	1070
charlesmn	0:0be0bd219e72	1071	#define VL53LX_PATCH__OFFSET_7_LO 0x0485
charlesmn	0:0be0bd219e72	1072
charlesmn	0:0be0bd219e72	1073	#define VL53LX_PATCH__OFFSET_8 0x0486
charlesmn	0:0be0bd219e72	1074
charlesmn	0:0be0bd219e72	1075	#define VL53LX_PATCH__OFFSET_8_HI 0x0486
charlesmn	0:0be0bd219e72	1076
charlesmn	0:0be0bd219e72	1077	#define VL53LX_PATCH__OFFSET_8_LO 0x0487
charlesmn	0:0be0bd219e72	1078
charlesmn	0:0be0bd219e72	1079	#define VL53LX_PATCH__OFFSET_9 0x0488
charlesmn	0:0be0bd219e72	1080
charlesmn	0:0be0bd219e72	1081	#define VL53LX_PATCH__OFFSET_9_HI 0x0488
charlesmn	0:0be0bd219e72	1082
charlesmn	0:0be0bd219e72	1083	#define VL53LX_PATCH__OFFSET_9_LO 0x0489
charlesmn	0:0be0bd219e72	1084
charlesmn	0:0be0bd219e72	1085	#define VL53LX_PATCH__OFFSET_10 0x048A
charlesmn	0:0be0bd219e72	1086
charlesmn	0:0be0bd219e72	1087	#define VL53LX_PATCH__OFFSET_10_HI 0x048A
charlesmn	0:0be0bd219e72	1088
charlesmn	0:0be0bd219e72	1089	#define VL53LX_PATCH__OFFSET_10_LO 0x048B
charlesmn	0:0be0bd219e72	1090
charlesmn	0:0be0bd219e72	1091	#define VL53LX_PATCH__OFFSET_11 0x048C
charlesmn	0:0be0bd219e72	1092
charlesmn	0:0be0bd219e72	1093	#define VL53LX_PATCH__OFFSET_11_HI 0x048C
charlesmn	0:0be0bd219e72	1094
charlesmn	0:0be0bd219e72	1095	#define VL53LX_PATCH__OFFSET_11_LO 0x048D
charlesmn	0:0be0bd219e72	1096
charlesmn	0:0be0bd219e72	1097	#define VL53LX_PATCH__OFFSET_12 0x048E
charlesmn	0:0be0bd219e72	1098
charlesmn	0:0be0bd219e72	1099	#define VL53LX_PATCH__OFFSET_12_HI 0x048E
charlesmn	0:0be0bd219e72	1100
charlesmn	0:0be0bd219e72	1101	#define VL53LX_PATCH__OFFSET_12_LO 0x048F
charlesmn	0:0be0bd219e72	1102
charlesmn	0:0be0bd219e72	1103	#define VL53LX_PATCH__OFFSET_13 0x0490
charlesmn	0:0be0bd219e72	1104
charlesmn	0:0be0bd219e72	1105	#define VL53LX_PATCH__OFFSET_13_HI 0x0490
charlesmn	0:0be0bd219e72	1106
charlesmn	0:0be0bd219e72	1107	#define VL53LX_PATCH__OFFSET_13_LO 0x0491
charlesmn	0:0be0bd219e72	1108
charlesmn	0:0be0bd219e72	1109	#define VL53LX_PATCH__OFFSET_14 0x0492
charlesmn	0:0be0bd219e72	1110
charlesmn	0:0be0bd219e72	1111	#define VL53LX_PATCH__OFFSET_14_HI 0x0492
charlesmn	0:0be0bd219e72	1112
charlesmn	0:0be0bd219e72	1113	#define VL53LX_PATCH__OFFSET_14_LO 0x0493
charlesmn	0:0be0bd219e72	1114
charlesmn	0:0be0bd219e72	1115	#define VL53LX_PATCH__OFFSET_15 0x0494
charlesmn	0:0be0bd219e72	1116
charlesmn	0:0be0bd219e72	1117	#define VL53LX_PATCH__OFFSET_15_HI 0x0494
charlesmn	0:0be0bd219e72	1118
charlesmn	0:0be0bd219e72	1119	#define VL53LX_PATCH__OFFSET_15_LO 0x0495
charlesmn	0:0be0bd219e72	1120
charlesmn	0:0be0bd219e72	1121	#define VL53LX_PATCH__ADDRESS_0 0x0496
charlesmn	0:0be0bd219e72	1122
charlesmn	0:0be0bd219e72	1123	#define VL53LX_PATCH__ADDRESS_0_HI 0x0496
charlesmn	0:0be0bd219e72	1124
charlesmn	0:0be0bd219e72	1125	#define VL53LX_PATCH__ADDRESS_0_LO 0x0497
charlesmn	0:0be0bd219e72	1126
charlesmn	0:0be0bd219e72	1127	#define VL53LX_PATCH__ADDRESS_1 0x0498
charlesmn	0:0be0bd219e72	1128
charlesmn	0:0be0bd219e72	1129	#define VL53LX_PATCH__ADDRESS_1_HI 0x0498
charlesmn	0:0be0bd219e72	1130
charlesmn	0:0be0bd219e72	1131	#define VL53LX_PATCH__ADDRESS_1_LO 0x0499
charlesmn	0:0be0bd219e72	1132
charlesmn	0:0be0bd219e72	1133	#define VL53LX_PATCH__ADDRESS_2 0x049A
charlesmn	0:0be0bd219e72	1134
charlesmn	0:0be0bd219e72	1135	#define VL53LX_PATCH__ADDRESS_2_HI 0x049A
charlesmn	0:0be0bd219e72	1136
charlesmn	0:0be0bd219e72	1137	#define VL53LX_PATCH__ADDRESS_2_LO 0x049B
charlesmn	0:0be0bd219e72	1138
charlesmn	0:0be0bd219e72	1139	#define VL53LX_PATCH__ADDRESS_3 0x049C
charlesmn	0:0be0bd219e72	1140
charlesmn	0:0be0bd219e72	1141	#define VL53LX_PATCH__ADDRESS_3_HI 0x049C
charlesmn	0:0be0bd219e72	1142
charlesmn	0:0be0bd219e72	1143	#define VL53LX_PATCH__ADDRESS_3_LO 0x049D
charlesmn	0:0be0bd219e72	1144
charlesmn	0:0be0bd219e72	1145	#define VL53LX_PATCH__ADDRESS_4 0x049E
charlesmn	0:0be0bd219e72	1146
charlesmn	0:0be0bd219e72	1147	#define VL53LX_PATCH__ADDRESS_4_HI 0x049E
charlesmn	0:0be0bd219e72	1148
charlesmn	0:0be0bd219e72	1149	#define VL53LX_PATCH__ADDRESS_4_LO 0x049F
charlesmn	0:0be0bd219e72	1150
charlesmn	0:0be0bd219e72	1151	#define VL53LX_PATCH__ADDRESS_5 0x04A0
charlesmn	0:0be0bd219e72	1152
charlesmn	0:0be0bd219e72	1153	#define VL53LX_PATCH__ADDRESS_5_HI 0x04A0
charlesmn	0:0be0bd219e72	1154
charlesmn	0:0be0bd219e72	1155	#define VL53LX_PATCH__ADDRESS_5_LO 0x04A1
charlesmn	0:0be0bd219e72	1156
charlesmn	0:0be0bd219e72	1157	#define VL53LX_PATCH__ADDRESS_6 0x04A2
charlesmn	0:0be0bd219e72	1158
charlesmn	0:0be0bd219e72	1159	#define VL53LX_PATCH__ADDRESS_6_HI 0x04A2
charlesmn	0:0be0bd219e72	1160
charlesmn	0:0be0bd219e72	1161	#define VL53LX_PATCH__ADDRESS_6_LO 0x04A3
charlesmn	0:0be0bd219e72	1162
charlesmn	0:0be0bd219e72	1163	#define VL53LX_PATCH__ADDRESS_7 0x04A4
charlesmn	0:0be0bd219e72	1164
charlesmn	0:0be0bd219e72	1165	#define VL53LX_PATCH__ADDRESS_7_HI 0x04A4
charlesmn	0:0be0bd219e72	1166
charlesmn	0:0be0bd219e72	1167	#define VL53LX_PATCH__ADDRESS_7_LO 0x04A5
charlesmn	0:0be0bd219e72	1168
charlesmn	0:0be0bd219e72	1169	#define VL53LX_PATCH__ADDRESS_8 0x04A6
charlesmn	0:0be0bd219e72	1170
charlesmn	0:0be0bd219e72	1171	#define VL53LX_PATCH__ADDRESS_8_HI 0x04A6
charlesmn	0:0be0bd219e72	1172
charlesmn	0:0be0bd219e72	1173	#define VL53LX_PATCH__ADDRESS_8_LO 0x04A7
charlesmn	0:0be0bd219e72	1174
charlesmn	0:0be0bd219e72	1175	#define VL53LX_PATCH__ADDRESS_9 0x04A8
charlesmn	0:0be0bd219e72	1176
charlesmn	0:0be0bd219e72	1177	#define VL53LX_PATCH__ADDRESS_9_HI 0x04A8
charlesmn	0:0be0bd219e72	1178
charlesmn	0:0be0bd219e72	1179	#define VL53LX_PATCH__ADDRESS_9_LO 0x04A9
charlesmn	0:0be0bd219e72	1180
charlesmn	0:0be0bd219e72	1181	#define VL53LX_PATCH__ADDRESS_10 0x04AA
charlesmn	0:0be0bd219e72	1182
charlesmn	0:0be0bd219e72	1183	#define VL53LX_PATCH__ADDRESS_10_HI 0x04AA
charlesmn	0:0be0bd219e72	1184
charlesmn	0:0be0bd219e72	1185	#define VL53LX_PATCH__ADDRESS_10_LO 0x04AB
charlesmn	0:0be0bd219e72	1186
charlesmn	0:0be0bd219e72	1187	#define VL53LX_PATCH__ADDRESS_11 0x04AC
charlesmn	0:0be0bd219e72	1188
charlesmn	0:0be0bd219e72	1189	#define VL53LX_PATCH__ADDRESS_11_HI 0x04AC
charlesmn	0:0be0bd219e72	1190
charlesmn	0:0be0bd219e72	1191	#define VL53LX_PATCH__ADDRESS_11_LO 0x04AD
charlesmn	0:0be0bd219e72	1192
charlesmn	0:0be0bd219e72	1193	#define VL53LX_PATCH__ADDRESS_12 0x04AE
charlesmn	0:0be0bd219e72	1194
charlesmn	0:0be0bd219e72	1195	#define VL53LX_PATCH__ADDRESS_12_HI 0x04AE
charlesmn	0:0be0bd219e72	1196
charlesmn	0:0be0bd219e72	1197	#define VL53LX_PATCH__ADDRESS_12_LO 0x04AF
charlesmn	0:0be0bd219e72	1198
charlesmn	0:0be0bd219e72	1199	#define VL53LX_PATCH__ADDRESS_13 0x04B0
charlesmn	0:0be0bd219e72	1200
charlesmn	0:0be0bd219e72	1201	#define VL53LX_PATCH__ADDRESS_13_HI 0x04B0
charlesmn	0:0be0bd219e72	1202
charlesmn	0:0be0bd219e72	1203	#define VL53LX_PATCH__ADDRESS_13_LO 0x04B1
charlesmn	0:0be0bd219e72	1204
charlesmn	0:0be0bd219e72	1205	#define VL53LX_PATCH__ADDRESS_14 0x04B2
charlesmn	0:0be0bd219e72	1206
charlesmn	0:0be0bd219e72	1207	#define VL53LX_PATCH__ADDRESS_14_HI 0x04B2
charlesmn	0:0be0bd219e72	1208
charlesmn	0:0be0bd219e72	1209	#define VL53LX_PATCH__ADDRESS_14_LO 0x04B3
charlesmn	0:0be0bd219e72	1210
charlesmn	0:0be0bd219e72	1211	#define VL53LX_PATCH__ADDRESS_15 0x04B4
charlesmn	0:0be0bd219e72	1212
charlesmn	0:0be0bd219e72	1213	#define VL53LX_PATCH__ADDRESS_15_HI 0x04B4
charlesmn	0:0be0bd219e72	1214
charlesmn	0:0be0bd219e72	1215	#define VL53LX_PATCH__ADDRESS_15_LO 0x04B5
charlesmn	0:0be0bd219e72	1216
charlesmn	0:0be0bd219e72	1217	#define VL53LX_SPI_ASYNC_MUX__CTRL 0x04C0
charlesmn	0:0be0bd219e72	1218
charlesmn	0:0be0bd219e72	1219	#define VL53LX_CLK__CONFIG 0x04C4
charlesmn	0:0be0bd219e72	1220
charlesmn	0:0be0bd219e72	1221	#define VL53LX_GPIO_LV_MUX__CTRL 0x04CC
charlesmn	0:0be0bd219e72	1222
charlesmn	0:0be0bd219e72	1223	#define VL53LX_GPIO_LV_PAD__CTRL 0x04CD
charlesmn	0:0be0bd219e72	1224
charlesmn	0:0be0bd219e72	1225	#define VL53LX_PAD_I2C_LV__CONFIG 0x04D0
charlesmn	0:0be0bd219e72	1226
charlesmn	0:0be0bd219e72	1227	#define VL53LX_PAD_STARTUP_MODE__VALUE_RO_GO1 0x04D4
charlesmn	0:0be0bd219e72	1228
charlesmn	0:0be0bd219e72	1229	#define VL53LX_HOST_IF__STATUS_GO1 0x04D5
charlesmn	0:0be0bd219e72	1230
charlesmn	0:0be0bd219e72	1231	#define VL53LX_MCU_CLK_GATING__CTRL 0x04D8
charlesmn	0:0be0bd219e72	1232
charlesmn	0:0be0bd219e72	1233	#define VL53LX_TEST__BIST_ROM_CTRL 0x04E0
charlesmn	0:0be0bd219e72	1234
charlesmn	0:0be0bd219e72	1235	#define VL53LX_TEST__BIST_ROM_RESULT 0x04E1
charlesmn	0:0be0bd219e72	1236
charlesmn	0:0be0bd219e72	1237	#define VL53LX_TEST__BIST_ROM_MCU_SIG 0x04E2
charlesmn	0:0be0bd219e72	1238
charlesmn	0:0be0bd219e72	1239	#define VL53LX_TEST__BIST_ROM_MCU_SIG_HI 0x04E2
charlesmn	0:0be0bd219e72	1240
charlesmn	0:0be0bd219e72	1241	#define VL53LX_TEST__BIST_ROM_MCU_SIG_LO 0x04E3
charlesmn	0:0be0bd219e72	1242
charlesmn	0:0be0bd219e72	1243	#define VL53LX_TEST__BIST_RAM_CTRL 0x04E4
charlesmn	0:0be0bd219e72	1244
charlesmn	0:0be0bd219e72	1245	#define VL53LX_TEST__BIST_RAM_RESULT 0x04E5
charlesmn	0:0be0bd219e72	1246
charlesmn	0:0be0bd219e72	1247	#define VL53LX_TEST__TMC 0x04E8
charlesmn	0:0be0bd219e72	1248
charlesmn	0:0be0bd219e72	1249	#define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD 0x04F0
charlesmn	0:0be0bd219e72	1250
charlesmn	0:0be0bd219e72	1251	#define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD_HI 0x04F0
charlesmn	0:0be0bd219e72	1252
charlesmn	0:0be0bd219e72	1253	#define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD_LO 0x04F1
charlesmn	0:0be0bd219e72	1254
charlesmn	0:0be0bd219e72	1255	#define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD 0x04F2
charlesmn	0:0be0bd219e72	1256
charlesmn	0:0be0bd219e72	1257	#define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD_HI 0x04F2
charlesmn	0:0be0bd219e72	1258
charlesmn	0:0be0bd219e72	1259	#define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD_LO 0x04F3
charlesmn	0:0be0bd219e72	1260
charlesmn	0:0be0bd219e72	1261	#define VL53LX_TEST__PLL_BIST_COUNT_OUT 0x04F4
charlesmn	0:0be0bd219e72	1262
charlesmn	0:0be0bd219e72	1263	#define VL53LX_TEST__PLL_BIST_COUNT_OUT_HI 0x04F4
charlesmn	0:0be0bd219e72	1264
charlesmn	0:0be0bd219e72	1265	#define VL53LX_TEST__PLL_BIST_COUNT_OUT_LO 0x04F5
charlesmn	0:0be0bd219e72	1266
charlesmn	0:0be0bd219e72	1267	#define VL53LX_TEST__PLL_BIST_GONOGO 0x04F6
charlesmn	0:0be0bd219e72	1268
charlesmn	0:0be0bd219e72	1269	#define VL53LX_TEST__PLL_BIST_CTRL 0x04F7
charlesmn	0:0be0bd219e72	1270
charlesmn	0:0be0bd219e72	1271	#define VL53LX_RANGING_CORE__DEVICE_ID 0x0680
charlesmn	0:0be0bd219e72	1272
charlesmn	0:0be0bd219e72	1273	#define VL53LX_RANGING_CORE__REVISION_ID 0x0681
charlesmn	0:0be0bd219e72	1274
charlesmn	0:0be0bd219e72	1275	#define VL53LX_RANGING_CORE__CLK_CTRL1 0x0683
charlesmn	0:0be0bd219e72	1276
charlesmn	0:0be0bd219e72	1277	#define VL53LX_RANGING_CORE__CLK_CTRL2 0x0684
charlesmn	0:0be0bd219e72	1278
charlesmn	0:0be0bd219e72	1279	#define VL53LX_RANGING_CORE__WOI_1 0x0685
charlesmn	0:0be0bd219e72	1280
charlesmn	0:0be0bd219e72	1281	#define VL53LX_RANGING_CORE__WOI_REF_1 0x0686
charlesmn	0:0be0bd219e72	1282
charlesmn	0:0be0bd219e72	1283	#define VL53LX_RANGING_CORE__START_RANGING 0x0687
charlesmn	0:0be0bd219e72	1284
charlesmn	0:0be0bd219e72	1285	#define VL53LX_RANGING_CORE__LOW_LIMIT_1 0x0690
charlesmn	0:0be0bd219e72	1286
charlesmn	0:0be0bd219e72	1287	#define VL53LX_RANGING_CORE__HIGH_LIMIT_1 0x0691
charlesmn	0:0be0bd219e72	1288
charlesmn	0:0be0bd219e72	1289	#define VL53LX_RANGING_CORE__LOW_LIMIT_REF_1 0x0692
charlesmn	0:0be0bd219e72	1290
charlesmn	0:0be0bd219e72	1291	#define VL53LX_RANGING_CORE__HIGH_LIMIT_REF_1 0x0693
charlesmn	0:0be0bd219e72	1292
charlesmn	0:0be0bd219e72	1293	#define VL53LX_RANGING_CORE__QUANTIFIER_1_MSB 0x0694
charlesmn	0:0be0bd219e72	1294
charlesmn	0:0be0bd219e72	1295	#define VL53LX_RANGING_CORE__QUANTIFIER_1_LSB 0x0695
charlesmn	0:0be0bd219e72	1296
charlesmn	0:0be0bd219e72	1297	#define VL53LX_RANGING_CORE__QUANTIFIER_REF_1_MSB 0x0696
charlesmn	0:0be0bd219e72	1298
charlesmn	0:0be0bd219e72	1299	#define VL53LX_RANGING_CORE__QUANTIFIER_REF_1_LSB 0x0697
charlesmn	0:0be0bd219e72	1300
charlesmn	0:0be0bd219e72	1301	#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_1_MSB 0x0698
charlesmn	0:0be0bd219e72	1302
charlesmn	0:0be0bd219e72	1303	#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_1_LSB 0x0699
charlesmn	0:0be0bd219e72	1304
charlesmn	0:0be0bd219e72	1305	#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB 0x069A
charlesmn	0:0be0bd219e72	1306
charlesmn	0:0be0bd219e72	1307	#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB 0x069B
charlesmn	0:0be0bd219e72	1308
charlesmn	0:0be0bd219e72	1309	#define VL53LX_RANGING_CORE__FILTER_STRENGTH_1 0x069C
charlesmn	0:0be0bd219e72	1310
charlesmn	0:0be0bd219e72	1311	#define VL53LX_RANGING_CORE__FILTER_STRENGTH_REF_1 0x069D
charlesmn	0:0be0bd219e72	1312
charlesmn	0:0be0bd219e72	1313	#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB 0x069E
charlesmn	0:0be0bd219e72	1314
charlesmn	0:0be0bd219e72	1315	#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB 0x069F
charlesmn	0:0be0bd219e72	1316
charlesmn	0:0be0bd219e72	1317	#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB 0x06A0
charlesmn	0:0be0bd219e72	1318
charlesmn	0:0be0bd219e72	1319	#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB 0x06A1
charlesmn	0:0be0bd219e72	1320
charlesmn	0:0be0bd219e72	1321	#define VL53LX_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB 0x06A4
charlesmn	0:0be0bd219e72	1322
charlesmn	0:0be0bd219e72	1323	#define VL53LX_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB 0x06A5
charlesmn	0:0be0bd219e72	1324
charlesmn	0:0be0bd219e72	1325	#define VL53LX_RANGING_CORE__INVERT_HW 0x06A6
charlesmn	0:0be0bd219e72	1326
charlesmn	0:0be0bd219e72	1327	#define VL53LX_RANGING_CORE__FORCE_HW 0x06A7
charlesmn	0:0be0bd219e72	1328
charlesmn	0:0be0bd219e72	1329	#define VL53LX_RANGING_CORE__STATIC_HW_VALUE 0x06A8
charlesmn	0:0be0bd219e72	1330
charlesmn	0:0be0bd219e72	1331	#define VL53LX_RANGING_CORE__FORCE_CONTINUOUS_AMBIENT 0x06A9
charlesmn	0:0be0bd219e72	1332
charlesmn	0:0be0bd219e72	1333	#define VL53LX_RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER 0x06AA
charlesmn	0:0be0bd219e72	1334
charlesmn	0:0be0bd219e72	1335	#define VL53LX_RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN 0x06AB
charlesmn	0:0be0bd219e72	1336
charlesmn	0:0be0bd219e72	1337	#define VL53LX_RANGING_CORE__INITIAL_PHASE_VALUE_1 0x06AC
charlesmn	0:0be0bd219e72	1338
charlesmn	0:0be0bd219e72	1339	#define VL53LX_RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 0x06AD
charlesmn	0:0be0bd219e72	1340
charlesmn	0:0be0bd219e72	1341	#define VL53LX_RANGING_CORE__FORCE_UP_IN 0x06AE
charlesmn	0:0be0bd219e72	1342
charlesmn	0:0be0bd219e72	1343	#define VL53LX_RANGING_CORE__FORCE_DN_IN 0x06AF
charlesmn	0:0be0bd219e72	1344
charlesmn	0:0be0bd219e72	1345	#define VL53LX_RANGING_CORE__STATIC_UP_VALUE_1 0x06B0
charlesmn	0:0be0bd219e72	1346
charlesmn	0:0be0bd219e72	1347	#define VL53LX_RANGING_CORE__STATIC_UP_VALUE_REF_1 0x06B1
charlesmn	0:0be0bd219e72	1348
charlesmn	0:0be0bd219e72	1349	#define VL53LX_RANGING_CORE__STATIC_DN_VALUE_1 0x06B2
charlesmn	0:0be0bd219e72	1350
charlesmn	0:0be0bd219e72	1351	#define VL53LX_RANGING_CORE__STATIC_DN_VALUE_REF_1 0x06B3
charlesmn	0:0be0bd219e72	1352
charlesmn	0:0be0bd219e72	1353	#define VL53LX_RANGING_CORE__MONITOR_UP_DN 0x06B4
charlesmn	0:0be0bd219e72	1354
charlesmn	0:0be0bd219e72	1355	#define VL53LX_RANGING_CORE__INVERT_UP_DN 0x06B5
charlesmn	0:0be0bd219e72	1356
charlesmn	0:0be0bd219e72	1357	#define VL53LX_RANGING_CORE__CPUMP_1 0x06B6
charlesmn	0:0be0bd219e72	1358
charlesmn	0:0be0bd219e72	1359	#define VL53LX_RANGING_CORE__CPUMP_2 0x06B7
charlesmn	0:0be0bd219e72	1360
charlesmn	0:0be0bd219e72	1361	#define VL53LX_RANGING_CORE__CPUMP_3 0x06B8
charlesmn	0:0be0bd219e72	1362
charlesmn	0:0be0bd219e72	1363	#define VL53LX_RANGING_CORE__OSC_1 0x06B9
charlesmn	0:0be0bd219e72	1364
charlesmn	0:0be0bd219e72	1365	#define VL53LX_RANGING_CORE__PLL_1 0x06BB
charlesmn	0:0be0bd219e72	1366
charlesmn	0:0be0bd219e72	1367	#define VL53LX_RANGING_CORE__PLL_2 0x06BC
charlesmn	0:0be0bd219e72	1368
charlesmn	0:0be0bd219e72	1369	#define VL53LX_RANGING_CORE__REFERENCE_1 0x06BD
charlesmn	0:0be0bd219e72	1370
charlesmn	0:0be0bd219e72	1371	#define VL53LX_RANGING_CORE__REFERENCE_3 0x06BF
charlesmn	0:0be0bd219e72	1372
charlesmn	0:0be0bd219e72	1373	#define VL53LX_RANGING_CORE__REFERENCE_4 0x06C0
charlesmn	0:0be0bd219e72	1374
charlesmn	0:0be0bd219e72	1375	#define VL53LX_RANGING_CORE__REFERENCE_5 0x06C1
charlesmn	0:0be0bd219e72	1376
charlesmn	0:0be0bd219e72	1377	#define VL53LX_RANGING_CORE__REGAVDD1V2 0x06C3
charlesmn	0:0be0bd219e72	1378
charlesmn	0:0be0bd219e72	1379	#define VL53LX_RANGING_CORE__CALIB_1 0x06C4
charlesmn	0:0be0bd219e72	1380
charlesmn	0:0be0bd219e72	1381	#define VL53LX_RANGING_CORE__CALIB_2 0x06C5
charlesmn	0:0be0bd219e72	1382
charlesmn	0:0be0bd219e72	1383	#define VL53LX_RANGING_CORE__CALIB_3 0x06C6
charlesmn	0:0be0bd219e72	1384
charlesmn	0:0be0bd219e72	1385	#define VL53LX_RANGING_CORE__TST_MUX_SEL1 0x06C9
charlesmn	0:0be0bd219e72	1386
charlesmn	0:0be0bd219e72	1387	#define VL53LX_RANGING_CORE__TST_MUX_SEL2 0x06CA
charlesmn	0:0be0bd219e72	1388
charlesmn	0:0be0bd219e72	1389	#define VL53LX_RANGING_CORE__TST_MUX 0x06CB
charlesmn	0:0be0bd219e72	1390
charlesmn	0:0be0bd219e72	1391	#define VL53LX_RANGING_CORE__GPIO_OUT_TESTMUX 0x06CC
charlesmn	0:0be0bd219e72	1392
charlesmn	0:0be0bd219e72	1393	#define VL53LX_RANGING_CORE__CUSTOM_FE 0x06CD
charlesmn	0:0be0bd219e72	1394
charlesmn	0:0be0bd219e72	1395	#define VL53LX_RANGING_CORE__CUSTOM_FE_2 0x06CE
charlesmn	0:0be0bd219e72	1396
charlesmn	0:0be0bd219e72	1397	#define VL53LX_RANGING_CORE__SPAD_READOUT 0x06CF
charlesmn	0:0be0bd219e72	1398
charlesmn	0:0be0bd219e72	1399	#define VL53LX_RANGING_CORE__SPAD_READOUT_1 0x06D0
charlesmn	0:0be0bd219e72	1400
charlesmn	0:0be0bd219e72	1401	#define VL53LX_RANGING_CORE__SPAD_READOUT_2 0x06D1
charlesmn	0:0be0bd219e72	1402
charlesmn	0:0be0bd219e72	1403	#define VL53LX_RANGING_CORE__SPAD_PS 0x06D2
charlesmn	0:0be0bd219e72	1404
charlesmn	0:0be0bd219e72	1405	#define VL53LX_RANGING_CORE__LASER_SAFETY_2 0x06D4
charlesmn	0:0be0bd219e72	1406
charlesmn	0:0be0bd219e72	1407	#define VL53LX_RANGING_CORE__NVM_CTRL__MODE 0x0780
charlesmn	0:0be0bd219e72	1408
charlesmn	0:0be0bd219e72	1409	#define VL53LX_RANGING_CORE__NVM_CTRL__PDN 0x0781
charlesmn	0:0be0bd219e72	1410
charlesmn	0:0be0bd219e72	1411	#define VL53LX_RANGING_CORE__NVM_CTRL__PROGN 0x0782
charlesmn	0:0be0bd219e72	1412
charlesmn	0:0be0bd219e72	1413	#define VL53LX_RANGING_CORE__NVM_CTRL__READN 0x0783
charlesmn	0:0be0bd219e72	1414
charlesmn	0:0be0bd219e72	1415	#define VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB 0x0784
charlesmn	0:0be0bd219e72	1416
charlesmn	0:0be0bd219e72	1417	#define VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB 0x0785
charlesmn	0:0be0bd219e72	1418
charlesmn	0:0be0bd219e72	1419	#define VL53LX_RANGING_CORE__NVM_CTRL__HV_RISE_MSB 0x0786
charlesmn	0:0be0bd219e72	1420
charlesmn	0:0be0bd219e72	1421	#define VL53LX_RANGING_CORE__NVM_CTRL__HV_RISE_LSB 0x0787
charlesmn	0:0be0bd219e72	1422
charlesmn	0:0be0bd219e72	1423	#define VL53LX_RANGING_CORE__NVM_CTRL__HV_FALL_MSB 0x0788
charlesmn	0:0be0bd219e72	1424
charlesmn	0:0be0bd219e72	1425	#define VL53LX_RANGING_CORE__NVM_CTRL__HV_FALL_LSB 0x0789
charlesmn	0:0be0bd219e72	1426
charlesmn	0:0be0bd219e72	1427	#define VL53LX_RANGING_CORE__NVM_CTRL__TST 0x078A
charlesmn	0:0be0bd219e72	1428
charlesmn	0:0be0bd219e72	1429	#define VL53LX_RANGING_CORE__NVM_CTRL__TESTREAD 0x078B
charlesmn	0:0be0bd219e72	1430
charlesmn	0:0be0bd219e72	1431	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_MMM 0x078C
charlesmn	0:0be0bd219e72	1432
charlesmn	0:0be0bd219e72	1433	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LMM 0x078D
charlesmn	0:0be0bd219e72	1434
charlesmn	0:0be0bd219e72	1435	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LLM 0x078E
charlesmn	0:0be0bd219e72	1436
charlesmn	0:0be0bd219e72	1437	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LLL 0x078F
charlesmn	0:0be0bd219e72	1438
charlesmn	0:0be0bd219e72	1439	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_MMM 0x0790
charlesmn	0:0be0bd219e72	1440
charlesmn	0:0be0bd219e72	1441	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LMM 0x0791
charlesmn	0:0be0bd219e72	1442
charlesmn	0:0be0bd219e72	1443	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LLM 0x0792
charlesmn	0:0be0bd219e72	1444
charlesmn	0:0be0bd219e72	1445	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LLL 0x0793
charlesmn	0:0be0bd219e72	1446
charlesmn	0:0be0bd219e72	1447	#define VL53LX_RANGING_CORE__NVM_CTRL__ADDR 0x0794
charlesmn	0:0be0bd219e72	1448
charlesmn	0:0be0bd219e72	1449	#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_ECC 0x0795
charlesmn	0:0be0bd219e72	1450
charlesmn	0:0be0bd219e72	1451	#define VL53LX_RANGING_CORE__RET_SPAD_EN_0 0x0796
charlesmn	0:0be0bd219e72	1452
charlesmn	0:0be0bd219e72	1453	#define VL53LX_RANGING_CORE__RET_SPAD_EN_1 0x0797
charlesmn	0:0be0bd219e72	1454
charlesmn	0:0be0bd219e72	1455	#define VL53LX_RANGING_CORE__RET_SPAD_EN_2 0x0798
charlesmn	0:0be0bd219e72	1456
charlesmn	0:0be0bd219e72	1457	#define VL53LX_RANGING_CORE__RET_SPAD_EN_3 0x0799
charlesmn	0:0be0bd219e72	1458
charlesmn	0:0be0bd219e72	1459	#define VL53LX_RANGING_CORE__RET_SPAD_EN_4 0x079A
charlesmn	0:0be0bd219e72	1460
charlesmn	0:0be0bd219e72	1461	#define VL53LX_RANGING_CORE__RET_SPAD_EN_5 0x079B
charlesmn	0:0be0bd219e72	1462
charlesmn	0:0be0bd219e72	1463	#define VL53LX_RANGING_CORE__RET_SPAD_EN_6 0x079C
charlesmn	0:0be0bd219e72	1464
charlesmn	0:0be0bd219e72	1465	#define VL53LX_RANGING_CORE__RET_SPAD_EN_7 0x079D
charlesmn	0:0be0bd219e72	1466
charlesmn	0:0be0bd219e72	1467	#define VL53LX_RANGING_CORE__RET_SPAD_EN_8 0x079E
charlesmn	0:0be0bd219e72	1468
charlesmn	0:0be0bd219e72	1469	#define VL53LX_RANGING_CORE__RET_SPAD_EN_9 0x079F
charlesmn	0:0be0bd219e72	1470
charlesmn	0:0be0bd219e72	1471	#define VL53LX_RANGING_CORE__RET_SPAD_EN_10 0x07A0
charlesmn	0:0be0bd219e72	1472
charlesmn	0:0be0bd219e72	1473	#define VL53LX_RANGING_CORE__RET_SPAD_EN_11 0x07A1
charlesmn	0:0be0bd219e72	1474
charlesmn	0:0be0bd219e72	1475	#define VL53LX_RANGING_CORE__RET_SPAD_EN_12 0x07A2
charlesmn	0:0be0bd219e72	1476
charlesmn	0:0be0bd219e72	1477	#define VL53LX_RANGING_CORE__RET_SPAD_EN_13 0x07A3
charlesmn	0:0be0bd219e72	1478
charlesmn	0:0be0bd219e72	1479	#define VL53LX_RANGING_CORE__RET_SPAD_EN_14 0x07A4
charlesmn	0:0be0bd219e72	1480
charlesmn	0:0be0bd219e72	1481	#define VL53LX_RANGING_CORE__RET_SPAD_EN_15 0x07A5
charlesmn	0:0be0bd219e72	1482
charlesmn	0:0be0bd219e72	1483	#define VL53LX_RANGING_CORE__RET_SPAD_EN_16 0x07A6
charlesmn	0:0be0bd219e72	1484
charlesmn	0:0be0bd219e72	1485	#define VL53LX_RANGING_CORE__RET_SPAD_EN_17 0x07A7
charlesmn	0:0be0bd219e72	1486
charlesmn	0:0be0bd219e72	1487	#define VL53LX_RANGING_CORE__SPAD_SHIFT_EN 0x07BA
charlesmn	0:0be0bd219e72	1488
charlesmn	0:0be0bd219e72	1489	#define VL53LX_RANGING_CORE__SPAD_DISABLE_CTRL 0x07BB
charlesmn	0:0be0bd219e72	1490
charlesmn	0:0be0bd219e72	1491	#define VL53LX_RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG 0x07BC
charlesmn	0:0be0bd219e72	1492
charlesmn	0:0be0bd219e72	1493	#define VL53LX_RANGING_CORE__SPI_MODE 0x07BD
charlesmn	0:0be0bd219e72	1494
charlesmn	0:0be0bd219e72	1495	#define VL53LX_RANGING_CORE__GPIO_DIR 0x07BE
charlesmn	0:0be0bd219e72	1496
charlesmn	0:0be0bd219e72	1497	#define VL53LX_RANGING_CORE__VCSEL_PERIOD 0x0880
charlesmn	0:0be0bd219e72	1498
charlesmn	0:0be0bd219e72	1499	#define VL53LX_RANGING_CORE__VCSEL_START 0x0881
charlesmn	0:0be0bd219e72	1500
charlesmn	0:0be0bd219e72	1501	#define VL53LX_RANGING_CORE__VCSEL_STOP 0x0882
charlesmn	0:0be0bd219e72	1502
charlesmn	0:0be0bd219e72	1503	#define VL53LX_RANGING_CORE__VCSEL_1 0x0885
charlesmn	0:0be0bd219e72	1504
charlesmn	0:0be0bd219e72	1505	#define VL53LX_RANGING_CORE__VCSEL_STATUS 0x088D
charlesmn	0:0be0bd219e72	1506
charlesmn	0:0be0bd219e72	1507	#define VL53LX_RANGING_CORE__STATUS 0x0980
charlesmn	0:0be0bd219e72	1508
charlesmn	0:0be0bd219e72	1509	#define VL53LX_RANGING_CORE__LASER_CONTINUITY_STATE 0x0981
charlesmn	0:0be0bd219e72	1510
charlesmn	0:0be0bd219e72	1511	#define VL53LX_RANGING_CORE__RANGE_1_MMM 0x0982
charlesmn	0:0be0bd219e72	1512
charlesmn	0:0be0bd219e72	1513	#define VL53LX_RANGING_CORE__RANGE_1_LMM 0x0983
charlesmn	0:0be0bd219e72	1514
charlesmn	0:0be0bd219e72	1515	#define VL53LX_RANGING_CORE__RANGE_1_LLM 0x0984
charlesmn	0:0be0bd219e72	1516
charlesmn	0:0be0bd219e72	1517	#define VL53LX_RANGING_CORE__RANGE_1_LLL 0x0985
charlesmn	0:0be0bd219e72	1518
charlesmn	0:0be0bd219e72	1519	#define VL53LX_RANGING_CORE__RANGE_REF_1_MMM 0x0986
charlesmn	0:0be0bd219e72	1520
charlesmn	0:0be0bd219e72	1521	#define VL53LX_RANGING_CORE__RANGE_REF_1_LMM 0x0987
charlesmn	0:0be0bd219e72	1522
charlesmn	0:0be0bd219e72	1523	#define VL53LX_RANGING_CORE__RANGE_REF_1_LLM 0x0988
charlesmn	0:0be0bd219e72	1524
charlesmn	0:0be0bd219e72	1525	#define VL53LX_RANGING_CORE__RANGE_REF_1_LLL 0x0989
charlesmn	0:0be0bd219e72	1526
charlesmn	0:0be0bd219e72	1527	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM 0x098A
charlesmn	0:0be0bd219e72	1528
charlesmn	0:0be0bd219e72	1529	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM 0x098B
charlesmn	0:0be0bd219e72	1530
charlesmn	0:0be0bd219e72	1531	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM 0x098C
charlesmn	0:0be0bd219e72	1532
charlesmn	0:0be0bd219e72	1533	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL 0x098D
charlesmn	0:0be0bd219e72	1534
charlesmn	0:0be0bd219e72	1535	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM 0x098E
charlesmn	0:0be0bd219e72	1536
charlesmn	0:0be0bd219e72	1537	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM 0x098F
charlesmn	0:0be0bd219e72	1538
charlesmn	0:0be0bd219e72	1539	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM 0x0990
charlesmn	0:0be0bd219e72	1540
charlesmn	0:0be0bd219e72	1541	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL 0x0991
charlesmn	0:0be0bd219e72	1542
charlesmn	0:0be0bd219e72	1543	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM 0x0992
charlesmn	0:0be0bd219e72	1544
charlesmn	0:0be0bd219e72	1545	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM 0x0993
charlesmn	0:0be0bd219e72	1546
charlesmn	0:0be0bd219e72	1547	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM 0x0994
charlesmn	0:0be0bd219e72	1548
charlesmn	0:0be0bd219e72	1549	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL 0x0995
charlesmn	0:0be0bd219e72	1550
charlesmn	0:0be0bd219e72	1551	#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM 0x0996
charlesmn	0:0be0bd219e72	1552
charlesmn	0:0be0bd219e72	1553	#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM 0x0997
charlesmn	0:0be0bd219e72	1554
charlesmn	0:0be0bd219e72	1555	#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL 0x0998
charlesmn	0:0be0bd219e72	1556
charlesmn	0:0be0bd219e72	1557	#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_MM 0x0999
charlesmn	0:0be0bd219e72	1558
charlesmn	0:0be0bd219e72	1559	#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_LM 0x099A
charlesmn	0:0be0bd219e72	1560
charlesmn	0:0be0bd219e72	1561	#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_LL 0x099B
charlesmn	0:0be0bd219e72	1562
charlesmn	0:0be0bd219e72	1563	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM 0x099C
charlesmn	0:0be0bd219e72	1564
charlesmn	0:0be0bd219e72	1565	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM 0x099D
charlesmn	0:0be0bd219e72	1566
charlesmn	0:0be0bd219e72	1567	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM 0x099E
charlesmn	0:0be0bd219e72	1568
charlesmn	0:0be0bd219e72	1569	#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL 0x099F
charlesmn	0:0be0bd219e72	1570
charlesmn	0:0be0bd219e72	1571	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM 0x09A0
charlesmn	0:0be0bd219e72	1572
charlesmn	0:0be0bd219e72	1573	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM 0x09A1
charlesmn	0:0be0bd219e72	1574
charlesmn	0:0be0bd219e72	1575	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM 0x09A2
charlesmn	0:0be0bd219e72	1576
charlesmn	0:0be0bd219e72	1577	#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL 0x09A3
charlesmn	0:0be0bd219e72	1578
charlesmn	0:0be0bd219e72	1579	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM 0x09A4
charlesmn	0:0be0bd219e72	1580
charlesmn	0:0be0bd219e72	1581	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM 0x09A5
charlesmn	0:0be0bd219e72	1582
charlesmn	0:0be0bd219e72	1583	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM 0x09A6
charlesmn	0:0be0bd219e72	1584
charlesmn	0:0be0bd219e72	1585	#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL 0x09A7
charlesmn	0:0be0bd219e72	1586
charlesmn	0:0be0bd219e72	1587	#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM 0x09A8
charlesmn	0:0be0bd219e72	1588
charlesmn	0:0be0bd219e72	1589	#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM 0x09A9
charlesmn	0:0be0bd219e72	1590
charlesmn	0:0be0bd219e72	1591	#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL 0x09AA
charlesmn	0:0be0bd219e72	1592
charlesmn	0:0be0bd219e72	1593	#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_MM 0x09AB
charlesmn	0:0be0bd219e72	1594
charlesmn	0:0be0bd219e72	1595	#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_LM 0x09AC
charlesmn	0:0be0bd219e72	1596
charlesmn	0:0be0bd219e72	1597	#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_LL 0x09AD
charlesmn	0:0be0bd219e72	1598
charlesmn	0:0be0bd219e72	1599	#define VL53LX_RANGING_CORE__GPIO_CONFIG__A0 0x0A00
charlesmn	0:0be0bd219e72	1600
charlesmn	0:0be0bd219e72	1601	#define VL53LX_RANGING_CORE__RESET_CONTROL__A0 0x0A01
charlesmn	0:0be0bd219e72	1602
charlesmn	0:0be0bd219e72	1603	#define VL53LX_RANGING_CORE__INTR_MANAGER__A0 0x0A02
charlesmn	0:0be0bd219e72	1604
charlesmn	0:0be0bd219e72	1605	#define VL53LX_RANGING_CORE__POWER_FSM_TIME_OSC__A0 0x0A06
charlesmn	0:0be0bd219e72	1606
charlesmn	0:0be0bd219e72	1607	#define VL53LX_RANGING_CORE__VCSEL_ATEST__A0 0x0A07
charlesmn	0:0be0bd219e72	1608
charlesmn	0:0be0bd219e72	1609	#define VL53LX_RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 0x0A08
charlesmn	0:0be0bd219e72	1610
charlesmn	0:0be0bd219e72	1611	#define VL53LX_RANGING_CORE__VCSEL_STOP_CLIPPED__A0 0x0A09
charlesmn	0:0be0bd219e72	1612
charlesmn	0:0be0bd219e72	1613	#define VL53LX_RANGING_CORE__CALIB_2__A0 0x0A0A
charlesmn	0:0be0bd219e72	1614
charlesmn	0:0be0bd219e72	1615	#define VL53LX_RANGING_CORE__STOP_CONDITION__A0 0x0A0B
charlesmn	0:0be0bd219e72	1616
charlesmn	0:0be0bd219e72	1617	#define VL53LX_RANGING_CORE__STATUS_RESET__A0 0x0A0C
charlesmn	0:0be0bd219e72	1618
charlesmn	0:0be0bd219e72	1619	#define VL53LX_RANGING_CORE__READOUT_CFG__A0 0x0A0D
charlesmn	0:0be0bd219e72	1620
charlesmn	0:0be0bd219e72	1621	#define VL53LX_RANGING_CORE__WINDOW_SETTING__A0 0x0A0E
charlesmn	0:0be0bd219e72	1622
charlesmn	0:0be0bd219e72	1623	#define VL53LX_RANGING_CORE__VCSEL_DELAY__A0 0x0A1A
charlesmn	0:0be0bd219e72	1624
charlesmn	0:0be0bd219e72	1625	#define VL53LX_RANGING_CORE__REFERENCE_2__A0 0x0A1B
charlesmn	0:0be0bd219e72	1626
charlesmn	0:0be0bd219e72	1627	#define VL53LX_RANGING_CORE__REGAVDD1V2__A0 0x0A1D
charlesmn	0:0be0bd219e72	1628
charlesmn	0:0be0bd219e72	1629	#define VL53LX_RANGING_CORE__TST_MUX__A0 0x0A1F
charlesmn	0:0be0bd219e72	1630
charlesmn	0:0be0bd219e72	1631	#define VL53LX_RANGING_CORE__CUSTOM_FE_2__A0 0x0A20
charlesmn	0:0be0bd219e72	1632
charlesmn	0:0be0bd219e72	1633	#define VL53LX_RANGING_CORE__SPAD_READOUT__A0 0x0A21
charlesmn	0:0be0bd219e72	1634
charlesmn	0:0be0bd219e72	1635	#define VL53LX_RANGING_CORE__CPUMP_1__A0 0x0A22
charlesmn	0:0be0bd219e72	1636
charlesmn	0:0be0bd219e72	1637	#define VL53LX_RANGING_CORE__SPARE_REGISTER__A0 0x0A23
charlesmn	0:0be0bd219e72	1638
charlesmn	0:0be0bd219e72	1639	#define VL53LX_RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 0x0A24
charlesmn	0:0be0bd219e72	1640
charlesmn	0:0be0bd219e72	1641	#define VL53LX_RANGING_CORE__RET_SPAD_EN_18 0x0A25
charlesmn	0:0be0bd219e72	1642
charlesmn	0:0be0bd219e72	1643	#define VL53LX_RANGING_CORE__RET_SPAD_EN_19 0x0A26
charlesmn	0:0be0bd219e72	1644
charlesmn	0:0be0bd219e72	1645	#define VL53LX_RANGING_CORE__RET_SPAD_EN_20 0x0A27
charlesmn	0:0be0bd219e72	1646
charlesmn	0:0be0bd219e72	1647	#define VL53LX_RANGING_CORE__RET_SPAD_EN_21 0x0A28
charlesmn	0:0be0bd219e72	1648
charlesmn	0:0be0bd219e72	1649	#define VL53LX_RANGING_CORE__RET_SPAD_EN_22 0x0A29
charlesmn	0:0be0bd219e72	1650
charlesmn	0:0be0bd219e72	1651	#define VL53LX_RANGING_CORE__RET_SPAD_EN_23 0x0A2A
charlesmn	0:0be0bd219e72	1652
charlesmn	0:0be0bd219e72	1653	#define VL53LX_RANGING_CORE__RET_SPAD_EN_24 0x0A2B
charlesmn	0:0be0bd219e72	1654
charlesmn	0:0be0bd219e72	1655	#define VL53LX_RANGING_CORE__RET_SPAD_EN_25 0x0A2C
charlesmn	0:0be0bd219e72	1656
charlesmn	0:0be0bd219e72	1657	#define VL53LX_RANGING_CORE__RET_SPAD_EN_26 0x0A2D
charlesmn	0:0be0bd219e72	1658
charlesmn	0:0be0bd219e72	1659	#define VL53LX_RANGING_CORE__RET_SPAD_EN_27 0x0A2E
charlesmn	0:0be0bd219e72	1660
charlesmn	0:0be0bd219e72	1661	#define VL53LX_RANGING_CORE__RET_SPAD_EN_28 0x0A2F
charlesmn	0:0be0bd219e72	1662
charlesmn	0:0be0bd219e72	1663	#define VL53LX_RANGING_CORE__RET_SPAD_EN_29 0x0A30
charlesmn	0:0be0bd219e72	1664
charlesmn	0:0be0bd219e72	1665	#define VL53LX_RANGING_CORE__RET_SPAD_EN_30 0x0A31
charlesmn	0:0be0bd219e72	1666
charlesmn	0:0be0bd219e72	1667	#define VL53LX_RANGING_CORE__RET_SPAD_EN_31 0x0A32
charlesmn	0:0be0bd219e72	1668
charlesmn	0:0be0bd219e72	1669	#define VL53LX_RANGING_CORE__REF_SPAD_EN_0__EWOK 0x0A33
charlesmn	0:0be0bd219e72	1670
charlesmn	0:0be0bd219e72	1671	#define VL53LX_RANGING_CORE__REF_SPAD_EN_1__EWOK 0x0A34
charlesmn	0:0be0bd219e72	1672
charlesmn	0:0be0bd219e72	1673	#define VL53LX_RANGING_CORE__REF_SPAD_EN_2__EWOK 0x0A35
charlesmn	0:0be0bd219e72	1674
charlesmn	0:0be0bd219e72	1675	#define VL53LX_RANGING_CORE__REF_SPAD_EN_3__EWOK 0x0A36
charlesmn	0:0be0bd219e72	1676
charlesmn	0:0be0bd219e72	1677	#define VL53LX_RANGING_CORE__REF_SPAD_EN_4__EWOK 0x0A37
charlesmn	0:0be0bd219e72	1678
charlesmn	0:0be0bd219e72	1679	#define VL53LX_RANGING_CORE__REF_SPAD_EN_5__EWOK 0x0A38
charlesmn	0:0be0bd219e72	1680
charlesmn	0:0be0bd219e72	1681	#define VL53LX_RANGING_CORE__REF_EN_START_SELECT 0x0A39
charlesmn	0:0be0bd219e72	1682
charlesmn	0:0be0bd219e72	1683	#define VL53LX_RANGING_CORE__REGDVDD1V2_ATEST__EWOK 0x0A41
charlesmn	0:0be0bd219e72	1684
charlesmn	0:0be0bd219e72	1685	#define VL53LX_SOFT_RESET_GO1 0x0B00
charlesmn	0:0be0bd219e72	1686
charlesmn	0:0be0bd219e72	1687	#define VL53LX_PRIVATE__PATCH_BASE_ADDR_RSLV 0x0E00
charlesmn	0:0be0bd219e72	1688
charlesmn	0:0be0bd219e72	1689	#define VL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS 0x0ED0
charlesmn	0:0be0bd219e72	1690
charlesmn	0:0be0bd219e72	1691	#define VL53LX_PREV_SHADOW_RESULT__RANGE_STATUS 0x0ED1
charlesmn	0:0be0bd219e72	1692
charlesmn	0:0be0bd219e72	1693	#define VL53LX_PREV_SHADOW_RESULT__REPORT_STATUS 0x0ED2
charlesmn	0:0be0bd219e72	1694
charlesmn	0:0be0bd219e72	1695	#define VL53LX_PREV_SHADOW_RESULT__STREAM_COUNT 0x0ED3
charlesmn	0:0be0bd219e72	1696
charlesmn	0:0be0bd219e72	1697	#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0ED4
charlesmn	0:0be0bd219e72	1698
charlesmn	0:0be0bd219e72	1699	#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0ED4
charlesmn	0:0be0bd219e72	1700
charlesmn	0:0be0bd219e72	1701	#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0ED5
charlesmn	0:0be0bd219e72	1702
charlesmn	0:0be0bd219e72	1703	#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0ED6
charlesmn	0:0be0bd219e72	1704
charlesmn	0:0be0bd219e72	1705	#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0ED6
charlesmn	0:0be0bd219e72	1706
charlesmn	0:0be0bd219e72	1707	#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0ED7
charlesmn	0:0be0bd219e72	1708
charlesmn	0:0be0bd219e72	1709	#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0ED8
charlesmn	0:0be0bd219e72	1710
charlesmn	0:0be0bd219e72	1711	#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0ED8
charlesmn	0:0be0bd219e72	1712
charlesmn	0:0be0bd219e72	1713	#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0ED9
charlesmn	0:0be0bd219e72	1714
charlesmn	0:0be0bd219e72	1715	#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0 0x0EDA
charlesmn	0:0be0bd219e72	1716
charlesmn	0:0be0bd219e72	1717	#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0_HI 0x0EDA
charlesmn	0:0be0bd219e72	1718
charlesmn	0:0be0bd219e72	1719	#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0_LO 0x0EDB
charlesmn	0:0be0bd219e72	1720
charlesmn	0:0be0bd219e72	1721	#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0 0x0EDC
charlesmn	0:0be0bd219e72	1722
charlesmn	0:0be0bd219e72	1723	#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0_HI 0x0EDC
charlesmn	0:0be0bd219e72	1724
charlesmn	0:0be0bd219e72	1725	#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0_LO 0x0EDD
charlesmn	0:0be0bd219e72	1726
charlesmn	0:0be0bd219e72	1727	#define VL53LX_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0EDE
charlesmn	0:0be0bd219e72	1728
charlesmn	0:0be0bd219e72	1729	#define VL53LX_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0EDE
charlesmn	0:0be0bd219e72	1730
charlesmn	0:0be0bd219e72	1731	#define VL53LX_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0EDF
charlesmn	0:0be0bd219e72	1732
charlesmn	0:0be0bd219e72	1733	#define VL53LX_PREV__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0EE0
charlesmn	0:0be0bd219e72	1734
charlesmn	0:0be0bd219e72	1735	#define VL53LX_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0EE0
charlesmn	0:0be0bd219e72	1736
charlesmn	0:0be0bd219e72	1737	#define VL53LX_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0EE1
charlesmn	0:0be0bd219e72	1738
charlesmn	0:0be0bd219e72	1739	#define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE2
charlesmn	0:0be0bd219e72	1740
charlesmn	0:0be0bd219e72	1741	#define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE2
charlesmn	0:0be0bd219e72	1742
charlesmn	0:0be0bd219e72	1743	#define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE3
charlesmn	0:0be0bd219e72	1744
charlesmn	0:0be0bd219e72	1745	#define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE4
charlesmn	0:0be0bd219e72	1746
charlesmn	0:0be0bd219e72	1747	#define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE4
charlesmn	0:0be0bd219e72	1748
charlesmn	0:0be0bd219e72	1749	#define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE5
charlesmn	0:0be0bd219e72	1750
charlesmn	0:0be0bd219e72	1751	#define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0EE6
charlesmn	0:0be0bd219e72	1752
charlesmn	0:0be0bd219e72	1753	#define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0EE6
charlesmn	0:0be0bd219e72	1754
charlesmn	0:0be0bd219e72	1755	#define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0EE7
charlesmn	0:0be0bd219e72	1756
charlesmn	0:0be0bd219e72	1757	#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0EE8
charlesmn	0:0be0bd219e72	1758
charlesmn	0:0be0bd219e72	1759	#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0EE8
charlesmn	0:0be0bd219e72	1760
charlesmn	0:0be0bd219e72	1761	#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0EE9
charlesmn	0:0be0bd219e72	1762
charlesmn	0:0be0bd219e72	1763	#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0EEA
charlesmn	0:0be0bd219e72	1764
charlesmn	0:0be0bd219e72	1765	#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0EEA
charlesmn	0:0be0bd219e72	1766
charlesmn	0:0be0bd219e72	1767	#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0EEB
charlesmn	0:0be0bd219e72	1768
charlesmn	0:0be0bd219e72	1769	#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0EEC
charlesmn	0:0be0bd219e72	1770
charlesmn	0:0be0bd219e72	1771	#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0EEC
charlesmn	0:0be0bd219e72	1772
charlesmn	0:0be0bd219e72	1773	#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0EED
charlesmn	0:0be0bd219e72	1774
charlesmn	0:0be0bd219e72	1775	#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1 0x0EEE
charlesmn	0:0be0bd219e72	1776
charlesmn	0:0be0bd219e72	1777	#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1_HI 0x0EEE
charlesmn	0:0be0bd219e72	1778
charlesmn	0:0be0bd219e72	1779	#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1_LO 0x0EEF
charlesmn	0:0be0bd219e72	1780
charlesmn	0:0be0bd219e72	1781	#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1 0x0EF0
charlesmn	0:0be0bd219e72	1782
charlesmn	0:0be0bd219e72	1783	#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1_HI 0x0EF0
charlesmn	0:0be0bd219e72	1784
charlesmn	0:0be0bd219e72	1785	#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1_LO 0x0EF1
charlesmn	0:0be0bd219e72	1786
charlesmn	0:0be0bd219e72	1787	#define VL53LX_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0EF2
charlesmn	0:0be0bd219e72	1788
charlesmn	0:0be0bd219e72	1789	#define VL53LX_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0EF2
charlesmn	0:0be0bd219e72	1790
charlesmn	0:0be0bd219e72	1791	#define VL53LX_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0EF3
charlesmn	0:0be0bd219e72	1792
charlesmn	0:0be0bd219e72	1793	#define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1 0x0EF4
charlesmn	0:0be0bd219e72	1794
charlesmn	0:0be0bd219e72	1795	#define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1_HI 0x0EF4
charlesmn	0:0be0bd219e72	1796
charlesmn	0:0be0bd219e72	1797	#define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1_LO 0x0EF5
charlesmn	0:0be0bd219e72	1798
charlesmn	0:0be0bd219e72	1799	#define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1 0x0EF6
charlesmn	0:0be0bd219e72	1800
charlesmn	0:0be0bd219e72	1801	#define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1_HI 0x0EF6
charlesmn	0:0be0bd219e72	1802
charlesmn	0:0be0bd219e72	1803	#define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1_LO 0x0EF7
charlesmn	0:0be0bd219e72	1804
charlesmn	0:0be0bd219e72	1805	#define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1 0x0EF8
charlesmn	0:0be0bd219e72	1806
charlesmn	0:0be0bd219e72	1807	#define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1_HI 0x0EF8
charlesmn	0:0be0bd219e72	1808
charlesmn	0:0be0bd219e72	1809	#define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1_LO 0x0EF9
charlesmn	0:0be0bd219e72	1810
charlesmn	0:0be0bd219e72	1811	#define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1 0x0EFA
charlesmn	0:0be0bd219e72	1812
charlesmn	0:0be0bd219e72	1813	#define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1_HI 0x0EFA
charlesmn	0:0be0bd219e72	1814
charlesmn	0:0be0bd219e72	1815	#define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1_LO 0x0EFB
charlesmn	0:0be0bd219e72	1816
charlesmn	0:0be0bd219e72	1817	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0EFC
charlesmn	0:0be0bd219e72	1818
charlesmn	0:0be0bd219e72	1819	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0EFC
charlesmn	0:0be0bd219e72	1820
charlesmn	0:0be0bd219e72	1821	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0EFD
charlesmn	0:0be0bd219e72	1822
charlesmn	0:0be0bd219e72	1823	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0EFE
charlesmn	0:0be0bd219e72	1824
charlesmn	0:0be0bd219e72	1825	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0EFF
charlesmn	0:0be0bd219e72	1826
charlesmn	0:0be0bd219e72	1827	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0F00
charlesmn	0:0be0bd219e72	1828
charlesmn	0:0be0bd219e72	1829	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0F00
charlesmn	0:0be0bd219e72	1830
charlesmn	0:0be0bd219e72	1831	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0F01
charlesmn	0:0be0bd219e72	1832
charlesmn	0:0be0bd219e72	1833	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0F02
charlesmn	0:0be0bd219e72	1834
charlesmn	0:0be0bd219e72	1835	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0F03
charlesmn	0:0be0bd219e72	1836
charlesmn	0:0be0bd219e72	1837	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0F04
charlesmn	0:0be0bd219e72	1838
charlesmn	0:0be0bd219e72	1839	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0F04
charlesmn	0:0be0bd219e72	1840
charlesmn	0:0be0bd219e72	1841	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0F05
charlesmn	0:0be0bd219e72	1842
charlesmn	0:0be0bd219e72	1843	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0F06
charlesmn	0:0be0bd219e72	1844
charlesmn	0:0be0bd219e72	1845	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0F07
charlesmn	0:0be0bd219e72	1846
charlesmn	0:0be0bd219e72	1847	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0F08
charlesmn	0:0be0bd219e72	1848
charlesmn	0:0be0bd219e72	1849	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0F08
charlesmn	0:0be0bd219e72	1850
charlesmn	0:0be0bd219e72	1851	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0F09
charlesmn	0:0be0bd219e72	1852
charlesmn	0:0be0bd219e72	1853	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0F0A
charlesmn	0:0be0bd219e72	1854
charlesmn	0:0be0bd219e72	1855	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0F0B
charlesmn	0:0be0bd219e72	1856
charlesmn	0:0be0bd219e72	1857	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0F0C
charlesmn	0:0be0bd219e72	1858
charlesmn	0:0be0bd219e72	1859	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0F0C
charlesmn	0:0be0bd219e72	1860
charlesmn	0:0be0bd219e72	1861	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0F0D
charlesmn	0:0be0bd219e72	1862
charlesmn	0:0be0bd219e72	1863	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0F0E
charlesmn	0:0be0bd219e72	1864
charlesmn	0:0be0bd219e72	1865	#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0F0F
charlesmn	0:0be0bd219e72	1866
charlesmn	0:0be0bd219e72	1867	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0F10
charlesmn	0:0be0bd219e72	1868
charlesmn	0:0be0bd219e72	1869	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0F10
charlesmn	0:0be0bd219e72	1870
charlesmn	0:0be0bd219e72	1871	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0F11
charlesmn	0:0be0bd219e72	1872
charlesmn	0:0be0bd219e72	1873	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0F12
charlesmn	0:0be0bd219e72	1874
charlesmn	0:0be0bd219e72	1875	#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0F13
charlesmn	0:0be0bd219e72	1876
charlesmn	0:0be0bd219e72	1877	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0F14
charlesmn	0:0be0bd219e72	1878
charlesmn	0:0be0bd219e72	1879	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0F14
charlesmn	0:0be0bd219e72	1880
charlesmn	0:0be0bd219e72	1881	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0F15
charlesmn	0:0be0bd219e72	1882
charlesmn	0:0be0bd219e72	1883	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0F16
charlesmn	0:0be0bd219e72	1884
charlesmn	0:0be0bd219e72	1885	#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0F17
charlesmn	0:0be0bd219e72	1886
charlesmn	0:0be0bd219e72	1887	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0F18
charlesmn	0:0be0bd219e72	1888
charlesmn	0:0be0bd219e72	1889	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0F18
charlesmn	0:0be0bd219e72	1890
charlesmn	0:0be0bd219e72	1891	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0F19
charlesmn	0:0be0bd219e72	1892
charlesmn	0:0be0bd219e72	1893	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0F1A
charlesmn	0:0be0bd219e72	1894
charlesmn	0:0be0bd219e72	1895	#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0F1B
charlesmn	0:0be0bd219e72	1896
charlesmn	0:0be0bd219e72	1897	#define VL53LX_PREV_SHADOW_RESULT_CORE__SPARE_0 0x0F1C
charlesmn	0:0be0bd219e72	1898
charlesmn	0:0be0bd219e72	1899	#define VL53LX_RESULT__DEBUG_STATUS 0x0F20
charlesmn	0:0be0bd219e72	1900
charlesmn	0:0be0bd219e72	1901	#define VL53LX_RESULT__DEBUG_STAGE 0x0F21
charlesmn	0:0be0bd219e72	1902
charlesmn	0:0be0bd219e72	1903	#define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH 0x0F24
charlesmn	0:0be0bd219e72	1904
charlesmn	0:0be0bd219e72	1905	#define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH_HI 0x0F24
charlesmn	0:0be0bd219e72	1906
charlesmn	0:0be0bd219e72	1907	#define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH_LO 0x0F25
charlesmn	0:0be0bd219e72	1908
charlesmn	0:0be0bd219e72	1909	#define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW 0x0F26
charlesmn	0:0be0bd219e72	1910
charlesmn	0:0be0bd219e72	1911	#define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW_HI 0x0F26
charlesmn	0:0be0bd219e72	1912
charlesmn	0:0be0bd219e72	1913	#define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW_LO 0x0F27
charlesmn	0:0be0bd219e72	1914
charlesmn	0:0be0bd219e72	1915	#define VL53LX_GPH__SYSTEM__INTERRUPT_CONFIG_GPIO 0x0F28
charlesmn	0:0be0bd219e72	1916
charlesmn	0:0be0bd219e72	1917	#define VL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL 0x0F2F
charlesmn	0:0be0bd219e72	1918
charlesmn	0:0be0bd219e72	1919	#define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30
charlesmn	0:0be0bd219e72	1920
charlesmn	0:0be0bd219e72	1921	#define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30
charlesmn	0:0be0bd219e72	1922
charlesmn	0:0be0bd219e72	1923	#define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31
charlesmn	0:0be0bd219e72	1924
charlesmn	0:0be0bd219e72	1925	#define VL53LX_GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0F32
charlesmn	0:0be0bd219e72	1926
charlesmn	0:0be0bd219e72	1927	#define VL53LX_GPH__DSS_CONFIG__MAX_SPADS_LIMIT 0x0F33
charlesmn	0:0be0bd219e72	1928
charlesmn	0:0be0bd219e72	1929	#define VL53LX_GPH__DSS_CONFIG__MIN_SPADS_LIMIT 0x0F34
charlesmn	0:0be0bd219e72	1930
charlesmn	0:0be0bd219e72	1931	#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 0x0F36
charlesmn	0:0be0bd219e72	1932
charlesmn	0:0be0bd219e72	1933	#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO 0x0F37
charlesmn	0:0be0bd219e72	1934
charlesmn	0:0be0bd219e72	1935	#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI 0x0F38
charlesmn	0:0be0bd219e72	1936
charlesmn	0:0be0bd219e72	1937	#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO 0x0F39
charlesmn	0:0be0bd219e72	1938
charlesmn	0:0be0bd219e72	1939	#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x0F3A
charlesmn	0:0be0bd219e72	1940
charlesmn	0:0be0bd219e72	1941	#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x0F3B
charlesmn	0:0be0bd219e72	1942
charlesmn	0:0be0bd219e72	1943	#define VL53LX_GPH__RANGE_CONFIG__VCSEL_PERIOD_A 0x0F3C
charlesmn	0:0be0bd219e72	1944
charlesmn	0:0be0bd219e72	1945	#define VL53LX_GPH__RANGE_CONFIG__VCSEL_PERIOD_B 0x0F3D
charlesmn	0:0be0bd219e72	1946
charlesmn	0:0be0bd219e72	1947	#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0F3E
charlesmn	0:0be0bd219e72	1948
charlesmn	0:0be0bd219e72	1949	#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0F3F
charlesmn	0:0be0bd219e72	1950
charlesmn	0:0be0bd219e72	1951	#define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH 0x0F40
charlesmn	0:0be0bd219e72	1952
charlesmn	0:0be0bd219e72	1953	#define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH_HI 0x0F40
charlesmn	0:0be0bd219e72	1954
charlesmn	0:0be0bd219e72	1955	#define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH_LO 0x0F41
charlesmn	0:0be0bd219e72	1956
charlesmn	0:0be0bd219e72	1957	#define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42
charlesmn	0:0be0bd219e72	1958
charlesmn	0:0be0bd219e72	1959	#define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42
charlesmn	0:0be0bd219e72	1960
charlesmn	0:0be0bd219e72	1961	#define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43
charlesmn	0:0be0bd219e72	1962
charlesmn	0:0be0bd219e72	1963	#define VL53LX_GPH__RANGE_CONFIG__VALID_PHASE_LOW 0x0F44
charlesmn	0:0be0bd219e72	1964
charlesmn	0:0be0bd219e72	1965	#define VL53LX_GPH__RANGE_CONFIG__VALID_PHASE_HIGH 0x0F45
charlesmn	0:0be0bd219e72	1966
charlesmn	0:0be0bd219e72	1967	#define VL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46
charlesmn	0:0be0bd219e72	1968
charlesmn	0:0be0bd219e72	1969	#define VL53LX_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47
charlesmn	0:0be0bd219e72	1970
charlesmn	0:0be0bd219e72	1971	#define VL53LX_DSS_CALC__ROI_CTRL 0x0F54
charlesmn	0:0be0bd219e72	1972
charlesmn	0:0be0bd219e72	1973	#define VL53LX_DSS_CALC__SPARE_1 0x0F55
charlesmn	0:0be0bd219e72	1974
charlesmn	0:0be0bd219e72	1975	#define VL53LX_DSS_CALC__SPARE_2 0x0F56
charlesmn	0:0be0bd219e72	1976
charlesmn	0:0be0bd219e72	1977	#define VL53LX_DSS_CALC__SPARE_3 0x0F57
charlesmn	0:0be0bd219e72	1978
charlesmn	0:0be0bd219e72	1979	#define VL53LX_DSS_CALC__SPARE_4 0x0F58
charlesmn	0:0be0bd219e72	1980
charlesmn	0:0be0bd219e72	1981	#define VL53LX_DSS_CALC__SPARE_5 0x0F59
charlesmn	0:0be0bd219e72	1982
charlesmn	0:0be0bd219e72	1983	#define VL53LX_DSS_CALC__SPARE_6 0x0F5A
charlesmn	0:0be0bd219e72	1984
charlesmn	0:0be0bd219e72	1985	#define VL53LX_DSS_CALC__SPARE_7 0x0F5B
charlesmn	0:0be0bd219e72	1986
charlesmn	0:0be0bd219e72	1987	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_0 0x0F5C
charlesmn	0:0be0bd219e72	1988
charlesmn	0:0be0bd219e72	1989	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_1 0x0F5D
charlesmn	0:0be0bd219e72	1990
charlesmn	0:0be0bd219e72	1991	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_2 0x0F5E
charlesmn	0:0be0bd219e72	1992
charlesmn	0:0be0bd219e72	1993	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_3 0x0F5F
charlesmn	0:0be0bd219e72	1994
charlesmn	0:0be0bd219e72	1995	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_4 0x0F60
charlesmn	0:0be0bd219e72	1996
charlesmn	0:0be0bd219e72	1997	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_5 0x0F61
charlesmn	0:0be0bd219e72	1998
charlesmn	0:0be0bd219e72	1999	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_6 0x0F62
charlesmn	0:0be0bd219e72	2000
charlesmn	0:0be0bd219e72	2001	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_7 0x0F63
charlesmn	0:0be0bd219e72	2002
charlesmn	0:0be0bd219e72	2003	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_8 0x0F64
charlesmn	0:0be0bd219e72	2004
charlesmn	0:0be0bd219e72	2005	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_9 0x0F65
charlesmn	0:0be0bd219e72	2006
charlesmn	0:0be0bd219e72	2007	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_10 0x0F66
charlesmn	0:0be0bd219e72	2008
charlesmn	0:0be0bd219e72	2009	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_11 0x0F67
charlesmn	0:0be0bd219e72	2010
charlesmn	0:0be0bd219e72	2011	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_12 0x0F68
charlesmn	0:0be0bd219e72	2012
charlesmn	0:0be0bd219e72	2013	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_13 0x0F69
charlesmn	0:0be0bd219e72	2014
charlesmn	0:0be0bd219e72	2015	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_14 0x0F6A
charlesmn	0:0be0bd219e72	2016
charlesmn	0:0be0bd219e72	2017	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_15 0x0F6B
charlesmn	0:0be0bd219e72	2018
charlesmn	0:0be0bd219e72	2019	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_16 0x0F6C
charlesmn	0:0be0bd219e72	2020
charlesmn	0:0be0bd219e72	2021	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_17 0x0F6D
charlesmn	0:0be0bd219e72	2022
charlesmn	0:0be0bd219e72	2023	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_18 0x0F6E
charlesmn	0:0be0bd219e72	2024
charlesmn	0:0be0bd219e72	2025	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_19 0x0F6F
charlesmn	0:0be0bd219e72	2026
charlesmn	0:0be0bd219e72	2027	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_20 0x0F70
charlesmn	0:0be0bd219e72	2028
charlesmn	0:0be0bd219e72	2029	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_21 0x0F71
charlesmn	0:0be0bd219e72	2030
charlesmn	0:0be0bd219e72	2031	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_22 0x0F72
charlesmn	0:0be0bd219e72	2032
charlesmn	0:0be0bd219e72	2033	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_23 0x0F73
charlesmn	0:0be0bd219e72	2034
charlesmn	0:0be0bd219e72	2035	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_24 0x0F74
charlesmn	0:0be0bd219e72	2036
charlesmn	0:0be0bd219e72	2037	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_25 0x0F75
charlesmn	0:0be0bd219e72	2038
charlesmn	0:0be0bd219e72	2039	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_26 0x0F76
charlesmn	0:0be0bd219e72	2040
charlesmn	0:0be0bd219e72	2041	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_27 0x0F77
charlesmn	0:0be0bd219e72	2042
charlesmn	0:0be0bd219e72	2043	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_28 0x0F78
charlesmn	0:0be0bd219e72	2044
charlesmn	0:0be0bd219e72	2045	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_29 0x0F79
charlesmn	0:0be0bd219e72	2046
charlesmn	0:0be0bd219e72	2047	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_30 0x0F7A
charlesmn	0:0be0bd219e72	2048
charlesmn	0:0be0bd219e72	2049	#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_31 0x0F7B
charlesmn	0:0be0bd219e72	2050
charlesmn	0:0be0bd219e72	2051	#define VL53LX_DSS_CALC__USER_ROI_0 0x0F7C
charlesmn	0:0be0bd219e72	2052
charlesmn	0:0be0bd219e72	2053	#define VL53LX_DSS_CALC__USER_ROI_1 0x0F7D
charlesmn	0:0be0bd219e72	2054
charlesmn	0:0be0bd219e72	2055	#define VL53LX_DSS_CALC__MODE_ROI_0 0x0F7E
charlesmn	0:0be0bd219e72	2056
charlesmn	0:0be0bd219e72	2057	#define VL53LX_DSS_CALC__MODE_ROI_1 0x0F7F
charlesmn	0:0be0bd219e72	2058
charlesmn	0:0be0bd219e72	2059	#define VL53LX_SIGMA_ESTIMATOR_CALC__SPARE_0 0x0F80
charlesmn	0:0be0bd219e72	2060
charlesmn	0:0be0bd219e72	2061	#define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS 0x0F82
charlesmn	0:0be0bd219e72	2062
charlesmn	0:0be0bd219e72	2063	#define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI 0x0F82
charlesmn	0:0be0bd219e72	2064
charlesmn	0:0be0bd219e72	2065	#define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO 0x0F83
charlesmn	0:0be0bd219e72	2066
charlesmn	0:0be0bd219e72	2067	#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF 0x0F84
charlesmn	0:0be0bd219e72	2068
charlesmn	0:0be0bd219e72	2069	#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 0x0F84
charlesmn	0:0be0bd219e72	2070
charlesmn	0:0be0bd219e72	2071	#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 0x0F85
charlesmn	0:0be0bd219e72	2072
charlesmn	0:0be0bd219e72	2073	#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 0x0F86
charlesmn	0:0be0bd219e72	2074
charlesmn	0:0be0bd219e72	2075	#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 0x0F87
charlesmn	0:0be0bd219e72	2076
charlesmn	0:0be0bd219e72	2077	#define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF 0x0F88
charlesmn	0:0be0bd219e72	2078
charlesmn	0:0be0bd219e72	2079	#define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF_HI 0x0F88
charlesmn	0:0be0bd219e72	2080
charlesmn	0:0be0bd219e72	2081	#define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF_LO 0x0F89
charlesmn	0:0be0bd219e72	2082
charlesmn	0:0be0bd219e72	2083	#define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD 0x0F8A
charlesmn	0:0be0bd219e72	2084
charlesmn	0:0be0bd219e72	2085	#define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD_HI 0x0F8A
charlesmn	0:0be0bd219e72	2086
charlesmn	0:0be0bd219e72	2087	#define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD_LO 0x0F8B
charlesmn	0:0be0bd219e72	2088
charlesmn	0:0be0bd219e72	2089	#define VL53LX_DSS_RESULT__ENABLED_BLOCKS 0x0F8C
charlesmn	0:0be0bd219e72	2090
charlesmn	0:0be0bd219e72	2091	#define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS 0x0F8E
charlesmn	0:0be0bd219e72	2092
charlesmn	0:0be0bd219e72	2093	#define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS_HI 0x0F8E
charlesmn	0:0be0bd219e72	2094
charlesmn	0:0be0bd219e72	2095	#define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS_LO 0x0F8F
charlesmn	0:0be0bd219e72	2096
charlesmn	0:0be0bd219e72	2097	#define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE 0x0F92
charlesmn	0:0be0bd219e72	2098
charlesmn	0:0be0bd219e72	2099	#define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE_HI 0x0F92
charlesmn	0:0be0bd219e72	2100
charlesmn	0:0be0bd219e72	2101	#define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE_LO 0x0F93
charlesmn	0:0be0bd219e72	2102
charlesmn	0:0be0bd219e72	2103	#define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE 0x0F94
charlesmn	0:0be0bd219e72	2104
charlesmn	0:0be0bd219e72	2105	#define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE_HI 0x0F94
charlesmn	0:0be0bd219e72	2106
charlesmn	0:0be0bd219e72	2107	#define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE_LO 0x0F95
charlesmn	0:0be0bd219e72	2108
charlesmn	0:0be0bd219e72	2109	#define VL53LX_MM_RESULT__TOTAL_OFFSET 0x0F96
charlesmn	0:0be0bd219e72	2110
charlesmn	0:0be0bd219e72	2111	#define VL53LX_MM_RESULT__TOTAL_OFFSET_HI 0x0F96
charlesmn	0:0be0bd219e72	2112
charlesmn	0:0be0bd219e72	2113	#define VL53LX_MM_RESULT__TOTAL_OFFSET_LO 0x0F97
charlesmn	0:0be0bd219e72	2114
charlesmn	0:0be0bd219e72	2115	#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS 0x0F98
charlesmn	0:0be0bd219e72	2116
charlesmn	0:0be0bd219e72	2117	#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 0x0F98
charlesmn	0:0be0bd219e72	2118
charlesmn	0:0be0bd219e72	2119	#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 0x0F99
charlesmn	0:0be0bd219e72	2120
charlesmn	0:0be0bd219e72	2121	#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 0x0F9A
charlesmn	0:0be0bd219e72	2122
charlesmn	0:0be0bd219e72	2123	#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 0x0F9B
charlesmn	0:0be0bd219e72	2124
charlesmn	0:0be0bd219e72	2125	#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS 0x0F9C
charlesmn	0:0be0bd219e72	2126
charlesmn	0:0be0bd219e72	2127	#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 0x0F9C
charlesmn	0:0be0bd219e72	2128
charlesmn	0:0be0bd219e72	2129	#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 0x0F9D
charlesmn	0:0be0bd219e72	2130
charlesmn	0:0be0bd219e72	2131	#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 0x0F9E
charlesmn	0:0be0bd219e72	2132
charlesmn	0:0be0bd219e72	2133	#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 0x0F9F
charlesmn	0:0be0bd219e72	2134
charlesmn	0:0be0bd219e72	2135	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS 0x0FA0
charlesmn	0:0be0bd219e72	2136
charlesmn	0:0be0bd219e72	2137	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 0x0FA0
charlesmn	0:0be0bd219e72	2138
charlesmn	0:0be0bd219e72	2139	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 0x0FA1
charlesmn	0:0be0bd219e72	2140
charlesmn	0:0be0bd219e72	2141	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 0x0FA2
charlesmn	0:0be0bd219e72	2142
charlesmn	0:0be0bd219e72	2143	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 0x0FA3
charlesmn	0:0be0bd219e72	2144
charlesmn	0:0be0bd219e72	2145	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS 0x0FA4
charlesmn	0:0be0bd219e72	2146
charlesmn	0:0be0bd219e72	2147	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 0x0FA4
charlesmn	0:0be0bd219e72	2148
charlesmn	0:0be0bd219e72	2149	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 0x0FA5
charlesmn	0:0be0bd219e72	2150
charlesmn	0:0be0bd219e72	2151	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 0x0FA6
charlesmn	0:0be0bd219e72	2152
charlesmn	0:0be0bd219e72	2153	#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 0x0FA7
charlesmn	0:0be0bd219e72	2154
charlesmn	0:0be0bd219e72	2155	#define VL53LX_RANGE_RESULT__ACCUM_PHASE 0x0FA8
charlesmn	0:0be0bd219e72	2156
charlesmn	0:0be0bd219e72	2157	#define VL53LX_RANGE_RESULT__ACCUM_PHASE_3 0x0FA8
charlesmn	0:0be0bd219e72	2158
charlesmn	0:0be0bd219e72	2159	#define VL53LX_RANGE_RESULT__ACCUM_PHASE_2 0x0FA9
charlesmn	0:0be0bd219e72	2160
charlesmn	0:0be0bd219e72	2161	#define VL53LX_RANGE_RESULT__ACCUM_PHASE_1 0x0FAA
charlesmn	0:0be0bd219e72	2162
charlesmn	0:0be0bd219e72	2163	#define VL53LX_RANGE_RESULT__ACCUM_PHASE_0 0x0FAB
charlesmn	0:0be0bd219e72	2164
charlesmn	0:0be0bd219e72	2165	#define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE 0x0FAC
charlesmn	0:0be0bd219e72	2166
charlesmn	0:0be0bd219e72	2167	#define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI 0x0FAC
charlesmn	0:0be0bd219e72	2168
charlesmn	0:0be0bd219e72	2169	#define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO 0x0FAD
charlesmn	0:0be0bd219e72	2170
charlesmn	0:0be0bd219e72	2171	#define VL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START 0x0FAE
charlesmn	0:0be0bd219e72	2172
charlesmn	0:0be0bd219e72	2173	#define VL53LX_SHADOW_RESULT__INTERRUPT_STATUS 0x0FB0
charlesmn	0:0be0bd219e72	2174
charlesmn	0:0be0bd219e72	2175	#define VL53LX_SHADOW_RESULT__RANGE_STATUS 0x0FB1
charlesmn	0:0be0bd219e72	2176
charlesmn	0:0be0bd219e72	2177	#define VL53LX_SHADOW_RESULT__REPORT_STATUS 0x0FB2
charlesmn	0:0be0bd219e72	2178
charlesmn	0:0be0bd219e72	2179	#define VL53LX_SHADOW_RESULT__STREAM_COUNT 0x0FB3
charlesmn	0:0be0bd219e72	2180
charlesmn	0:0be0bd219e72	2181	#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FB4
charlesmn	0:0be0bd219e72	2182
charlesmn	0:0be0bd219e72	2183	#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FB4
charlesmn	0:0be0bd219e72	2184
charlesmn	0:0be0bd219e72	2185	#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FB5
charlesmn	0:0be0bd219e72	2186
charlesmn	0:0be0bd219e72	2187	#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FB6
charlesmn	0:0be0bd219e72	2188
charlesmn	0:0be0bd219e72	2189	#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FB6
charlesmn	0:0be0bd219e72	2190
charlesmn	0:0be0bd219e72	2191	#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FB7
charlesmn	0:0be0bd219e72	2192
charlesmn	0:0be0bd219e72	2193	#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0FB8
charlesmn	0:0be0bd219e72	2194
charlesmn	0:0be0bd219e72	2195	#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0FB8
charlesmn	0:0be0bd219e72	2196
charlesmn	0:0be0bd219e72	2197	#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0FB9
charlesmn	0:0be0bd219e72	2198
charlesmn	0:0be0bd219e72	2199	#define VL53LX_SHADOW_RESULT__SIGMA_SD0 0x0FBA
charlesmn	0:0be0bd219e72	2200
charlesmn	0:0be0bd219e72	2201	#define VL53LX_SHADOW_RESULT__SIGMA_SD0_HI 0x0FBA
charlesmn	0:0be0bd219e72	2202
charlesmn	0:0be0bd219e72	2203	#define VL53LX_SHADOW_RESULT__SIGMA_SD0_LO 0x0FBB
charlesmn	0:0be0bd219e72	2204
charlesmn	0:0be0bd219e72	2205	#define VL53LX_SHADOW_RESULT__PHASE_SD0 0x0FBC
charlesmn	0:0be0bd219e72	2206
charlesmn	0:0be0bd219e72	2207	#define VL53LX_SHADOW_RESULT__PHASE_SD0_HI 0x0FBC
charlesmn	0:0be0bd219e72	2208
charlesmn	0:0be0bd219e72	2209	#define VL53LX_SHADOW_RESULT__PHASE_SD0_LO 0x0FBD
charlesmn	0:0be0bd219e72	2210
charlesmn	0:0be0bd219e72	2211	#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0FBE
charlesmn	0:0be0bd219e72	2212
charlesmn	0:0be0bd219e72	2213	#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0FBE
charlesmn	0:0be0bd219e72	2214
charlesmn	0:0be0bd219e72	2215	#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0FBF
charlesmn	0:0be0bd219e72	2216
charlesmn	0:0be0bd219e72	2217	#define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0FC0
charlesmn	0:0be0bd219e72	2218
charlesmn	0:0be0bd219e72	2219	#define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0FC0
charlesmn	0:0be0bd219e72	2220
charlesmn	0:0be0bd219e72	2221	#define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0FC1
charlesmn	0:0be0bd219e72	2222
charlesmn	0:0be0bd219e72	2223	#define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC2
charlesmn	0:0be0bd219e72	2224
charlesmn	0:0be0bd219e72	2225	#define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC2
charlesmn	0:0be0bd219e72	2226
charlesmn	0:0be0bd219e72	2227	#define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC3
charlesmn	0:0be0bd219e72	2228
charlesmn	0:0be0bd219e72	2229	#define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC4
charlesmn	0:0be0bd219e72	2230
charlesmn	0:0be0bd219e72	2231	#define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC4
charlesmn	0:0be0bd219e72	2232
charlesmn	0:0be0bd219e72	2233	#define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC5
charlesmn	0:0be0bd219e72	2234
charlesmn	0:0be0bd219e72	2235	#define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FC6
charlesmn	0:0be0bd219e72	2236
charlesmn	0:0be0bd219e72	2237	#define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FC6
charlesmn	0:0be0bd219e72	2238
charlesmn	0:0be0bd219e72	2239	#define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FC7
charlesmn	0:0be0bd219e72	2240
charlesmn	0:0be0bd219e72	2241	#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0FC8
charlesmn	0:0be0bd219e72	2242
charlesmn	0:0be0bd219e72	2243	#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0FC8
charlesmn	0:0be0bd219e72	2244
charlesmn	0:0be0bd219e72	2245	#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0FC9
charlesmn	0:0be0bd219e72	2246
charlesmn	0:0be0bd219e72	2247	#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0FCA
charlesmn	0:0be0bd219e72	2248
charlesmn	0:0be0bd219e72	2249	#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0FCA
charlesmn	0:0be0bd219e72	2250
charlesmn	0:0be0bd219e72	2251	#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0FCB
charlesmn	0:0be0bd219e72	2252
charlesmn	0:0be0bd219e72	2253	#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0FCC
charlesmn	0:0be0bd219e72	2254
charlesmn	0:0be0bd219e72	2255	#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0FCC
charlesmn	0:0be0bd219e72	2256
charlesmn	0:0be0bd219e72	2257	#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0FCD
charlesmn	0:0be0bd219e72	2258
charlesmn	0:0be0bd219e72	2259	#define VL53LX_SHADOW_RESULT__SIGMA_SD1 0x0FCE
charlesmn	0:0be0bd219e72	2260
charlesmn	0:0be0bd219e72	2261	#define VL53LX_SHADOW_RESULT__SIGMA_SD1_HI 0x0FCE
charlesmn	0:0be0bd219e72	2262
charlesmn	0:0be0bd219e72	2263	#define VL53LX_SHADOW_RESULT__SIGMA_SD1_LO 0x0FCF
charlesmn	0:0be0bd219e72	2264
charlesmn	0:0be0bd219e72	2265	#define VL53LX_SHADOW_RESULT__PHASE_SD1 0x0FD0
charlesmn	0:0be0bd219e72	2266
charlesmn	0:0be0bd219e72	2267	#define VL53LX_SHADOW_RESULT__PHASE_SD1_HI 0x0FD0
charlesmn	0:0be0bd219e72	2268
charlesmn	0:0be0bd219e72	2269	#define VL53LX_SHADOW_RESULT__PHASE_SD1_LO 0x0FD1
charlesmn	0:0be0bd219e72	2270
charlesmn	0:0be0bd219e72	2271	#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0FD2
charlesmn	0:0be0bd219e72	2272
charlesmn	0:0be0bd219e72	2273	#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0FD2
charlesmn	0:0be0bd219e72	2274
charlesmn	0:0be0bd219e72	2275	#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0FD3
charlesmn	0:0be0bd219e72	2276
charlesmn	0:0be0bd219e72	2277	#define VL53LX_SHADOW_RESULT__SPARE_0_SD1 0x0FD4
charlesmn	0:0be0bd219e72	2278
charlesmn	0:0be0bd219e72	2279	#define VL53LX_SHADOW_RESULT__SPARE_0_SD1_HI 0x0FD4
charlesmn	0:0be0bd219e72	2280
charlesmn	0:0be0bd219e72	2281	#define VL53LX_SHADOW_RESULT__SPARE_0_SD1_LO 0x0FD5
charlesmn	0:0be0bd219e72	2282
charlesmn	0:0be0bd219e72	2283	#define VL53LX_SHADOW_RESULT__SPARE_1_SD1 0x0FD6
charlesmn	0:0be0bd219e72	2284
charlesmn	0:0be0bd219e72	2285	#define VL53LX_SHADOW_RESULT__SPARE_1_SD1_HI 0x0FD6
charlesmn	0:0be0bd219e72	2286
charlesmn	0:0be0bd219e72	2287	#define VL53LX_SHADOW_RESULT__SPARE_1_SD1_LO 0x0FD7
charlesmn	0:0be0bd219e72	2288
charlesmn	0:0be0bd219e72	2289	#define VL53LX_SHADOW_RESULT__SPARE_2_SD1 0x0FD8
charlesmn	0:0be0bd219e72	2290
charlesmn	0:0be0bd219e72	2291	#define VL53LX_SHADOW_RESULT__SPARE_2_SD1_HI 0x0FD8
charlesmn	0:0be0bd219e72	2292
charlesmn	0:0be0bd219e72	2293	#define VL53LX_SHADOW_RESULT__SPARE_2_SD1_LO 0x0FD9
charlesmn	0:0be0bd219e72	2294
charlesmn	0:0be0bd219e72	2295	#define VL53LX_SHADOW_RESULT__SPARE_3_SD1 0x0FDA
charlesmn	0:0be0bd219e72	2296
charlesmn	0:0be0bd219e72	2297	#define VL53LX_SHADOW_RESULT__THRESH_INFO 0x0FDB
charlesmn	0:0be0bd219e72	2298
charlesmn	0:0be0bd219e72	2299	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0FDC
charlesmn	0:0be0bd219e72	2300
charlesmn	0:0be0bd219e72	2301	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0FDC
charlesmn	0:0be0bd219e72	2302
charlesmn	0:0be0bd219e72	2303	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0FDD
charlesmn	0:0be0bd219e72	2304
charlesmn	0:0be0bd219e72	2305	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0FDE
charlesmn	0:0be0bd219e72	2306
charlesmn	0:0be0bd219e72	2307	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0FDF
charlesmn	0:0be0bd219e72	2308
charlesmn	0:0be0bd219e72	2309	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0FE0
charlesmn	0:0be0bd219e72	2310
charlesmn	0:0be0bd219e72	2311	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0FE0
charlesmn	0:0be0bd219e72	2312
charlesmn	0:0be0bd219e72	2313	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0FE1
charlesmn	0:0be0bd219e72	2314
charlesmn	0:0be0bd219e72	2315	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0FE2
charlesmn	0:0be0bd219e72	2316
charlesmn	0:0be0bd219e72	2317	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0FE3
charlesmn	0:0be0bd219e72	2318
charlesmn	0:0be0bd219e72	2319	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0FE4
charlesmn	0:0be0bd219e72	2320
charlesmn	0:0be0bd219e72	2321	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0FE4
charlesmn	0:0be0bd219e72	2322
charlesmn	0:0be0bd219e72	2323	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0FE5
charlesmn	0:0be0bd219e72	2324
charlesmn	0:0be0bd219e72	2325	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0FE6
charlesmn	0:0be0bd219e72	2326
charlesmn	0:0be0bd219e72	2327	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0FE7
charlesmn	0:0be0bd219e72	2328
charlesmn	0:0be0bd219e72	2329	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0FE8
charlesmn	0:0be0bd219e72	2330
charlesmn	0:0be0bd219e72	2331	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0FE8
charlesmn	0:0be0bd219e72	2332
charlesmn	0:0be0bd219e72	2333	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0FE9
charlesmn	0:0be0bd219e72	2334
charlesmn	0:0be0bd219e72	2335	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0FEA
charlesmn	0:0be0bd219e72	2336
charlesmn	0:0be0bd219e72	2337	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0FEB
charlesmn	0:0be0bd219e72	2338
charlesmn	0:0be0bd219e72	2339	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0FEC
charlesmn	0:0be0bd219e72	2340
charlesmn	0:0be0bd219e72	2341	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0FEC
charlesmn	0:0be0bd219e72	2342
charlesmn	0:0be0bd219e72	2343	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0FED
charlesmn	0:0be0bd219e72	2344
charlesmn	0:0be0bd219e72	2345	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0FEE
charlesmn	0:0be0bd219e72	2346
charlesmn	0:0be0bd219e72	2347	#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0FEF
charlesmn	0:0be0bd219e72	2348
charlesmn	0:0be0bd219e72	2349	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0FF0
charlesmn	0:0be0bd219e72	2350
charlesmn	0:0be0bd219e72	2351	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0FF0
charlesmn	0:0be0bd219e72	2352
charlesmn	0:0be0bd219e72	2353	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0FF1
charlesmn	0:0be0bd219e72	2354
charlesmn	0:0be0bd219e72	2355	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0FF2
charlesmn	0:0be0bd219e72	2356
charlesmn	0:0be0bd219e72	2357	#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0FF3
charlesmn	0:0be0bd219e72	2358
charlesmn	0:0be0bd219e72	2359	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0FF4
charlesmn	0:0be0bd219e72	2360
charlesmn	0:0be0bd219e72	2361	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0FF4
charlesmn	0:0be0bd219e72	2362
charlesmn	0:0be0bd219e72	2363	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0FF5
charlesmn	0:0be0bd219e72	2364
charlesmn	0:0be0bd219e72	2365	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0FF6
charlesmn	0:0be0bd219e72	2366
charlesmn	0:0be0bd219e72	2367	#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0FF7
charlesmn	0:0be0bd219e72	2368
charlesmn	0:0be0bd219e72	2369	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0FF8
charlesmn	0:0be0bd219e72	2370
charlesmn	0:0be0bd219e72	2371	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0FF8
charlesmn	0:0be0bd219e72	2372
charlesmn	0:0be0bd219e72	2373	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0FF9
charlesmn	0:0be0bd219e72	2374
charlesmn	0:0be0bd219e72	2375	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0FFA
charlesmn	0:0be0bd219e72	2376
charlesmn	0:0be0bd219e72	2377	#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0FFB
charlesmn	0:0be0bd219e72	2378
charlesmn	0:0be0bd219e72	2379	#define VL53LX_SHADOW_RESULT_CORE__SPARE_0 0x0FFC
charlesmn	0:0be0bd219e72	2380
charlesmn	0:0be0bd219e72	2381	#define VL53LX_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x0FFE
charlesmn	0:0be0bd219e72	2382
charlesmn	0:0be0bd219e72	2383	#define VL53LX_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x0FFF
charlesmn	0:0be0bd219e72	2384
charlesmn	0:0be0bd219e72	2385
charlesmn	0:0be0bd219e72	2386
charlesmn	0:0be0bd219e72	2387
charlesmn	0:0be0bd219e72	2388
charlesmn	0:0be0bd219e72	2389	// define from vl53lx_error_exceptions.h
charlesmn	0:0be0bd219e72	2390
charlesmn	0:0be0bd219e72	2391	#ifndef _VL53LX_ERROR_EXCEPTIONS_H_
charlesmn	0:0be0bd219e72	2392	#define _VL53LX_ERROR_EXCEPTIONS_H_
charlesmn	0:0be0bd219e72	2393
charlesmn	0:0be0bd219e72	2394	#define IGNORE_DIVISION_BY_ZERO 0
charlesmn	0:0be0bd219e72	2395
charlesmn	0:0be0bd219e72	2396	#define IGNORE_XTALK_EXTRACTION_NO_SAMPLE_FAIL 0
charlesmn	0:0be0bd219e72	2397	#define IGNORE_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL 0
charlesmn	0:0be0bd219e72	2398	#define IGNORE_XTALK_EXTRACTION_NO_SAMPLE_FOR_GRADIENT_WARN 0
charlesmn	0:0be0bd219e72	2399	#define IGNORE_XTALK_EXTRACTION_SIGMA_LIMIT_FOR_GRADIENT_WARN 0
charlesmn	0:0be0bd219e72	2400	#define IGNORE_XTALK_EXTRACTION_MISSING_SAMPLES_WARN 0
charlesmn	0:0be0bd219e72	2401
charlesmn	0:0be0bd219e72	2402	#define IGNORE_REF_SPAD_CHAR_NOT_ENOUGH_SPADS 0
charlesmn	0:0be0bd219e72	2403	#define IGNORE_REF_SPAD_CHAR_RATE_TOO_HIGH 0
charlesmn	0:0be0bd219e72	2404	#define IGNORE_REF_SPAD_CHAR_RATE_TOO_LOW 0
charlesmn	0:0be0bd219e72	2405
charlesmn	0:0be0bd219e72	2406	#define IGNORE_OFFSET_CAL_MISSING_SAMPLES 0
charlesmn	0:0be0bd219e72	2407	#define IGNORE_OFFSET_CAL_SIGMA_TOO_HIGH 0
charlesmn	0:0be0bd219e72	2408	#define IGNORE_OFFSET_CAL_RATE_TOO_HIGH 0
charlesmn	0:0be0bd219e72	2409	#define IGNORE_OFFSET_CAL_SPAD_COUNT_TOO_LOW 0
charlesmn	0:0be0bd219e72	2410
charlesmn	0:0be0bd219e72	2411	#define IGNORE_ZONE_CAL_MISSING_SAMPLES 0
charlesmn	0:0be0bd219e72	2412	#define IGNORE_ZONE_CAL_SIGMA_TOO_HIGH 0
charlesmn	0:0be0bd219e72	2413	#define IGNORE_ZONE_CAL_RATE_TOO_HIGH 0
charlesmn	0:0be0bd219e72	2414
charlesmn	0:0be0bd219e72	2415	#endif
charlesmn	0:0be0bd219e72	2416
charlesmn	0:0be0bd219e72	2417	// define from vl53lx_platform_user_defines.h
charlesmn	0:0be0bd219e72	2418
charlesmn	0:0be0bd219e72	2419	#define do_division_u(dividend, divisor) (dividend / divisor)
charlesmn	0:0be0bd219e72	2420
charlesmn	0:0be0bd219e72	2421	#define do_division_s(dividend, divisor) (dividend / divisor)
charlesmn	0:0be0bd219e72	2422
charlesmn	0:0be0bd219e72	2423
charlesmn	0:0be0bd219e72	2424
charlesmn	0:0be0bd219e72	2425	#ifdef _MSC_VER
charlesmn	0:0be0bd219e72	2426	#define DISABLE_WARNINGS() { \
charlesmn	0:0be0bd219e72	2427	__pragma(warning(push)); \
charlesmn	0:0be0bd219e72	2428	__pragma(warning(disable:4127)); \
charlesmn	0:0be0bd219e72	2429	}
charlesmn	0:0be0bd219e72	2430	#define ENABLE_WARNINGS() { \
charlesmn	0:0be0bd219e72	2431	__pragma(warning( pop )); \
charlesmn	0:0be0bd219e72	2432	}
charlesmn	0:0be0bd219e72	2433	#else
charlesmn	0:0be0bd219e72	2434
charlesmn	0:0be0bd219e72	2435
charlesmn	0:0be0bd219e72	2436	#define DISABLE_WARNINGS()
charlesmn	0:0be0bd219e72	2437	#define ENABLE_WARNINGS()
charlesmn	0:0be0bd219e72	2438	#endif
charlesmn	0:0be0bd219e72	2439
charlesmn	0:0be0bd219e72	2440
charlesmn	0:0be0bd219e72	2441
charlesmn	0:0be0bd219e72	2442
charlesmn	0:0be0bd219e72	2443	/vl53lx_register_settings.h/
charlesmn	0:0be0bd219e72	2444
charlesmn	0:0be0bd219e72	2445
charlesmn	0:0be0bd219e72	2446	#define VL53LX_DEVICESCHEDULERMODE_PSEUDO_SOLO 0x00
charlesmn	0:0be0bd219e72	2447	#define VL53LX_DEVICESCHEDULERMODE_STREAMING 0x01
charlesmn	0:0be0bd219e72	2448	#define VL53LX_DEVICESCHEDULERMODE_HISTOGRAM 0x02
charlesmn	0:0be0bd219e72	2449
charlesmn	0:0be0bd219e72	2450
charlesmn	0:0be0bd219e72	2451
charlesmn	0:0be0bd219e72	2452
charlesmn	0:0be0bd219e72	2453
charlesmn	0:0be0bd219e72	2454	#define VL53LX_DEVICEREADOUTMODE_SINGLE_SD (0x00 << 2)
charlesmn	0:0be0bd219e72	2455	#define VL53LX_DEVICEREADOUTMODE_DUAL_SD (0x01 << 2)
charlesmn	0:0be0bd219e72	2456	#define VL53LX_DEVICEREADOUTMODE_SPLIT_READOUT (0x02 << 2)
charlesmn	0:0be0bd219e72	2457	#define VL53LX_DEVICEREADOUTMODE_SPLIT_MANUAL (0x03 << 2)
charlesmn	0:0be0bd219e72	2458
charlesmn	0:0be0bd219e72	2459
charlesmn	0:0be0bd219e72	2460
charlesmn	0:0be0bd219e72	2461
charlesmn	0:0be0bd219e72	2462
charlesmn	0:0be0bd219e72	2463
charlesmn	0:0be0bd219e72	2464	#define VL53LX_DEVICEMEASUREMENTMODE_MODE_MASK 0xF0
charlesmn	0:0be0bd219e72	2465	#define VL53LX_DEVICEMEASUREMENTMODE_STOP_MASK 0x0F
charlesmn	0:0be0bd219e72	2466
charlesmn	0:0be0bd219e72	2467	#define VL53LX_GROUPEDPARAMETERHOLD_ID_MASK 0x02
charlesmn	0:0be0bd219e72	2468
charlesmn	0:0be0bd219e72	2469
charlesmn	0:0be0bd219e72	2470
charlesmn	0:0be0bd219e72	2471	#define VL53LX_EWOK_I2C_DEV_ADDR_DEFAULT 0x29
charlesmn	0:0be0bd219e72	2472
charlesmn	0:0be0bd219e72	2473	#define VL53LX_OSC_FREQUENCY 0x00
charlesmn	0:0be0bd219e72	2474	#define VL53LX_OSC_TRIM_DEFAULT 0x00
charlesmn	0:0be0bd219e72	2475	#define VL53LX_OSC_FREQ_SET_DEFAULT 0x00
charlesmn	0:0be0bd219e72	2476
charlesmn	0:0be0bd219e72	2477	#define VL53LX_RANGE_HISTOGRAM_REF 0x08
charlesmn	0:0be0bd219e72	2478	#define VL53LX_RANGE_HISTOGRAM_RET 0x10
charlesmn	0:0be0bd219e72	2479	#define VL53LX_RANGE_HISTOGRAM_BOTH 0x18
charlesmn	0:0be0bd219e72	2480	#define VL53LX_RANGE_HISTOGRAM_INIT 0x20
charlesmn	0:0be0bd219e72	2481	#define VL53LX_RANGE_VHV_INIT 0x40
charlesmn	0:0be0bd219e72	2482
charlesmn	0:0be0bd219e72	2483
charlesmn	0:0be0bd219e72	2484	#define VL53LX_RESULT_RANGE_STATUS 0x1F
charlesmn	0:0be0bd219e72	2485
charlesmn	0:0be0bd219e72	2486
charlesmn	0:0be0bd219e72	2487	#define VL53LX_SYSTEM__SEED_CONFIG__MANUAL 0x00
charlesmn	0:0be0bd219e72	2488	#define VL53LX_SYSTEM__SEED_CONFIG__STANDARD 0x01
charlesmn	0:0be0bd219e72	2489	#define VL53LX_SYSTEM__SEED_CONFIG__EVEN_UPDATE_ONLY 0x02
charlesmn	0:0be0bd219e72	2490
charlesmn	0:0be0bd219e72	2491
charlesmn	0:0be0bd219e72	2492	#define VL53LX_INTERRUPT_CONFIG_LEVEL_LOW 0x00
charlesmn	0:0be0bd219e72	2493	#define VL53LX_INTERRUPT_CONFIG_LEVEL_HIGH 0x01
charlesmn	0:0be0bd219e72	2494	#define VL53LX_INTERRUPT_CONFIG_OUT_OF_WINDOW 0x02
charlesmn	0:0be0bd219e72	2495	#define VL53LX_INTERRUPT_CONFIG_IN_WINDOW 0x03
charlesmn	0:0be0bd219e72	2496	#define VL53LX_INTERRUPT_CONFIG_NEW_SAMPLE_READY 0x20
charlesmn	0:0be0bd219e72	2497
charlesmn	0:0be0bd219e72	2498
charlesmn	0:0be0bd219e72	2499	#define VL53LX_CLEAR_RANGE_INT 0x01
charlesmn	0:0be0bd219e72	2500	#define VL53LX_CLEAR_ERROR_INT 0x02
charlesmn	0:0be0bd219e72	2501
charlesmn	0:0be0bd219e72	2502
charlesmn	0:0be0bd219e72	2503	#define VL53LX_SEQUENCE_VHV_EN 0x01
charlesmn	0:0be0bd219e72	2504	#define VL53LX_SEQUENCE_PHASECAL_EN 0x02
charlesmn	0:0be0bd219e72	2505	#define VL53LX_SEQUENCE_REFERENCE_PHASE_EN 0x04
charlesmn	0:0be0bd219e72	2506	#define VL53LX_SEQUENCE_DSS1_EN 0x08
charlesmn	0:0be0bd219e72	2507	#define VL53LX_SEQUENCE_DSS2_EN 0x10
charlesmn	0:0be0bd219e72	2508	#define VL53LX_SEQUENCE_MM1_EN 0x20
charlesmn	0:0be0bd219e72	2509	#define VL53LX_SEQUENCE_MM2_EN 0x40
charlesmn	0:0be0bd219e72	2510	#define VL53LX_SEQUENCE_RANGE_EN 0x80
charlesmn	0:0be0bd219e72	2511
charlesmn	0:0be0bd219e72	2512
charlesmn	0:0be0bd219e72	2513	#define VL53LX_DSS_CONTROL__ROI_SUBTRACT 0x20
charlesmn	0:0be0bd219e72	2514	#define VL53LX_DSS_CONTROL__ROI_INTERSECT 0x10
charlesmn	0:0be0bd219e72	2515
charlesmn	0:0be0bd219e72	2516	#define VL53LX_DSS_CONTROL__MODE_DISABLED 0x00
charlesmn	0:0be0bd219e72	2517	#define VL53LX_DSS_CONTROL__MODE_TARGET_RATE 0x01
charlesmn	0:0be0bd219e72	2518	#define VL53LX_DSS_CONTROL__MODE_EFFSPADS 0x02
charlesmn	0:0be0bd219e72	2519	#define VL53LX_DSS_CONTROL__MODE_BLOCKSELECT 0x03
charlesmn	0:0be0bd219e72	2520
charlesmn	0:0be0bd219e72	2521
charlesmn	0:0be0bd219e72	2522
charlesmn	0:0be0bd219e72	2523	#define VL53LX_RANGING_CORE__SPAD_READOUT__STANDARD 0x45
charlesmn	0:0be0bd219e72	2524	#define VL53LX_RANGING_CORE__SPAD_READOUT__RETURN_ARRAY_ONLY 0x05
charlesmn	0:0be0bd219e72	2525	#define VL53LX_RANGING_CORE__SPAD_READOUT__REFERENCE_ARRAY_ONLY 0x55
charlesmn	0:0be0bd219e72	2526	#define VL53LX_RANGING_CORE__SPAD_READOUT__RETURN_SPLIT_ARRAY 0x25
charlesmn	0:0be0bd219e72	2527	#define VL53LX_RANGING_CORE__SPAD_READOUT__CALIB_PULSES 0xF5
charlesmn	0:0be0bd219e72	2528
charlesmn	0:0be0bd219e72	2529
charlesmn	0:0be0bd219e72	2530	#define VL53LX_LASER_SAFETY__KEY_VALUE 0x6C
charlesmn	0:0be0bd219e72	2531
charlesmn	0:0be0bd219e72	2532
charlesmn	0:0be0bd219e72	2533
charlesmn	0:0be0bd219e72	2534	#define VL53LX_RANGE_STATUS__RANGE_STATUS_MASK 0x1F
charlesmn	0:0be0bd219e72	2535	#define VL53LX_RANGE_STATUS__MAX_THRESHOLD_HIT_MASK 0x20
charlesmn	0:0be0bd219e72	2536	#define VL53LX_RANGE_STATUS__MIN_THRESHOLD_HIT_MASK 0x40
charlesmn	0:0be0bd219e72	2537	#define VL53LX_RANGE_STATUS__GPH_ID_RANGE_STATUS_MASK 0x80
charlesmn	0:0be0bd219e72	2538
charlesmn	0:0be0bd219e72	2539
charlesmn	0:0be0bd219e72	2540
charlesmn	0:0be0bd219e72	2541	#define VL53LX_INTERRUPT_STATUS__INT_STATUS_MASK 0x07
charlesmn	0:0be0bd219e72	2542	#define VL53LX_INTERRUPT_STATUS__INT_ERROR_STATUS_MASK 0x18
charlesmn	0:0be0bd219e72	2543	#define VL53LX_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK 0x20
charlesmn	0:0be0bd219e72	2544
charlesmn	0:0be0bd219e72	2545
charlesmn	0:0be0bd219e72	2546	/* vl53lx_nvm_map.h */
charlesmn	0:0be0bd219e72	2547
charlesmn	0:0be0bd219e72	2548
charlesmn	0:0be0bd219e72	2549
charlesmn	0:0be0bd219e72	2550
charlesmn	0:0be0bd219e72	2551	#define VL53LX_NVM__IDENTIFICATION__MODEL_ID 0x0008
charlesmn	0:0be0bd219e72	2552
charlesmn	0:0be0bd219e72	2553	#define VL53LX_NVM__IDENTIFICATION__MODULE_TYPE 0x000C
charlesmn	0:0be0bd219e72	2554
charlesmn	0:0be0bd219e72	2555	#define VL53LX_NVM__IDENTIFICATION__REVISION_ID 0x000D
charlesmn	0:0be0bd219e72	2556
charlesmn	0:0be0bd219e72	2557	#define VL53LX_NVM__IDENTIFICATION__MODULE_ID 0x000E
charlesmn	0:0be0bd219e72	2558
charlesmn	0:0be0bd219e72	2559	#define VL53LX_NVM__I2C_VALID 0x0010
charlesmn	0:0be0bd219e72	2560
charlesmn	0:0be0bd219e72	2561	#define VL53LX_NVM__I2C_SLAVE__DEVICE_ADDRESS 0x0011
charlesmn	0:0be0bd219e72	2562
charlesmn	0:0be0bd219e72	2563	#define VL53LX_NVM__EWS__OSC_MEASURED__FAST_OSC_FREQUENCY 0x0014
charlesmn	0:0be0bd219e72	2564
charlesmn	0:0be0bd219e72	2565	#define VL53LX_NVM__EWS__FAST_OSC_TRIM_MAX 0x0016
charlesmn	0:0be0bd219e72	2566
charlesmn	0:0be0bd219e72	2567	#define VL53LX_NVM__EWS__FAST_OSC_FREQ_SET 0x0017
charlesmn	0:0be0bd219e72	2568
charlesmn	0:0be0bd219e72	2569	#define VL53LX_NVM__EWS__SLOW_OSC_CALIBRATION 0x0018
charlesmn	0:0be0bd219e72	2570
charlesmn	0:0be0bd219e72	2571	#define VL53LX_NVM__FMT__OSC_MEASURED__FAST_OSC_FREQUENCY 0x001C
charlesmn	0:0be0bd219e72	2572
charlesmn	0:0be0bd219e72	2573	#define VL53LX_NVM__FMT__FAST_OSC_TRIM_MAX 0x001E
charlesmn	0:0be0bd219e72	2574
charlesmn	0:0be0bd219e72	2575	#define VL53LX_NVM__FMT__FAST_OSC_FREQ_SET 0x001F
charlesmn	0:0be0bd219e72	2576
charlesmn	0:0be0bd219e72	2577	#define VL53LX_NVM__FMT__SLOW_OSC_CALIBRATION 0x0020
charlesmn	0:0be0bd219e72	2578
charlesmn	0:0be0bd219e72	2579	#define VL53LX_NVM__VHV_CONFIG_UNLOCK 0x0028
charlesmn	0:0be0bd219e72	2580
charlesmn	0:0be0bd219e72	2581	#define VL53LX_NVM__REF_SELVDDPIX 0x0029
charlesmn	0:0be0bd219e72	2582
charlesmn	0:0be0bd219e72	2583	#define VL53LX_NVM__REF_SELVQUENCH 0x002A
charlesmn	0:0be0bd219e72	2584
charlesmn	0:0be0bd219e72	2585	#define VL53LX_NVM__REGAVDD1V2_SEL_REGDVDD1V2_SEL 0x002B
charlesmn	0:0be0bd219e72	2586
charlesmn	0:0be0bd219e72	2587	#define VL53LX_NVM__VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x002C
charlesmn	0:0be0bd219e72	2588
charlesmn	0:0be0bd219e72	2589	#define VL53LX_NVM__VHV_CONFIG__COUNT_THRESH 0x002D
charlesmn	0:0be0bd219e72	2590
charlesmn	0:0be0bd219e72	2591	#define VL53LX_NVM__VHV_CONFIG__OFFSET 0x002E
charlesmn	0:0be0bd219e72	2592
charlesmn	0:0be0bd219e72	2593	#define VL53LX_NVM__VHV_CONFIG__INIT 0x002F
charlesmn	0:0be0bd219e72	2594
charlesmn	0:0be0bd219e72	2595	#define VL53LX_NVM__LASER_SAFETY__VCSEL_TRIM_LL 0x0030
charlesmn	0:0be0bd219e72	2596
charlesmn	0:0be0bd219e72	2597	#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_LL 0x0031
charlesmn	0:0be0bd219e72	2598
charlesmn	0:0be0bd219e72	2599	#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LL 0x0032
charlesmn	0:0be0bd219e72	2600
charlesmn	0:0be0bd219e72	2601	#define VL53LX_NVM__LASER_SAFETY__MULT_LL 0x0034
charlesmn	0:0be0bd219e72	2602
charlesmn	0:0be0bd219e72	2603	#define VL53LX_NVM__LASER_SAFETY__CLIP_LL 0x0035
charlesmn	0:0be0bd219e72	2604
charlesmn	0:0be0bd219e72	2605	#define VL53LX_NVM__LASER_SAFETY__VCSEL_TRIM_LD 0x0038
charlesmn	0:0be0bd219e72	2606
charlesmn	0:0be0bd219e72	2607	#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_LD 0x0039
charlesmn	0:0be0bd219e72	2608
charlesmn	0:0be0bd219e72	2609	#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LD 0x003A
charlesmn	0:0be0bd219e72	2610
charlesmn	0:0be0bd219e72	2611	#define VL53LX_NVM__LASER_SAFETY__MULT_LD 0x003C
charlesmn	0:0be0bd219e72	2612
charlesmn	0:0be0bd219e72	2613	#define VL53LX_NVM__LASER_SAFETY__CLIP_LD 0x003D
charlesmn	0:0be0bd219e72	2614
charlesmn	0:0be0bd219e72	2615	#define VL53LX_NVM__LASER_SAFETY_LOCK_BYTE 0x0040
charlesmn	0:0be0bd219e72	2616
charlesmn	0:0be0bd219e72	2617	#define VL53LX_NVM__LASER_SAFETY_UNLOCK_BYTE 0x0044
charlesmn	0:0be0bd219e72	2618
charlesmn	0:0be0bd219e72	2619	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_0_ 0x0048
charlesmn	0:0be0bd219e72	2620
charlesmn	0:0be0bd219e72	2621	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_1_ 0x0049
charlesmn	0:0be0bd219e72	2622
charlesmn	0:0be0bd219e72	2623	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_2_ 0x004A
charlesmn	0:0be0bd219e72	2624
charlesmn	0:0be0bd219e72	2625	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_3_ 0x004B
charlesmn	0:0be0bd219e72	2626
charlesmn	0:0be0bd219e72	2627	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_4_ 0x004C
charlesmn	0:0be0bd219e72	2628
charlesmn	0:0be0bd219e72	2629	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_5_ 0x004D
charlesmn	0:0be0bd219e72	2630
charlesmn	0:0be0bd219e72	2631	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_6_ 0x004E
charlesmn	0:0be0bd219e72	2632
charlesmn	0:0be0bd219e72	2633	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_7_ 0x004F
charlesmn	0:0be0bd219e72	2634
charlesmn	0:0be0bd219e72	2635	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_8_ 0x0050
charlesmn	0:0be0bd219e72	2636
charlesmn	0:0be0bd219e72	2637	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_9_ 0x0051
charlesmn	0:0be0bd219e72	2638
charlesmn	0:0be0bd219e72	2639	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_10_ 0x0052
charlesmn	0:0be0bd219e72	2640
charlesmn	0:0be0bd219e72	2641	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_11_ 0x0053
charlesmn	0:0be0bd219e72	2642
charlesmn	0:0be0bd219e72	2643	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_12_ 0x0054
charlesmn	0:0be0bd219e72	2644
charlesmn	0:0be0bd219e72	2645	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_13_ 0x0055
charlesmn	0:0be0bd219e72	2646
charlesmn	0:0be0bd219e72	2647	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_14_ 0x0056
charlesmn	0:0be0bd219e72	2648
charlesmn	0:0be0bd219e72	2649	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_15_ 0x0057
charlesmn	0:0be0bd219e72	2650
charlesmn	0:0be0bd219e72	2651	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_16_ 0x0058
charlesmn	0:0be0bd219e72	2652
charlesmn	0:0be0bd219e72	2653	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_17_ 0x0059
charlesmn	0:0be0bd219e72	2654
charlesmn	0:0be0bd219e72	2655	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_18_ 0x005A
charlesmn	0:0be0bd219e72	2656
charlesmn	0:0be0bd219e72	2657	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_19_ 0x005B
charlesmn	0:0be0bd219e72	2658
charlesmn	0:0be0bd219e72	2659	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_20_ 0x005C
charlesmn	0:0be0bd219e72	2660
charlesmn	0:0be0bd219e72	2661	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_21_ 0x005D
charlesmn	0:0be0bd219e72	2662
charlesmn	0:0be0bd219e72	2663	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_22_ 0x005E
charlesmn	0:0be0bd219e72	2664
charlesmn	0:0be0bd219e72	2665	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_23_ 0x005F
charlesmn	0:0be0bd219e72	2666
charlesmn	0:0be0bd219e72	2667	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_24_ 0x0060
charlesmn	0:0be0bd219e72	2668
charlesmn	0:0be0bd219e72	2669	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_25_ 0x0061
charlesmn	0:0be0bd219e72	2670
charlesmn	0:0be0bd219e72	2671	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_26_ 0x0062
charlesmn	0:0be0bd219e72	2672
charlesmn	0:0be0bd219e72	2673	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_27_ 0x0063
charlesmn	0:0be0bd219e72	2674
charlesmn	0:0be0bd219e72	2675	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_28_ 0x0064
charlesmn	0:0be0bd219e72	2676
charlesmn	0:0be0bd219e72	2677	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_29_ 0x0065
charlesmn	0:0be0bd219e72	2678
charlesmn	0:0be0bd219e72	2679	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_30_ 0x0066
charlesmn	0:0be0bd219e72	2680
charlesmn	0:0be0bd219e72	2681	#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_31_ 0x0067
charlesmn	0:0be0bd219e72	2682
charlesmn	0:0be0bd219e72	2683	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_0_ 0x0068
charlesmn	0:0be0bd219e72	2684
charlesmn	0:0be0bd219e72	2685	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_1_ 0x0069
charlesmn	0:0be0bd219e72	2686
charlesmn	0:0be0bd219e72	2687	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_2_ 0x006A
charlesmn	0:0be0bd219e72	2688
charlesmn	0:0be0bd219e72	2689	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_3_ 0x006B
charlesmn	0:0be0bd219e72	2690
charlesmn	0:0be0bd219e72	2691	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_4_ 0x006C
charlesmn	0:0be0bd219e72	2692
charlesmn	0:0be0bd219e72	2693	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_5_ 0x006D
charlesmn	0:0be0bd219e72	2694
charlesmn	0:0be0bd219e72	2695	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_0_ 0x0070
charlesmn	0:0be0bd219e72	2696
charlesmn	0:0be0bd219e72	2697	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_1_ 0x0071
charlesmn	0:0be0bd219e72	2698
charlesmn	0:0be0bd219e72	2699	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_2_ 0x0072
charlesmn	0:0be0bd219e72	2700
charlesmn	0:0be0bd219e72	2701	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_3_ 0x0073
charlesmn	0:0be0bd219e72	2702
charlesmn	0:0be0bd219e72	2703	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_4_ 0x0074
charlesmn	0:0be0bd219e72	2704
charlesmn	0:0be0bd219e72	2705	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_5_ 0x0075
charlesmn	0:0be0bd219e72	2706
charlesmn	0:0be0bd219e72	2707	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_0_ 0x0078
charlesmn	0:0be0bd219e72	2708
charlesmn	0:0be0bd219e72	2709	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_1_ 0x0079
charlesmn	0:0be0bd219e72	2710
charlesmn	0:0be0bd219e72	2711	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_2_ 0x007A
charlesmn	0:0be0bd219e72	2712
charlesmn	0:0be0bd219e72	2713	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_3_ 0x007B
charlesmn	0:0be0bd219e72	2714
charlesmn	0:0be0bd219e72	2715	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_4_ 0x007C
charlesmn	0:0be0bd219e72	2716
charlesmn	0:0be0bd219e72	2717	#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_5_ 0x007D
charlesmn	0:0be0bd219e72	2718
charlesmn	0:0be0bd219e72	2719	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_0_ 0x0080
charlesmn	0:0be0bd219e72	2720
charlesmn	0:0be0bd219e72	2721	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_1_ 0x0081
charlesmn	0:0be0bd219e72	2722
charlesmn	0:0be0bd219e72	2723	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_2_ 0x0082
charlesmn	0:0be0bd219e72	2724
charlesmn	0:0be0bd219e72	2725	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_3_ 0x0083
charlesmn	0:0be0bd219e72	2726
charlesmn	0:0be0bd219e72	2727	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_4_ 0x0084
charlesmn	0:0be0bd219e72	2728
charlesmn	0:0be0bd219e72	2729	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_5_ 0x0085
charlesmn	0:0be0bd219e72	2730
charlesmn	0:0be0bd219e72	2731	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_6_ 0x0086
charlesmn	0:0be0bd219e72	2732
charlesmn	0:0be0bd219e72	2733	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_7_ 0x0087
charlesmn	0:0be0bd219e72	2734
charlesmn	0:0be0bd219e72	2735	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_8_ 0x0088
charlesmn	0:0be0bd219e72	2736
charlesmn	0:0be0bd219e72	2737	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_9_ 0x0089
charlesmn	0:0be0bd219e72	2738
charlesmn	0:0be0bd219e72	2739	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_10_ 0x008A
charlesmn	0:0be0bd219e72	2740
charlesmn	0:0be0bd219e72	2741	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_11_ 0x008B
charlesmn	0:0be0bd219e72	2742
charlesmn	0:0be0bd219e72	2743	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_12_ 0x008C
charlesmn	0:0be0bd219e72	2744
charlesmn	0:0be0bd219e72	2745	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_13_ 0x008D
charlesmn	0:0be0bd219e72	2746
charlesmn	0:0be0bd219e72	2747	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_14_ 0x008E
charlesmn	0:0be0bd219e72	2748
charlesmn	0:0be0bd219e72	2749	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_15_ 0x008F
charlesmn	0:0be0bd219e72	2750
charlesmn	0:0be0bd219e72	2751	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_16_ 0x0090
charlesmn	0:0be0bd219e72	2752
charlesmn	0:0be0bd219e72	2753	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_17_ 0x0091
charlesmn	0:0be0bd219e72	2754
charlesmn	0:0be0bd219e72	2755	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_18_ 0x0092
charlesmn	0:0be0bd219e72	2756
charlesmn	0:0be0bd219e72	2757	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_19_ 0x0093
charlesmn	0:0be0bd219e72	2758
charlesmn	0:0be0bd219e72	2759	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_20_ 0x0094
charlesmn	0:0be0bd219e72	2760
charlesmn	0:0be0bd219e72	2761	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_21_ 0x0095
charlesmn	0:0be0bd219e72	2762
charlesmn	0:0be0bd219e72	2763	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_22_ 0x0096
charlesmn	0:0be0bd219e72	2764
charlesmn	0:0be0bd219e72	2765	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_23_ 0x0097
charlesmn	0:0be0bd219e72	2766
charlesmn	0:0be0bd219e72	2767	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_24_ 0x0098
charlesmn	0:0be0bd219e72	2768
charlesmn	0:0be0bd219e72	2769	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_25_ 0x0099
charlesmn	0:0be0bd219e72	2770
charlesmn	0:0be0bd219e72	2771	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_26_ 0x009A
charlesmn	0:0be0bd219e72	2772
charlesmn	0:0be0bd219e72	2773	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_27_ 0x009B
charlesmn	0:0be0bd219e72	2774
charlesmn	0:0be0bd219e72	2775	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_28_ 0x009C
charlesmn	0:0be0bd219e72	2776
charlesmn	0:0be0bd219e72	2777	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_29_ 0x009D
charlesmn	0:0be0bd219e72	2778
charlesmn	0:0be0bd219e72	2779	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_30_ 0x009E
charlesmn	0:0be0bd219e72	2780
charlesmn	0:0be0bd219e72	2781	#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_31_ 0x009F
charlesmn	0:0be0bd219e72	2782
charlesmn	0:0be0bd219e72	2783	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_0_ 0x00A0
charlesmn	0:0be0bd219e72	2784
charlesmn	0:0be0bd219e72	2785	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_1_ 0x00A1
charlesmn	0:0be0bd219e72	2786
charlesmn	0:0be0bd219e72	2787	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_2_ 0x00A2
charlesmn	0:0be0bd219e72	2788
charlesmn	0:0be0bd219e72	2789	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_3_ 0x00A3
charlesmn	0:0be0bd219e72	2790
charlesmn	0:0be0bd219e72	2791	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_4_ 0x00A4
charlesmn	0:0be0bd219e72	2792
charlesmn	0:0be0bd219e72	2793	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_5_ 0x00A5
charlesmn	0:0be0bd219e72	2794
charlesmn	0:0be0bd219e72	2795	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_0_ 0x00A8
charlesmn	0:0be0bd219e72	2796
charlesmn	0:0be0bd219e72	2797	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_1_ 0x00A9
charlesmn	0:0be0bd219e72	2798
charlesmn	0:0be0bd219e72	2799	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_2_ 0x00AA
charlesmn	0:0be0bd219e72	2800
charlesmn	0:0be0bd219e72	2801	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_3_ 0x00AB
charlesmn	0:0be0bd219e72	2802
charlesmn	0:0be0bd219e72	2803	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_4_ 0x00AC
charlesmn	0:0be0bd219e72	2804
charlesmn	0:0be0bd219e72	2805	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_5_ 0x00AD
charlesmn	0:0be0bd219e72	2806
charlesmn	0:0be0bd219e72	2807	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_0_ 0x00B0
charlesmn	0:0be0bd219e72	2808
charlesmn	0:0be0bd219e72	2809	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_1_ 0x00B1
charlesmn	0:0be0bd219e72	2810
charlesmn	0:0be0bd219e72	2811	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_2_ 0x00B2
charlesmn	0:0be0bd219e72	2812
charlesmn	0:0be0bd219e72	2813	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_3_ 0x00B3
charlesmn	0:0be0bd219e72	2814
charlesmn	0:0be0bd219e72	2815	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_4_ 0x00B4
charlesmn	0:0be0bd219e72	2816
charlesmn	0:0be0bd219e72	2817	#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_5_ 0x00B5
charlesmn	0:0be0bd219e72	2818
charlesmn	0:0be0bd219e72	2819	#define VL53LX_NVM__FMT__ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x00B8
charlesmn	0:0be0bd219e72	2820
charlesmn	0:0be0bd219e72	2821	#define VL53LX_NVM__FMT__ROI_CONFIG__MODE_ROI_XY_SIZE 0x00B9
charlesmn	0:0be0bd219e72	2822
charlesmn	0:0be0bd219e72	2823	#define VL53LX_NVM__FMT__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00BC
charlesmn	0:0be0bd219e72	2824
charlesmn	0:0be0bd219e72	2825	#define VL53LX_NVM__FMT__REF_SPAD_MAN__REF_LOCATION 0x00BD
charlesmn	0:0be0bd219e72	2826
charlesmn	0:0be0bd219e72	2827	#define VL53LX_NVM__FMT__MM_CONFIG__INNER_OFFSET_MM 0x00C0
charlesmn	0:0be0bd219e72	2828
charlesmn	0:0be0bd219e72	2829	#define VL53LX_NVM__FMT__MM_CONFIG__OUTER_OFFSET_MM 0x00C2
charlesmn	0:0be0bd219e72	2830
charlesmn	0:0be0bd219e72	2831	#define VL53LX_NVM__FMT__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00C4
charlesmn	0:0be0bd219e72	2832
charlesmn	0:0be0bd219e72	2833	#define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00C8
charlesmn	0:0be0bd219e72	2834
charlesmn	0:0be0bd219e72	2835	#define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS \
charlesmn	0:0be0bd219e72	2836	0x00CA
charlesmn	0:0be0bd219e72	2837
charlesmn	0:0be0bd219e72	2838	#define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS \
charlesmn	0:0be0bd219e72	2839	0x00CC
charlesmn	0:0be0bd219e72	2840
charlesmn	0:0be0bd219e72	2841	#define VL53LX_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00CE
charlesmn	0:0be0bd219e72	2842
charlesmn	0:0be0bd219e72	2843	#define VL53LX_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00CF
charlesmn	0:0be0bd219e72	2844
charlesmn	0:0be0bd219e72	2845	#define VL53LX_NVM__CUSTOMER_NVM_SPACE_PROGRAMMED 0x00E0
charlesmn	0:0be0bd219e72	2846
charlesmn	0:0be0bd219e72	2847	#define VL53LX_NVM__CUST__I2C_SLAVE__DEVICE_ADDRESS 0x00E4
charlesmn	0:0be0bd219e72	2848
charlesmn	0:0be0bd219e72	2849	#define VL53LX_NVM__CUST__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00E8
charlesmn	0:0be0bd219e72	2850
charlesmn	0:0be0bd219e72	2851	#define VL53LX_NVM__CUST__REF_SPAD_MAN__REF_LOCATION 0x00E9
charlesmn	0:0be0bd219e72	2852
charlesmn	0:0be0bd219e72	2853	#define VL53LX_NVM__CUST__MM_CONFIG__INNER_OFFSET_MM 0x00EC
charlesmn	0:0be0bd219e72	2854
charlesmn	0:0be0bd219e72	2855	#define VL53LX_NVM__CUST__MM_CONFIG__OUTER_OFFSET_MM 0x00EE
charlesmn	0:0be0bd219e72	2856
charlesmn	0:0be0bd219e72	2857	#define VL53LX_NVM__CUST__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00F0
charlesmn	0:0be0bd219e72	2858
charlesmn	0:0be0bd219e72	2859	#define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00F4
charlesmn	0:0be0bd219e72	2860
charlesmn	0:0be0bd219e72	2861	#define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS \
charlesmn	0:0be0bd219e72	2862	0x00F6
charlesmn	0:0be0bd219e72	2863
charlesmn	0:0be0bd219e72	2864	#define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS \
charlesmn	0:0be0bd219e72	2865	0x00F8
charlesmn	0:0be0bd219e72	2866
charlesmn	0:0be0bd219e72	2867	#define VL53LX_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00FA
charlesmn	0:0be0bd219e72	2868
charlesmn	0:0be0bd219e72	2869	#define VL53LX_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00FB
charlesmn	0:0be0bd219e72	2870
charlesmn	0:0be0bd219e72	2871	#define VL53LX_NVM__FMT__FGC__BYTE_0 0x01DC
charlesmn	0:0be0bd219e72	2872
charlesmn	0:0be0bd219e72	2873	#define VL53LX_NVM__FMT__FGC__BYTE_1 0x01DD
charlesmn	0:0be0bd219e72	2874
charlesmn	0:0be0bd219e72	2875	#define VL53LX_NVM__FMT__FGC__BYTE_2 0x01DE
charlesmn	0:0be0bd219e72	2876
charlesmn	0:0be0bd219e72	2877	#define VL53LX_NVM__FMT__FGC__BYTE_3 0x01DF
charlesmn	0:0be0bd219e72	2878
charlesmn	0:0be0bd219e72	2879	#define VL53LX_NVM__FMT__FGC__BYTE_4 0x01E0
charlesmn	0:0be0bd219e72	2880
charlesmn	0:0be0bd219e72	2881	#define VL53LX_NVM__FMT__FGC__BYTE_5 0x01E1
charlesmn	0:0be0bd219e72	2882
charlesmn	0:0be0bd219e72	2883	#define VL53LX_NVM__FMT__FGC__BYTE_6 0x01E2
charlesmn	0:0be0bd219e72	2884
charlesmn	0:0be0bd219e72	2885	#define VL53LX_NVM__FMT__FGC__BYTE_7 0x01E3
charlesmn	0:0be0bd219e72	2886
charlesmn	0:0be0bd219e72	2887	#define VL53LX_NVM__FMT__FGC__BYTE_8 0x01E4
charlesmn	0:0be0bd219e72	2888
charlesmn	0:0be0bd219e72	2889	#define VL53LX_NVM__FMT__FGC__BYTE_9 0x01E5
charlesmn	0:0be0bd219e72	2890
charlesmn	0:0be0bd219e72	2891	#define VL53LX_NVM__FMT__FGC__BYTE_10 0x01E6
charlesmn	0:0be0bd219e72	2892
charlesmn	0:0be0bd219e72	2893	#define VL53LX_NVM__FMT__FGC__BYTE_11 0x01E7
charlesmn	0:0be0bd219e72	2894
charlesmn	0:0be0bd219e72	2895	#define VL53LX_NVM__FMT__FGC__BYTE_12 0x01E8
charlesmn	0:0be0bd219e72	2896
charlesmn	0:0be0bd219e72	2897	#define VL53LX_NVM__FMT__FGC__BYTE_13 0x01E9
charlesmn	0:0be0bd219e72	2898
charlesmn	0:0be0bd219e72	2899	#define VL53LX_NVM__FMT__FGC__BYTE_14 0x01EA
charlesmn	0:0be0bd219e72	2900
charlesmn	0:0be0bd219e72	2901	#define VL53LX_NVM__FMT__FGC__BYTE_15 0x01EB
charlesmn	0:0be0bd219e72	2902
charlesmn	0:0be0bd219e72	2903	#define VL53LX_NVM__FMT__TEST_PROGRAM_MAJOR_MINOR 0x01EC
charlesmn	0:0be0bd219e72	2904
charlesmn	0:0be0bd219e72	2905	#define VL53LX_NVM__FMT__MAP_MAJOR_MINOR 0x01ED
charlesmn	0:0be0bd219e72	2906
charlesmn	0:0be0bd219e72	2907	#define VL53LX_NVM__FMT__YEAR_MONTH 0x01EE
charlesmn	0:0be0bd219e72	2908
charlesmn	0:0be0bd219e72	2909	#define VL53LX_NVM__FMT__DAY_MODULE_DATE_PHASE 0x01EF
charlesmn	0:0be0bd219e72	2910
charlesmn	0:0be0bd219e72	2911	#define VL53LX_NVM__FMT__TIME 0x01F0
charlesmn	0:0be0bd219e72	2912
charlesmn	0:0be0bd219e72	2913	#define VL53LX_NVM__FMT__TESTER_ID 0x01F2
charlesmn	0:0be0bd219e72	2914
charlesmn	0:0be0bd219e72	2915	#define VL53LX_NVM__FMT__SITE_ID 0x01F3
charlesmn	0:0be0bd219e72	2916
charlesmn	0:0be0bd219e72	2917	#define VL53LX_NVM__EWS__TEST_PROGRAM_MAJOR_MINOR 0x01F4
charlesmn	0:0be0bd219e72	2918
charlesmn	0:0be0bd219e72	2919	#define VL53LX_NVM__EWS__PROBE_CARD_MAJOR_MINOR 0x01F5
charlesmn	0:0be0bd219e72	2920
charlesmn	0:0be0bd219e72	2921	#define VL53LX_NVM__EWS__TESTER_ID 0x01F6
charlesmn	0:0be0bd219e72	2922
charlesmn	0:0be0bd219e72	2923	#define VL53LX_NVM__EWS__LOT__BYTE_0 0x01F8
charlesmn	0:0be0bd219e72	2924
charlesmn	0:0be0bd219e72	2925	#define VL53LX_NVM__EWS__LOT__BYTE_1 0x01F9
charlesmn	0:0be0bd219e72	2926
charlesmn	0:0be0bd219e72	2927	#define VL53LX_NVM__EWS__LOT__BYTE_2 0x01FA
charlesmn	0:0be0bd219e72	2928
charlesmn	0:0be0bd219e72	2929	#define VL53LX_NVM__EWS__LOT__BYTE_3 0x01FB
charlesmn	0:0be0bd219e72	2930
charlesmn	0:0be0bd219e72	2931	#define VL53LX_NVM__EWS__LOT__BYTE_4 0x01FC
charlesmn	0:0be0bd219e72	2932
charlesmn	0:0be0bd219e72	2933	#define VL53LX_NVM__EWS__LOT__BYTE_5 0x01FD
charlesmn	0:0be0bd219e72	2934
charlesmn	0:0be0bd219e72	2935	#define VL53LX_NVM__EWS__WAFER 0x01FD
charlesmn	0:0be0bd219e72	2936
charlesmn	0:0be0bd219e72	2937	#define VL53LX_NVM__EWS__XCOORD 0x01FE
charlesmn	0:0be0bd219e72	2938
charlesmn	0:0be0bd219e72	2939	#define VL53LX_NVM__EWS__YCOORD 0x01FF
charlesmn	0:0be0bd219e72	2940
charlesmn	0:0be0bd219e72	2941
charlesmn	0:0be0bd219e72	2942	#define VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_INDEX 0x00B8
charlesmn	0:0be0bd219e72	2943	#define VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE 4
charlesmn	0:0be0bd219e72	2944
charlesmn	0:0be0bd219e72	2945	#define VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_INDEX 0x015C
charlesmn	0:0be0bd219e72	2946	#define VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE 56
charlesmn	0:0be0bd219e72	2947
charlesmn	0:0be0bd219e72	2948	#define VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_INDEX 0x0194
charlesmn	0:0be0bd219e72	2949	#define VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE 8
charlesmn	0:0be0bd219e72	2950
charlesmn	0:0be0bd219e72	2951	#define VL53LX_NVM__FMT__RANGE_RESULTS__140MM_MM_PRE_RANGE 0x019C
charlesmn	0:0be0bd219e72	2952	#define VL53LX_NVM__FMT__RANGE_RESULTS__140MM_DARK 0x01AC
charlesmn	0:0be0bd219e72	2953	#define VL53LX_NVM__FMT__RANGE_RESULTS__400MM_DARK 0x01BC
charlesmn	0:0be0bd219e72	2954	#define VL53LX_NVM__FMT__RANGE_RESULTS__400MM_AMBIENT 0x01CC
charlesmn	0:0be0bd219e72	2955	#define VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES 16
charlesmn	0:0be0bd219e72	2956
charlesmn	0:0be0bd219e72	2957
charlesmn	0:0be0bd219e72	2958
charlesmn	0:0be0bd219e72	2959
charlesmn	0:0be0bd219e72	2960
charlesmn	0:0be0bd219e72	2961
charlesmn	0:0be0bd219e72	2962	/* vl53lx_tuning_parm_defaults.h */
charlesmn	0:0be0bd219e72	2963
charlesmn	0:0be0bd219e72	2964
charlesmn	0:0be0bd219e72	2965
charlesmn	0:0be0bd219e72	2966	#define VL53LX_TUNINGPARM_VERSION_DEFAULT \
charlesmn	0:0be0bd219e72	2967	((uint16_t) 29)
charlesmn	0:0be0bd219e72	2968	#define VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT \
charlesmn	0:0be0bd219e72	2969	((uint16_t) 14)
charlesmn	0:0be0bd219e72	2970	#define VL53LX_TUNINGPARM_LLD_VERSION_DEFAULT \
charlesmn	0:0be0bd219e72	2971	((uint16_t) 12180)
charlesmn	0:0be0bd219e72	2972	#define VL53LX_TUNINGPARM_HIST_ALGO_SELECT_DEFAULT \
charlesmn	0:0be0bd219e72	2973	((uint8_t) 4)
charlesmn	0:0be0bd219e72	2974	#define VL53LX_TUNINGPARM_HIST_TARGET_ORDER_DEFAULT \
charlesmn	0:0be0bd219e72	2975	((uint8_t) 1)
charlesmn	0:0be0bd219e72	2976	#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_0_DEFAULT \
charlesmn	0:0be0bd219e72	2977	((uint8_t) 1)
charlesmn	0:0be0bd219e72	2978	#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_1_DEFAULT \
charlesmn	0:0be0bd219e72	2979	((uint8_t) 2)
charlesmn	0:0be0bd219e72	2980	#define VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD_DEFAULT \
charlesmn	0:0be0bd219e72	2981	((uint8_t) 1)
charlesmn	0:0be0bd219e72	2982	#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0_DEFAULT \
charlesmn	0:0be0bd219e72	2983	((uint8_t) 80)
charlesmn	0:0be0bd219e72	2984	#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1_DEFAULT \
charlesmn	0:0be0bd219e72	2985	((uint8_t) 100)
charlesmn	0:0be0bd219e72	2986	#define VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS_DEFAULT \
charlesmn	0:0be0bd219e72	2987	((int32_t) 16)
charlesmn	0:0be0bd219e72	2988	#define VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER_DEFAULT \
charlesmn	0:0be0bd219e72	2989	((uint16_t) 4157)
charlesmn	0:0be0bd219e72	2990	#define VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD_DEFAULT \
charlesmn	0:0be0bd219e72	2991	((uint16_t) 50)
charlesmn	0:0be0bd219e72	2992	#define VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT_DEFAULT \
charlesmn	0:0be0bd219e72	2993	((int32_t) 100)
charlesmn	0:0be0bd219e72	2994	#define VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM_DEFAULT \
charlesmn	0:0be0bd219e72	2995	((uint8_t) 1)
charlesmn	0:0be0bd219e72	2996	#define VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM_DEFAULT \
charlesmn	0:0be0bd219e72	2997	((uint16_t) 180)
charlesmn	0:0be0bd219e72	2998	#define VL53LX_TUNINGPARM_HIST_GAIN_FACTOR_DEFAULT \
charlesmn	0:0be0bd219e72	2999	((uint16_t) 1987)
charlesmn	0:0be0bd219e72	3000	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE_DEFAULT \
charlesmn	0:0be0bd219e72	3001	((uint8_t) 8)
charlesmn	0:0be0bd219e72	3002	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3003	((uint16_t) 0)
charlesmn	0:0be0bd219e72	3004	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_DEFAULT \
charlesmn	0:0be0bd219e72	3005	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3006	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT_DEFAULT \
charlesmn	0:0be0bd219e72	3007	((uint16_t) 2048)
charlesmn	0:0be0bd219e72	3008	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3009	((uint8_t) 9)
charlesmn	0:0be0bd219e72	3010	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3011	((uint8_t) 5)
charlesmn	0:0be0bd219e72	3012	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3013	((uint8_t) 3)
charlesmn	0:0be0bd219e72	3014	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3015	((uint8_t) 6)
charlesmn	0:0be0bd219e72	3016	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3017	((uint8_t) 6)
charlesmn	0:0be0bd219e72	3018	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3019	((uint8_t) 6)
charlesmn	0:0be0bd219e72	3020	#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3021	((int16_t) -50)
charlesmn	0:0be0bd219e72	3022	#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3023	((int16_t) 50)
charlesmn	0:0be0bd219e72	3024	#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3025	((uint16_t) 140)
charlesmn	0:0be0bd219e72	3026	#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE_DEFAULT \
charlesmn	0:0be0bd219e72	3027	((uint16_t) 50)
charlesmn	0:0be0bd219e72	3028	#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3029	((uint16_t) 400)
charlesmn	0:0be0bd219e72	3030	#define VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA_DEFAULT \
charlesmn	0:0be0bd219e72	3031	((uint8_t) 80)
charlesmn	0:0be0bd219e72	3032	#define VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3033	((int16_t) 0)
charlesmn	0:0be0bd219e72	3034	#define VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE_DEFAULT \
charlesmn	0:0be0bd219e72	3035	((uint8_t) 2)
charlesmn	0:0be0bd219e72	3036	#define VL53LX_TUNINGPARM_PHASECAL_TARGET_DEFAULT \
charlesmn	0:0be0bd219e72	3037	((uint8_t) 33)
charlesmn	0:0be0bd219e72	3038	#define VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE_DEFAULT \
charlesmn	0:0be0bd219e72	3039	((uint16_t) 0)
charlesmn	0:0be0bd219e72	3040	#define VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR_DEFAULT \
charlesmn	0:0be0bd219e72	3041	((uint16_t) 2011)
charlesmn	0:0be0bd219e72	3042	#define VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3043	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3044	#define VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3045	((uint16_t) 60)
charlesmn	0:0be0bd219e72	3046	#define VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3047	((uint16_t) 60)
charlesmn	0:0be0bd219e72	3048	#define VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3049	((uint16_t) 60)
charlesmn	0:0be0bd219e72	3050	#define VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3051	((uint16_t) 128)
charlesmn	0:0be0bd219e72	3052	#define VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3053	((uint16_t) 128)
charlesmn	0:0be0bd219e72	3054	#define VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3055	((uint16_t) 128)
charlesmn	0:0be0bd219e72	3056	#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH_DEFAULT \
charlesmn	0:0be0bd219e72	3057	((uint8_t) 8)
charlesmn	0:0be0bd219e72	3058	#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS_DEFAULT \
charlesmn	0:0be0bd219e72	3059	((uint8_t) 16)
charlesmn	0:0be0bd219e72	3060	#define VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3061	((uint8_t) 1)
charlesmn	0:0be0bd219e72	3062	#define VL53LX_TUNINGPARM_LITE_RIT_MULT_DEFAULT \
charlesmn	0:0be0bd219e72	3063	((uint8_t) 64)
charlesmn	0:0be0bd219e72	3064	#define VL53LX_TUNINGPARM_LITE_SEED_CONFIG_DEFAULT \
charlesmn	0:0be0bd219e72	3065	((uint8_t) 2)
charlesmn	0:0be0bd219e72	3066	#define VL53LX_TUNINGPARM_LITE_QUANTIFIER_DEFAULT \
charlesmn	0:0be0bd219e72	3067	((uint8_t) 2)
charlesmn	0:0be0bd219e72	3068	#define VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT_DEFAULT \
charlesmn	0:0be0bd219e72	3069	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3070	#define VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3071	((int16_t) 0)
charlesmn	0:0be0bd219e72	3072	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3073	((uint8_t) 14)
charlesmn	0:0be0bd219e72	3074	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3075	((uint8_t) 10)
charlesmn	0:0be0bd219e72	3076	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3077	((uint8_t) 6)
charlesmn	0:0be0bd219e72	3078	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3079	((uint8_t) 14)
charlesmn	0:0be0bd219e72	3080	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3081	((uint8_t) 10)
charlesmn	0:0be0bd219e72	3082	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE_DEFAULT \
charlesmn	0:0be0bd219e72	3083	((uint8_t) 6)
charlesmn	0:0be0bd219e72	3084	#define VL53LX_TUNINGPARM_TIMED_SEED_CONFIG_DEFAULT \
charlesmn	0:0be0bd219e72	3085	((uint8_t) 1)
charlesmn	0:0be0bd219e72	3086	#define VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA_DEFAULT \
charlesmn	0:0be0bd219e72	3087	((uint8_t) 32)
charlesmn	0:0be0bd219e72	3088	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0_DEFAULT \
charlesmn	0:0be0bd219e72	3089	((uint16_t) 15)
charlesmn	0:0be0bd219e72	3090	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1_DEFAULT \
charlesmn	0:0be0bd219e72	3091	((uint16_t) 52)
charlesmn	0:0be0bd219e72	3092	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2_DEFAULT \
charlesmn	0:0be0bd219e72	3093	((uint16_t) 200)
charlesmn	0:0be0bd219e72	3094	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3_DEFAULT \
charlesmn	0:0be0bd219e72	3095	((uint16_t) 364)
charlesmn	0:0be0bd219e72	3096	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4_DEFAULT \
charlesmn	0:0be0bd219e72	3097	((uint16_t) 400)
charlesmn	0:0be0bd219e72	3098	#define VL53LX_TUNINGPARM_VHV_LOOPBOUND_DEFAULT \
charlesmn	0:0be0bd219e72	3099	((uint8_t) 129)
charlesmn	0:0be0bd219e72	3100	#define VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE_DEFAULT \
charlesmn	0:0be0bd219e72	3101	((uint8_t) 8)
charlesmn	0:0be0bd219e72	3102	#define VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD_DEFAULT \
charlesmn	0:0be0bd219e72	3103	((uint8_t) 11)
charlesmn	0:0be0bd219e72	3104	#define VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3105	((uint32_t) 1000)
charlesmn	0:0be0bd219e72	3106	#define VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3107	((uint16_t) 2560)
charlesmn	0:0be0bd219e72	3108	#define VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3109	((uint16_t) 1280)
charlesmn	0:0be0bd219e72	3110	#define VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3111	((uint16_t) 5120)
charlesmn	0:0be0bd219e72	3112	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES_DEFAULT \
charlesmn	0:0be0bd219e72	3113	((uint8_t) 7)
charlesmn	0:0be0bd219e72	3114	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3115	((int16_t) -70)
charlesmn	0:0be0bd219e72	3116	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3117	((int16_t) 70)
charlesmn	0:0be0bd219e72	3118	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3119	((uint16_t) 5120)
charlesmn	0:0be0bd219e72	3120	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3121	((uint32_t) 15000)
charlesmn	0:0be0bd219e72	3122	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3123	((uint16_t) 640)
charlesmn	0:0be0bd219e72	3124	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3125	((uint16_t) 140)
charlesmn	0:0be0bd219e72	3126	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3127	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3128	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3129	((uint32_t) 10000)
charlesmn	0:0be0bd219e72	3130	#define VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3131	((uint16_t) 2560)
charlesmn	0:0be0bd219e72	3132	#define VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3133	((uint32_t) 15000)
charlesmn	0:0be0bd219e72	3134	#define VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3135	((uint32_t) 13000)
charlesmn	0:0be0bd219e72	3136	#define VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3137	((uint32_t) 13000)
charlesmn	0:0be0bd219e72	3138	#define VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES_DEFAULT \
charlesmn	0:0be0bd219e72	3139	((uint8_t) 8)
charlesmn	0:0be0bd219e72	3140	#define VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES_DEFAULT \
charlesmn	0:0be0bd219e72	3141	((uint8_t) 40)
charlesmn	0:0be0bd219e72	3142	#define VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES_DEFAULT \
charlesmn	0:0be0bd219e72	3143	((uint8_t) 9)
charlesmn	0:0be0bd219e72	3144	#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3145	((uint16_t) 5120)
charlesmn	0:0be0bd219e72	3146	#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3147	((uint32_t) 15000)
charlesmn	0:0be0bd219e72	3148	#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3149	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3150	#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES_DEFAULT \
charlesmn	0:0be0bd219e72	3151	((uint16_t) 16)
charlesmn	0:0be0bd219e72	3152	#define VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3153	((uint32_t) 1000)
charlesmn	0:0be0bd219e72	3154	#define VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES_DEFAULT \
charlesmn	0:0be0bd219e72	3155	((uint16_t) 8)
charlesmn	0:0be0bd219e72	3156	#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD_DEFAULT \
charlesmn	0:0be0bd219e72	3157	((uint8_t) 18)
charlesmn	0:0be0bd219e72	3158	#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_START_DEFAULT \
charlesmn	0:0be0bd219e72	3159	((uint8_t) 15)
charlesmn	0:0be0bd219e72	3160	#define VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3161	((uint16_t) 12)
charlesmn	0:0be0bd219e72	3162	#define VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3163	((uint16_t) 2560)
charlesmn	0:0be0bd219e72	3164	#define VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3165	((uint16_t) 5120)
charlesmn	0:0be0bd219e72	3166	#define VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3167	((uint16_t) 5120)
charlesmn	0:0be0bd219e72	3168	#define VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3169	((uint16_t) 2560)
charlesmn	0:0be0bd219e72	3170	#define VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3171	((uint32_t) 1000)
charlesmn	0:0be0bd219e72	3172	#define VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3173	((uint32_t) 15000)
charlesmn	0:0be0bd219e72	3174	#define VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3175	((uint32_t) 9000)
charlesmn	0:0be0bd219e72	3176	#define VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3177	((uint32_t) 6000)
charlesmn	0:0be0bd219e72	3178	#define VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3179	((uint32_t) 15000)
charlesmn	0:0be0bd219e72	3180	#define VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3181	((uint32_t) 9000)
charlesmn	0:0be0bd219e72	3182	#define VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3183	((uint32_t) 6000)
charlesmn	0:0be0bd219e72	3184	#define VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3185	((uint32_t) 1000)
charlesmn	0:0be0bd219e72	3186	#define VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3187	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3188	#define VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3189	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3190	#define VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3191	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3192	#define VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3193	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3194	#define VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3195	((uint32_t) 63000)
charlesmn	0:0be0bd219e72	3196	#define VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3197	((uint32_t) 2500)
charlesmn	0:0be0bd219e72	3198	#define VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3199	((uint32_t) 2500)
charlesmn	0:0be0bd219e72	3200	#define VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3201	((uint32_t) 13000)
charlesmn	0:0be0bd219e72	3202	#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN_DEFAULT \
charlesmn	0:0be0bd219e72	3203	((uint16_t) 0)
charlesmn	0:0be0bd219e72	3204	#define VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN_DEFAULT \
charlesmn	0:0be0bd219e72	3205	((uint32_t) 100)
charlesmn	0:0be0bd219e72	3206	#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_DEFAULT \
charlesmn	0:0be0bd219e72	3207	((uint32_t) 0)
charlesmn	0:0be0bd219e72	3208	#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI_DEFAULT \
charlesmn	0:0be0bd219e72	3209	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3210	#define VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT_DEFAULT \
charlesmn	0:0be0bd219e72	3211	((uint32_t) 200)
charlesmn	0:0be0bd219e72	3212	#define VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA_DEFAULT \
charlesmn	0:0be0bd219e72	3213	((uint32_t) 2048)
charlesmn	0:0be0bd219e72	3214	#define VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA_DEFAULT \
charlesmn	0:0be0bd219e72	3215	((uint32_t) 308)
charlesmn	0:0be0bd219e72	3216	#define VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT_DEFAULT \
charlesmn	0:0be0bd219e72	3217	((uint32_t) 10240)
charlesmn	0:0be0bd219e72	3218	#define VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD_DEFAULT \
charlesmn	0:0be0bd219e72	3219	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3220	#define VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER_DEFAULT \
charlesmn	0:0be0bd219e72	3221	((int16_t) 256)
charlesmn	0:0be0bd219e72	3222	#define VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER_DEFAULT \
charlesmn	0:0be0bd219e72	3223	((int16_t) 256)
charlesmn	0:0be0bd219e72	3224	#define VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET_DEFAULT \
charlesmn	0:0be0bd219e72	3225	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3226	#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY_DEFAULT \
charlesmn	0:0be0bd219e72	3227	((uint8_t) 0)
charlesmn	0:0be0bd219e72	3228	#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD_DEFAULT \
charlesmn	0:0be0bd219e72	3229	((uint32_t) 128)
charlesmn	0:0be0bd219e72	3230	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3231	((uint32_t) 57671680)
charlesmn	0:0be0bd219e72	3232	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT_DEFAULT \
charlesmn	0:0be0bd219e72	3233	((uint32_t) 40)
charlesmn	0:0be0bd219e72	3234	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3235	((uint32_t) 410)
charlesmn	0:0be0bd219e72	3236	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM_DEFAULT \
charlesmn	0:0be0bd219e72	3237	((uint16_t) 900)
charlesmn	0:0be0bd219e72	3238	#define VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND_DEFAULT \
charlesmn	0:0be0bd219e72	3239	((uint8_t) 3)
charlesmn	0:0be0bd219e72	3240	#define VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3241	((uint32_t) 1)
charlesmn	0:0be0bd219e72	3242	#define VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US_DEFAULT \
charlesmn	0:0be0bd219e72	3243	((uint32_t) 8000)
charlesmn	0:0be0bd219e72	3244	#define VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS_DEFAULT \
charlesmn	0:0be0bd219e72	3245	((uint16_t) 10240)
charlesmn	0:0be0bd219e72	3246	#define VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER_DEFAULT \
charlesmn	0:0be0bd219e72	3247	((uint32_t) 0)
charlesmn	0:0be0bd219e72	3248	#define VL53LX_TUNINGPARM_HIST_MERGE_DEFAULT \
charlesmn	0:0be0bd219e72	3249	((uint32_t) 1)
charlesmn	0:0be0bd219e72	3250	#define VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD_DEFAULT \
charlesmn	0:0be0bd219e72	3251	((uint32_t) 15000)
charlesmn	0:0be0bd219e72	3252	#define VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE_DEFAULT \
charlesmn	0:0be0bd219e72	3253	((uint32_t) 6)
charlesmn	0:0be0bd219e72	3254	#define VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR_DEFAULT \
charlesmn	0:0be0bd219e72	3255	((uint32_t) 2000)
charlesmn	0:0be0bd219e72	3256
charlesmn	0:0be0bd219e72	3257
charlesmn	0:0be0bd219e72	3258
charlesmn	0:0be0bd219e72	3259	/* vl53lx_preset_setup.h */
charlesmn	0:0be0bd219e72	3260
charlesmn	0:0be0bd219e72	3261
charlesmn	0:0be0bd219e72	3262	/* indexes for the bare driver tuning setting API function */
charlesmn	0:0be0bd219e72	3263
charlesmn	0:0be0bd219e72	3264	enum VL53LX_Tuning_t {
charlesmn	0:0be0bd219e72	3265	VL53LX_TUNING_VERSION = 0,
charlesmn	0:0be0bd219e72	3266	VL53LX_TUNING_PROXY_MIN,
charlesmn	0:0be0bd219e72	3267	VL53LX_TUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM,
charlesmn	0:0be0bd219e72	3268	VL53LX_TUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER,
charlesmn	0:0be0bd219e72	3269	VL53LX_TUNING_MIN_AMBIENT_DMAX_VALID,
charlesmn	0:0be0bd219e72	3270	VL53LX_TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER,
charlesmn	0:0be0bd219e72	3271	VL53LX_TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM,
charlesmn	0:0be0bd219e72	3272	VL53LX_TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT,
charlesmn	0:0be0bd219e72	3273	VL53LX_TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN,
charlesmn	0:0be0bd219e72	3274	VL53LX_TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET,
charlesmn	0:0be0bd219e72	3275	VL53LX_TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR,
charlesmn	0:0be0bd219e72	3276	VL53LX_TUNING_MAX_TUNABLE_KEY
charlesmn	0:0be0bd219e72	3277	};
charlesmn	0:0be0bd219e72	3278
charlesmn	0:0be0bd219e72	3279
charlesmn	0:0be0bd219e72	3280	/* default values for the tuning settings parameters */
charlesmn	0:0be0bd219e72	3281	#define TUNING_VERSION 0x0007
charlesmn	0:0be0bd219e72	3282
charlesmn	0:0be0bd219e72	3283	#define TUNING_PROXY_MIN -30 /* min distance in mm */
charlesmn	0:0be0bd219e72	3284	#define TUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM 600
charlesmn	0:0be0bd219e72	3285	/* Target distance in mm for single target Xtalk */
charlesmn	0:0be0bd219e72	3286	#define TUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER 50
charlesmn	0:0be0bd219e72	3287	/* Number of sample used for single target Xtalk */
charlesmn	0:0be0bd219e72	3288	#define TUNING_MIN_AMBIENT_DMAX_VALID 8
charlesmn	0:0be0bd219e72	3289	/* Minimum ambient level to state the Dmax returned by the device is valid */
charlesmn	0:0be0bd219e72	3290	#ifdef SMALL_FOOTPRINT
charlesmn	0:0be0bd219e72	3291	#define TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER 50
charlesmn	0:0be0bd219e72	3292	#else
charlesmn	0:0be0bd219e72	3293	#define TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER 10
charlesmn	0:0be0bd219e72	3294	#endif
charlesmn	0:0be0bd219e72	3295	/* Maximum loops to perform simple offset calibration */
charlesmn	0:0be0bd219e72	3296	#define TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM 600
charlesmn	0:0be0bd219e72	3297	/* Target distance in mm for target Xtalk from Bins method*/
charlesmn	0:0be0bd219e72	3298	#ifdef SMALL_FOOTPRINT
charlesmn	0:0be0bd219e72	3299	#define TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT 1
charlesmn	0:0be0bd219e72	3300	#else
charlesmn	0:0be0bd219e72	3301	#define TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT 3
charlesmn	0:0be0bd219e72	3302	#endif
charlesmn	0:0be0bd219e72	3303	/* Number of loops done during the simple offset calibration*/
charlesmn	0:0be0bd219e72	3304	#define TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR_DEFAULT 9
charlesmn	0:0be0bd219e72	3305	/* zero distance offset calibration non linear compensation default value */
charlesmn	0:0be0bd219e72	3306
charlesmn	0:0be0bd219e72	3307	/* The following settings are related to the fix for ticket EwokP #558410 */
charlesmn	0:0be0bd219e72	3308	#define TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN 24
charlesmn	0:0be0bd219e72	3309	/* Acceptance margin for the xtalk_shape bin_data sum computation */
charlesmn	0:0be0bd219e72	3310	#define TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET 50
charlesmn	0:0be0bd219e72	3311	/* Recovery value for Xtalk compensation plane offset in kcps */
charlesmn	0:0be0bd219e72	3312	/* 50 stands for ~0.10 kcps cover glass in 7.9 format */
charlesmn	0:0be0bd219e72	3313	/* End of settings related to the fix for ticket EwokP #558410 */
charlesmn	0:0be0bd219e72	3314
charlesmn	0:0be0bd219e72	3315
charlesmn	0:0be0bd219e72	3316
charlesmn	0:0be0bd219e72	3317
charlesmn	0:0be0bd219e72	3318	// define from vl53lx_platform_user_config
charlesmn	0:0be0bd219e72	3319
charlesmn	0:0be0bd219e72	3320	#define VL53LX_BYTES_PER_WORD 2
charlesmn	0:0be0bd219e72	3321	#define VL53LX_BYTES_PER_DWORD 4
charlesmn	0:0be0bd219e72	3322
charlesmn	0:0be0bd219e72	3323	/* Define polling delays */
charlesmn	0:0be0bd219e72	3324	#define VL53LX_BOOT_COMPLETION_POLLING_TIMEOUT_MS 500
charlesmn	0:0be0bd219e72	3325	#define VL53LX_RANGE_COMPLETION_POLLING_TIMEOUT_MS 2000
charlesmn	0:0be0bd219e72	3326	#define VL53LX_TEST_COMPLETION_POLLING_TIMEOUT_MS 10000
charlesmn	0:0be0bd219e72	3327
charlesmn	0:0be0bd219e72	3328	#define VL53LX_POLLING_DELAY_MS 1
charlesmn	0:0be0bd219e72	3329
charlesmn	0:0be0bd219e72	3330	/* Define LLD TuningParms Page Base Address
charlesmn	0:0be0bd219e72	3331	* - Part of Patch_AddedTuningParms_11761
charlesmn	0:0be0bd219e72	3332	*/
charlesmn	0:0be0bd219e72	3333	#define VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS 0x8000
charlesmn	0:0be0bd219e72	3334	#define VL53LX_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS 0xC000
charlesmn	0:0be0bd219e72	3335
charlesmn	0:0be0bd219e72	3336	#define VL53LX_OFFSET_CAL_MIN_MM1_EFFECTIVE_SPADS 0x0500
charlesmn	0:0be0bd219e72	3337	/*!< Lower Limit for the MM1 effective SPAD count during offset
charlesmn	0:0be0bd219e72	3338	calibration Format 8.8 0x0500 -> 5.0 effective SPADs */
charlesmn	0:0be0bd219e72	3339
charlesmn	0:0be0bd219e72	3340	#define VL53LX_GAIN_FACTOR__STANDARD_DEFAULT 0x0800
charlesmn	0:0be0bd219e72	3341	/*!< Default standard ranging gain correction factor
charlesmn	0:0be0bd219e72	3342	1.11 format. 1.0 = 0x0800, 0.980 = 0x07D7 */
charlesmn	0:0be0bd219e72	3343	#define VL53LX_GAIN_FACTOR__HISTOGRAM_DEFAULT 0x0800
charlesmn	0:0be0bd219e72	3344	/*!< Default histogram ranging gain correction factor
charlesmn	0:0be0bd219e72	3345	1.11 format. 1.0 = 0x0800, 0.975 = 0x07CC */
charlesmn	0:0be0bd219e72	3346
charlesmn	0:0be0bd219e72	3347
charlesmn	0:0be0bd219e72	3348	#define VL53LX_OFFSET_CAL_MIN_EFFECTIVE_SPADS 0x0500
charlesmn	0:0be0bd219e72	3349	/*!< Lower Limit for the MM1 effective SPAD count during offset
charlesmn	0:0be0bd219e72	3350	calibration Format 8.8 0x0500 -> 5.0 effective SPADs */
charlesmn	0:0be0bd219e72	3351
charlesmn	0:0be0bd219e72	3352	#define VL53LX_OFFSET_CAL_MAX_PRE_PEAK_RATE_MCPS 0x1900
charlesmn	0:0be0bd219e72	3353	/*!< Max Limit for the pre range preak rate during offset
charlesmn	0:0be0bd219e72	3354	calibration Format 9.7 0x1900 -> 50.0 Mcps.
charlesmn	0:0be0bd219e72	3355	If larger then in pile up */
charlesmn	0:0be0bd219e72	3356
charlesmn	0:0be0bd219e72	3357	#define VL53LX_OFFSET_CAL_MAX_SIGMA_MM 0x0040
charlesmn	0:0be0bd219e72	3358	/*!< Max sigma estimate limit during offset calibration
charlesmn	0:0be0bd219e72	3359	Check applies to pre-range, mm1 and mm2 ranges
charlesmn	0:0be0bd219e72	3360	Format 14.2 0x0040 -> 16.0mm. */
charlesmn	0:0be0bd219e72	3361
charlesmn	0:0be0bd219e72	3362	#define VL53LX_ZONE_CAL_MAX_PRE_PEAK_RATE_MCPS 0x1900
charlesmn	0:0be0bd219e72	3363	/*!< Max Peak Rate Limit for the during zone calibration
charlesmn	0:0be0bd219e72	3364	Format 9.7 0x1900 -> 50.0 Mcps.
charlesmn	0:0be0bd219e72	3365	If larger then in pile up */
charlesmn	0:0be0bd219e72	3366
charlesmn	0:0be0bd219e72	3367	#define VL53LX_ZONE_CAL_MAX_SIGMA_MM 0x0040
charlesmn	0:0be0bd219e72	3368	/*!< Max sigma estimate limit during zone calibration
charlesmn	0:0be0bd219e72	3369	Format 14.2 0x0040 -> 16.0mm. */
charlesmn	0:0be0bd219e72	3370
charlesmn	0:0be0bd219e72	3371
charlesmn	0:0be0bd219e72	3372	#define VL53LX_XTALK_EXTRACT_MAX_SIGMA_MM 0x008C
charlesmn	0:0be0bd219e72	3373	/*!< Max Sigma value allowed for a successful xtalk extraction
charlesmn	0:0be0bd219e72	3374	Format 14.2 0x008C -> 35.0 mm.*/
charlesmn	0:0be0bd219e72	3375
charlesmn	0:0be0bd219e72	3376	#ifndef VL53LX_MAX_USER_ZONES
charlesmn	0:0be0bd219e72	3377	#define VL53LX_MAX_USER_ZONES 16
charlesmn	0:0be0bd219e72	3378	/*!< Max number of user Zones - maximal limitation from
charlesmn	0:0be0bd219e72	3379	FW stream divide - value of 254 */
charlesmn	0:0be0bd219e72	3380	#endif
charlesmn	0:0be0bd219e72	3381
charlesmn	0:0be0bd219e72	3382	#define VL53LX_MAX_RANGE_RESULTS 4
charlesmn	0:0be0bd219e72	3383	#define VL53LX_BUFFER_SIZE 5
charlesmn	0:0be0bd219e72	3384
charlesmn	0:0be0bd219e72	3385	/*!< Sets the maximum number of targets distances the histogram
charlesmn	0:0be0bd219e72	3386	post processing can generate */
charlesmn	0:0be0bd219e72	3387
charlesmn	0:0be0bd219e72	3388	#define VL53LX_MAX_STRING_LENGTH 512
charlesmn	0:0be0bd219e72	3389	/!< Sets the maximum string length /
charlesmn	0:0be0bd219e72	3390
charlesmn	0:0be0bd219e72	3391
charlesmn	0:0be0bd219e72	3392	// typedef from vl53lx_types.h
charlesmn	0:0be0bd219e72	3393
charlesmn	0:0be0bd219e72	3394
charlesmn	0:0be0bd219e72	3395	#ifndef NULL
charlesmn	0:0be0bd219e72	3396	#error "Error NULL definition should be done. Please add required include "
charlesmn	0:0be0bd219e72	3397	#endif
charlesmn	0:0be0bd219e72	3398
charlesmn	0:0be0bd219e72	3399
charlesmn	0:0be0bd219e72	3400	#if !defined(STDINT_H) && !defined(_STDINT_H) && !defined(_GCC_STDINT_H) && !defined(__STDINT_DECLS) && !defined(_GCC_WRAP_STDINT_H) && !defined(_STDINT)
charlesmn	0:0be0bd219e72	3401
charlesmn	0:0be0bd219e72	3402	#pragma message("Please review type definition of STDINT define for your platform and add to list above ")
charlesmn	0:0be0bd219e72	3403
charlesmn	0:0be0bd219e72	3404	typedef unsigned long long uint64_t;
charlesmn	0:0be0bd219e72	3405	typedef unsigned int uint32_t;
charlesmn	0:0be0bd219e72	3406	typedef int int32_t;
charlesmn	0:0be0bd219e72	3407	typedef unsigned short uint16_t;
charlesmn	0:0be0bd219e72	3408	typedef short int16_t;
charlesmn	0:0be0bd219e72	3409	typedef unsigned char uint8_t;
charlesmn	0:0be0bd219e72	3410	typedef signed char int8_t;
charlesmn	0:0be0bd219e72	3411
charlesmn	0:0be0bd219e72	3412	#endif
charlesmn	0:0be0bd219e72	3413
charlesmn	0:0be0bd219e72	3414	typedef uint32_t FixPoint1616_t;
charlesmn	0:0be0bd219e72	3415
charlesmn	0:0be0bd219e72	3416
charlesmn	0:0be0bd219e72	3417
charlesmn	0:0be0bd219e72	3418	// define from vl53lx_error_codes.h
charlesmn	0:0be0bd219e72	3419
charlesmn	0:0be0bd219e72	3420
charlesmn	0:0be0bd219e72	3421
charlesmn	0:0be0bd219e72	3422	/*
charlesmn	0:0be0bd219e72	3423	****************************************
charlesmn	0:0be0bd219e72	3424	* PRIVATE define do not edit
charlesmn	0:0be0bd219e72	3425	***************************************
charlesmn	0:0be0bd219e72	3426	*/
charlesmn	0:0be0bd219e72	3427
charlesmn	0:0be0bd219e72	3428	/*
charlesmn	0:0be0bd219e72	3429	* @defgroup VL53LX_define_Error_group Error and Warning code returned by API
charlesmn	0:0be0bd219e72	3430	* The following DEFINE are used to identify the PAL ERROR
charlesmn	0:0be0bd219e72	3431	* @{
charlesmn	0:0be0bd219e72	3432	*/
charlesmn	0:0be0bd219e72	3433
charlesmn	0:0be0bd219e72	3434	typedef int8_t VL53LX_Error;
charlesmn	0:0be0bd219e72	3435
charlesmn	0:0be0bd219e72	3436	#define VL53LX_ERROR_NONE ((VL53LX_Error) 0)
charlesmn	0:0be0bd219e72	3437	#define VL53LX_ERROR_CALIBRATION_WARNING ((VL53LX_Error) - 1)
charlesmn	0:0be0bd219e72	3438	/*!< Warning invalid calibration data may be in used
charlesmn	0:0be0bd219e72	3439	* \a VL53LX_InitData()
charlesmn	0:0be0bd219e72	3440	* \a VL53LX_GetOffsetCalibrationData
charlesmn	0:0be0bd219e72	3441	* \a VL53LX_SetOffsetCalibrationData
charlesmn	0:0be0bd219e72	3442	*/
charlesmn	0:0be0bd219e72	3443	#define VL53LX_ERROR_MIN_CLIPPED ((VL53LX_Error) - 2)
charlesmn	0:0be0bd219e72	3444	/!< Warning parameter passed was clipped to min before to be applied /
charlesmn	0:0be0bd219e72	3445
charlesmn	0:0be0bd219e72	3446	#define VL53LX_ERROR_UNDEFINED ((VL53LX_Error) - 3)
charlesmn	0:0be0bd219e72	3447	/!< Unqualified error /
charlesmn	0:0be0bd219e72	3448	#define VL53LX_ERROR_INVALID_PARAMS ((VL53LX_Error) - 4)
charlesmn	0:0be0bd219e72	3449	/!< Parameter passed is invalid or out of range /
charlesmn	0:0be0bd219e72	3450	#define VL53LX_ERROR_NOT_SUPPORTED ((VL53LX_Error) - 5)
charlesmn	0:0be0bd219e72	3451	/!< Function is not supported in current mode or configuration /
charlesmn	0:0be0bd219e72	3452	#define VL53LX_ERROR_RANGE_ERROR ((VL53LX_Error) - 6)
charlesmn	0:0be0bd219e72	3453	/!< Device report a ranging error interrupt status /
charlesmn	0:0be0bd219e72	3454	#define VL53LX_ERROR_TIME_OUT ((VL53LX_Error) - 7)
charlesmn	0:0be0bd219e72	3455	/!< Aborted due to time out /
charlesmn	0:0be0bd219e72	3456	#define VL53LX_ERROR_MODE_NOT_SUPPORTED ((VL53LX_Error) - 8)
charlesmn	0:0be0bd219e72	3457	/!< Asked mode is not supported by the device /
charlesmn	0:0be0bd219e72	3458	#define VL53LX_ERROR_BUFFER_TOO_SMALL ((VL53LX_Error) - 9)
charlesmn	0:0be0bd219e72	3459	/!< ... /
charlesmn	0:0be0bd219e72	3460	#define VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL ((VL53LX_Error) - 10)
charlesmn	0:0be0bd219e72	3461	/!< Supplied buffer is larger than I2C supports /
charlesmn	0:0be0bd219e72	3462	#define VL53LX_ERROR_GPIO_NOT_EXISTING ((VL53LX_Error) - 11)
charlesmn	0:0be0bd219e72	3463	/!< User tried to setup a non-existing GPIO pin /
charlesmn	0:0be0bd219e72	3464	#define VL53LX_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED ((VL53LX_Error) - 12)
charlesmn	0:0be0bd219e72	3465	/!< unsupported GPIO functionality /
charlesmn	0:0be0bd219e72	3466	#define VL53LX_ERROR_CONTROL_INTERFACE ((VL53LX_Error) - 13)
charlesmn	0:0be0bd219e72	3467	/!< error reported from IO functions /
charlesmn	0:0be0bd219e72	3468	#define VL53LX_ERROR_INVALID_COMMAND ((VL53LX_Error) - 14)
charlesmn	0:0be0bd219e72	3469	/*!< The command is not allowed in the current device state
charlesmn	0:0be0bd219e72	3470	* (power down)
charlesmn	0:0be0bd219e72	3471	*/
charlesmn	0:0be0bd219e72	3472	#define VL53LX_ERROR_DIVISION_BY_ZERO ((VL53LX_Error) - 15)
charlesmn	0:0be0bd219e72	3473	/!< In the function a division by zero occurs /
charlesmn	0:0be0bd219e72	3474	#define VL53LX_ERROR_REF_SPAD_INIT ((VL53LX_Error) - 16)
charlesmn	0:0be0bd219e72	3475	/!< Error during reference SPAD initialization /
charlesmn	0:0be0bd219e72	3476	#define VL53LX_ERROR_GPH_SYNC_CHECK_FAIL ((VL53LX_Error) - 17)
charlesmn	0:0be0bd219e72	3477	/!< GPH sync interrupt check fail - API out of sync with device/
charlesmn	0:0be0bd219e72	3478	#define VL53LX_ERROR_STREAM_COUNT_CHECK_FAIL ((VL53LX_Error) - 18)
charlesmn	0:0be0bd219e72	3479	/!< Stream count check fail - API out of sync with device /
charlesmn	0:0be0bd219e72	3480	#define VL53LX_ERROR_GPH_ID_CHECK_FAIL ((VL53LX_Error) - 19)
charlesmn	0:0be0bd219e72	3481	/!< GPH ID check fail - API out of sync with device /
charlesmn	0:0be0bd219e72	3482	#define VL53LX_ERROR_ZONE_STREAM_COUNT_CHECK_FAIL ((VL53LX_Error) - 20)
charlesmn	0:0be0bd219e72	3483	/!< Zone dynamic config stream count check failed - API out of sync /
charlesmn	0:0be0bd219e72	3484	#define VL53LX_ERROR_ZONE_GPH_ID_CHECK_FAIL ((VL53LX_Error) - 21)
charlesmn	0:0be0bd219e72	3485	/!< Zone dynamic config GPH ID check failed - API out of sync /
charlesmn	0:0be0bd219e72	3486
charlesmn	0:0be0bd219e72	3487	#define VL53LX_ERROR_XTALK_EXTRACTION_NO_SAMPLE_FAIL ((VL53LX_Error) - 22)
charlesmn	0:0be0bd219e72	3488	/*!< Thrown when run_xtalk_extraction fn has 0 successful samples
charlesmn	0:0be0bd219e72	3489	* when using the full array to sample the xtalk. In this case there is
charlesmn	0:0be0bd219e72	3490	* not enough information to generate new Xtalk parm info. The function
charlesmn	0:0be0bd219e72	3491	* will exit and leave the current xtalk parameters unaltered
charlesmn	0:0be0bd219e72	3492	*/
charlesmn	0:0be0bd219e72	3493	#define VL53LX_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL ((VL53LX_Error) - 23)
charlesmn	0:0be0bd219e72	3494	/*!< Thrown when run_xtalk_extraction fn has found that the
charlesmn	0:0be0bd219e72	3495	* avg sigma estimate of the full array xtalk sample is > than the
charlesmn	0:0be0bd219e72	3496	* maximal limit allowed. In this case the xtalk sample is too noisy for
charlesmn	0:0be0bd219e72	3497	* measurement. The function will exit and leave the current xtalk
charlesmn	0:0be0bd219e72	3498	* parameters unaltered.
charlesmn	0:0be0bd219e72	3499	*/
charlesmn	0:0be0bd219e72	3500
charlesmn	0:0be0bd219e72	3501
charlesmn	0:0be0bd219e72	3502	#define VL53LX_ERROR_OFFSET_CAL_NO_SAMPLE_FAIL ((VL53LX_Error) - 24)
charlesmn	0:0be0bd219e72	3503	/*!< Thrown if there one of stages has no valid offset calibration
charlesmn	0:0be0bd219e72	3504	* samples. A fatal error calibration not valid
charlesmn	0:0be0bd219e72	3505	*/
charlesmn	0:0be0bd219e72	3506	#define VL53LX_ERROR_OFFSET_CAL_NO_SPADS_ENABLED_FAIL ((VL53LX_Error) - 25)
charlesmn	0:0be0bd219e72	3507	/*!< Thrown if there one of stages has zero effective SPADS
charlesmn	0:0be0bd219e72	3508	* Traps the case when MM1 SPADs is zero.
charlesmn	0:0be0bd219e72	3509	* A fatal error calibration not valid
charlesmn	0:0be0bd219e72	3510	*/
charlesmn	0:0be0bd219e72	3511	#define VL53LX_ERROR_ZONE_CAL_NO_SAMPLE_FAIL ((VL53LX_Error) - 26)
charlesmn	0:0be0bd219e72	3512	/*!< Thrown if then some of the zones have no valid samples
charlesmn	0:0be0bd219e72	3513	* A fatal error calibration not valid
charlesmn	0:0be0bd219e72	3514	*/
charlesmn	0:0be0bd219e72	3515
charlesmn	0:0be0bd219e72	3516	#define VL53LX_ERROR_TUNING_PARM_KEY_MISMATCH ((VL53LX_Error) - 27)
charlesmn	0:0be0bd219e72	3517	/*!< Thrown if the tuning file key table version does not match with
charlesmn	0:0be0bd219e72	3518	* expected value. The driver expects the key table version to match
charlesmn	0:0be0bd219e72	3519	* the compiled default version number in the define
charlesmn	0:0be0bd219e72	3520	* #VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT
charlesmn	0:0be0bd219e72	3521	*/
charlesmn	0:0be0bd219e72	3522
charlesmn	0:0be0bd219e72	3523	#define VL53LX_WARNING_REF_SPAD_CHAR_NOT_ENOUGH_SPADS ((VL53LX_Error) - 28)
charlesmn	0:0be0bd219e72	3524	/!< Thrown if there are less than 5 good SPADs are available. /
charlesmn	0:0be0bd219e72	3525	#define VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_HIGH ((VL53LX_Error) - 29)
charlesmn	0:0be0bd219e72	3526	/*!< Thrown if the final reference rate is greater than
charlesmn	0:0be0bd219e72	3527	* the upper reference rate limit - default is 40 Mcps.
charlesmn	0:0be0bd219e72	3528	* Implies a minimum Q3 (x10) SPAD (5) selected
charlesmn	0:0be0bd219e72	3529	*/
charlesmn	0:0be0bd219e72	3530	#define VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_LOW ((VL53LX_Error) - 30)
charlesmn	0:0be0bd219e72	3531	/*!< Thrown if the final reference rate is less than
charlesmn	0:0be0bd219e72	3532	* the lower reference rate limit - default is 10 Mcps.
charlesmn	0:0be0bd219e72	3533	* Implies maximum Q1 (x1) SPADs selected
charlesmn	0:0be0bd219e72	3534	*/
charlesmn	0:0be0bd219e72	3535
charlesmn	0:0be0bd219e72	3536
charlesmn	0:0be0bd219e72	3537	#define VL53LX_WARNING_OFFSET_CAL_MISSING_SAMPLES ((VL53LX_Error) - 31)
charlesmn	0:0be0bd219e72	3538	/*!< Thrown if there is less than the requested number of
charlesmn	0:0be0bd219e72	3539	* valid samples.
charlesmn	0:0be0bd219e72	3540	*/
charlesmn	0:0be0bd219e72	3541	#define VL53LX_WARNING_OFFSET_CAL_SIGMA_TOO_HIGH ((VL53LX_Error) - 32)
charlesmn	0:0be0bd219e72	3542	/*!< Thrown if the offset calibration range sigma estimate is greater
charlesmn	0:0be0bd219e72	3543	* than 8.0 mm. This is the recommended min value to yield a stable
charlesmn	0:0be0bd219e72	3544	* offset measurement
charlesmn	0:0be0bd219e72	3545	*/
charlesmn	0:0be0bd219e72	3546	#define VL53LX_WARNING_OFFSET_CAL_RATE_TOO_HIGH ((VL53LX_Error) - 33)
charlesmn	0:0be0bd219e72	3547	/*!< Thrown when VL53LX_run_offset_calibration() peak rate is greater
charlesmn	0:0be0bd219e72	3548	* than that 50.0Mcps. This is the recommended max rate to avoid
charlesmn	0:0be0bd219e72	3549	* pile-up influencing the offset measurement
charlesmn	0:0be0bd219e72	3550	*/
charlesmn	0:0be0bd219e72	3551	#define VL53LX_WARNING_OFFSET_CAL_SPAD_COUNT_TOO_LOW ((VL53LX_Error) - 34)
charlesmn	0:0be0bd219e72	3552	/*!< Thrown when VL53LX_run_offset_calibration() when one of stages
charlesmn	0:0be0bd219e72	3553	* range has less that 5.0 effective SPADS. This is the recommended
charlesmn	0:0be0bd219e72	3554	* min value to yield a stable offset
charlesmn	0:0be0bd219e72	3555	*/
charlesmn	0:0be0bd219e72	3556
charlesmn	0:0be0bd219e72	3557
charlesmn	0:0be0bd219e72	3558	#define VL53LX_WARNING_ZONE_CAL_MISSING_SAMPLES ((VL53LX_Error) - 35)
charlesmn	0:0be0bd219e72	3559	/*!< Thrown if one of more of the zones have less than
charlesmn	0:0be0bd219e72	3560	* the requested number of valid samples
charlesmn	0:0be0bd219e72	3561	*/
charlesmn	0:0be0bd219e72	3562	#define VL53LX_WARNING_ZONE_CAL_SIGMA_TOO_HIGH ((VL53LX_Error) - 36)
charlesmn	0:0be0bd219e72	3563	/*!< Thrown if one or more zones have sigma estimate value greater
charlesmn	0:0be0bd219e72	3564	* than 8.0 mm. This is the recommended min value to yield a stable
charlesmn	0:0be0bd219e72	3565	* offset measurement
charlesmn	0:0be0bd219e72	3566	*/
charlesmn	0:0be0bd219e72	3567	#define VL53LX_WARNING_ZONE_CAL_RATE_TOO_HIGH ((VL53LX_Error) - 37)
charlesmn	0:0be0bd219e72	3568	/*!< Thrown if one of more zones have peak rate higher than
charlesmn	0:0be0bd219e72	3569	* that 50.0Mcps. This is the recommended max rate to avoid
charlesmn	0:0be0bd219e72	3570	* pile-up influencing the offset measurement
charlesmn	0:0be0bd219e72	3571	*/
charlesmn	0:0be0bd219e72	3572
charlesmn	0:0be0bd219e72	3573
charlesmn	0:0be0bd219e72	3574	#define VL53LX_WARNING_XTALK_MISSING_SAMPLES ((VL53LX_Error) - 38)
charlesmn	0:0be0bd219e72	3575	/*!< Thrown to notify that some of the xtalk samples did not yield
charlesmn	0:0be0bd219e72	3576	* valid ranging pulse data while attempting to measure
charlesmn	0:0be0bd219e72	3577	* the xtalk signal in vl53lx_run_xtalk_extract(). This can signify any
charlesmn	0:0be0bd219e72	3578	* of the zones are missing samples, for further debug information the
charlesmn	0:0be0bd219e72	3579	* xtalk_results struct should be referred to. This warning is for
charlesmn	0:0be0bd219e72	3580	* notification only, xtalk pulse and shape have still been generated
charlesmn	0:0be0bd219e72	3581	*/
charlesmn	0:0be0bd219e72	3582	#define VL53LX_WARNING_XTALK_NO_SAMPLES_FOR_GRADIENT ((VL53LX_Error) - 39)
charlesmn	0:0be0bd219e72	3583	/*!< Thrown to notify that some of the xtalk samples used for gradient
charlesmn	0:0be0bd219e72	3584	* generation did not yield valid ranging pulse data while attempting to
charlesmn	0:0be0bd219e72	3585	* measure the xtalk signal in vl53lx_run_xtalk_extract(). This can
charlesmn	0:0be0bd219e72	3586	* signify that any one of the zones 0-3 yielded no successful samples.
charlesmn	0:0be0bd219e72	3587	* xtalk_results struct should be referred to for further debug info.
charlesmn	0:0be0bd219e72	3588	* This warning is for notification only, the xtalk pulse and shape
charlesmn	0:0be0bd219e72	3589	* have still been generated.
charlesmn	0:0be0bd219e72	3590	*/
charlesmn	0:0be0bd219e72	3591	#define VL53LX_WARNING_XTALK_SIGMA_LIMIT_FOR_GRADIENT ((VL53LX_Error) - 40)
charlesmn	0:0be0bd219e72	3592	/*!< Thrown to notify that some of the xtalk samples used for gradient
charlesmn	0:0be0bd219e72	3593	* generation did not pass the sigma limit check while attempting to
charlesmn	0:0be0bd219e72	3594	* measure the xtalk signal in vl53lx_run_xtalk_extract(). This can
charlesmn	0:0be0bd219e72	3595	* signify that any one of the zones 0-3 yielded an avg sigma_mm
charlesmn	0:0be0bd219e72	3596	* value > the limit. The xtalk_results struct should be referred to for
charlesmn	0:0be0bd219e72	3597	* further debug info.
charlesmn	0:0be0bd219e72	3598	* This warning is for notification only, the xtalk pulse and shape
charlesmn	0:0be0bd219e72	3599	* have still been generated.
charlesmn	0:0be0bd219e72	3600	*/
charlesmn	0:0be0bd219e72	3601
charlesmn	0:0be0bd219e72	3602	#define VL53LX_ERROR_NOT_IMPLEMENTED ((VL53LX_Error) - 41)
charlesmn	0:0be0bd219e72	3603	/*!< Tells requested functionality has not been implemented yet or
charlesmn	0:0be0bd219e72	3604	* not compatible with the device
charlesmn	0:0be0bd219e72	3605	*/
charlesmn	0:0be0bd219e72	3606	#define VL53LX_ERROR_PLATFORM_SPECIFIC_START ((VL53LX_Error) - 60)
charlesmn	0:0be0bd219e72	3607	/!< Tells the starting code for platform /
charlesmn	0:0be0bd219e72	3608	/** @} VL53LX_define_Error_group */
charlesmn	0:0be0bd219e72	3609
charlesmn	0:0be0bd219e72	3610
charlesmn	0:0be0bd219e72	3611
charlesmn	0:0be0bd219e72	3612	/* vl53lx_dmax_private_structs.h */
charlesmn	0:0be0bd219e72	3613
charlesmn	0:0be0bd219e72	3614
charlesmn	0:0be0bd219e72	3615
charlesmn	0:0be0bd219e72	3616
charlesmn	0:0be0bd219e72	3617
charlesmn	0:0be0bd219e72	3618
charlesmn	0:0be0bd219e72	3619
charlesmn	0:0be0bd219e72	3620
charlesmn	0:0be0bd219e72	3621	typedef struct {
charlesmn	0:0be0bd219e72	3622
charlesmn	0:0be0bd219e72	3623	uint32_t VL53LX_p_037;
charlesmn	0:0be0bd219e72	3624
charlesmn	0:0be0bd219e72	3625
charlesmn	0:0be0bd219e72	3626
charlesmn	0:0be0bd219e72	3627	uint8_t VL53LX_p_063;
charlesmn	0:0be0bd219e72	3628
charlesmn	0:0be0bd219e72	3629
charlesmn	0:0be0bd219e72	3630	uint8_t VL53LX_p_064;
charlesmn	0:0be0bd219e72	3631
charlesmn	0:0be0bd219e72	3632
charlesmn	0:0be0bd219e72	3633
charlesmn	0:0be0bd219e72	3634	uint16_t VL53LX_p_065;
charlesmn	0:0be0bd219e72	3635
charlesmn	0:0be0bd219e72	3636
charlesmn	0:0be0bd219e72	3637	uint16_t VL53LX_p_066;
charlesmn	0:0be0bd219e72	3638
charlesmn	0:0be0bd219e72	3639
charlesmn	0:0be0bd219e72	3640	uint16_t VL53LX_p_067;
charlesmn	0:0be0bd219e72	3641
charlesmn	0:0be0bd219e72	3642
charlesmn	0:0be0bd219e72	3643	uint16_t VL53LX_p_038;
charlesmn	0:0be0bd219e72	3644
charlesmn	0:0be0bd219e72	3645
charlesmn	0:0be0bd219e72	3646
charlesmn	0:0be0bd219e72	3647	uint32_t VL53LX_p_009;
charlesmn	0:0be0bd219e72	3648
charlesmn	0:0be0bd219e72	3649
charlesmn	0:0be0bd219e72	3650	uint32_t VL53LX_p_033;
charlesmn	0:0be0bd219e72	3651
charlesmn	0:0be0bd219e72	3652
charlesmn	0:0be0bd219e72	3653
charlesmn	0:0be0bd219e72	3654	uint16_t VL53LX_p_034;
charlesmn	0:0be0bd219e72	3655
charlesmn	0:0be0bd219e72	3656
charlesmn	0:0be0bd219e72	3657
charlesmn	0:0be0bd219e72	3658	uint16_t VL53LX_p_004;
charlesmn	0:0be0bd219e72	3659
charlesmn	0:0be0bd219e72	3660
charlesmn	0:0be0bd219e72	3661
charlesmn	0:0be0bd219e72	3662	uint32_t VL53LX_p_028;
charlesmn	0:0be0bd219e72	3663
charlesmn	0:0be0bd219e72	3664
charlesmn	0:0be0bd219e72	3665	uint32_t VL53LX_p_035;
charlesmn	0:0be0bd219e72	3666
charlesmn	0:0be0bd219e72	3667
charlesmn	0:0be0bd219e72	3668
charlesmn	0:0be0bd219e72	3669	int16_t VL53LX_p_036;
charlesmn	0:0be0bd219e72	3670
charlesmn	0:0be0bd219e72	3671
charlesmn	0:0be0bd219e72	3672	int16_t VL53LX_p_022;
charlesmn	0:0be0bd219e72	3673
charlesmn	0:0be0bd219e72	3674
charlesmn	0:0be0bd219e72	3675
charlesmn	0:0be0bd219e72	3676	} VL53LX_hist_gen3_dmax_private_data_t;
charlesmn	0:0be0bd219e72	3677
charlesmn	0:0be0bd219e72	3678
charlesmn	0:0be0bd219e72	3679
charlesmn	0:0be0bd219e72	3680
charlesmn	0:0be0bd219e72	3681	// def & typedef from vl53lx_ll_device.h
charlesmn	0:0be0bd219e72	3682
charlesmn	0:0be0bd219e72	3683
charlesmn	0:0be0bd219e72	3684	#define VL53LX_I2C 0x01
charlesmn	0:0be0bd219e72	3685	#define VL53LX_SPI 0x00
charlesmn	0:0be0bd219e72	3686
charlesmn	0:0be0bd219e72	3687
charlesmn	0:0be0bd219e72	3688
charlesmn	0:0be0bd219e72	3689
charlesmn	0:0be0bd219e72	3690
charlesmn	0:0be0bd219e72	3691	typedef uint8_t VL53LX_WaitMethod;
charlesmn	0:0be0bd219e72	3692
charlesmn	0:0be0bd219e72	3693	#define VL53LX_WAIT_METHOD_BLOCKING ((VL53LX_WaitMethod) 0)
charlesmn	0:0be0bd219e72	3694	#define VL53LX_WAIT_METHOD_NON_BLOCKING ((VL53LX_WaitMethod) 1)
charlesmn	0:0be0bd219e72	3695
charlesmn	0:0be0bd219e72	3696
charlesmn	0:0be0bd219e72	3697
charlesmn	0:0be0bd219e72	3698
charlesmn	0:0be0bd219e72	3699	typedef uint8_t VL53LX_DeviceState;
charlesmn	0:0be0bd219e72	3700
charlesmn	0:0be0bd219e72	3701	#define VL53LX_DEVICESTATE_POWERDOWN ((VL53LX_DeviceState) 0)
charlesmn	0:0be0bd219e72	3702	#define VL53LX_DEVICESTATE_HW_STANDBY ((VL53LX_DeviceState) 1)
charlesmn	0:0be0bd219e72	3703	#define VL53LX_DEVICESTATE_FW_COLDBOOT ((VL53LX_DeviceState) 2)
charlesmn	0:0be0bd219e72	3704	#define VL53LX_DEVICESTATE_SW_STANDBY ((VL53LX_DeviceState) 3)
charlesmn	0:0be0bd219e72	3705	#define VL53LX_DEVICESTATE_RANGING_DSS_AUTO ((VL53LX_DeviceState) 4)
charlesmn	0:0be0bd219e72	3706	#define VL53LX_DEVICESTATE_RANGING_DSS_MANUAL ((VL53LX_DeviceState) 5)
charlesmn	0:0be0bd219e72	3707	#define VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC ((VL53LX_DeviceState) 6)
charlesmn	0:0be0bd219e72	3708	#define VL53LX_DEVICESTATE_RANGING_GATHER_DATA ((VL53LX_DeviceState) 7)
charlesmn	0:0be0bd219e72	3709	#define VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA ((VL53LX_DeviceState) 8)
charlesmn	0:0be0bd219e72	3710
charlesmn	0:0be0bd219e72	3711	#define VL53LX_DEVICESTATE_UNKNOWN ((VL53LX_DeviceState) 98)
charlesmn	0:0be0bd219e72	3712	#define VL53LX_DEVICESTATE_ERROR ((VL53LX_DeviceState) 99)
charlesmn	0:0be0bd219e72	3713
charlesmn	0:0be0bd219e72	3714
charlesmn	0:0be0bd219e72	3715
charlesmn	0:0be0bd219e72	3716
charlesmn	0:0be0bd219e72	3717
charlesmn	0:0be0bd219e72	3718	typedef uint8_t VL53LX_DeviceZonePreset;
charlesmn	0:0be0bd219e72	3719
charlesmn	0:0be0bd219e72	3720	#define VL53LX_DEVICEZONEPRESET_NONE \
charlesmn	0:0be0bd219e72	3721	((VL53LX_DeviceZonePreset) 0)
charlesmn	0:0be0bd219e72	3722
charlesmn	0:0be0bd219e72	3723	#define VL53LX_DEVICEZONEPRESET_XTALK_PLANAR \
charlesmn	0:0be0bd219e72	3724	((VL53LX_DeviceZonePreset) 1)
charlesmn	0:0be0bd219e72	3725	#define VL53LX_DEVICEZONEPRESET_1X1_SIZE_16X16 \
charlesmn	0:0be0bd219e72	3726	((VL53LX_DeviceZonePreset) 2)
charlesmn	0:0be0bd219e72	3727	#define VL53LX_DEVICEZONEPRESET_1X2_SIZE_16X8 \
charlesmn	0:0be0bd219e72	3728	((VL53LX_DeviceZonePreset) 3)
charlesmn	0:0be0bd219e72	3729	#define VL53LX_DEVICEZONEPRESET_2X1_SIZE_8X16 \
charlesmn	0:0be0bd219e72	3730	((VL53LX_DeviceZonePreset) 4)
charlesmn	0:0be0bd219e72	3731	#define VL53LX_DEVICEZONEPRESET_2X2_SIZE_8X8 \
charlesmn	0:0be0bd219e72	3732	((VL53LX_DeviceZonePreset) 5)
charlesmn	0:0be0bd219e72	3733	#define VL53LX_DEVICEZONEPRESET_3X3_SIZE_5X5 \
charlesmn	0:0be0bd219e72	3734	((VL53LX_DeviceZonePreset) 6)
charlesmn	0:0be0bd219e72	3735	#define VL53LX_DEVICEZONEPRESET_4X4_SIZE_4X4 \
charlesmn	0:0be0bd219e72	3736	((VL53LX_DeviceZonePreset) 7)
charlesmn	0:0be0bd219e72	3737	#define VL53LX_DEVICEZONEPRESET_5X5_SIZE_4X4 \
charlesmn	0:0be0bd219e72	3738	((VL53LX_DeviceZonePreset) 8)
charlesmn	0:0be0bd219e72	3739	#define VL53LX_DEVICEZONEPRESET_11X11_SIZE_5X5 \
charlesmn	0:0be0bd219e72	3740	((VL53LX_DeviceZonePreset) 9)
charlesmn	0:0be0bd219e72	3741	#define VL53LX_DEVICEZONEPRESET_13X13_SIZE_4X4 \
charlesmn	0:0be0bd219e72	3742	((VL53LX_DeviceZonePreset) 10)
charlesmn	0:0be0bd219e72	3743
charlesmn	0:0be0bd219e72	3744	#define VL53LX_DEVICEZONEPRESET_1X1_SIZE_4X4_POS_8X8 \
charlesmn	0:0be0bd219e72	3745	((VL53LX_DeviceZonePreset) 11)
charlesmn	0:0be0bd219e72	3746
charlesmn	0:0be0bd219e72	3747	#define VL53LX_DEVICEZONEPRESET_CUSTOM \
charlesmn	0:0be0bd219e72	3748	((VL53LX_DeviceZonePreset) 255)
charlesmn	0:0be0bd219e72	3749
charlesmn	0:0be0bd219e72	3750
charlesmn	0:0be0bd219e72	3751
charlesmn	0:0be0bd219e72	3752
charlesmn	0:0be0bd219e72	3753
charlesmn	0:0be0bd219e72	3754	typedef uint8_t VL53LX_DevicePresetModes;
charlesmn	0:0be0bd219e72	3755
charlesmn	0:0be0bd219e72	3756	#define VL53LX_DEVICEPRESETMODE_NONE \
charlesmn	0:0be0bd219e72	3757	((VL53LX_DevicePresetModes) 0)
charlesmn	0:0be0bd219e72	3758	#define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING \
charlesmn	0:0be0bd219e72	3759	((VL53LX_DevicePresetModes) 1)
charlesmn	0:0be0bd219e72	3760	#define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_SHORT_RANGE \
charlesmn	0:0be0bd219e72	3761	((VL53LX_DevicePresetModes) 2)
charlesmn	0:0be0bd219e72	3762	#define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_LONG_RANGE \
charlesmn	0:0be0bd219e72	3763	((VL53LX_DevicePresetModes) 3)
charlesmn	0:0be0bd219e72	3764	#define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_MM1_CAL \
charlesmn	0:0be0bd219e72	3765	((VL53LX_DevicePresetModes) 4)
charlesmn	0:0be0bd219e72	3766	#define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_MM2_CAL \
charlesmn	0:0be0bd219e72	3767	((VL53LX_DevicePresetModes) 5)
charlesmn	0:0be0bd219e72	3768	#define VL53LX_DEVICEPRESETMODE_TIMED_RANGING \
charlesmn	0:0be0bd219e72	3769	((VL53LX_DevicePresetModes) 6)
charlesmn	0:0be0bd219e72	3770	#define VL53LX_DEVICEPRESETMODE_TIMED_RANGING_SHORT_RANGE \
charlesmn	0:0be0bd219e72	3771	((VL53LX_DevicePresetModes) 7)
charlesmn	0:0be0bd219e72	3772	#define VL53LX_DEVICEPRESETMODE_TIMED_RANGING_LONG_RANGE \
charlesmn	0:0be0bd219e72	3773	((VL53LX_DevicePresetModes) 8)
charlesmn	0:0be0bd219e72	3774	#define VL53LX_DEVICEPRESETMODE_NEAR_FARRANGING \
charlesmn	0:0be0bd219e72	3775	((VL53LX_DevicePresetModes) 9)
charlesmn	0:0be0bd219e72	3776	#define VL53LX_DEVICEPRESETMODE_QUADRANT_RANGING \
charlesmn	0:0be0bd219e72	3777	((VL53LX_DevicePresetModes) 10)
charlesmn	0:0be0bd219e72	3778	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING \
charlesmn	0:0be0bd219e72	3779	((VL53LX_DevicePresetModes) 11)
charlesmn	0:0be0bd219e72	3780	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_SHORT_TIMING \
charlesmn	0:0be0bd219e72	3781	((VL53LX_DevicePresetModes) 12)
charlesmn	0:0be0bd219e72	3782	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_CHARACTERISATION \
charlesmn	0:0be0bd219e72	3783	((VL53LX_DevicePresetModes) 13)
charlesmn	0:0be0bd219e72	3784	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_XTALK_PLANAR \
charlesmn	0:0be0bd219e72	3785	((VL53LX_DevicePresetModes) 14)
charlesmn	0:0be0bd219e72	3786	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_XTALK_MM1 \
charlesmn	0:0be0bd219e72	3787	((VL53LX_DevicePresetModes) 15)
charlesmn	0:0be0bd219e72	3788	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_XTALK_MM2 \
charlesmn	0:0be0bd219e72	3789	((VL53LX_DevicePresetModes) 16)
charlesmn	0:0be0bd219e72	3790	#define VL53LX_DEVICEPRESETMODE_OLT \
charlesmn	0:0be0bd219e72	3791	((VL53LX_DevicePresetModes) 17)
charlesmn	0:0be0bd219e72	3792	#define VL53LX_DEVICEPRESETMODE_SINGLESHOT_RANGING \
charlesmn	0:0be0bd219e72	3793	((VL53LX_DevicePresetModes) 18)
charlesmn	0:0be0bd219e72	3794	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_REF_ARRAY \
charlesmn	0:0be0bd219e72	3795	((VL53LX_DevicePresetModes) 19)
charlesmn	0:0be0bd219e72	3796	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_WITH_MM1 \
charlesmn	0:0be0bd219e72	3797	((VL53LX_DevicePresetModes) 20)
charlesmn	0:0be0bd219e72	3798	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_WITH_MM2 \
charlesmn	0:0be0bd219e72	3799	((VL53LX_DevicePresetModes) 21)
charlesmn	0:0be0bd219e72	3800	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_MM1_CAL \
charlesmn	0:0be0bd219e72	3801	((VL53LX_DevicePresetModes) 22)
charlesmn	0:0be0bd219e72	3802	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_MM2_CAL \
charlesmn	0:0be0bd219e72	3803	((VL53LX_DevicePresetModes) 23)
charlesmn	0:0be0bd219e72	3804	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MULTIZONE \
charlesmn	0:0be0bd219e72	3805	((VL53LX_DevicePresetModes) 24)
charlesmn	0:0be0bd219e72	3806	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MULTIZONE_SHORT_RANGE \
charlesmn	0:0be0bd219e72	3807	((VL53LX_DevicePresetModes) 25)
charlesmn	0:0be0bd219e72	3808	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MULTIZONE_LONG_RANGE \
charlesmn	0:0be0bd219e72	3809	((VL53LX_DevicePresetModes) 26)
charlesmn	0:0be0bd219e72	3810	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE \
charlesmn	0:0be0bd219e72	3811	((VL53LX_DevicePresetModes) 27)
charlesmn	0:0be0bd219e72	3812	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE_MM1 \
charlesmn	0:0be0bd219e72	3813	((VL53LX_DevicePresetModes) 28)
charlesmn	0:0be0bd219e72	3814	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE_MM2 \
charlesmn	0:0be0bd219e72	3815	((VL53LX_DevicePresetModes) 29)
charlesmn	0:0be0bd219e72	3816	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE \
charlesmn	0:0be0bd219e72	3817	((VL53LX_DevicePresetModes) 30)
charlesmn	0:0be0bd219e72	3818	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE_MM1 \
charlesmn	0:0be0bd219e72	3819	((VL53LX_DevicePresetModes) 31)
charlesmn	0:0be0bd219e72	3820	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE_MM2 \
charlesmn	0:0be0bd219e72	3821	((VL53LX_DevicePresetModes) 32)
charlesmn	0:0be0bd219e72	3822	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE \
charlesmn	0:0be0bd219e72	3823	((VL53LX_DevicePresetModes) 33)
charlesmn	0:0be0bd219e72	3824	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE_MM1 \
charlesmn	0:0be0bd219e72	3825	((VL53LX_DevicePresetModes) 34)
charlesmn	0:0be0bd219e72	3826	#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE_MM2 \
charlesmn	0:0be0bd219e72	3827	((VL53LX_DevicePresetModes) 35)
charlesmn	0:0be0bd219e72	3828	#define VL53LX_DEVICEPRESETMODE_LOWPOWERAUTO_SHORT_RANGE \
charlesmn	0:0be0bd219e72	3829	((VL53LX_DevicePresetModes) 36)
charlesmn	0:0be0bd219e72	3830	#define VL53LX_DEVICEPRESETMODE_LOWPOWERAUTO_MEDIUM_RANGE \
charlesmn	0:0be0bd219e72	3831	((VL53LX_DevicePresetModes) 37)
charlesmn	0:0be0bd219e72	3832	#define VL53LX_DEVICEPRESETMODE_LOWPOWERAUTO_LONG_RANGE \
charlesmn	0:0be0bd219e72	3833	((VL53LX_DevicePresetModes) 38)
charlesmn	0:0be0bd219e72	3834	#define VL53LX_DEVICEPRESETMODE_SPECIAL_HISTOGRAM_SHORT_RANGE \
charlesmn	0:0be0bd219e72	3835	((VL53LX_DevicePresetModes) 39)
charlesmn	0:0be0bd219e72	3836
charlesmn	0:0be0bd219e72	3837
charlesmn	0:0be0bd219e72	3838
charlesmn	0:0be0bd219e72	3839
charlesmn	0:0be0bd219e72	3840
charlesmn	0:0be0bd219e72	3841	typedef uint8_t VL53LX_DeviceMeasurementModes;
charlesmn	0:0be0bd219e72	3842
charlesmn	0:0be0bd219e72	3843	#define VL53LX_DEVICEMEASUREMENTMODE_STOP \
charlesmn	0:0be0bd219e72	3844	((VL53LX_DeviceMeasurementModes) 0x00)
charlesmn	0:0be0bd219e72	3845	#define VL53LX_DEVICEMEASUREMENTMODE_SINGLESHOT \
charlesmn	0:0be0bd219e72	3846	((VL53LX_DeviceMeasurementModes) 0x10)
charlesmn	0:0be0bd219e72	3847	#define VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK \
charlesmn	0:0be0bd219e72	3848	((VL53LX_DeviceMeasurementModes) 0x20)
charlesmn	0:0be0bd219e72	3849	#define VL53LX_DEVICEMEASUREMENTMODE_TIMED \
charlesmn	0:0be0bd219e72	3850	((VL53LX_DeviceMeasurementModes) 0x40)
charlesmn	0:0be0bd219e72	3851	#define VL53LX_DEVICEMEASUREMENTMODE_ABORT \
charlesmn	0:0be0bd219e72	3852	((VL53LX_DeviceMeasurementModes) 0x80)
charlesmn	0:0be0bd219e72	3853
charlesmn	0:0be0bd219e72	3854
charlesmn	0:0be0bd219e72	3855
charlesmn	0:0be0bd219e72	3856
charlesmn	0:0be0bd219e72	3857
charlesmn	0:0be0bd219e72	3858	typedef uint8_t VL53LX_OffsetCalibrationMode;
charlesmn	0:0be0bd219e72	3859
charlesmn	0:0be0bd219e72	3860	#define VL53LX_OFFSETCALIBRATIONMODE__NONE \
charlesmn	0:0be0bd219e72	3861	((VL53LX_OffsetCalibrationMode) 0)
charlesmn	0:0be0bd219e72	3862	#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD \
charlesmn	0:0be0bd219e72	3863	((VL53LX_OffsetCalibrationMode) 1)
charlesmn	0:0be0bd219e72	3864	#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__HISTOGRAM \
charlesmn	0:0be0bd219e72	3865	((VL53LX_OffsetCalibrationMode) 2)
charlesmn	0:0be0bd219e72	3866	#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD_PRE_RANGE_ONLY \
charlesmn	0:0be0bd219e72	3867	((VL53LX_OffsetCalibrationMode) 3)
charlesmn	0:0be0bd219e72	3868	#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__HISTOGRAM_PRE_RANGE_ONLY \
charlesmn	0:0be0bd219e72	3869	((VL53LX_OffsetCalibrationMode) 4)
charlesmn	0:0be0bd219e72	3870
charlesmn	0:0be0bd219e72	3871
charlesmn	0:0be0bd219e72	3872
charlesmn	0:0be0bd219e72	3873
charlesmn	0:0be0bd219e72	3874
charlesmn	0:0be0bd219e72	3875	typedef uint8_t VL53LX_OffsetCorrectionMode;
charlesmn	0:0be0bd219e72	3876
charlesmn	0:0be0bd219e72	3877	#define VL53LX_OFFSETCORRECTIONMODE__NONE \
charlesmn	0:0be0bd219e72	3878	((VL53LX_OffsetCorrectionMode) 0)
charlesmn	0:0be0bd219e72	3879	#define VL53LX_OFFSETCORRECTIONMODE__MM1_MM2_OFFSETS \
charlesmn	0:0be0bd219e72	3880	((VL53LX_OffsetCorrectionMode) 1)
charlesmn	0:0be0bd219e72	3881	#define VL53LX_OFFSETCORRECTIONMODE__PER_VCSEL_OFFSETS \
charlesmn	0:0be0bd219e72	3882	((VL53LX_OffsetCorrectionMode) 3)
charlesmn	0:0be0bd219e72	3883
charlesmn	0:0be0bd219e72	3884
charlesmn	0:0be0bd219e72	3885
charlesmn	0:0be0bd219e72	3886
charlesmn	0:0be0bd219e72	3887
charlesmn	0:0be0bd219e72	3888	typedef uint8_t VL53LX_DeviceDmaxMode;
charlesmn	0:0be0bd219e72	3889
charlesmn	0:0be0bd219e72	3890	#define VL53LX_DEVICEDMAXMODE__NONE \
charlesmn	0:0be0bd219e72	3891	((VL53LX_DeviceDmaxMode) 0)
charlesmn	0:0be0bd219e72	3892	#define VL53LX_DEVICEDMAXMODE__FMT_CAL_DATA \
charlesmn	0:0be0bd219e72	3893	((VL53LX_DeviceDmaxMode) 1)
charlesmn	0:0be0bd219e72	3894	#define VL53LX_DEVICEDMAXMODE__CUST_CAL_DATA \
charlesmn	0:0be0bd219e72	3895	((VL53LX_DeviceDmaxMode) 2)
charlesmn	0:0be0bd219e72	3896
charlesmn	0:0be0bd219e72	3897
charlesmn	0:0be0bd219e72	3898
charlesmn	0:0be0bd219e72	3899
charlesmn	0:0be0bd219e72	3900
charlesmn	0:0be0bd219e72	3901	typedef uint8_t VL53LX_DeviceSequenceConfig;
charlesmn	0:0be0bd219e72	3902
charlesmn	0:0be0bd219e72	3903	#define VL53LX_DEVICESEQUENCECONFIG_VHV \
charlesmn	0:0be0bd219e72	3904	((VL53LX_DeviceSequenceConfig) 0)
charlesmn	0:0be0bd219e72	3905	#define VL53LX_DEVICESEQUENCECONFIG_PHASECAL \
charlesmn	0:0be0bd219e72	3906	((VL53LX_DeviceSequenceConfig) 1)
charlesmn	0:0be0bd219e72	3907	#define VL53LX_DEVICESEQUENCECONFIG_REFERENCE_PHASE \
charlesmn	0:0be0bd219e72	3908	((VL53LX_DeviceSequenceConfig) 2)
charlesmn	0:0be0bd219e72	3909	#define VL53LX_DEVICESEQUENCECONFIG_DSS1 \
charlesmn	0:0be0bd219e72	3910	((VL53LX_DeviceSequenceConfig) 3)
charlesmn	0:0be0bd219e72	3911	#define VL53LX_DEVICESEQUENCECONFIG_DSS2 \
charlesmn	0:0be0bd219e72	3912	((VL53LX_DeviceSequenceConfig) 4)
charlesmn	0:0be0bd219e72	3913	#define VL53LX_DEVICESEQUENCECONFIG_MM1 \
charlesmn	0:0be0bd219e72	3914	((VL53LX_DeviceSequenceConfig) 5)
charlesmn	0:0be0bd219e72	3915	#define VL53LX_DEVICESEQUENCECONFIG_MM2 \
charlesmn	0:0be0bd219e72	3916	((VL53LX_DeviceSequenceConfig) 6)
charlesmn	0:0be0bd219e72	3917	#define VL53LX_DEVICESEQUENCECONFIG_RANGE \
charlesmn	0:0be0bd219e72	3918	((VL53LX_DeviceSequenceConfig) 7)
charlesmn	0:0be0bd219e72	3919
charlesmn	0:0be0bd219e72	3920
charlesmn	0:0be0bd219e72	3921
charlesmn	0:0be0bd219e72	3922
charlesmn	0:0be0bd219e72	3923
charlesmn	0:0be0bd219e72	3924	typedef uint8_t VL53LX_DeviceInterruptPolarity;
charlesmn	0:0be0bd219e72	3925
charlesmn	0:0be0bd219e72	3926	#define VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_HIGH \
charlesmn	0:0be0bd219e72	3927	((VL53LX_DeviceInterruptPolarity) 0x00)
charlesmn	0:0be0bd219e72	3928	#define VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_LOW \
charlesmn	0:0be0bd219e72	3929	((VL53LX_DeviceInterruptPolarity) 0x10)
charlesmn	0:0be0bd219e72	3930	#define VL53LX_DEVICEINTERRUPTPOLARITY_BIT_MASK \
charlesmn	0:0be0bd219e72	3931	((VL53LX_DeviceInterruptPolarity) 0x10)
charlesmn	0:0be0bd219e72	3932	#define VL53LX_DEVICEINTERRUPTPOLARITY_CLEAR_MASK \
charlesmn	0:0be0bd219e72	3933	((VL53LX_DeviceInterruptPolarity) 0xEF)
charlesmn	0:0be0bd219e72	3934
charlesmn	0:0be0bd219e72	3935
charlesmn	0:0be0bd219e72	3936
charlesmn	0:0be0bd219e72	3937
charlesmn	0:0be0bd219e72	3938
charlesmn	0:0be0bd219e72	3939	typedef uint8_t VL53LX_DeviceGpioMode;
charlesmn	0:0be0bd219e72	3940
charlesmn	0:0be0bd219e72	3941	#define VL53LX_DEVICEGPIOMODE_OUTPUT_CONSTANT_ZERO \
charlesmn	0:0be0bd219e72	3942	((VL53LX_DeviceGpioMode) 0x00)
charlesmn	0:0be0bd219e72	3943	#define VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_AND_ERROR_INTERRUPTS \
charlesmn	0:0be0bd219e72	3944	((VL53LX_DeviceGpioMode) 0x01)
charlesmn	0:0be0bd219e72	3945	#define VL53LX_DEVICEGPIOMODE_OUTPUT_TIMIER_INTERRUPTS \
charlesmn	0:0be0bd219e72	3946	((VL53LX_DeviceGpioMode) 0x02)
charlesmn	0:0be0bd219e72	3947	#define VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_MODE_INTERRUPT_STATUS \
charlesmn	0:0be0bd219e72	3948	((VL53LX_DeviceGpioMode) 0x03)
charlesmn	0:0be0bd219e72	3949	#define VL53LX_DEVICEGPIOMODE_OUTPUT_SLOW_OSCILLATOR_CLOCK \
charlesmn	0:0be0bd219e72	3950	((VL53LX_DeviceGpioMode) 0x04)
charlesmn	0:0be0bd219e72	3951	#define VL53LX_DEVICEGPIOMODE_BIT_MASK \
charlesmn	0:0be0bd219e72	3952	((VL53LX_DeviceGpioMode) 0x0F)
charlesmn	0:0be0bd219e72	3953	#define VL53LX_DEVICEGPIOMODE_CLEAR_MASK \
charlesmn	0:0be0bd219e72	3954	((VL53LX_DeviceGpioMode) 0xF0)
charlesmn	0:0be0bd219e72	3955
charlesmn	0:0be0bd219e72	3956
charlesmn	0:0be0bd219e72	3957
charlesmn	0:0be0bd219e72	3958
charlesmn	0:0be0bd219e72	3959
charlesmn	0:0be0bd219e72	3960	typedef uint8_t VL53LX_DeviceError;
charlesmn	0:0be0bd219e72	3961
charlesmn	0:0be0bd219e72	3962	#define VL53LX_DEVICEERROR_NOUPDATE \
charlesmn	0:0be0bd219e72	3963	((VL53LX_DeviceError) 0)
charlesmn	0:0be0bd219e72	3964
charlesmn	0:0be0bd219e72	3965	#define VL53LX_DEVICEERROR_VCSELCONTINUITYTESTFAILURE \
charlesmn	0:0be0bd219e72	3966	((VL53LX_DeviceError) 1)
charlesmn	0:0be0bd219e72	3967	#define VL53LX_DEVICEERROR_VCSELWATCHDOGTESTFAILURE \
charlesmn	0:0be0bd219e72	3968	((VL53LX_DeviceError) 2)
charlesmn	0:0be0bd219e72	3969	#define VL53LX_DEVICEERROR_NOVHVVALUEFOUND \
charlesmn	0:0be0bd219e72	3970	((VL53LX_DeviceError) 3)
charlesmn	0:0be0bd219e72	3971	#define VL53LX_DEVICEERROR_MSRCNOTARGET \
charlesmn	0:0be0bd219e72	3972	((VL53LX_DeviceError) 4)
charlesmn	0:0be0bd219e72	3973	#define VL53LX_DEVICEERROR_RANGEPHASECHECK \
charlesmn	0:0be0bd219e72	3974	((VL53LX_DeviceError) 5)
charlesmn	0:0be0bd219e72	3975	#define VL53LX_DEVICEERROR_SIGMATHRESHOLDCHECK \
charlesmn	0:0be0bd219e72	3976	((VL53LX_DeviceError) 6)
charlesmn	0:0be0bd219e72	3977	#define VL53LX_DEVICEERROR_PHASECONSISTENCY \
charlesmn	0:0be0bd219e72	3978	((VL53LX_DeviceError) 7)
charlesmn	0:0be0bd219e72	3979	#define VL53LX_DEVICEERROR_MINCLIP \
charlesmn	0:0be0bd219e72	3980	((VL53LX_DeviceError) 8)
charlesmn	0:0be0bd219e72	3981	#define VL53LX_DEVICEERROR_RANGECOMPLETE \
charlesmn	0:0be0bd219e72	3982	((VL53LX_DeviceError) 9)
charlesmn	0:0be0bd219e72	3983	#define VL53LX_DEVICEERROR_ALGOUNDERFLOW \
charlesmn	0:0be0bd219e72	3984	((VL53LX_DeviceError) 10)
charlesmn	0:0be0bd219e72	3985	#define VL53LX_DEVICEERROR_ALGOOVERFLOW \
charlesmn	0:0be0bd219e72	3986	((VL53LX_DeviceError) 11)
charlesmn	0:0be0bd219e72	3987	#define VL53LX_DEVICEERROR_RANGEIGNORETHRESHOLD \
charlesmn	0:0be0bd219e72	3988	((VL53LX_DeviceError) 12)
charlesmn	0:0be0bd219e72	3989	#define VL53LX_DEVICEERROR_USERROICLIP \
charlesmn	0:0be0bd219e72	3990	((VL53LX_DeviceError) 13)
charlesmn	0:0be0bd219e72	3991	#define VL53LX_DEVICEERROR_REFSPADCHARNOTENOUGHDPADS \
charlesmn	0:0be0bd219e72	3992	((VL53LX_DeviceError) 14)
charlesmn	0:0be0bd219e72	3993	#define VL53LX_DEVICEERROR_REFSPADCHARMORETHANTARGET \
charlesmn	0:0be0bd219e72	3994	((VL53LX_DeviceError) 15)
charlesmn	0:0be0bd219e72	3995	#define VL53LX_DEVICEERROR_REFSPADCHARLESSTHANTARGET \
charlesmn	0:0be0bd219e72	3996	((VL53LX_DeviceError) 16)
charlesmn	0:0be0bd219e72	3997	#define VL53LX_DEVICEERROR_MULTCLIPFAIL \
charlesmn	0:0be0bd219e72	3998	((VL53LX_DeviceError) 17)
charlesmn	0:0be0bd219e72	3999	#define VL53LX_DEVICEERROR_GPHSTREAMCOUNT0READY \
charlesmn	0:0be0bd219e72	4000	((VL53LX_DeviceError) 18)
charlesmn	0:0be0bd219e72	4001	#define VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK \
charlesmn	0:0be0bd219e72	4002	((VL53LX_DeviceError) 19)
charlesmn	0:0be0bd219e72	4003	#define VL53LX_DEVICEERROR_EVENTCONSISTENCY \
charlesmn	0:0be0bd219e72	4004	((VL53LX_DeviceError) 20)
charlesmn	0:0be0bd219e72	4005	#define VL53LX_DEVICEERROR_MINSIGNALEVENTCHECK \
charlesmn	0:0be0bd219e72	4006	((VL53LX_DeviceError) 21)
charlesmn	0:0be0bd219e72	4007	#define VL53LX_DEVICEERROR_RANGECOMPLETE_MERGED_PULSE \
charlesmn	0:0be0bd219e72	4008	((VL53LX_DeviceError) 22)
charlesmn	0:0be0bd219e72	4009
charlesmn	0:0be0bd219e72	4010
charlesmn	0:0be0bd219e72	4011	#define VL53LX_DEVICEERROR_PREV_RANGE_NO_TARGETS \
charlesmn	0:0be0bd219e72	4012	((VL53LX_DeviceError) 23)
charlesmn	0:0be0bd219e72	4013
charlesmn	0:0be0bd219e72	4014
charlesmn	0:0be0bd219e72	4015
charlesmn	0:0be0bd219e72	4016
charlesmn	0:0be0bd219e72	4017
charlesmn	0:0be0bd219e72	4018	typedef uint8_t VL53LX_DeviceReportStatus;
charlesmn	0:0be0bd219e72	4019
charlesmn	0:0be0bd219e72	4020	#define VL53LX_DEVICEREPORTSTATUS_NOUPDATE \
charlesmn	0:0be0bd219e72	4021	((VL53LX_DeviceReportStatus) 0)
charlesmn	0:0be0bd219e72	4022
charlesmn	0:0be0bd219e72	4023	#define VL53LX_DEVICEREPORTSTATUS_ROI_SETUP \
charlesmn	0:0be0bd219e72	4024	((VL53LX_DeviceReportStatus) 1)
charlesmn	0:0be0bd219e72	4025	#define VL53LX_DEVICEREPORTSTATUS_VHV \
charlesmn	0:0be0bd219e72	4026	((VL53LX_DeviceReportStatus) 2)
charlesmn	0:0be0bd219e72	4027	#define VL53LX_DEVICEREPORTSTATUS_PHASECAL \
charlesmn	0:0be0bd219e72	4028	((VL53LX_DeviceReportStatus) 3)
charlesmn	0:0be0bd219e72	4029	#define VL53LX_DEVICEREPORTSTATUS_REFERENCE_PHASE \
charlesmn	0:0be0bd219e72	4030	((VL53LX_DeviceReportStatus) 4)
charlesmn	0:0be0bd219e72	4031	#define VL53LX_DEVICEREPORTSTATUS_DSS1 \
charlesmn	0:0be0bd219e72	4032	((VL53LX_DeviceReportStatus) 5)
charlesmn	0:0be0bd219e72	4033	#define VL53LX_DEVICEREPORTSTATUS_DSS2 \
charlesmn	0:0be0bd219e72	4034	((VL53LX_DeviceReportStatus) 6)
charlesmn	0:0be0bd219e72	4035	#define VL53LX_DEVICEREPORTSTATUS_MM1 \
charlesmn	0:0be0bd219e72	4036	((VL53LX_DeviceReportStatus) 7)
charlesmn	0:0be0bd219e72	4037	#define VL53LX_DEVICEREPORTSTATUS_MM2 \
charlesmn	0:0be0bd219e72	4038	((VL53LX_DeviceReportStatus) 8)
charlesmn	0:0be0bd219e72	4039	#define VL53LX_DEVICEREPORTSTATUS_RANGE \
charlesmn	0:0be0bd219e72	4040	((VL53LX_DeviceReportStatus) 9)
charlesmn	0:0be0bd219e72	4041	#define VL53LX_DEVICEREPORTSTATUS_HISTOGRAM \
charlesmn	0:0be0bd219e72	4042	((VL53LX_DeviceReportStatus) 10)
charlesmn	0:0be0bd219e72	4043
charlesmn	0:0be0bd219e72	4044
charlesmn	0:0be0bd219e72	4045
charlesmn	0:0be0bd219e72	4046
charlesmn	0:0be0bd219e72	4047
charlesmn	0:0be0bd219e72	4048	typedef uint8_t VL53LX_DeviceDssMode;
charlesmn	0:0be0bd219e72	4049
charlesmn	0:0be0bd219e72	4050	#define VL53LX_DEVICEDSSMODE__DISABLED \
charlesmn	0:0be0bd219e72	4051	((VL53LX_DeviceDssMode) 0)
charlesmn	0:0be0bd219e72	4052	#define VL53LX_DEVICEDSSMODE__TARGET_RATE \
charlesmn	0:0be0bd219e72	4053	((VL53LX_DeviceDssMode) 1)
charlesmn	0:0be0bd219e72	4054	#define VL53LX_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS \
charlesmn	0:0be0bd219e72	4055	((VL53LX_DeviceDssMode) 2)
charlesmn	0:0be0bd219e72	4056	#define VL53LX_DEVICEDSSMODE__BLOCK_SELECT \
charlesmn	0:0be0bd219e72	4057	((VL53LX_DeviceDssMode) 3)
charlesmn	0:0be0bd219e72	4058
charlesmn	0:0be0bd219e72	4059
charlesmn	0:0be0bd219e72	4060
charlesmn	0:0be0bd219e72	4061
charlesmn	0:0be0bd219e72	4062
charlesmn	0:0be0bd219e72	4063
charlesmn	0:0be0bd219e72	4064	typedef uint8_t VL53LX_HistAlgoSelect;
charlesmn	0:0be0bd219e72	4065
charlesmn	0:0be0bd219e72	4066	#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN1 \
charlesmn	0:0be0bd219e72	4067	((VL53LX_HistAlgoSelect) 1)
charlesmn	0:0be0bd219e72	4068	#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN2 \
charlesmn	0:0be0bd219e72	4069	((VL53LX_HistAlgoSelect) 2)
charlesmn	0:0be0bd219e72	4070	#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN3 \
charlesmn	0:0be0bd219e72	4071	((VL53LX_HistAlgoSelect) 3)
charlesmn	0:0be0bd219e72	4072	#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN4 \
charlesmn	0:0be0bd219e72	4073	((VL53LX_HistAlgoSelect) 4)
charlesmn	0:0be0bd219e72	4074
charlesmn	0:0be0bd219e72	4075
charlesmn	0:0be0bd219e72	4076
charlesmn	0:0be0bd219e72	4077
charlesmn	0:0be0bd219e72	4078
charlesmn	0:0be0bd219e72	4079
charlesmn	0:0be0bd219e72	4080	typedef uint8_t VL53LX_HistTargetOrder;
charlesmn	0:0be0bd219e72	4081
charlesmn	0:0be0bd219e72	4082	#define VL53LX_HIST_TARGET_ORDER__INCREASING_DISTANCE \
charlesmn	0:0be0bd219e72	4083	((VL53LX_HistTargetOrder) 1)
charlesmn	0:0be0bd219e72	4084	#define VL53LX_HIST_TARGET_ORDER__STRONGEST_FIRST \
charlesmn	0:0be0bd219e72	4085	((VL53LX_HistTargetOrder) 2)
charlesmn	0:0be0bd219e72	4086
charlesmn	0:0be0bd219e72	4087
charlesmn	0:0be0bd219e72	4088
charlesmn	0:0be0bd219e72	4089
charlesmn	0:0be0bd219e72	4090
charlesmn	0:0be0bd219e72	4091
charlesmn	0:0be0bd219e72	4092	typedef uint8_t VL53LX_HistAmbEstMethod;
charlesmn	0:0be0bd219e72	4093
charlesmn	0:0be0bd219e72	4094	#define VL53LX_HIST_AMB_EST_METHOD__AMBIENT_BINS \
charlesmn	0:0be0bd219e72	4095	((VL53LX_HistAmbEstMethod) 1)
charlesmn	0:0be0bd219e72	4096	#define VL53LX_HIST_AMB_EST_METHOD__THRESHOLDED_BINS \
charlesmn	0:0be0bd219e72	4097	((VL53LX_HistAmbEstMethod) 2)
charlesmn	0:0be0bd219e72	4098
charlesmn	0:0be0bd219e72	4099
charlesmn	0:0be0bd219e72	4100
charlesmn	0:0be0bd219e72	4101
charlesmn	0:0be0bd219e72	4102
charlesmn	0:0be0bd219e72	4103
charlesmn	0:0be0bd219e72	4104	typedef uint8_t VL53LX_HistXtalkCompEnable;
charlesmn	0:0be0bd219e72	4105
charlesmn	0:0be0bd219e72	4106	#define VL53LX_HIST_XTALK_COMP__DIS \
charlesmn	0:0be0bd219e72	4107	((VL53LX_HistXtalkCompEnable) 0)
charlesmn	0:0be0bd219e72	4108	#define VL53LX_HIST_XTALK_COMP__EN \
charlesmn	0:0be0bd219e72	4109	((VL53LX_HistXtalkCompEnable) 1)
charlesmn	0:0be0bd219e72	4110
charlesmn	0:0be0bd219e72	4111
charlesmn	0:0be0bd219e72	4112
charlesmn	0:0be0bd219e72	4113
charlesmn	0:0be0bd219e72	4114	typedef uint8_t VL53LX_DeviceConfigLevel;
charlesmn	0:0be0bd219e72	4115
charlesmn	0:0be0bd219e72	4116	#define VL53LX_DEVICECONFIGLEVEL_SYSTEM_CONTROL \
charlesmn	0:0be0bd219e72	4117	((VL53LX_DeviceConfigLevel) 0)
charlesmn	0:0be0bd219e72	4118
charlesmn	0:0be0bd219e72	4119	#define VL53LX_DEVICECONFIGLEVEL_DYNAMIC_ONWARDS \
charlesmn	0:0be0bd219e72	4120	((VL53LX_DeviceConfigLevel) 1)
charlesmn	0:0be0bd219e72	4121
charlesmn	0:0be0bd219e72	4122	#define VL53LX_DEVICECONFIGLEVEL_TIMING_ONWARDS \
charlesmn	0:0be0bd219e72	4123	((VL53LX_DeviceConfigLevel) 2)
charlesmn	0:0be0bd219e72	4124
charlesmn	0:0be0bd219e72	4125	#define VL53LX_DEVICECONFIGLEVEL_GENERAL_ONWARDS \
charlesmn	0:0be0bd219e72	4126	((VL53LX_DeviceConfigLevel) 3)
charlesmn	0:0be0bd219e72	4127
charlesmn	0:0be0bd219e72	4128	#define VL53LX_DEVICECONFIGLEVEL_STATIC_ONWARDS \
charlesmn	0:0be0bd219e72	4129	((VL53LX_DeviceConfigLevel) 4)
charlesmn	0:0be0bd219e72	4130
charlesmn	0:0be0bd219e72	4131	#define VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS \
charlesmn	0:0be0bd219e72	4132	((VL53LX_DeviceConfigLevel) 5)
charlesmn	0:0be0bd219e72	4133
charlesmn	0:0be0bd219e72	4134	#define VL53LX_DEVICECONFIGLEVEL_FULL \
charlesmn	0:0be0bd219e72	4135	((VL53LX_DeviceConfigLevel) 6)
charlesmn	0:0be0bd219e72	4136
charlesmn	0:0be0bd219e72	4137
charlesmn	0:0be0bd219e72	4138
charlesmn	0:0be0bd219e72	4139
charlesmn	0:0be0bd219e72	4140
charlesmn	0:0be0bd219e72	4141
charlesmn	0:0be0bd219e72	4142	typedef uint8_t VL53LX_DeviceResultsLevel;
charlesmn	0:0be0bd219e72	4143
charlesmn	0:0be0bd219e72	4144	#define VL53LX_DEVICERESULTSLEVEL_SYSTEM_RESULTS \
charlesmn	0:0be0bd219e72	4145	((VL53LX_DeviceResultsLevel) 0)
charlesmn	0:0be0bd219e72	4146
charlesmn	0:0be0bd219e72	4147	#define VL53LX_DEVICERESULTSLEVEL_UPTO_CORE \
charlesmn	0:0be0bd219e72	4148	((VL53LX_DeviceResultsLevel) 1)
charlesmn	0:0be0bd219e72	4149
charlesmn	0:0be0bd219e72	4150	#define VL53LX_DEVICERESULTSLEVEL_FULL \
charlesmn	0:0be0bd219e72	4151	((VL53LX_DeviceResultsLevel) 2)
charlesmn	0:0be0bd219e72	4152
charlesmn	0:0be0bd219e72	4153
charlesmn	0:0be0bd219e72	4154
charlesmn	0:0be0bd219e72	4155
charlesmn	0:0be0bd219e72	4156
charlesmn	0:0be0bd219e72	4157
charlesmn	0:0be0bd219e72	4158
charlesmn	0:0be0bd219e72	4159	typedef uint8_t VL53LX_DeviceTestMode;
charlesmn	0:0be0bd219e72	4160
charlesmn	0:0be0bd219e72	4161	#define VL53LX_DEVICETESTMODE_NONE \
charlesmn	0:0be0bd219e72	4162	((VL53LX_DeviceTestMode) 0x00)
charlesmn	0:0be0bd219e72	4163
charlesmn	0:0be0bd219e72	4164	#define VL53LX_DEVICETESTMODE_NVM_ZERO \
charlesmn	0:0be0bd219e72	4165	((VL53LX_DeviceTestMode) 0x01)
charlesmn	0:0be0bd219e72	4166
charlesmn	0:0be0bd219e72	4167	#define VL53LX_DEVICETESTMODE_NVM_COPY \
charlesmn	0:0be0bd219e72	4168	((VL53LX_DeviceTestMode) 0x02)
charlesmn	0:0be0bd219e72	4169
charlesmn	0:0be0bd219e72	4170	#define VL53LX_DEVICETESTMODE_PATCH \
charlesmn	0:0be0bd219e72	4171	((VL53LX_DeviceTestMode) 0x03)
charlesmn	0:0be0bd219e72	4172
charlesmn	0:0be0bd219e72	4173	#define VL53LX_DEVICETESTMODE_DCR \
charlesmn	0:0be0bd219e72	4174	((VL53LX_DeviceTestMode) 0x04)
charlesmn	0:0be0bd219e72	4175
charlesmn	0:0be0bd219e72	4176	#define VL53LX_DEVICETESTMODE_LCR_VCSEL_OFF \
charlesmn	0:0be0bd219e72	4177	((VL53LX_DeviceTestMode) 0x05)
charlesmn	0:0be0bd219e72	4178
charlesmn	0:0be0bd219e72	4179	#define VL53LX_DEVICETESTMODE_LCR_VCSEL_ON \
charlesmn	0:0be0bd219e72	4180	((VL53LX_DeviceTestMode) 0x06)
charlesmn	0:0be0bd219e72	4181
charlesmn	0:0be0bd219e72	4182	#define VL53LX_DEVICETESTMODE_SPOT_CENTRE_LOCATE \
charlesmn	0:0be0bd219e72	4183	((VL53LX_DeviceTestMode) 0x07)
charlesmn	0:0be0bd219e72	4184
charlesmn	0:0be0bd219e72	4185	#define VL53LX_DEVICETESTMODE_REF_SPAD_CHAR_WITH_PRE_VHV \
charlesmn	0:0be0bd219e72	4186	((VL53LX_DeviceTestMode) 0x08)
charlesmn	0:0be0bd219e72	4187
charlesmn	0:0be0bd219e72	4188	#define VL53LX_DEVICETESTMODE_REF_SPAD_CHAR_ONLY \
charlesmn	0:0be0bd219e72	4189	((VL53LX_DeviceTestMode) 0x09)
charlesmn	0:0be0bd219e72	4190
charlesmn	0:0be0bd219e72	4191
charlesmn	0:0be0bd219e72	4192
charlesmn	0:0be0bd219e72	4193
charlesmn	0:0be0bd219e72	4194
charlesmn	0:0be0bd219e72	4195
charlesmn	0:0be0bd219e72	4196
charlesmn	0:0be0bd219e72	4197	typedef uint8_t VL53LX_DeviceSscArray;
charlesmn	0:0be0bd219e72	4198
charlesmn	0:0be0bd219e72	4199	#define VL53LX_DEVICESSCARRAY_RTN ((VL53LX_DeviceSscArray) 0x00)
charlesmn	0:0be0bd219e72	4200
charlesmn	0:0be0bd219e72	4201	#define VL53LX_DEVICETESTMODE_REF ((VL53LX_DeviceSscArray) 0x01)
charlesmn	0:0be0bd219e72	4202
charlesmn	0:0be0bd219e72	4203
charlesmn	0:0be0bd219e72	4204
charlesmn	0:0be0bd219e72	4205
charlesmn	0:0be0bd219e72	4206
charlesmn	0:0be0bd219e72	4207
charlesmn	0:0be0bd219e72	4208
charlesmn	0:0be0bd219e72	4209	#define VL53LX_RETURN_ARRAY_ONLY 0x01
charlesmn	0:0be0bd219e72	4210
charlesmn	0:0be0bd219e72	4211	#define VL53LX_REFERENCE_ARRAY_ONLY 0x10
charlesmn	0:0be0bd219e72	4212
charlesmn	0:0be0bd219e72	4213	#define VL53LX_BOTH_RETURN_AND_REFERENCE_ARRAYS 0x11
charlesmn	0:0be0bd219e72	4214
charlesmn	0:0be0bd219e72	4215	#define VL53LX_NEITHER_RETURN_AND_REFERENCE_ARRAYS 0x00
charlesmn	0:0be0bd219e72	4216
charlesmn	0:0be0bd219e72	4217
charlesmn	0:0be0bd219e72	4218
charlesmn	0:0be0bd219e72	4219
charlesmn	0:0be0bd219e72	4220
charlesmn	0:0be0bd219e72	4221
charlesmn	0:0be0bd219e72	4222	#define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_HIGH 0x00
charlesmn	0:0be0bd219e72	4223
charlesmn	0:0be0bd219e72	4224	#define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_LOW 0x10
charlesmn	0:0be0bd219e72	4225
charlesmn	0:0be0bd219e72	4226	#define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_MASK 0x10
charlesmn	0:0be0bd219e72	4227
charlesmn	0:0be0bd219e72	4228
charlesmn	0:0be0bd219e72	4229
charlesmn	0:0be0bd219e72	4230
charlesmn	0:0be0bd219e72	4231
charlesmn	0:0be0bd219e72	4232
charlesmn	0:0be0bd219e72	4233	#define VL53LX_POLLING_DELAY_US 1000
charlesmn	0:0be0bd219e72	4234
charlesmn	0:0be0bd219e72	4235	#define VL53LX_SOFTWARE_RESET_DURATION_US 100
charlesmn	0:0be0bd219e72	4236
charlesmn	0:0be0bd219e72	4237	#define VL53LX_FIRMWARE_BOOT_TIME_US 1200
charlesmn	0:0be0bd219e72	4238
charlesmn	0:0be0bd219e72	4239	#define VL53LX_ENABLE_POWERFORCE_SETTLING_TIME_US 250
charlesmn	0:0be0bd219e72	4240
charlesmn	0:0be0bd219e72	4241	#define VL53LX_SPAD_ARRAY_WIDTH 16
charlesmn	0:0be0bd219e72	4242
charlesmn	0:0be0bd219e72	4243	#define VL53LX_SPAD_ARRAY_HEIGHT 16
charlesmn	0:0be0bd219e72	4244
charlesmn	0:0be0bd219e72	4245	#define VL53LX_NVM_SIZE_IN_BYTES 512
charlesmn	0:0be0bd219e72	4246
charlesmn	0:0be0bd219e72	4247	#define VL53LX_NO_OF_SPAD_ENABLES 256
charlesmn	0:0be0bd219e72	4248
charlesmn	0:0be0bd219e72	4249	#define VL53LX_RTN_SPAD_BUFFER_SIZE 32
charlesmn	0:0be0bd219e72	4250
charlesmn	0:0be0bd219e72	4251	#define VL53LX_REF_SPAD_BUFFER_SIZE 6
charlesmn	0:0be0bd219e72	4252
charlesmn	0:0be0bd219e72	4253	#define VL53LX_AMBIENT_WINDOW_VCSEL_PERIODS 256
charlesmn	0:0be0bd219e72	4254
charlesmn	0:0be0bd219e72	4255	#define VL53LX_RANGING_WINDOW_VCSEL_PERIODS 2048
charlesmn	0:0be0bd219e72	4256
charlesmn	0:0be0bd219e72	4257	#define VL53LX_MACRO_PERIOD_VCSEL_PERIODS \
charlesmn	0:0be0bd219e72	4258	(VL53LX_AMBIENT_WINDOW_VCSEL_PERIODS + \
charlesmn	0:0be0bd219e72	4259	VL53LX_RANGING_WINDOW_VCSEL_PERIODS)
charlesmn	0:0be0bd219e72	4260
charlesmn	0:0be0bd219e72	4261	#define VL53LX_MAX_ALLOWED_PHASE 0xFFFF
charlesmn	0:0be0bd219e72	4262
charlesmn	0:0be0bd219e72	4263
charlesmn	0:0be0bd219e72	4264	#define VL53LX_RTN_SPAD_UNITY_TRANSMISSION 0x0100
charlesmn	0:0be0bd219e72	4265
charlesmn	0:0be0bd219e72	4266	#define VL53LX_RTN_SPAD_APERTURE_TRANSMISSION 0x0038
charlesmn	0:0be0bd219e72	4267
charlesmn	0:0be0bd219e72	4268
charlesmn	0:0be0bd219e72	4269	#define VL53LX_SPAD_TOTAL_COUNT_MAX ((0x01 << 29) - 1)
charlesmn	0:0be0bd219e72	4270
charlesmn	0:0be0bd219e72	4271	#define VL53LX_SPAD_TOTAL_COUNT_RES_THRES (0x01 << 24)
charlesmn	0:0be0bd219e72	4272
charlesmn	0:0be0bd219e72	4273	#define VL53LX_COUNT_RATE_INTERNAL_MAX ((0x01 << 24) - 1)
charlesmn	0:0be0bd219e72	4274
charlesmn	0:0be0bd219e72	4275	#define VL53LX_SPEED_OF_LIGHT_IN_AIR 299704
charlesmn	0:0be0bd219e72	4276
charlesmn	0:0be0bd219e72	4277	#define VL53LX_SPEED_OF_LIGHT_IN_AIR_DIV_8 (299704 >> 3)
charlesmn	0:0be0bd219e72	4278
charlesmn	0:0be0bd219e72	4279
charlesmn	0:0be0bd219e72	4280
charlesmn	0:0be0bd219e72	4281
charlesmn	0:0be0bd219e72	4282
charlesmn	0:0be0bd219e72	4283
charlesmn	0:0be0bd219e72	4284
charlesmn	0:0be0bd219e72	4285
charlesmn	0:0be0bd219e72	4286	typedef uint8_t VL53LX_ZoneConfig_BinConfig_select;
charlesmn	0:0be0bd219e72	4287
charlesmn	0:0be0bd219e72	4288	#define VL53LX_ZONECONFIG_BINCONFIG__LOWAMB \
charlesmn	0:0be0bd219e72	4289	((VL53LX_ZoneConfig_BinConfig_select) 1)
charlesmn	0:0be0bd219e72	4290	#define VL53LX_ZONECONFIG_BINCONFIG__MIDAMB \
charlesmn	0:0be0bd219e72	4291	((VL53LX_ZoneConfig_BinConfig_select) 2)
charlesmn	0:0be0bd219e72	4292	#define VL53LX_ZONECONFIG_BINCONFIG__HIGHAMB \
charlesmn	0:0be0bd219e72	4293	((VL53LX_ZoneConfig_BinConfig_select) 3)
charlesmn	0:0be0bd219e72	4294
charlesmn	0:0be0bd219e72	4295
charlesmn	0:0be0bd219e72	4296
charlesmn	0:0be0bd219e72	4297
charlesmn	0:0be0bd219e72	4298
charlesmn	0:0be0bd219e72	4299	typedef uint8_t VL53LX_GPIO_Interrupt_Mode;
charlesmn	0:0be0bd219e72	4300
charlesmn	0:0be0bd219e72	4301	#define VL53LX_GPIOINTMODE_LEVEL_LOW \
charlesmn	0:0be0bd219e72	4302	((VL53LX_GPIO_Interrupt_Mode) 0)
charlesmn	0:0be0bd219e72	4303
charlesmn	0:0be0bd219e72	4304	#define VL53LX_GPIOINTMODE_LEVEL_HIGH \
charlesmn	0:0be0bd219e72	4305	((VL53LX_GPIO_Interrupt_Mode) 1)
charlesmn	0:0be0bd219e72	4306
charlesmn	0:0be0bd219e72	4307	#define VL53LX_GPIOINTMODE_OUT_OF_WINDOW \
charlesmn	0:0be0bd219e72	4308	((VL53LX_GPIO_Interrupt_Mode) 2)
charlesmn	0:0be0bd219e72	4309
charlesmn	0:0be0bd219e72	4310	#define VL53LX_GPIOINTMODE_IN_WINDOW \
charlesmn	0:0be0bd219e72	4311	((VL53LX_GPIO_Interrupt_Mode) 3)
charlesmn	0:0be0bd219e72	4312
charlesmn	0:0be0bd219e72	4313
charlesmn	0:0be0bd219e72	4314
charlesmn	0:0be0bd219e72	4315
charlesmn	0:0be0bd219e72	4316
charlesmn	0:0be0bd219e72	4317
charlesmn	0:0be0bd219e72	4318	typedef uint16_t VL53LX_TuningParms;
charlesmn	0:0be0bd219e72	4319
charlesmn	0:0be0bd219e72	4320	#define VL53LX_TUNINGPARMS_LLD_PUBLIC_MIN_ADDRESS \
charlesmn	0:0be0bd219e72	4321	((VL53LX_TuningParms) VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS)
charlesmn	0:0be0bd219e72	4322	#define VL53LX_TUNINGPARMS_LLD_PUBLIC_MAX_ADDRESS \
charlesmn	0:0be0bd219e72	4323	((VL53LX_TuningParms) VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR)
charlesmn	0:0be0bd219e72	4324
charlesmn	0:0be0bd219e72	4325	#define VL53LX_TUNINGPARMS_LLD_PRIVATE_MIN_ADDRESS \
charlesmn	0:0be0bd219e72	4326	((VL53LX_TuningParms) VL53LX_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS)
charlesmn	0:0be0bd219e72	4327	#define VL53LX_TUNINGPARMS_LLD_PRIVATE_MAX_ADDRESS \
charlesmn	0:0be0bd219e72	4328	((VL53LX_TuningParms) VL53LX_TUNINGPARMS_LLD_PRIVATE_MIN_ADDRESS)
charlesmn	0:0be0bd219e72	4329
charlesmn	0:0be0bd219e72	4330	#define VL53LX_TUNINGPARM_VERSION \
charlesmn	0:0be0bd219e72	4331	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 0))
charlesmn	0:0be0bd219e72	4332	#define VL53LX_TUNINGPARM_KEY_TABLE_VERSION \
charlesmn	0:0be0bd219e72	4333	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 1))
charlesmn	0:0be0bd219e72	4334	#define VL53LX_TUNINGPARM_LLD_VERSION \
charlesmn	0:0be0bd219e72	4335	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 2))
charlesmn	0:0be0bd219e72	4336	#define VL53LX_TUNINGPARM_HIST_ALGO_SELECT \
charlesmn	0:0be0bd219e72	4337	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 3))
charlesmn	0:0be0bd219e72	4338	#define VL53LX_TUNINGPARM_HIST_TARGET_ORDER \
charlesmn	0:0be0bd219e72	4339	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 4))
charlesmn	0:0be0bd219e72	4340	#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_0 \
charlesmn	0:0be0bd219e72	4341	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 5))
charlesmn	0:0be0bd219e72	4342	#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_1 \
charlesmn	0:0be0bd219e72	4343	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 6))
charlesmn	0:0be0bd219e72	4344	#define VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD \
charlesmn	0:0be0bd219e72	4345	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 7))
charlesmn	0:0be0bd219e72	4346	#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0 \
charlesmn	0:0be0bd219e72	4347	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 8))
charlesmn	0:0be0bd219e72	4348	#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1 \
charlesmn	0:0be0bd219e72	4349	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 9))
charlesmn	0:0be0bd219e72	4350	#define VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS \
charlesmn	0:0be0bd219e72	4351	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 10))
charlesmn	0:0be0bd219e72	4352	#define VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER \
charlesmn	0:0be0bd219e72	4353	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 11))
charlesmn	0:0be0bd219e72	4354	#define VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD \
charlesmn	0:0be0bd219e72	4355	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 12))
charlesmn	0:0be0bd219e72	4356	#define VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT \
charlesmn	0:0be0bd219e72	4357	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 13))
charlesmn	0:0be0bd219e72	4358	#define VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM \
charlesmn	0:0be0bd219e72	4359	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 14))
charlesmn	0:0be0bd219e72	4360	#define VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM \
charlesmn	0:0be0bd219e72	4361	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 15))
charlesmn	0:0be0bd219e72	4362	#define VL53LX_TUNINGPARM_HIST_GAIN_FACTOR \
charlesmn	0:0be0bd219e72	4363	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 16))
charlesmn	0:0be0bd219e72	4364	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE \
charlesmn	0:0be0bd219e72	4365	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 17))
charlesmn	0:0be0bd219e72	4366	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM \
charlesmn	0:0be0bd219e72	4367	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 18))
charlesmn	0:0be0bd219e72	4368	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA \
charlesmn	0:0be0bd219e72	4369	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 19))
charlesmn	0:0be0bd219e72	4370	#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT \
charlesmn	0:0be0bd219e72	4371	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 20))
charlesmn	0:0be0bd219e72	4372	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE \
charlesmn	0:0be0bd219e72	4373	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 21))
charlesmn	0:0be0bd219e72	4374	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE \
charlesmn	0:0be0bd219e72	4375	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 22))
charlesmn	0:0be0bd219e72	4376	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE \
charlesmn	0:0be0bd219e72	4377	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 23))
charlesmn	0:0be0bd219e72	4378	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE \
charlesmn	0:0be0bd219e72	4379	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 24))
charlesmn	0:0be0bd219e72	4380	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE \
charlesmn	0:0be0bd219e72	4381	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 25))
charlesmn	0:0be0bd219e72	4382	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE \
charlesmn	0:0be0bd219e72	4383	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 26))
charlesmn	0:0be0bd219e72	4384	#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM \
charlesmn	0:0be0bd219e72	4385	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 27))
charlesmn	0:0be0bd219e72	4386	#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM \
charlesmn	0:0be0bd219e72	4387	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 28))
charlesmn	0:0be0bd219e72	4388	#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM \
charlesmn	0:0be0bd219e72	4389	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 29))
charlesmn	0:0be0bd219e72	4390	#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE \
charlesmn	0:0be0bd219e72	4391	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 30))
charlesmn	0:0be0bd219e72	4392	#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS \
charlesmn	0:0be0bd219e72	4393	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 31))
charlesmn	0:0be0bd219e72	4394	#define VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA \
charlesmn	0:0be0bd219e72	4395	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 32))
charlesmn	0:0be0bd219e72	4396	#define VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS \
charlesmn	0:0be0bd219e72	4397	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 33))
charlesmn	0:0be0bd219e72	4398	#define VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE \
charlesmn	0:0be0bd219e72	4399	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 34))
charlesmn	0:0be0bd219e72	4400	#define VL53LX_TUNINGPARM_PHASECAL_TARGET \
charlesmn	0:0be0bd219e72	4401	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 35))
charlesmn	0:0be0bd219e72	4402	#define VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE \
charlesmn	0:0be0bd219e72	4403	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 36))
charlesmn	0:0be0bd219e72	4404	#define VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR \
charlesmn	0:0be0bd219e72	4405	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 37))
charlesmn	0:0be0bd219e72	4406	#define VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM \
charlesmn	0:0be0bd219e72	4407	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 38))
charlesmn	0:0be0bd219e72	4408	#define VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM \
charlesmn	0:0be0bd219e72	4409	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 39))
charlesmn	0:0be0bd219e72	4410	#define VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM \
charlesmn	0:0be0bd219e72	4411	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 40))
charlesmn	0:0be0bd219e72	4412	#define VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM \
charlesmn	0:0be0bd219e72	4413	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 41))
charlesmn	0:0be0bd219e72	4414	#define VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS \
charlesmn	0:0be0bd219e72	4415	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 42))
charlesmn	0:0be0bd219e72	4416	#define VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS \
charlesmn	0:0be0bd219e72	4417	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 43))
charlesmn	0:0be0bd219e72	4418	#define VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS \
charlesmn	0:0be0bd219e72	4419	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 44))
charlesmn	0:0be0bd219e72	4420	#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH \
charlesmn	0:0be0bd219e72	4421	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 45))
charlesmn	0:0be0bd219e72	4422	#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS \
charlesmn	0:0be0bd219e72	4423	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 46))
charlesmn	0:0be0bd219e72	4424	#define VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM \
charlesmn	0:0be0bd219e72	4425	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 47))
charlesmn	0:0be0bd219e72	4426	#define VL53LX_TUNINGPARM_LITE_RIT_MULT \
charlesmn	0:0be0bd219e72	4427	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 48))
charlesmn	0:0be0bd219e72	4428	#define VL53LX_TUNINGPARM_LITE_SEED_CONFIG \
charlesmn	0:0be0bd219e72	4429	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 49))
charlesmn	0:0be0bd219e72	4430	#define VL53LX_TUNINGPARM_LITE_QUANTIFIER \
charlesmn	0:0be0bd219e72	4431	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 50))
charlesmn	0:0be0bd219e72	4432	#define VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT \
charlesmn	0:0be0bd219e72	4433	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 51))
charlesmn	0:0be0bd219e72	4434	#define VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS \
charlesmn	0:0be0bd219e72	4435	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 52))
charlesmn	0:0be0bd219e72	4436	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE \
charlesmn	0:0be0bd219e72	4437	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 53))
charlesmn	0:0be0bd219e72	4438	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE \
charlesmn	0:0be0bd219e72	4439	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 54))
charlesmn	0:0be0bd219e72	4440	#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE \
charlesmn	0:0be0bd219e72	4441	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 55))
charlesmn	0:0be0bd219e72	4442	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE \
charlesmn	0:0be0bd219e72	4443	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 56))
charlesmn	0:0be0bd219e72	4444	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE \
charlesmn	0:0be0bd219e72	4445	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 57))
charlesmn	0:0be0bd219e72	4446	#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE \
charlesmn	0:0be0bd219e72	4447	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 58))
charlesmn	0:0be0bd219e72	4448	#define VL53LX_TUNINGPARM_TIMED_SEED_CONFIG \
charlesmn	0:0be0bd219e72	4449	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 59))
charlesmn	0:0be0bd219e72	4450	#define VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA \
charlesmn	0:0be0bd219e72	4451	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 60))
charlesmn	0:0be0bd219e72	4452	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0 \
charlesmn	0:0be0bd219e72	4453	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 61))
charlesmn	0:0be0bd219e72	4454	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1 \
charlesmn	0:0be0bd219e72	4455	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 62))
charlesmn	0:0be0bd219e72	4456	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2 \
charlesmn	0:0be0bd219e72	4457	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 63))
charlesmn	0:0be0bd219e72	4458	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3 \
charlesmn	0:0be0bd219e72	4459	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 64))
charlesmn	0:0be0bd219e72	4460	#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4 \
charlesmn	0:0be0bd219e72	4461	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 65))
charlesmn	0:0be0bd219e72	4462	#define VL53LX_TUNINGPARM_VHV_LOOPBOUND \
charlesmn	0:0be0bd219e72	4463	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 66))
charlesmn	0:0be0bd219e72	4464	#define VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE \
charlesmn	0:0be0bd219e72	4465	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 67))
charlesmn	0:0be0bd219e72	4466	#define VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD \
charlesmn	0:0be0bd219e72	4467	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 68))
charlesmn	0:0be0bd219e72	4468	#define VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4469	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 69))
charlesmn	0:0be0bd219e72	4470	#define VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS \
charlesmn	0:0be0bd219e72	4471	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 70))
charlesmn	0:0be0bd219e72	4472	#define VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS \
charlesmn	0:0be0bd219e72	4473	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 71))
charlesmn	0:0be0bd219e72	4474	#define VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS \
charlesmn	0:0be0bd219e72	4475	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 72))
charlesmn	0:0be0bd219e72	4476	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES \
charlesmn	0:0be0bd219e72	4477	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 73))
charlesmn	0:0be0bd219e72	4478	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM \
charlesmn	0:0be0bd219e72	4479	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 74))
charlesmn	0:0be0bd219e72	4480	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM \
charlesmn	0:0be0bd219e72	4481	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 75))
charlesmn	0:0be0bd219e72	4482	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS \
charlesmn	0:0be0bd219e72	4483	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 76))
charlesmn	0:0be0bd219e72	4484	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4485	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 77))
charlesmn	0:0be0bd219e72	4486	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS \
charlesmn	0:0be0bd219e72	4487	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 78))
charlesmn	0:0be0bd219e72	4488	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM \
charlesmn	0:0be0bd219e72	4489	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 79))
charlesmn	0:0be0bd219e72	4490	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4491	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 80))
charlesmn	0:0be0bd219e72	4492	#define VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4493	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 81))
charlesmn	0:0be0bd219e72	4494	#define VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS \
charlesmn	0:0be0bd219e72	4495	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 82))
charlesmn	0:0be0bd219e72	4496	#define VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4497	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 83))
charlesmn	0:0be0bd219e72	4498	#define VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4499	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 84))
charlesmn	0:0be0bd219e72	4500	#define VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4501	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 85))
charlesmn	0:0be0bd219e72	4502	#define VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES \
charlesmn	0:0be0bd219e72	4503	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 86))
charlesmn	0:0be0bd219e72	4504	#define VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES \
charlesmn	0:0be0bd219e72	4505	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 87))
charlesmn	0:0be0bd219e72	4506	#define VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES \
charlesmn	0:0be0bd219e72	4507	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 88))
charlesmn	0:0be0bd219e72	4508	#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS \
charlesmn	0:0be0bd219e72	4509	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 89))
charlesmn	0:0be0bd219e72	4510	#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4511	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 90))
charlesmn	0:0be0bd219e72	4512	#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4513	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 91))
charlesmn	0:0be0bd219e72	4514	#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES \
charlesmn	0:0be0bd219e72	4515	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 92))
charlesmn	0:0be0bd219e72	4516	#define VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4517	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 93))
charlesmn	0:0be0bd219e72	4518	#define VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES \
charlesmn	0:0be0bd219e72	4519	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 94))
charlesmn	0:0be0bd219e72	4520	#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD \
charlesmn	0:0be0bd219e72	4521	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 95))
charlesmn	0:0be0bd219e72	4522	#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_START \
charlesmn	0:0be0bd219e72	4523	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 96))
charlesmn	0:0be0bd219e72	4524	#define VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS \
charlesmn	0:0be0bd219e72	4525	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 97))
charlesmn	0:0be0bd219e72	4526	#define VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \
charlesmn	0:0be0bd219e72	4527	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 98))
charlesmn	0:0be0bd219e72	4528	#define VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \
charlesmn	0:0be0bd219e72	4529	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 99))
charlesmn	0:0be0bd219e72	4530	#define VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \
charlesmn	0:0be0bd219e72	4531	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 100))
charlesmn	0:0be0bd219e72	4532	#define VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \
charlesmn	0:0be0bd219e72	4533	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 101))
charlesmn	0:0be0bd219e72	4534	#define VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4535	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 102))
charlesmn	0:0be0bd219e72	4536	#define VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4537	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 103))
charlesmn	0:0be0bd219e72	4538	#define VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4539	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 104))
charlesmn	0:0be0bd219e72	4540	#define VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4541	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 105))
charlesmn	0:0be0bd219e72	4542	#define VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4543	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 106))
charlesmn	0:0be0bd219e72	4544	#define VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4545	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 107))
charlesmn	0:0be0bd219e72	4546	#define VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4547	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 108))
charlesmn	0:0be0bd219e72	4548	#define VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4549	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 109))
charlesmn	0:0be0bd219e72	4550	#define VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4551	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 110))
charlesmn	0:0be0bd219e72	4552	#define VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4553	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 111))
charlesmn	0:0be0bd219e72	4554	#define VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4555	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 112))
charlesmn	0:0be0bd219e72	4556	#define VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4557	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 113))
charlesmn	0:0be0bd219e72	4558	#define VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4559	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 114))
charlesmn	0:0be0bd219e72	4560	#define VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4561	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 115))
charlesmn	0:0be0bd219e72	4562	#define VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4563	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 116))
charlesmn	0:0be0bd219e72	4564	#define VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4565	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 117))
charlesmn	0:0be0bd219e72	4566	#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN \
charlesmn	0:0be0bd219e72	4567	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 118))
charlesmn	0:0be0bd219e72	4568	#define VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN \
charlesmn	0:0be0bd219e72	4569	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 119))
charlesmn	0:0be0bd219e72	4570	#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT \
charlesmn	0:0be0bd219e72	4571	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 120))
charlesmn	0:0be0bd219e72	4572	#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI \
charlesmn	0:0be0bd219e72	4573	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 121))
charlesmn	0:0be0bd219e72	4574	#define VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT \
charlesmn	0:0be0bd219e72	4575	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 122))
charlesmn	0:0be0bd219e72	4576	#define VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA \
charlesmn	0:0be0bd219e72	4577	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 123))
charlesmn	0:0be0bd219e72	4578	#define VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA \
charlesmn	0:0be0bd219e72	4579	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 124))
charlesmn	0:0be0bd219e72	4580	#define VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT \
charlesmn	0:0be0bd219e72	4581	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 125))
charlesmn	0:0be0bd219e72	4582	#define VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD \
charlesmn	0:0be0bd219e72	4583	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 126))
charlesmn	0:0be0bd219e72	4584	#define VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER \
charlesmn	0:0be0bd219e72	4585	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 127))
charlesmn	0:0be0bd219e72	4586	#define VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER \
charlesmn	0:0be0bd219e72	4587	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 128))
charlesmn	0:0be0bd219e72	4588	#define VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET \
charlesmn	0:0be0bd219e72	4589	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 129))
charlesmn	0:0be0bd219e72	4590	#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY \
charlesmn	0:0be0bd219e72	4591	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 130))
charlesmn	0:0be0bd219e72	4592	#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD \
charlesmn	0:0be0bd219e72	4593	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 131))
charlesmn	0:0be0bd219e72	4594	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS \
charlesmn	0:0be0bd219e72	4595	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 132))
charlesmn	0:0be0bd219e72	4596	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT \
charlesmn	0:0be0bd219e72	4597	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 133))
charlesmn	0:0be0bd219e72	4598	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS \
charlesmn	0:0be0bd219e72	4599	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 134))
charlesmn	0:0be0bd219e72	4600	#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM \
charlesmn	0:0be0bd219e72	4601	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 135))
charlesmn	0:0be0bd219e72	4602	#define VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND \
charlesmn	0:0be0bd219e72	4603	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 136))
charlesmn	0:0be0bd219e72	4604	#define VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4605	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 137))
charlesmn	0:0be0bd219e72	4606	#define VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US \
charlesmn	0:0be0bd219e72	4607	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 138))
charlesmn	0:0be0bd219e72	4608	#define VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS \
charlesmn	0:0be0bd219e72	4609	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 139))
charlesmn	0:0be0bd219e72	4610	#define VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER \
charlesmn	0:0be0bd219e72	4611	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 140))
charlesmn	0:0be0bd219e72	4612	#define VL53LX_TUNINGPARM_HIST_MERGE \
charlesmn	0:0be0bd219e72	4613	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 141))
charlesmn	0:0be0bd219e72	4614	#define VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD \
charlesmn	0:0be0bd219e72	4615	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 142))
charlesmn	0:0be0bd219e72	4616	#define VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE \
charlesmn	0:0be0bd219e72	4617	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 143))
charlesmn	0:0be0bd219e72	4618	#define VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR \
charlesmn	0:0be0bd219e72	4619	((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 144))
charlesmn	0:0be0bd219e72	4620
charlesmn	0:0be0bd219e72	4621	// define from vl53lx_platform_log.h
charlesmn	0:0be0bd219e72	4622
charlesmn	0:0be0bd219e72	4623	#define VL53LX_TRACE_LEVEL_NONE 0x00000000
charlesmn	0:0be0bd219e72	4624	#define VL53LX_TRACE_LEVEL_ERRORS 0x00000001
charlesmn	0:0be0bd219e72	4625	#define VL53LX_TRACE_LEVEL_WARNING 0x00000002
charlesmn	0:0be0bd219e72	4626	#define VL53LX_TRACE_LEVEL_INFO 0x00000004
charlesmn	0:0be0bd219e72	4627	#define VL53LX_TRACE_LEVEL_DEBUG 0x00000008
charlesmn	0:0be0bd219e72	4628	#define VL53LX_TRACE_LEVEL_ALL 0x00000010
charlesmn	0:0be0bd219e72	4629	#define VL53LX_TRACE_LEVEL_IGNORE 0x00000020
charlesmn	0:0be0bd219e72	4630
charlesmn	0:0be0bd219e72	4631	#define VL53LX_TRACE_FUNCTION_NONE 0x00000000
charlesmn	0:0be0bd219e72	4632	#define VL53LX_TRACE_FUNCTION_I2C 0x00000001
charlesmn	0:0be0bd219e72	4633	#define VL53LX_TRACE_FUNCTION_ALL 0x7fffffff
charlesmn	0:0be0bd219e72	4634
charlesmn	0:0be0bd219e72	4635	#define VL53LX_TRACE_MODULE_NONE 0x00000000
charlesmn	0:0be0bd219e72	4636	#define VL53LX_TRACE_MODULE_API 0x00000001
charlesmn	0:0be0bd219e72	4637	#define VL53LX_TRACE_MODULE_CORE 0x00000002
charlesmn	0:0be0bd219e72	4638	#define VL53LX_TRACE_MODULE_PROTECTED 0x00000004
charlesmn	0:0be0bd219e72	4639	#define VL53LX_TRACE_MODULE_HISTOGRAM 0x00000008
charlesmn	0:0be0bd219e72	4640	#define VL53LX_TRACE_MODULE_REGISTERS 0x00000010
charlesmn	0:0be0bd219e72	4641	#define VL53LX_TRACE_MODULE_PLATFORM 0x00000020
charlesmn	0:0be0bd219e72	4642	#define VL53LX_TRACE_MODULE_NVM 0x00000040
charlesmn	0:0be0bd219e72	4643	#define VL53LX_TRACE_MODULE_CALIBRATION_DATA 0x00000080
charlesmn	0:0be0bd219e72	4644	#define VL53LX_TRACE_MODULE_NVM_DATA 0x00000100
charlesmn	0:0be0bd219e72	4645	#define VL53LX_TRACE_MODULE_HISTOGRAM_DATA 0x00000200
charlesmn	0:0be0bd219e72	4646	#define VL53LX_TRACE_MODULE_RANGE_RESULTS_DATA 0x00000400
charlesmn	0:0be0bd219e72	4647	#define VL53LX_TRACE_MODULE_XTALK_DATA 0x00000800
charlesmn	0:0be0bd219e72	4648	#define VL53LX_TRACE_MODULE_OFFSET_DATA 0x00001000
charlesmn	0:0be0bd219e72	4649	#define VL53LX_TRACE_MODULE_DATA_INIT 0x00002000
charlesmn	0:0be0bd219e72	4650	#define VL53LX_TRACE_MODULE_REF_SPAD_CHAR 0x00004000
charlesmn	0:0be0bd219e72	4651	#define VL53LX_TRACE_MODULE_SPAD_RATE_MAP 0x00008000
charlesmn	0:0be0bd219e72	4652
charlesmn	0:0be0bd219e72	4653
charlesmn	0:0be0bd219e72	4654
charlesmn	0:0be0bd219e72	4655	// define & typedef from vl53lx_register_structs.h
charlesmn	0:0be0bd219e72	4656
charlesmn	0:0be0bd219e72	4657
charlesmn	0:0be0bd219e72	4658	#define VL53LX_STATIC_NVM_MANAGED_I2C_INDEX \
charlesmn	0:0be0bd219e72	4659	VL53LX_I2C_SLAVE__DEVICE_ADDRESS
charlesmn	0:0be0bd219e72	4660	#define VL53LX_CUSTOMER_NVM_MANAGED_I2C_INDEX \
charlesmn	0:0be0bd219e72	4661	VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0
charlesmn	0:0be0bd219e72	4662	#define VL53LX_STATIC_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4663	VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS
charlesmn	0:0be0bd219e72	4664	#define VL53LX_GENERAL_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4665	VL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE
charlesmn	0:0be0bd219e72	4666	#define VL53LX_TIMING_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4667	VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI
charlesmn	0:0be0bd219e72	4668	#define VL53LX_DYNAMIC_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4669	VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0
charlesmn	0:0be0bd219e72	4670	#define VL53LX_SYSTEM_CONTROL_I2C_INDEX \
charlesmn	0:0be0bd219e72	4671	VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE
charlesmn	0:0be0bd219e72	4672	#define VL53LX_SYSTEM_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4673	VL53LX_RESULT__INTERRUPT_STATUS
charlesmn	0:0be0bd219e72	4674	#define VL53LX_CORE_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4675	VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
charlesmn	0:0be0bd219e72	4676	#define VL53LX_DEBUG_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4677	VL53LX_PHASECAL_RESULT__REFERENCE_PHASE
charlesmn	0:0be0bd219e72	4678	#define VL53LX_NVM_COPY_DATA_I2C_INDEX \
charlesmn	0:0be0bd219e72	4679	VL53LX_IDENTIFICATION__MODEL_ID
charlesmn	0:0be0bd219e72	4680	#define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4681	VL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS
charlesmn	0:0be0bd219e72	4682	#define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4683	VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
charlesmn	0:0be0bd219e72	4684	#define VL53LX_PATCH_DEBUG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4685	VL53LX_RESULT__DEBUG_STATUS
charlesmn	0:0be0bd219e72	4686	#define VL53LX_GPH_GENERAL_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4687	VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH
charlesmn	0:0be0bd219e72	4688	#define VL53LX_GPH_STATIC_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4689	VL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL
charlesmn	0:0be0bd219e72	4690	#define VL53LX_GPH_TIMING_CONFIG_I2C_INDEX \
charlesmn	0:0be0bd219e72	4691	VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI
charlesmn	0:0be0bd219e72	4692	#define VL53LX_FW_INTERNAL_I2C_INDEX \
charlesmn	0:0be0bd219e72	4693	VL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV
charlesmn	0:0be0bd219e72	4694	#define VL53LX_PATCH_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4695	VL53LX_DSS_CALC__ROI_CTRL
charlesmn	0:0be0bd219e72	4696	#define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4697	VL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START
charlesmn	0:0be0bd219e72	4698	#define VL53LX_SHADOW_CORE_RESULTS_I2C_INDEX \
charlesmn	0:0be0bd219e72	4699	VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
charlesmn	0:0be0bd219e72	4700
charlesmn	0:0be0bd219e72	4701	#define VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11
charlesmn	0:0be0bd219e72	4702	#define VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23
charlesmn	0:0be0bd219e72	4703	#define VL53LX_STATIC_CONFIG_I2C_SIZE_BYTES 32
charlesmn	0:0be0bd219e72	4704	#define VL53LX_GENERAL_CONFIG_I2C_SIZE_BYTES 22
charlesmn	0:0be0bd219e72	4705	#define VL53LX_TIMING_CONFIG_I2C_SIZE_BYTES 23
charlesmn	0:0be0bd219e72	4706	#define VL53LX_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18
charlesmn	0:0be0bd219e72	4707	#define VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES 5
charlesmn	0:0be0bd219e72	4708	#define VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES 44
charlesmn	0:0be0bd219e72	4709	#define VL53LX_CORE_RESULTS_I2C_SIZE_BYTES 33
charlesmn	0:0be0bd219e72	4710	#define VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES 56
charlesmn	0:0be0bd219e72	4711	#define VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES 49
charlesmn	0:0be0bd219e72	4712	#define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44
charlesmn	0:0be0bd219e72	4713	#define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33
charlesmn	0:0be0bd219e72	4714	#define VL53LX_PATCH_DEBUG_I2C_SIZE_BYTES 2
charlesmn	0:0be0bd219e72	4715	#define VL53LX_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5
charlesmn	0:0be0bd219e72	4716	#define VL53LX_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6
charlesmn	0:0be0bd219e72	4717	#define VL53LX_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16
charlesmn	0:0be0bd219e72	4718	#define VL53LX_FW_INTERNAL_I2C_SIZE_BYTES 2
charlesmn	0:0be0bd219e72	4719	#define VL53LX_PATCH_RESULTS_I2C_SIZE_BYTES 90
charlesmn	0:0be0bd219e72	4720	#define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82
charlesmn	0:0be0bd219e72	4721	#define VL53LX_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33
charlesmn	0:0be0bd219e72	4722
charlesmn	0:0be0bd219e72	4723
charlesmn	0:0be0bd219e72	4724
charlesmn	0:0be0bd219e72	4725
charlesmn	0:0be0bd219e72	4726	typedef struct {
charlesmn	0:0be0bd219e72	4727	uint8_t i2c_slave__device_address;
charlesmn	0:0be0bd219e72	4728
charlesmn	0:0be0bd219e72	4729	uint8_t ana_config__vhv_ref_sel_vddpix;
charlesmn	0:0be0bd219e72	4730
charlesmn	0:0be0bd219e72	4731	uint8_t ana_config__vhv_ref_sel_vquench;
charlesmn	0:0be0bd219e72	4732
charlesmn	0:0be0bd219e72	4733	uint8_t ana_config__reg_avdd1v2_sel;
charlesmn	0:0be0bd219e72	4734
charlesmn	0:0be0bd219e72	4735	uint8_t ana_config__fast_osc__trim;
charlesmn	0:0be0bd219e72	4736
charlesmn	0:0be0bd219e72	4737	uint16_t osc_measured__fast_osc__frequency;
charlesmn	0:0be0bd219e72	4738
charlesmn	0:0be0bd219e72	4739	uint8_t vhv_config__timeout_macrop_loop_bound;
charlesmn	0:0be0bd219e72	4740
charlesmn	0:0be0bd219e72	4741	uint8_t vhv_config__count_thresh;
charlesmn	0:0be0bd219e72	4742
charlesmn	0:0be0bd219e72	4743	uint8_t vhv_config__offset;
charlesmn	0:0be0bd219e72	4744
charlesmn	0:0be0bd219e72	4745	uint8_t vhv_config__init;
charlesmn	0:0be0bd219e72	4746
charlesmn	0:0be0bd219e72	4747	} VL53LX_static_nvm_managed_t;
charlesmn	0:0be0bd219e72	4748
charlesmn	0:0be0bd219e72	4749
charlesmn	0:0be0bd219e72	4750
charlesmn	0:0be0bd219e72	4751
charlesmn	0:0be0bd219e72	4752	typedef struct {
charlesmn	0:0be0bd219e72	4753	uint8_t global_config__spad_enables_ref_0;
charlesmn	0:0be0bd219e72	4754
charlesmn	0:0be0bd219e72	4755	uint8_t global_config__spad_enables_ref_1;
charlesmn	0:0be0bd219e72	4756
charlesmn	0:0be0bd219e72	4757	uint8_t global_config__spad_enables_ref_2;
charlesmn	0:0be0bd219e72	4758
charlesmn	0:0be0bd219e72	4759	uint8_t global_config__spad_enables_ref_3;
charlesmn	0:0be0bd219e72	4760
charlesmn	0:0be0bd219e72	4761	uint8_t global_config__spad_enables_ref_4;
charlesmn	0:0be0bd219e72	4762
charlesmn	0:0be0bd219e72	4763	uint8_t global_config__spad_enables_ref_5;
charlesmn	0:0be0bd219e72	4764
charlesmn	0:0be0bd219e72	4765	uint8_t global_config__ref_en_start_select;
charlesmn	0:0be0bd219e72	4766
charlesmn	0:0be0bd219e72	4767	uint8_t ref_spad_man__num_requested_ref_spads;
charlesmn	0:0be0bd219e72	4768
charlesmn	0:0be0bd219e72	4769	uint8_t ref_spad_man__ref_location;
charlesmn	0:0be0bd219e72	4770
charlesmn	0:0be0bd219e72	4771	uint16_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	4772
charlesmn	0:0be0bd219e72	4773	int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	4774
charlesmn	0:0be0bd219e72	4775	int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	4776
charlesmn	0:0be0bd219e72	4777	uint16_t ref_spad_char__total_rate_target_mcps;
charlesmn	0:0be0bd219e72	4778
charlesmn	0:0be0bd219e72	4779	int16_t algo__part_to_part_range_offset_mm;
charlesmn	0:0be0bd219e72	4780
charlesmn	0:0be0bd219e72	4781	int16_t mm_config__inner_offset_mm;
charlesmn	0:0be0bd219e72	4782
charlesmn	0:0be0bd219e72	4783	int16_t mm_config__outer_offset_mm;
charlesmn	0:0be0bd219e72	4784
charlesmn	0:0be0bd219e72	4785	} VL53LX_customer_nvm_managed_t;
charlesmn	0:0be0bd219e72	4786
charlesmn	0:0be0bd219e72	4787
charlesmn	0:0be0bd219e72	4788
charlesmn	0:0be0bd219e72	4789
charlesmn	0:0be0bd219e72	4790	typedef struct {
charlesmn	0:0be0bd219e72	4791	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	4792
charlesmn	0:0be0bd219e72	4793	uint8_t debug__ctrl;
charlesmn	0:0be0bd219e72	4794
charlesmn	0:0be0bd219e72	4795	uint8_t test_mode__ctrl;
charlesmn	0:0be0bd219e72	4796
charlesmn	0:0be0bd219e72	4797	uint8_t clk_gating__ctrl;
charlesmn	0:0be0bd219e72	4798
charlesmn	0:0be0bd219e72	4799	uint8_t nvm_bist__ctrl;
charlesmn	0:0be0bd219e72	4800
charlesmn	0:0be0bd219e72	4801	uint8_t nvm_bist__num_nvm_words;
charlesmn	0:0be0bd219e72	4802
charlesmn	0:0be0bd219e72	4803	uint8_t nvm_bist__start_address;
charlesmn	0:0be0bd219e72	4804
charlesmn	0:0be0bd219e72	4805	uint8_t host_if__status;
charlesmn	0:0be0bd219e72	4806
charlesmn	0:0be0bd219e72	4807	uint8_t pad_i2c_hv__config;
charlesmn	0:0be0bd219e72	4808
charlesmn	0:0be0bd219e72	4809	uint8_t pad_i2c_hv__extsup_config;
charlesmn	0:0be0bd219e72	4810
charlesmn	0:0be0bd219e72	4811	uint8_t gpio_hv_pad__ctrl;
charlesmn	0:0be0bd219e72	4812
charlesmn	0:0be0bd219e72	4813	uint8_t gpio_hv_mux__ctrl;
charlesmn	0:0be0bd219e72	4814
charlesmn	0:0be0bd219e72	4815	uint8_t gpio__tio_hv_status;
charlesmn	0:0be0bd219e72	4816
charlesmn	0:0be0bd219e72	4817	uint8_t gpio__fio_hv_status;
charlesmn	0:0be0bd219e72	4818
charlesmn	0:0be0bd219e72	4819	uint8_t ana_config__spad_sel_pswidth;
charlesmn	0:0be0bd219e72	4820
charlesmn	0:0be0bd219e72	4821	uint8_t ana_config__vcsel_pulse_width_offset;
charlesmn	0:0be0bd219e72	4822
charlesmn	0:0be0bd219e72	4823	uint8_t ana_config__fast_osc__config_ctrl;
charlesmn	0:0be0bd219e72	4824
charlesmn	0:0be0bd219e72	4825	uint8_t sigma_estimator__effective_pulse_width_ns;
charlesmn	0:0be0bd219e72	4826
charlesmn	0:0be0bd219e72	4827	uint8_t sigma_estimator__effective_ambient_width_ns;
charlesmn	0:0be0bd219e72	4828
charlesmn	0:0be0bd219e72	4829	uint8_t sigma_estimator__sigma_ref_mm;
charlesmn	0:0be0bd219e72	4830
charlesmn	0:0be0bd219e72	4831	uint8_t algo__crosstalk_compensation_valid_height_mm;
charlesmn	0:0be0bd219e72	4832
charlesmn	0:0be0bd219e72	4833	uint8_t spare_host_config__static_config_spare_0;
charlesmn	0:0be0bd219e72	4834
charlesmn	0:0be0bd219e72	4835	uint8_t spare_host_config__static_config_spare_1;
charlesmn	0:0be0bd219e72	4836
charlesmn	0:0be0bd219e72	4837	uint16_t algo__range_ignore_threshold_mcps;
charlesmn	0:0be0bd219e72	4838
charlesmn	0:0be0bd219e72	4839	uint8_t algo__range_ignore_valid_height_mm;
charlesmn	0:0be0bd219e72	4840
charlesmn	0:0be0bd219e72	4841	uint8_t algo__range_min_clip;
charlesmn	0:0be0bd219e72	4842
charlesmn	0:0be0bd219e72	4843	uint8_t algo__consistency_check__tolerance;
charlesmn	0:0be0bd219e72	4844
charlesmn	0:0be0bd219e72	4845	uint8_t spare_host_config__static_config_spare_2;
charlesmn	0:0be0bd219e72	4846
charlesmn	0:0be0bd219e72	4847	uint8_t sd_config__reset_stages_msb;
charlesmn	0:0be0bd219e72	4848
charlesmn	0:0be0bd219e72	4849	uint8_t sd_config__reset_stages_lsb;
charlesmn	0:0be0bd219e72	4850
charlesmn	0:0be0bd219e72	4851	} VL53LX_static_config_t;
charlesmn	0:0be0bd219e72	4852
charlesmn	0:0be0bd219e72	4853
charlesmn	0:0be0bd219e72	4854
charlesmn	0:0be0bd219e72	4855
charlesmn	0:0be0bd219e72	4856	typedef struct {
charlesmn	0:0be0bd219e72	4857	uint8_t gph_config__stream_count_update_value;
charlesmn	0:0be0bd219e72	4858
charlesmn	0:0be0bd219e72	4859	uint8_t global_config__stream_divider;
charlesmn	0:0be0bd219e72	4860
charlesmn	0:0be0bd219e72	4861	uint8_t system__interrupt_config_gpio;
charlesmn	0:0be0bd219e72	4862
charlesmn	0:0be0bd219e72	4863	uint8_t cal_config__vcsel_start;
charlesmn	0:0be0bd219e72	4864
charlesmn	0:0be0bd219e72	4865	uint16_t cal_config__repeat_rate;
charlesmn	0:0be0bd219e72	4866
charlesmn	0:0be0bd219e72	4867	uint8_t global_config__vcsel_width;
charlesmn	0:0be0bd219e72	4868
charlesmn	0:0be0bd219e72	4869	uint8_t phasecal_config__timeout_macrop;
charlesmn	0:0be0bd219e72	4870
charlesmn	0:0be0bd219e72	4871	uint8_t phasecal_config__target;
charlesmn	0:0be0bd219e72	4872
charlesmn	0:0be0bd219e72	4873	uint8_t phasecal_config__override;
charlesmn	0:0be0bd219e72	4874
charlesmn	0:0be0bd219e72	4875	uint8_t dss_config__roi_mode_control;
charlesmn	0:0be0bd219e72	4876
charlesmn	0:0be0bd219e72	4877	uint16_t system__thresh_rate_high;
charlesmn	0:0be0bd219e72	4878
charlesmn	0:0be0bd219e72	4879	uint16_t system__thresh_rate_low;
charlesmn	0:0be0bd219e72	4880
charlesmn	0:0be0bd219e72	4881	uint16_t dss_config__manual_effective_spads_select;
charlesmn	0:0be0bd219e72	4882
charlesmn	0:0be0bd219e72	4883	uint8_t dss_config__manual_block_select;
charlesmn	0:0be0bd219e72	4884
charlesmn	0:0be0bd219e72	4885	uint8_t dss_config__aperture_attenuation;
charlesmn	0:0be0bd219e72	4886
charlesmn	0:0be0bd219e72	4887	uint8_t dss_config__max_spads_limit;
charlesmn	0:0be0bd219e72	4888
charlesmn	0:0be0bd219e72	4889	uint8_t dss_config__min_spads_limit;
charlesmn	0:0be0bd219e72	4890
charlesmn	0:0be0bd219e72	4891	} VL53LX_general_config_t;
charlesmn	0:0be0bd219e72	4892
charlesmn	0:0be0bd219e72	4893
charlesmn	0:0be0bd219e72	4894
charlesmn	0:0be0bd219e72	4895
charlesmn	0:0be0bd219e72	4896	typedef struct {
charlesmn	0:0be0bd219e72	4897	uint8_t mm_config__timeout_macrop_a_hi;
charlesmn	0:0be0bd219e72	4898
charlesmn	0:0be0bd219e72	4899	uint8_t mm_config__timeout_macrop_a_lo;
charlesmn	0:0be0bd219e72	4900
charlesmn	0:0be0bd219e72	4901	uint8_t mm_config__timeout_macrop_b_hi;
charlesmn	0:0be0bd219e72	4902
charlesmn	0:0be0bd219e72	4903	uint8_t mm_config__timeout_macrop_b_lo;
charlesmn	0:0be0bd219e72	4904
charlesmn	0:0be0bd219e72	4905	uint8_t range_config__timeout_macrop_a_hi;
charlesmn	0:0be0bd219e72	4906
charlesmn	0:0be0bd219e72	4907	uint8_t range_config__timeout_macrop_a_lo;
charlesmn	0:0be0bd219e72	4908
charlesmn	0:0be0bd219e72	4909	uint8_t range_config__vcsel_period_a;
charlesmn	0:0be0bd219e72	4910
charlesmn	0:0be0bd219e72	4911	uint8_t range_config__timeout_macrop_b_hi;
charlesmn	0:0be0bd219e72	4912
charlesmn	0:0be0bd219e72	4913	uint8_t range_config__timeout_macrop_b_lo;
charlesmn	0:0be0bd219e72	4914
charlesmn	0:0be0bd219e72	4915	uint8_t range_config__vcsel_period_b;
charlesmn	0:0be0bd219e72	4916
charlesmn	0:0be0bd219e72	4917	uint16_t range_config__sigma_thresh;
charlesmn	0:0be0bd219e72	4918
charlesmn	0:0be0bd219e72	4919	uint16_t range_config__min_count_rate_rtn_limit_mcps;
charlesmn	0:0be0bd219e72	4920
charlesmn	0:0be0bd219e72	4921	uint8_t range_config__valid_phase_low;
charlesmn	0:0be0bd219e72	4922
charlesmn	0:0be0bd219e72	4923	uint8_t range_config__valid_phase_high;
charlesmn	0:0be0bd219e72	4924
charlesmn	0:0be0bd219e72	4925	uint32_t system__intermeasurement_period;
charlesmn	0:0be0bd219e72	4926
charlesmn	0:0be0bd219e72	4927	uint8_t system__fractional_enable;
charlesmn	0:0be0bd219e72	4928
charlesmn	0:0be0bd219e72	4929	} VL53LX_timing_config_t;
charlesmn	0:0be0bd219e72	4930
charlesmn	0:0be0bd219e72	4931
charlesmn	0:0be0bd219e72	4932
charlesmn	0:0be0bd219e72	4933
charlesmn	0:0be0bd219e72	4934	typedef struct {
charlesmn	0:0be0bd219e72	4935	uint8_t system__grouped_parameter_hold_0;
charlesmn	0:0be0bd219e72	4936
charlesmn	0:0be0bd219e72	4937	uint16_t system__thresh_high;
charlesmn	0:0be0bd219e72	4938
charlesmn	0:0be0bd219e72	4939	uint16_t system__thresh_low;
charlesmn	0:0be0bd219e72	4940
charlesmn	0:0be0bd219e72	4941	uint8_t system__enable_xtalk_per_quadrant;
charlesmn	0:0be0bd219e72	4942
charlesmn	0:0be0bd219e72	4943	uint8_t system__seed_config;
charlesmn	0:0be0bd219e72	4944
charlesmn	0:0be0bd219e72	4945	uint8_t sd_config__woi_sd0;
charlesmn	0:0be0bd219e72	4946
charlesmn	0:0be0bd219e72	4947	uint8_t sd_config__woi_sd1;
charlesmn	0:0be0bd219e72	4948
charlesmn	0:0be0bd219e72	4949	uint8_t sd_config__initial_phase_sd0;
charlesmn	0:0be0bd219e72	4950
charlesmn	0:0be0bd219e72	4951	uint8_t sd_config__initial_phase_sd1;
charlesmn	0:0be0bd219e72	4952
charlesmn	0:0be0bd219e72	4953	uint8_t system__grouped_parameter_hold_1;
charlesmn	0:0be0bd219e72	4954
charlesmn	0:0be0bd219e72	4955	uint8_t sd_config__first_order_select;
charlesmn	0:0be0bd219e72	4956
charlesmn	0:0be0bd219e72	4957	uint8_t sd_config__quantifier;
charlesmn	0:0be0bd219e72	4958
charlesmn	0:0be0bd219e72	4959	uint8_t roi_config__user_roi_centre_spad;
charlesmn	0:0be0bd219e72	4960
charlesmn	0:0be0bd219e72	4961	uint8_t roi_config__user_roi_requested_global_xy_size;
charlesmn	0:0be0bd219e72	4962
charlesmn	0:0be0bd219e72	4963	uint8_t system__sequence_config;
charlesmn	0:0be0bd219e72	4964
charlesmn	0:0be0bd219e72	4965	uint8_t system__grouped_parameter_hold;
charlesmn	0:0be0bd219e72	4966
charlesmn	0:0be0bd219e72	4967	} VL53LX_dynamic_config_t;
charlesmn	0:0be0bd219e72	4968
charlesmn	0:0be0bd219e72	4969
charlesmn	0:0be0bd219e72	4970
charlesmn	0:0be0bd219e72	4971
charlesmn	0:0be0bd219e72	4972	typedef struct {
charlesmn	0:0be0bd219e72	4973	uint8_t power_management__go1_power_force;
charlesmn	0:0be0bd219e72	4974
charlesmn	0:0be0bd219e72	4975	uint8_t system__stream_count_ctrl;
charlesmn	0:0be0bd219e72	4976
charlesmn	0:0be0bd219e72	4977	uint8_t firmware__enable;
charlesmn	0:0be0bd219e72	4978
charlesmn	0:0be0bd219e72	4979	uint8_t system__interrupt_clear;
charlesmn	0:0be0bd219e72	4980
charlesmn	0:0be0bd219e72	4981	uint8_t system__mode_start;
charlesmn	0:0be0bd219e72	4982
charlesmn	0:0be0bd219e72	4983	} VL53LX_system_control_t;
charlesmn	0:0be0bd219e72	4984
charlesmn	0:0be0bd219e72	4985
charlesmn	0:0be0bd219e72	4986
charlesmn	0:0be0bd219e72	4987
charlesmn	0:0be0bd219e72	4988	typedef struct {
charlesmn	0:0be0bd219e72	4989	uint8_t result__interrupt_status;
charlesmn	0:0be0bd219e72	4990
charlesmn	0:0be0bd219e72	4991	uint8_t result__range_status;
charlesmn	0:0be0bd219e72	4992
charlesmn	0:0be0bd219e72	4993	uint8_t result__report_status;
charlesmn	0:0be0bd219e72	4994
charlesmn	0:0be0bd219e72	4995	uint8_t result__stream_count;
charlesmn	0:0be0bd219e72	4996
charlesmn	0:0be0bd219e72	4997	uint16_t result__dss_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	4998
charlesmn	0:0be0bd219e72	4999	uint16_t result__peak_signal_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5000
charlesmn	0:0be0bd219e72	5001	uint16_t result__ambient_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5002
charlesmn	0:0be0bd219e72	5003	uint16_t result__sigma_sd0;
charlesmn	0:0be0bd219e72	5004
charlesmn	0:0be0bd219e72	5005	uint16_t result__phase_sd0;
charlesmn	0:0be0bd219e72	5006
charlesmn	0:0be0bd219e72	5007	uint16_t result__final_crosstalk_corrected_range_mm_sd0;
charlesmn	0:0be0bd219e72	5008
charlesmn	0:0be0bd219e72	5009	uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
charlesmn	0:0be0bd219e72	5010
charlesmn	0:0be0bd219e72	5011	uint16_t result__mm_inner_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5012
charlesmn	0:0be0bd219e72	5013	uint16_t result__mm_outer_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5014
charlesmn	0:0be0bd219e72	5015	uint16_t result__avg_signal_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5016
charlesmn	0:0be0bd219e72	5017	uint16_t result__dss_actual_effective_spads_sd1;
charlesmn	0:0be0bd219e72	5018
charlesmn	0:0be0bd219e72	5019	uint16_t result__peak_signal_count_rate_mcps_sd1;
charlesmn	0:0be0bd219e72	5020
charlesmn	0:0be0bd219e72	5021	uint16_t result__ambient_count_rate_mcps_sd1;
charlesmn	0:0be0bd219e72	5022
charlesmn	0:0be0bd219e72	5023	uint16_t result__sigma_sd1;
charlesmn	0:0be0bd219e72	5024
charlesmn	0:0be0bd219e72	5025	uint16_t result__phase_sd1;
charlesmn	0:0be0bd219e72	5026
charlesmn	0:0be0bd219e72	5027	uint16_t result__final_crosstalk_corrected_range_mm_sd1;
charlesmn	0:0be0bd219e72	5028
charlesmn	0:0be0bd219e72	5029	uint16_t result__spare_0_sd1;
charlesmn	0:0be0bd219e72	5030
charlesmn	0:0be0bd219e72	5031	uint16_t result__spare_1_sd1;
charlesmn	0:0be0bd219e72	5032
charlesmn	0:0be0bd219e72	5033	uint16_t result__spare_2_sd1;
charlesmn	0:0be0bd219e72	5034
charlesmn	0:0be0bd219e72	5035	uint8_t result__spare_3_sd1;
charlesmn	0:0be0bd219e72	5036
charlesmn	0:0be0bd219e72	5037	uint8_t result__thresh_info;
charlesmn	0:0be0bd219e72	5038
charlesmn	0:0be0bd219e72	5039	} VL53LX_system_results_t;
charlesmn	0:0be0bd219e72	5040
charlesmn	0:0be0bd219e72	5041
charlesmn	0:0be0bd219e72	5042
charlesmn	0:0be0bd219e72	5043
charlesmn	0:0be0bd219e72	5044	typedef struct {
charlesmn	0:0be0bd219e72	5045	uint32_t result_core__ambient_window_events_sd0;
charlesmn	0:0be0bd219e72	5046
charlesmn	0:0be0bd219e72	5047	uint32_t result_core__ranging_total_events_sd0;
charlesmn	0:0be0bd219e72	5048
charlesmn	0:0be0bd219e72	5049	int32_t result_core__signal_total_events_sd0;
charlesmn	0:0be0bd219e72	5050
charlesmn	0:0be0bd219e72	5051	uint32_t result_core__total_periods_elapsed_sd0;
charlesmn	0:0be0bd219e72	5052
charlesmn	0:0be0bd219e72	5053	uint32_t result_core__ambient_window_events_sd1;
charlesmn	0:0be0bd219e72	5054
charlesmn	0:0be0bd219e72	5055	uint32_t result_core__ranging_total_events_sd1;
charlesmn	0:0be0bd219e72	5056
charlesmn	0:0be0bd219e72	5057	int32_t result_core__signal_total_events_sd1;
charlesmn	0:0be0bd219e72	5058
charlesmn	0:0be0bd219e72	5059	uint32_t result_core__total_periods_elapsed_sd1;
charlesmn	0:0be0bd219e72	5060
charlesmn	0:0be0bd219e72	5061	uint8_t result_core__spare_0;
charlesmn	0:0be0bd219e72	5062
charlesmn	0:0be0bd219e72	5063	} VL53LX_core_results_t;
charlesmn	0:0be0bd219e72	5064
charlesmn	0:0be0bd219e72	5065
charlesmn	0:0be0bd219e72	5066
charlesmn	0:0be0bd219e72	5067
charlesmn	0:0be0bd219e72	5068	typedef struct {
charlesmn	0:0be0bd219e72	5069	uint16_t phasecal_result__reference_phase;
charlesmn	0:0be0bd219e72	5070
charlesmn	0:0be0bd219e72	5071	uint8_t phasecal_result__vcsel_start;
charlesmn	0:0be0bd219e72	5072
charlesmn	0:0be0bd219e72	5073	uint8_t ref_spad_char_result__num_actual_ref_spads;
charlesmn	0:0be0bd219e72	5074
charlesmn	0:0be0bd219e72	5075	uint8_t ref_spad_char_result__ref_location;
charlesmn	0:0be0bd219e72	5076
charlesmn	0:0be0bd219e72	5077	uint8_t vhv_result__coldboot_status;
charlesmn	0:0be0bd219e72	5078
charlesmn	0:0be0bd219e72	5079	uint8_t vhv_result__search_result;
charlesmn	0:0be0bd219e72	5080
charlesmn	0:0be0bd219e72	5081	uint8_t vhv_result__latest_setting;
charlesmn	0:0be0bd219e72	5082
charlesmn	0:0be0bd219e72	5083	uint16_t result__osc_calibrate_val;
charlesmn	0:0be0bd219e72	5084
charlesmn	0:0be0bd219e72	5085	uint8_t ana_config__powerdown_go1;
charlesmn	0:0be0bd219e72	5086
charlesmn	0:0be0bd219e72	5087	uint8_t ana_config__ref_bg_ctrl;
charlesmn	0:0be0bd219e72	5088
charlesmn	0:0be0bd219e72	5089	uint8_t ana_config__regdvdd1v2_ctrl;
charlesmn	0:0be0bd219e72	5090
charlesmn	0:0be0bd219e72	5091	uint8_t ana_config__osc_slow_ctrl;
charlesmn	0:0be0bd219e72	5092
charlesmn	0:0be0bd219e72	5093	uint8_t test_mode__status;
charlesmn	0:0be0bd219e72	5094
charlesmn	0:0be0bd219e72	5095	uint8_t firmware__system_status;
charlesmn	0:0be0bd219e72	5096
charlesmn	0:0be0bd219e72	5097	uint8_t firmware__mode_status;
charlesmn	0:0be0bd219e72	5098
charlesmn	0:0be0bd219e72	5099	uint8_t firmware__secondary_mode_status;
charlesmn	0:0be0bd219e72	5100
charlesmn	0:0be0bd219e72	5101	uint16_t firmware__cal_repeat_rate_counter;
charlesmn	0:0be0bd219e72	5102
charlesmn	0:0be0bd219e72	5103	uint16_t gph__system__thresh_high;
charlesmn	0:0be0bd219e72	5104
charlesmn	0:0be0bd219e72	5105	uint16_t gph__system__thresh_low;
charlesmn	0:0be0bd219e72	5106
charlesmn	0:0be0bd219e72	5107	uint8_t gph__system__enable_xtalk_per_quadrant;
charlesmn	0:0be0bd219e72	5108
charlesmn	0:0be0bd219e72	5109	uint8_t gph__spare_0;
charlesmn	0:0be0bd219e72	5110
charlesmn	0:0be0bd219e72	5111	uint8_t gph__sd_config__woi_sd0;
charlesmn	0:0be0bd219e72	5112
charlesmn	0:0be0bd219e72	5113	uint8_t gph__sd_config__woi_sd1;
charlesmn	0:0be0bd219e72	5114
charlesmn	0:0be0bd219e72	5115	uint8_t gph__sd_config__initial_phase_sd0;
charlesmn	0:0be0bd219e72	5116
charlesmn	0:0be0bd219e72	5117	uint8_t gph__sd_config__initial_phase_sd1;
charlesmn	0:0be0bd219e72	5118
charlesmn	0:0be0bd219e72	5119	uint8_t gph__sd_config__first_order_select;
charlesmn	0:0be0bd219e72	5120
charlesmn	0:0be0bd219e72	5121	uint8_t gph__sd_config__quantifier;
charlesmn	0:0be0bd219e72	5122
charlesmn	0:0be0bd219e72	5123	uint8_t gph__roi_config__user_roi_centre_spad;
charlesmn	0:0be0bd219e72	5124
charlesmn	0:0be0bd219e72	5125	uint8_t gph__roi_config__user_roi_requested_global_xy_size;
charlesmn	0:0be0bd219e72	5126
charlesmn	0:0be0bd219e72	5127	uint8_t gph__system__sequence_config;
charlesmn	0:0be0bd219e72	5128
charlesmn	0:0be0bd219e72	5129	uint8_t gph__gph_id;
charlesmn	0:0be0bd219e72	5130
charlesmn	0:0be0bd219e72	5131	uint8_t system__interrupt_set;
charlesmn	0:0be0bd219e72	5132
charlesmn	0:0be0bd219e72	5133	uint8_t interrupt_manager__enables;
charlesmn	0:0be0bd219e72	5134
charlesmn	0:0be0bd219e72	5135	uint8_t interrupt_manager__clear;
charlesmn	0:0be0bd219e72	5136
charlesmn	0:0be0bd219e72	5137	uint8_t interrupt_manager__status;
charlesmn	0:0be0bd219e72	5138
charlesmn	0:0be0bd219e72	5139	uint8_t mcu_to_host_bank__wr_access_en;
charlesmn	0:0be0bd219e72	5140
charlesmn	0:0be0bd219e72	5141	uint8_t power_management__go1_reset_status;
charlesmn	0:0be0bd219e72	5142
charlesmn	0:0be0bd219e72	5143	uint8_t pad_startup_mode__value_ro;
charlesmn	0:0be0bd219e72	5144
charlesmn	0:0be0bd219e72	5145	uint8_t pad_startup_mode__value_ctrl;
charlesmn	0:0be0bd219e72	5146
charlesmn	0:0be0bd219e72	5147	uint32_t pll_period_us;
charlesmn	0:0be0bd219e72	5148
charlesmn	0:0be0bd219e72	5149	uint32_t interrupt_scheduler__data_out;
charlesmn	0:0be0bd219e72	5150
charlesmn	0:0be0bd219e72	5151	uint8_t nvm_bist__complete;
charlesmn	0:0be0bd219e72	5152
charlesmn	0:0be0bd219e72	5153	uint8_t nvm_bist__status;
charlesmn	0:0be0bd219e72	5154
charlesmn	0:0be0bd219e72	5155	} VL53LX_debug_results_t;
charlesmn	0:0be0bd219e72	5156
charlesmn	0:0be0bd219e72	5157
charlesmn	0:0be0bd219e72	5158
charlesmn	0:0be0bd219e72	5159
charlesmn	0:0be0bd219e72	5160	typedef struct {
charlesmn	0:0be0bd219e72	5161	uint8_t identification__model_id;
charlesmn	0:0be0bd219e72	5162
charlesmn	0:0be0bd219e72	5163	uint8_t identification__module_type;
charlesmn	0:0be0bd219e72	5164
charlesmn	0:0be0bd219e72	5165	uint8_t identification__revision_id;
charlesmn	0:0be0bd219e72	5166
charlesmn	0:0be0bd219e72	5167	uint16_t identification__module_id;
charlesmn	0:0be0bd219e72	5168
charlesmn	0:0be0bd219e72	5169	uint8_t ana_config__fast_osc__trim_max;
charlesmn	0:0be0bd219e72	5170
charlesmn	0:0be0bd219e72	5171	uint8_t ana_config__fast_osc__freq_set;
charlesmn	0:0be0bd219e72	5172
charlesmn	0:0be0bd219e72	5173	uint8_t ana_config__vcsel_trim;
charlesmn	0:0be0bd219e72	5174
charlesmn	0:0be0bd219e72	5175	uint8_t ana_config__vcsel_selion;
charlesmn	0:0be0bd219e72	5176
charlesmn	0:0be0bd219e72	5177	uint8_t ana_config__vcsel_selion_max;
charlesmn	0:0be0bd219e72	5178
charlesmn	0:0be0bd219e72	5179	uint8_t protected_laser_safety__lock_bit;
charlesmn	0:0be0bd219e72	5180
charlesmn	0:0be0bd219e72	5181	uint8_t laser_safety__key;
charlesmn	0:0be0bd219e72	5182
charlesmn	0:0be0bd219e72	5183	uint8_t laser_safety__key_ro;
charlesmn	0:0be0bd219e72	5184
charlesmn	0:0be0bd219e72	5185	uint8_t laser_safety__clip;
charlesmn	0:0be0bd219e72	5186
charlesmn	0:0be0bd219e72	5187	uint8_t laser_safety__mult;
charlesmn	0:0be0bd219e72	5188
charlesmn	0:0be0bd219e72	5189	uint8_t global_config__spad_enables_rtn_0;
charlesmn	0:0be0bd219e72	5190
charlesmn	0:0be0bd219e72	5191	uint8_t global_config__spad_enables_rtn_1;
charlesmn	0:0be0bd219e72	5192
charlesmn	0:0be0bd219e72	5193	uint8_t global_config__spad_enables_rtn_2;
charlesmn	0:0be0bd219e72	5194
charlesmn	0:0be0bd219e72	5195	uint8_t global_config__spad_enables_rtn_3;
charlesmn	0:0be0bd219e72	5196
charlesmn	0:0be0bd219e72	5197	uint8_t global_config__spad_enables_rtn_4;
charlesmn	0:0be0bd219e72	5198
charlesmn	0:0be0bd219e72	5199	uint8_t global_config__spad_enables_rtn_5;
charlesmn	0:0be0bd219e72	5200
charlesmn	0:0be0bd219e72	5201	uint8_t global_config__spad_enables_rtn_6;
charlesmn	0:0be0bd219e72	5202
charlesmn	0:0be0bd219e72	5203	uint8_t global_config__spad_enables_rtn_7;
charlesmn	0:0be0bd219e72	5204
charlesmn	0:0be0bd219e72	5205	uint8_t global_config__spad_enables_rtn_8;
charlesmn	0:0be0bd219e72	5206
charlesmn	0:0be0bd219e72	5207	uint8_t global_config__spad_enables_rtn_9;
charlesmn	0:0be0bd219e72	5208
charlesmn	0:0be0bd219e72	5209	uint8_t global_config__spad_enables_rtn_10;
charlesmn	0:0be0bd219e72	5210
charlesmn	0:0be0bd219e72	5211	uint8_t global_config__spad_enables_rtn_11;
charlesmn	0:0be0bd219e72	5212
charlesmn	0:0be0bd219e72	5213	uint8_t global_config__spad_enables_rtn_12;
charlesmn	0:0be0bd219e72	5214
charlesmn	0:0be0bd219e72	5215	uint8_t global_config__spad_enables_rtn_13;
charlesmn	0:0be0bd219e72	5216
charlesmn	0:0be0bd219e72	5217	uint8_t global_config__spad_enables_rtn_14;
charlesmn	0:0be0bd219e72	5218
charlesmn	0:0be0bd219e72	5219	uint8_t global_config__spad_enables_rtn_15;
charlesmn	0:0be0bd219e72	5220
charlesmn	0:0be0bd219e72	5221	uint8_t global_config__spad_enables_rtn_16;
charlesmn	0:0be0bd219e72	5222
charlesmn	0:0be0bd219e72	5223	uint8_t global_config__spad_enables_rtn_17;
charlesmn	0:0be0bd219e72	5224
charlesmn	0:0be0bd219e72	5225	uint8_t global_config__spad_enables_rtn_18;
charlesmn	0:0be0bd219e72	5226
charlesmn	0:0be0bd219e72	5227	uint8_t global_config__spad_enables_rtn_19;
charlesmn	0:0be0bd219e72	5228
charlesmn	0:0be0bd219e72	5229	uint8_t global_config__spad_enables_rtn_20;
charlesmn	0:0be0bd219e72	5230
charlesmn	0:0be0bd219e72	5231	uint8_t global_config__spad_enables_rtn_21;
charlesmn	0:0be0bd219e72	5232
charlesmn	0:0be0bd219e72	5233	uint8_t global_config__spad_enables_rtn_22;
charlesmn	0:0be0bd219e72	5234
charlesmn	0:0be0bd219e72	5235	uint8_t global_config__spad_enables_rtn_23;
charlesmn	0:0be0bd219e72	5236
charlesmn	0:0be0bd219e72	5237	uint8_t global_config__spad_enables_rtn_24;
charlesmn	0:0be0bd219e72	5238
charlesmn	0:0be0bd219e72	5239	uint8_t global_config__spad_enables_rtn_25;
charlesmn	0:0be0bd219e72	5240
charlesmn	0:0be0bd219e72	5241	uint8_t global_config__spad_enables_rtn_26;
charlesmn	0:0be0bd219e72	5242
charlesmn	0:0be0bd219e72	5243	uint8_t global_config__spad_enables_rtn_27;
charlesmn	0:0be0bd219e72	5244
charlesmn	0:0be0bd219e72	5245	uint8_t global_config__spad_enables_rtn_28;
charlesmn	0:0be0bd219e72	5246
charlesmn	0:0be0bd219e72	5247	uint8_t global_config__spad_enables_rtn_29;
charlesmn	0:0be0bd219e72	5248
charlesmn	0:0be0bd219e72	5249	uint8_t global_config__spad_enables_rtn_30;
charlesmn	0:0be0bd219e72	5250
charlesmn	0:0be0bd219e72	5251	uint8_t global_config__spad_enables_rtn_31;
charlesmn	0:0be0bd219e72	5252
charlesmn	0:0be0bd219e72	5253	uint8_t roi_config__mode_roi_centre_spad;
charlesmn	0:0be0bd219e72	5254
charlesmn	0:0be0bd219e72	5255	uint8_t roi_config__mode_roi_xy_size;
charlesmn	0:0be0bd219e72	5256
charlesmn	0:0be0bd219e72	5257	} VL53LX_nvm_copy_data_t;
charlesmn	0:0be0bd219e72	5258
charlesmn	0:0be0bd219e72	5259
charlesmn	0:0be0bd219e72	5260
charlesmn	0:0be0bd219e72	5261
charlesmn	0:0be0bd219e72	5262	typedef struct {
charlesmn	0:0be0bd219e72	5263	uint8_t prev_shadow_result__interrupt_status;
charlesmn	0:0be0bd219e72	5264
charlesmn	0:0be0bd219e72	5265	uint8_t prev_shadow_result__range_status;
charlesmn	0:0be0bd219e72	5266
charlesmn	0:0be0bd219e72	5267	uint8_t prev_shadow_result__report_status;
charlesmn	0:0be0bd219e72	5268
charlesmn	0:0be0bd219e72	5269	uint8_t prev_shadow_result__stream_count;
charlesmn	0:0be0bd219e72	5270
charlesmn	0:0be0bd219e72	5271	uint16_t prev_shadow_result__dss_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5272
charlesmn	0:0be0bd219e72	5273	uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5274
charlesmn	0:0be0bd219e72	5275	uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5276
charlesmn	0:0be0bd219e72	5277	uint16_t prev_shadow_result__sigma_sd0;
charlesmn	0:0be0bd219e72	5278
charlesmn	0:0be0bd219e72	5279	uint16_t prev_shadow_result__phase_sd0;
charlesmn	0:0be0bd219e72	5280
charlesmn	0:0be0bd219e72	5281	uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0;
charlesmn	0:0be0bd219e72	5282
charlesmn	0:0be0bd219e72	5283	uint16_t
charlesmn	0:0be0bd219e72	5284	psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
charlesmn	0:0be0bd219e72	5285
charlesmn	0:0be0bd219e72	5286	uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5287
charlesmn	0:0be0bd219e72	5288	uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5289
charlesmn	0:0be0bd219e72	5290	uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5291
charlesmn	0:0be0bd219e72	5292	uint16_t prev_shadow_result__dss_actual_effective_spads_sd1;
charlesmn	0:0be0bd219e72	5293
charlesmn	0:0be0bd219e72	5294	uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1;
charlesmn	0:0be0bd219e72	5295
charlesmn	0:0be0bd219e72	5296	uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1;
charlesmn	0:0be0bd219e72	5297
charlesmn	0:0be0bd219e72	5298	uint16_t prev_shadow_result__sigma_sd1;
charlesmn	0:0be0bd219e72	5299
charlesmn	0:0be0bd219e72	5300	uint16_t prev_shadow_result__phase_sd1;
charlesmn	0:0be0bd219e72	5301
charlesmn	0:0be0bd219e72	5302	uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1;
charlesmn	0:0be0bd219e72	5303
charlesmn	0:0be0bd219e72	5304	uint16_t prev_shadow_result__spare_0_sd1;
charlesmn	0:0be0bd219e72	5305
charlesmn	0:0be0bd219e72	5306	uint16_t prev_shadow_result__spare_1_sd1;
charlesmn	0:0be0bd219e72	5307
charlesmn	0:0be0bd219e72	5308	uint16_t prev_shadow_result__spare_2_sd1;
charlesmn	0:0be0bd219e72	5309
charlesmn	0:0be0bd219e72	5310	uint16_t prev_shadow_result__spare_3_sd1;
charlesmn	0:0be0bd219e72	5311
charlesmn	0:0be0bd219e72	5312	} VL53LX_prev_shadow_system_results_t;
charlesmn	0:0be0bd219e72	5313
charlesmn	0:0be0bd219e72	5314
charlesmn	0:0be0bd219e72	5315
charlesmn	0:0be0bd219e72	5316
charlesmn	0:0be0bd219e72	5317	typedef struct {
charlesmn	0:0be0bd219e72	5318	uint32_t prev_shadow_result_core__ambient_window_events_sd0;
charlesmn	0:0be0bd219e72	5319
charlesmn	0:0be0bd219e72	5320	uint32_t prev_shadow_result_core__ranging_total_events_sd0;
charlesmn	0:0be0bd219e72	5321
charlesmn	0:0be0bd219e72	5322	int32_t prev_shadow_result_core__signal_total_events_sd0;
charlesmn	0:0be0bd219e72	5323
charlesmn	0:0be0bd219e72	5324	uint32_t prev_shadow_result_core__total_periods_elapsed_sd0;
charlesmn	0:0be0bd219e72	5325
charlesmn	0:0be0bd219e72	5326	uint32_t prev_shadow_result_core__ambient_window_events_sd1;
charlesmn	0:0be0bd219e72	5327
charlesmn	0:0be0bd219e72	5328	uint32_t prev_shadow_result_core__ranging_total_events_sd1;
charlesmn	0:0be0bd219e72	5329
charlesmn	0:0be0bd219e72	5330	int32_t prev_shadow_result_core__signal_total_events_sd1;
charlesmn	0:0be0bd219e72	5331
charlesmn	0:0be0bd219e72	5332	uint32_t prev_shadow_result_core__total_periods_elapsed_sd1;
charlesmn	0:0be0bd219e72	5333
charlesmn	0:0be0bd219e72	5334	uint8_t prev_shadow_result_core__spare_0;
charlesmn	0:0be0bd219e72	5335
charlesmn	0:0be0bd219e72	5336	} VL53LX_prev_shadow_core_results_t;
charlesmn	0:0be0bd219e72	5337
charlesmn	0:0be0bd219e72	5338
charlesmn	0:0be0bd219e72	5339
charlesmn	0:0be0bd219e72	5340
charlesmn	0:0be0bd219e72	5341	typedef struct {
charlesmn	0:0be0bd219e72	5342	uint8_t result__debug_status;
charlesmn	0:0be0bd219e72	5343
charlesmn	0:0be0bd219e72	5344	uint8_t result__debug_stage;
charlesmn	0:0be0bd219e72	5345
charlesmn	0:0be0bd219e72	5346	} VL53LX_patch_debug_t;
charlesmn	0:0be0bd219e72	5347
charlesmn	0:0be0bd219e72	5348
charlesmn	0:0be0bd219e72	5349
charlesmn	0:0be0bd219e72	5350
charlesmn	0:0be0bd219e72	5351	typedef struct {
charlesmn	0:0be0bd219e72	5352	uint16_t gph__system__thresh_rate_high;
charlesmn	0:0be0bd219e72	5353
charlesmn	0:0be0bd219e72	5354	uint16_t gph__system__thresh_rate_low;
charlesmn	0:0be0bd219e72	5355
charlesmn	0:0be0bd219e72	5356	uint8_t gph__system__interrupt_config_gpio;
charlesmn	0:0be0bd219e72	5357
charlesmn	0:0be0bd219e72	5358	} VL53LX_gph_general_config_t;
charlesmn	0:0be0bd219e72	5359
charlesmn	0:0be0bd219e72	5360
charlesmn	0:0be0bd219e72	5361
charlesmn	0:0be0bd219e72	5362
charlesmn	0:0be0bd219e72	5363	typedef struct {
charlesmn	0:0be0bd219e72	5364	uint8_t gph__dss_config__roi_mode_control;
charlesmn	0:0be0bd219e72	5365
charlesmn	0:0be0bd219e72	5366	uint16_t gph__dss_config__manual_effective_spads_select;
charlesmn	0:0be0bd219e72	5367
charlesmn	0:0be0bd219e72	5368	uint8_t gph__dss_config__manual_block_select;
charlesmn	0:0be0bd219e72	5369
charlesmn	0:0be0bd219e72	5370	uint8_t gph__dss_config__max_spads_limit;
charlesmn	0:0be0bd219e72	5371
charlesmn	0:0be0bd219e72	5372	uint8_t gph__dss_config__min_spads_limit;
charlesmn	0:0be0bd219e72	5373
charlesmn	0:0be0bd219e72	5374	} VL53LX_gph_static_config_t;
charlesmn	0:0be0bd219e72	5375
charlesmn	0:0be0bd219e72	5376
charlesmn	0:0be0bd219e72	5377
charlesmn	0:0be0bd219e72	5378
charlesmn	0:0be0bd219e72	5379	typedef struct {
charlesmn	0:0be0bd219e72	5380	uint8_t gph__mm_config__timeout_macrop_a_hi;
charlesmn	0:0be0bd219e72	5381
charlesmn	0:0be0bd219e72	5382	uint8_t gph__mm_config__timeout_macrop_a_lo;
charlesmn	0:0be0bd219e72	5383
charlesmn	0:0be0bd219e72	5384	uint8_t gph__mm_config__timeout_macrop_b_hi;
charlesmn	0:0be0bd219e72	5385
charlesmn	0:0be0bd219e72	5386	uint8_t gph__mm_config__timeout_macrop_b_lo;
charlesmn	0:0be0bd219e72	5387
charlesmn	0:0be0bd219e72	5388	uint8_t gph__range_config__timeout_macrop_a_hi;
charlesmn	0:0be0bd219e72	5389
charlesmn	0:0be0bd219e72	5390	uint8_t gph__range_config__timeout_macrop_a_lo;
charlesmn	0:0be0bd219e72	5391
charlesmn	0:0be0bd219e72	5392	uint8_t gph__range_config__vcsel_period_a;
charlesmn	0:0be0bd219e72	5393
charlesmn	0:0be0bd219e72	5394	uint8_t gph__range_config__vcsel_period_b;
charlesmn	0:0be0bd219e72	5395
charlesmn	0:0be0bd219e72	5396	uint8_t gph__range_config__timeout_macrop_b_hi;
charlesmn	0:0be0bd219e72	5397
charlesmn	0:0be0bd219e72	5398	uint8_t gph__range_config__timeout_macrop_b_lo;
charlesmn	0:0be0bd219e72	5399
charlesmn	0:0be0bd219e72	5400	uint16_t gph__range_config__sigma_thresh;
charlesmn	0:0be0bd219e72	5401
charlesmn	0:0be0bd219e72	5402	uint16_t gph__range_config__min_count_rate_rtn_limit_mcps;
charlesmn	0:0be0bd219e72	5403
charlesmn	0:0be0bd219e72	5404	uint8_t gph__range_config__valid_phase_low;
charlesmn	0:0be0bd219e72	5405
charlesmn	0:0be0bd219e72	5406	uint8_t gph__range_config__valid_phase_high;
charlesmn	0:0be0bd219e72	5407
charlesmn	0:0be0bd219e72	5408	} VL53LX_gph_timing_config_t;
charlesmn	0:0be0bd219e72	5409
charlesmn	0:0be0bd219e72	5410
charlesmn	0:0be0bd219e72	5411
charlesmn	0:0be0bd219e72	5412
charlesmn	0:0be0bd219e72	5413	typedef struct {
charlesmn	0:0be0bd219e72	5414	uint8_t firmware__internal_stream_count_div;
charlesmn	0:0be0bd219e72	5415
charlesmn	0:0be0bd219e72	5416	uint8_t firmware__internal_stream_counter_val;
charlesmn	0:0be0bd219e72	5417
charlesmn	0:0be0bd219e72	5418	} VL53LX_fw_internal_t;
charlesmn	0:0be0bd219e72	5419
charlesmn	0:0be0bd219e72	5420
charlesmn	0:0be0bd219e72	5421
charlesmn	0:0be0bd219e72	5422
charlesmn	0:0be0bd219e72	5423	typedef struct {
charlesmn	0:0be0bd219e72	5424	uint8_t dss_calc__roi_ctrl;
charlesmn	0:0be0bd219e72	5425
charlesmn	0:0be0bd219e72	5426	uint8_t dss_calc__spare_1;
charlesmn	0:0be0bd219e72	5427
charlesmn	0:0be0bd219e72	5428	uint8_t dss_calc__spare_2;
charlesmn	0:0be0bd219e72	5429
charlesmn	0:0be0bd219e72	5430	uint8_t dss_calc__spare_3;
charlesmn	0:0be0bd219e72	5431
charlesmn	0:0be0bd219e72	5432	uint8_t dss_calc__spare_4;
charlesmn	0:0be0bd219e72	5433
charlesmn	0:0be0bd219e72	5434	uint8_t dss_calc__spare_5;
charlesmn	0:0be0bd219e72	5435
charlesmn	0:0be0bd219e72	5436	uint8_t dss_calc__spare_6;
charlesmn	0:0be0bd219e72	5437
charlesmn	0:0be0bd219e72	5438	uint8_t dss_calc__spare_7;
charlesmn	0:0be0bd219e72	5439
charlesmn	0:0be0bd219e72	5440	uint8_t dss_calc__user_roi_spad_en_0;
charlesmn	0:0be0bd219e72	5441
charlesmn	0:0be0bd219e72	5442	uint8_t dss_calc__user_roi_spad_en_1;
charlesmn	0:0be0bd219e72	5443
charlesmn	0:0be0bd219e72	5444	uint8_t dss_calc__user_roi_spad_en_2;
charlesmn	0:0be0bd219e72	5445
charlesmn	0:0be0bd219e72	5446	uint8_t dss_calc__user_roi_spad_en_3;
charlesmn	0:0be0bd219e72	5447
charlesmn	0:0be0bd219e72	5448	uint8_t dss_calc__user_roi_spad_en_4;
charlesmn	0:0be0bd219e72	5449
charlesmn	0:0be0bd219e72	5450	uint8_t dss_calc__user_roi_spad_en_5;
charlesmn	0:0be0bd219e72	5451
charlesmn	0:0be0bd219e72	5452	uint8_t dss_calc__user_roi_spad_en_6;
charlesmn	0:0be0bd219e72	5453
charlesmn	0:0be0bd219e72	5454	uint8_t dss_calc__user_roi_spad_en_7;
charlesmn	0:0be0bd219e72	5455
charlesmn	0:0be0bd219e72	5456	uint8_t dss_calc__user_roi_spad_en_8;
charlesmn	0:0be0bd219e72	5457
charlesmn	0:0be0bd219e72	5458	uint8_t dss_calc__user_roi_spad_en_9;
charlesmn	0:0be0bd219e72	5459
charlesmn	0:0be0bd219e72	5460	uint8_t dss_calc__user_roi_spad_en_10;
charlesmn	0:0be0bd219e72	5461
charlesmn	0:0be0bd219e72	5462	uint8_t dss_calc__user_roi_spad_en_11;
charlesmn	0:0be0bd219e72	5463
charlesmn	0:0be0bd219e72	5464	uint8_t dss_calc__user_roi_spad_en_12;
charlesmn	0:0be0bd219e72	5465
charlesmn	0:0be0bd219e72	5466	uint8_t dss_calc__user_roi_spad_en_13;
charlesmn	0:0be0bd219e72	5467
charlesmn	0:0be0bd219e72	5468	uint8_t dss_calc__user_roi_spad_en_14;
charlesmn	0:0be0bd219e72	5469
charlesmn	0:0be0bd219e72	5470	uint8_t dss_calc__user_roi_spad_en_15;
charlesmn	0:0be0bd219e72	5471
charlesmn	0:0be0bd219e72	5472	uint8_t dss_calc__user_roi_spad_en_16;
charlesmn	0:0be0bd219e72	5473
charlesmn	0:0be0bd219e72	5474	uint8_t dss_calc__user_roi_spad_en_17;
charlesmn	0:0be0bd219e72	5475
charlesmn	0:0be0bd219e72	5476	uint8_t dss_calc__user_roi_spad_en_18;
charlesmn	0:0be0bd219e72	5477
charlesmn	0:0be0bd219e72	5478	uint8_t dss_calc__user_roi_spad_en_19;
charlesmn	0:0be0bd219e72	5479
charlesmn	0:0be0bd219e72	5480	uint8_t dss_calc__user_roi_spad_en_20;
charlesmn	0:0be0bd219e72	5481
charlesmn	0:0be0bd219e72	5482	uint8_t dss_calc__user_roi_spad_en_21;
charlesmn	0:0be0bd219e72	5483
charlesmn	0:0be0bd219e72	5484	uint8_t dss_calc__user_roi_spad_en_22;
charlesmn	0:0be0bd219e72	5485
charlesmn	0:0be0bd219e72	5486	uint8_t dss_calc__user_roi_spad_en_23;
charlesmn	0:0be0bd219e72	5487
charlesmn	0:0be0bd219e72	5488	uint8_t dss_calc__user_roi_spad_en_24;
charlesmn	0:0be0bd219e72	5489
charlesmn	0:0be0bd219e72	5490	uint8_t dss_calc__user_roi_spad_en_25;
charlesmn	0:0be0bd219e72	5491
charlesmn	0:0be0bd219e72	5492	uint8_t dss_calc__user_roi_spad_en_26;
charlesmn	0:0be0bd219e72	5493
charlesmn	0:0be0bd219e72	5494	uint8_t dss_calc__user_roi_spad_en_27;
charlesmn	0:0be0bd219e72	5495
charlesmn	0:0be0bd219e72	5496	uint8_t dss_calc__user_roi_spad_en_28;
charlesmn	0:0be0bd219e72	5497
charlesmn	0:0be0bd219e72	5498	uint8_t dss_calc__user_roi_spad_en_29;
charlesmn	0:0be0bd219e72	5499
charlesmn	0:0be0bd219e72	5500	uint8_t dss_calc__user_roi_spad_en_30;
charlesmn	0:0be0bd219e72	5501
charlesmn	0:0be0bd219e72	5502	uint8_t dss_calc__user_roi_spad_en_31;
charlesmn	0:0be0bd219e72	5503
charlesmn	0:0be0bd219e72	5504	uint8_t dss_calc__user_roi_0;
charlesmn	0:0be0bd219e72	5505
charlesmn	0:0be0bd219e72	5506	uint8_t dss_calc__user_roi_1;
charlesmn	0:0be0bd219e72	5507
charlesmn	0:0be0bd219e72	5508	uint8_t dss_calc__mode_roi_0;
charlesmn	0:0be0bd219e72	5509
charlesmn	0:0be0bd219e72	5510	uint8_t dss_calc__mode_roi_1;
charlesmn	0:0be0bd219e72	5511
charlesmn	0:0be0bd219e72	5512	uint8_t sigma_estimator_calc__spare_0;
charlesmn	0:0be0bd219e72	5513
charlesmn	0:0be0bd219e72	5514	uint16_t vhv_result__peak_signal_rate_mcps;
charlesmn	0:0be0bd219e72	5515
charlesmn	0:0be0bd219e72	5516	uint32_t vhv_result__signal_total_events_ref;
charlesmn	0:0be0bd219e72	5517
charlesmn	0:0be0bd219e72	5518	uint16_t phasecal_result__phase_output_ref;
charlesmn	0:0be0bd219e72	5519
charlesmn	0:0be0bd219e72	5520	uint16_t dss_result__total_rate_per_spad;
charlesmn	0:0be0bd219e72	5521
charlesmn	0:0be0bd219e72	5522	uint8_t dss_result__enabled_blocks;
charlesmn	0:0be0bd219e72	5523
charlesmn	0:0be0bd219e72	5524	uint16_t dss_result__num_requested_spads;
charlesmn	0:0be0bd219e72	5525
charlesmn	0:0be0bd219e72	5526	uint16_t mm_result__inner_intersection_rate;
charlesmn	0:0be0bd219e72	5527
charlesmn	0:0be0bd219e72	5528	uint16_t mm_result__outer_complement_rate;
charlesmn	0:0be0bd219e72	5529
charlesmn	0:0be0bd219e72	5530	uint16_t mm_result__total_offset;
charlesmn	0:0be0bd219e72	5531
charlesmn	0:0be0bd219e72	5532	uint32_t xtalk_calc__xtalk_for_enabled_spads;
charlesmn	0:0be0bd219e72	5533
charlesmn	0:0be0bd219e72	5534	uint32_t xtalk_result__avg_xtalk_user_roi_kcps;
charlesmn	0:0be0bd219e72	5535
charlesmn	0:0be0bd219e72	5536	uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps;
charlesmn	0:0be0bd219e72	5537
charlesmn	0:0be0bd219e72	5538	uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps;
charlesmn	0:0be0bd219e72	5539
charlesmn	0:0be0bd219e72	5540	uint32_t range_result__accum_phase;
charlesmn	0:0be0bd219e72	5541
charlesmn	0:0be0bd219e72	5542	uint16_t range_result__offset_corrected_range;
charlesmn	0:0be0bd219e72	5543
charlesmn	0:0be0bd219e72	5544	} VL53LX_patch_results_t;
charlesmn	0:0be0bd219e72	5545
charlesmn	0:0be0bd219e72	5546
charlesmn	0:0be0bd219e72	5547
charlesmn	0:0be0bd219e72	5548
charlesmn	0:0be0bd219e72	5549	typedef struct {
charlesmn	0:0be0bd219e72	5550	uint8_t shadow_phasecal_result__vcsel_start;
charlesmn	0:0be0bd219e72	5551
charlesmn	0:0be0bd219e72	5552	uint8_t shadow_result__interrupt_status;
charlesmn	0:0be0bd219e72	5553
charlesmn	0:0be0bd219e72	5554	uint8_t shadow_result__range_status;
charlesmn	0:0be0bd219e72	5555
charlesmn	0:0be0bd219e72	5556	uint8_t shadow_result__report_status;
charlesmn	0:0be0bd219e72	5557
charlesmn	0:0be0bd219e72	5558	uint8_t shadow_result__stream_count;
charlesmn	0:0be0bd219e72	5559
charlesmn	0:0be0bd219e72	5560	uint16_t shadow_result__dss_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5561
charlesmn	0:0be0bd219e72	5562	uint16_t shadow_result__peak_signal_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5563
charlesmn	0:0be0bd219e72	5564	uint16_t shadow_result__ambient_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5565
charlesmn	0:0be0bd219e72	5566	uint16_t shadow_result__sigma_sd0;
charlesmn	0:0be0bd219e72	5567
charlesmn	0:0be0bd219e72	5568	uint16_t shadow_result__phase_sd0;
charlesmn	0:0be0bd219e72	5569
charlesmn	0:0be0bd219e72	5570	uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0;
charlesmn	0:0be0bd219e72	5571
charlesmn	0:0be0bd219e72	5572	uint16_t
charlesmn	0:0be0bd219e72	5573	shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;
charlesmn	0:0be0bd219e72	5574
charlesmn	0:0be0bd219e72	5575	uint16_t shadow_result__mm_inner_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5576
charlesmn	0:0be0bd219e72	5577	uint16_t shadow_result__mm_outer_actual_effective_spads_sd0;
charlesmn	0:0be0bd219e72	5578
charlesmn	0:0be0bd219e72	5579	uint16_t shadow_result__avg_signal_count_rate_mcps_sd0;
charlesmn	0:0be0bd219e72	5580
charlesmn	0:0be0bd219e72	5581	uint16_t shadow_result__dss_actual_effective_spads_sd1;
charlesmn	0:0be0bd219e72	5582
charlesmn	0:0be0bd219e72	5583	uint16_t shadow_result__peak_signal_count_rate_mcps_sd1;
charlesmn	0:0be0bd219e72	5584
charlesmn	0:0be0bd219e72	5585	uint16_t shadow_result__ambient_count_rate_mcps_sd1;
charlesmn	0:0be0bd219e72	5586
charlesmn	0:0be0bd219e72	5587	uint16_t shadow_result__sigma_sd1;
charlesmn	0:0be0bd219e72	5588
charlesmn	0:0be0bd219e72	5589	uint16_t shadow_result__phase_sd1;
charlesmn	0:0be0bd219e72	5590
charlesmn	0:0be0bd219e72	5591	uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1;
charlesmn	0:0be0bd219e72	5592
charlesmn	0:0be0bd219e72	5593	uint16_t shadow_result__spare_0_sd1;
charlesmn	0:0be0bd219e72	5594
charlesmn	0:0be0bd219e72	5595	uint16_t shadow_result__spare_1_sd1;
charlesmn	0:0be0bd219e72	5596
charlesmn	0:0be0bd219e72	5597	uint16_t shadow_result__spare_2_sd1;
charlesmn	0:0be0bd219e72	5598
charlesmn	0:0be0bd219e72	5599	uint8_t shadow_result__spare_3_sd1;
charlesmn	0:0be0bd219e72	5600
charlesmn	0:0be0bd219e72	5601	uint8_t shadow_result__thresh_info;
charlesmn	0:0be0bd219e72	5602
charlesmn	0:0be0bd219e72	5603	uint8_t shadow_phasecal_result__reference_phase_hi;
charlesmn	0:0be0bd219e72	5604
charlesmn	0:0be0bd219e72	5605	uint8_t shadow_phasecal_result__reference_phase_lo;
charlesmn	0:0be0bd219e72	5606
charlesmn	0:0be0bd219e72	5607	} VL53LX_shadow_system_results_t;
charlesmn	0:0be0bd219e72	5608
charlesmn	0:0be0bd219e72	5609
charlesmn	0:0be0bd219e72	5610
charlesmn	0:0be0bd219e72	5611
charlesmn	0:0be0bd219e72	5612	typedef struct {
charlesmn	0:0be0bd219e72	5613	uint32_t shadow_result_core__ambient_window_events_sd0;
charlesmn	0:0be0bd219e72	5614
charlesmn	0:0be0bd219e72	5615	uint32_t shadow_result_core__ranging_total_events_sd0;
charlesmn	0:0be0bd219e72	5616
charlesmn	0:0be0bd219e72	5617	int32_t shadow_result_core__signal_total_events_sd0;
charlesmn	0:0be0bd219e72	5618
charlesmn	0:0be0bd219e72	5619	uint32_t shadow_result_core__total_periods_elapsed_sd0;
charlesmn	0:0be0bd219e72	5620
charlesmn	0:0be0bd219e72	5621	uint32_t shadow_result_core__ambient_window_events_sd1;
charlesmn	0:0be0bd219e72	5622
charlesmn	0:0be0bd219e72	5623	uint32_t shadow_result_core__ranging_total_events_sd1;
charlesmn	0:0be0bd219e72	5624
charlesmn	0:0be0bd219e72	5625	int32_t shadow_result_core__signal_total_events_sd1;
charlesmn	0:0be0bd219e72	5626
charlesmn	0:0be0bd219e72	5627	uint32_t shadow_result_core__total_periods_elapsed_sd1;
charlesmn	0:0be0bd219e72	5628
charlesmn	0:0be0bd219e72	5629	uint8_t shadow_result_core__spare_0;
charlesmn	0:0be0bd219e72	5630
charlesmn	0:0be0bd219e72	5631	} VL53LX_shadow_core_results_t;
charlesmn	0:0be0bd219e72	5632
charlesmn	0:0be0bd219e72	5633
charlesmn	0:0be0bd219e72	5634	// typedef from vl53lx_dmax_structs.h
charlesmn	0:0be0bd219e72	5635
charlesmn	0:0be0bd219e72	5636	#define VL53LX_MAX_AMBIENT_DMAX_VALUES 5
charlesmn	0:0be0bd219e72	5637
charlesmn	0:0be0bd219e72	5638	typedef struct {
charlesmn	0:0be0bd219e72	5639	uint16_t ref__actual_effective_spads;
charlesmn	0:0be0bd219e72	5640	uint16_t ref__peak_signal_count_rate_mcps;
charlesmn	0:0be0bd219e72	5641	uint16_t ref__distance_mm;
charlesmn	0:0be0bd219e72	5642	uint16_t ref_reflectance_pc;
charlesmn	0:0be0bd219e72	5643	uint16_t coverglass_transmission;
charlesmn	0:0be0bd219e72	5644
charlesmn	0:0be0bd219e72	5645	} VL53LX_dmax_calibration_data_t;
charlesmn	0:0be0bd219e72	5646
charlesmn	0:0be0bd219e72	5647
charlesmn	0:0be0bd219e72	5648
charlesmn	0:0be0bd219e72	5649
charlesmn	0:0be0bd219e72	5650	typedef struct {
charlesmn	0:0be0bd219e72	5651	uint8_t signal_thresh_sigma;
charlesmn	0:0be0bd219e72	5652	uint8_t ambient_thresh_sigma;
charlesmn	0:0be0bd219e72	5653	int32_t min_ambient_thresh_events;
charlesmn	0:0be0bd219e72	5654	int32_t signal_total_events_limit;
charlesmn	0:0be0bd219e72	5655	uint16_t target_reflectance_for_dmax_calc[VL53LX_MAX_AMBIENT_DMAX_VALUES];
charlesmn	0:0be0bd219e72	5656	uint16_t max_effective_spads;
charlesmn	0:0be0bd219e72	5657	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	5658	uint8_t dss_config__aperture_attenuation;
charlesmn	0:0be0bd219e72	5659	} VL53LX_hist_gen3_dmax_config_t;
charlesmn	0:0be0bd219e72	5660
charlesmn	0:0be0bd219e72	5661
charlesmn	0:0be0bd219e72	5662
charlesmn	0:0be0bd219e72	5663	// define & typedef from vl53lx_hist_structs.h
charlesmn	0:0be0bd219e72	5664
charlesmn	0:0be0bd219e72	5665	#define VL53LX_MAX_BIN_SEQUENCE_LENGTH 6
charlesmn	0:0be0bd219e72	5666	#define VL53LX_MAX_BIN_SEQUENCE_CODE 15
charlesmn	0:0be0bd219e72	5667	#define VL53LX_HISTOGRAM_BUFFER_SIZE 24
charlesmn	0:0be0bd219e72	5668	#define VL53LX_XTALK_HISTO_BINS 12
charlesmn	0:0be0bd219e72	5669
charlesmn	0:0be0bd219e72	5670
charlesmn	0:0be0bd219e72	5671
charlesmn	0:0be0bd219e72	5672	typedef struct {
charlesmn	0:0be0bd219e72	5673
charlesmn	0:0be0bd219e72	5674	uint8_t histogram_config__spad_array_selection;
charlesmn	0:0be0bd219e72	5675
charlesmn	0:0be0bd219e72	5676	uint8_t histogram_config__low_amb_even_bin_0_1;
charlesmn	0:0be0bd219e72	5677	uint8_t histogram_config__low_amb_even_bin_2_3;
charlesmn	0:0be0bd219e72	5678	uint8_t histogram_config__low_amb_even_bin_4_5;
charlesmn	0:0be0bd219e72	5679
charlesmn	0:0be0bd219e72	5680	uint8_t histogram_config__low_amb_odd_bin_0_1;
charlesmn	0:0be0bd219e72	5681	uint8_t histogram_config__low_amb_odd_bin_2_3;
charlesmn	0:0be0bd219e72	5682	uint8_t histogram_config__low_amb_odd_bin_4_5;
charlesmn	0:0be0bd219e72	5683
charlesmn	0:0be0bd219e72	5684	uint8_t histogram_config__mid_amb_even_bin_0_1;
charlesmn	0:0be0bd219e72	5685	uint8_t histogram_config__mid_amb_even_bin_2_3;
charlesmn	0:0be0bd219e72	5686	uint8_t histogram_config__mid_amb_even_bin_4_5;
charlesmn	0:0be0bd219e72	5687
charlesmn	0:0be0bd219e72	5688	uint8_t histogram_config__mid_amb_odd_bin_0_1;
charlesmn	0:0be0bd219e72	5689	uint8_t histogram_config__mid_amb_odd_bin_2;
charlesmn	0:0be0bd219e72	5690	uint8_t histogram_config__mid_amb_odd_bin_3_4;
charlesmn	0:0be0bd219e72	5691	uint8_t histogram_config__mid_amb_odd_bin_5;
charlesmn	0:0be0bd219e72	5692
charlesmn	0:0be0bd219e72	5693	uint8_t histogram_config__user_bin_offset;
charlesmn	0:0be0bd219e72	5694
charlesmn	0:0be0bd219e72	5695	uint8_t histogram_config__high_amb_even_bin_0_1;
charlesmn	0:0be0bd219e72	5696	uint8_t histogram_config__high_amb_even_bin_2_3;
charlesmn	0:0be0bd219e72	5697	uint8_t histogram_config__high_amb_even_bin_4_5;
charlesmn	0:0be0bd219e72	5698
charlesmn	0:0be0bd219e72	5699	uint8_t histogram_config__high_amb_odd_bin_0_1;
charlesmn	0:0be0bd219e72	5700	uint8_t histogram_config__high_amb_odd_bin_2_3;
charlesmn	0:0be0bd219e72	5701	uint8_t histogram_config__high_amb_odd_bin_4_5;
charlesmn	0:0be0bd219e72	5702
charlesmn	0:0be0bd219e72	5703	uint16_t histogram_config__amb_thresh_low;
charlesmn	0:0be0bd219e72	5704
charlesmn	0:0be0bd219e72	5705	uint16_t histogram_config__amb_thresh_high;
charlesmn	0:0be0bd219e72	5706
charlesmn	0:0be0bd219e72	5707
charlesmn	0:0be0bd219e72	5708	} VL53LX_histogram_config_t;
charlesmn	0:0be0bd219e72	5709
charlesmn	0:0be0bd219e72	5710
charlesmn	0:0be0bd219e72	5711
charlesmn	0:0be0bd219e72	5712
charlesmn	0:0be0bd219e72	5713	typedef struct {
charlesmn	0:0be0bd219e72	5714
charlesmn	0:0be0bd219e72	5715	VL53LX_HistAlgoSelect hist_algo_select;
charlesmn	0:0be0bd219e72	5716
charlesmn	0:0be0bd219e72	5717
charlesmn	0:0be0bd219e72	5718	VL53LX_HistTargetOrder hist_target_order;
charlesmn	0:0be0bd219e72	5719
charlesmn	0:0be0bd219e72	5720
charlesmn	0:0be0bd219e72	5721	uint8_t filter_woi0;
charlesmn	0:0be0bd219e72	5722
charlesmn	0:0be0bd219e72	5723	uint8_t filter_woi1;
charlesmn	0:0be0bd219e72	5724
charlesmn	0:0be0bd219e72	5725
charlesmn	0:0be0bd219e72	5726	VL53LX_HistAmbEstMethod hist_amb_est_method;
charlesmn	0:0be0bd219e72	5727
charlesmn	0:0be0bd219e72	5728	uint8_t ambient_thresh_sigma0;
charlesmn	0:0be0bd219e72	5729
charlesmn	0:0be0bd219e72	5730	uint8_t ambient_thresh_sigma1;
charlesmn	0:0be0bd219e72	5731
charlesmn	0:0be0bd219e72	5732
charlesmn	0:0be0bd219e72	5733
charlesmn	0:0be0bd219e72	5734	uint16_t ambient_thresh_events_scaler;
charlesmn	0:0be0bd219e72	5735
charlesmn	0:0be0bd219e72	5736
charlesmn	0:0be0bd219e72	5737
charlesmn	0:0be0bd219e72	5738	int32_t min_ambient_thresh_events;
charlesmn	0:0be0bd219e72	5739
charlesmn	0:0be0bd219e72	5740	uint16_t noise_threshold;
charlesmn	0:0be0bd219e72	5741
charlesmn	0:0be0bd219e72	5742
charlesmn	0:0be0bd219e72	5743	int32_t signal_total_events_limit;
charlesmn	0:0be0bd219e72	5744
charlesmn	0:0be0bd219e72	5745	uint8_t sigma_estimator__sigma_ref_mm;
charlesmn	0:0be0bd219e72	5746
charlesmn	0:0be0bd219e72	5747	uint16_t sigma_thresh;
charlesmn	0:0be0bd219e72	5748
charlesmn	0:0be0bd219e72	5749	int16_t range_offset_mm;
charlesmn	0:0be0bd219e72	5750
charlesmn	0:0be0bd219e72	5751	uint16_t gain_factor;
charlesmn	0:0be0bd219e72	5752
charlesmn	0:0be0bd219e72	5753
charlesmn	0:0be0bd219e72	5754	uint8_t valid_phase_low;
charlesmn	0:0be0bd219e72	5755
charlesmn	0:0be0bd219e72	5756	uint8_t valid_phase_high;
charlesmn	0:0be0bd219e72	5757
charlesmn	0:0be0bd219e72	5758	uint8_t algo__consistency_check__phase_tolerance;
charlesmn	0:0be0bd219e72	5759
charlesmn	0:0be0bd219e72	5760	uint8_t algo__consistency_check__event_sigma;
charlesmn	0:0be0bd219e72	5761
charlesmn	0:0be0bd219e72	5762
charlesmn	0:0be0bd219e72	5763
charlesmn	0:0be0bd219e72	5764	uint16_t algo__consistency_check__event_min_spad_count;
charlesmn	0:0be0bd219e72	5765
charlesmn	0:0be0bd219e72	5766
charlesmn	0:0be0bd219e72	5767
charlesmn	0:0be0bd219e72	5768	uint16_t algo__consistency_check__min_max_tolerance;
charlesmn	0:0be0bd219e72	5769
charlesmn	0:0be0bd219e72	5770
charlesmn	0:0be0bd219e72	5771	uint8_t algo__crosstalk_compensation_enable;
charlesmn	0:0be0bd219e72	5772
charlesmn	0:0be0bd219e72	5773	uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	5774
charlesmn	0:0be0bd219e72	5775	int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	5776
charlesmn	0:0be0bd219e72	5777	int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	5778
charlesmn	0:0be0bd219e72	5779
charlesmn	0:0be0bd219e72	5780	int16_t algo__crosstalk_detect_min_valid_range_mm;
charlesmn	0:0be0bd219e72	5781
charlesmn	0:0be0bd219e72	5782	int16_t algo__crosstalk_detect_max_valid_range_mm;
charlesmn	0:0be0bd219e72	5783
charlesmn	0:0be0bd219e72	5784	uint16_t algo__crosstalk_detect_max_valid_rate_kcps;
charlesmn	0:0be0bd219e72	5785
charlesmn	0:0be0bd219e72	5786	uint16_t algo__crosstalk_detect_max_sigma_mm;
charlesmn	0:0be0bd219e72	5787
charlesmn	0:0be0bd219e72	5788
charlesmn	0:0be0bd219e72	5789
charlesmn	0:0be0bd219e72	5790	uint8_t algo__crosstalk_detect_event_sigma;
charlesmn	0:0be0bd219e72	5791
charlesmn	0:0be0bd219e72	5792
charlesmn	0:0be0bd219e72	5793
charlesmn	0:0be0bd219e72	5794	uint16_t algo__crosstalk_detect_min_max_tolerance;
charlesmn	0:0be0bd219e72	5795
charlesmn	0:0be0bd219e72	5796
charlesmn	0:0be0bd219e72	5797	} VL53LX_hist_post_process_config_t;
charlesmn	0:0be0bd219e72	5798
charlesmn	0:0be0bd219e72	5799
charlesmn	0:0be0bd219e72	5800
charlesmn	0:0be0bd219e72	5801	typedef struct {
charlesmn	0:0be0bd219e72	5802
charlesmn	0:0be0bd219e72	5803
charlesmn	0:0be0bd219e72	5804	VL53LX_DeviceState cfg_device_state;
charlesmn	0:0be0bd219e72	5805
charlesmn	0:0be0bd219e72	5806	VL53LX_DeviceState rd_device_state;
charlesmn	0:0be0bd219e72	5807
charlesmn	0:0be0bd219e72	5808
charlesmn	0:0be0bd219e72	5809	uint8_t zone_id;
charlesmn	0:0be0bd219e72	5810
charlesmn	0:0be0bd219e72	5811	uint32_t time_stamp;
charlesmn	0:0be0bd219e72	5812
charlesmn	0:0be0bd219e72	5813
charlesmn	0:0be0bd219e72	5814	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	5815
charlesmn	0:0be0bd219e72	5816	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	5817
charlesmn	0:0be0bd219e72	5818	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	5819
charlesmn	0:0be0bd219e72	5820	uint8_t number_of_ambient_bins;
charlesmn	0:0be0bd219e72	5821
charlesmn	0:0be0bd219e72	5822	uint8_t bin_seq[VL53LX_MAX_BIN_SEQUENCE_LENGTH];
charlesmn	0:0be0bd219e72	5823
charlesmn	0:0be0bd219e72	5824	uint8_t bin_rep[VL53LX_MAX_BIN_SEQUENCE_LENGTH];
charlesmn	0:0be0bd219e72	5825
charlesmn	0:0be0bd219e72	5826	int32_t bin_data[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5827
charlesmn	0:0be0bd219e72	5828
charlesmn	0:0be0bd219e72	5829	uint8_t result__interrupt_status;
charlesmn	0:0be0bd219e72	5830
charlesmn	0:0be0bd219e72	5831	uint8_t result__range_status;
charlesmn	0:0be0bd219e72	5832
charlesmn	0:0be0bd219e72	5833	uint8_t result__report_status;
charlesmn	0:0be0bd219e72	5834
charlesmn	0:0be0bd219e72	5835	uint8_t result__stream_count;
charlesmn	0:0be0bd219e72	5836
charlesmn	0:0be0bd219e72	5837	uint16_t result__dss_actual_effective_spads;
charlesmn	0:0be0bd219e72	5838
charlesmn	0:0be0bd219e72	5839
charlesmn	0:0be0bd219e72	5840	uint16_t phasecal_result__reference_phase;
charlesmn	0:0be0bd219e72	5841
charlesmn	0:0be0bd219e72	5842	uint8_t phasecal_result__vcsel_start;
charlesmn	0:0be0bd219e72	5843
charlesmn	0:0be0bd219e72	5844	uint8_t cal_config__vcsel_start;
charlesmn	0:0be0bd219e72	5845
charlesmn	0:0be0bd219e72	5846	uint16_t vcsel_width;
charlesmn	0:0be0bd219e72	5847
charlesmn	0:0be0bd219e72	5848	uint8_t VL53LX_p_005;
charlesmn	0:0be0bd219e72	5849
charlesmn	0:0be0bd219e72	5850	uint16_t VL53LX_p_015;
charlesmn	0:0be0bd219e72	5851
charlesmn	0:0be0bd219e72	5852	uint32_t total_periods_elapsed;
charlesmn	0:0be0bd219e72	5853
charlesmn	0:0be0bd219e72	5854
charlesmn	0:0be0bd219e72	5855	uint32_t peak_duration_us;
charlesmn	0:0be0bd219e72	5856
charlesmn	0:0be0bd219e72	5857	uint32_t woi_duration_us;
charlesmn	0:0be0bd219e72	5858
charlesmn	0:0be0bd219e72	5859
charlesmn	0:0be0bd219e72	5860	int32_t min_bin_value;
charlesmn	0:0be0bd219e72	5861
charlesmn	0:0be0bd219e72	5862	int32_t max_bin_value;
charlesmn	0:0be0bd219e72	5863
charlesmn	0:0be0bd219e72	5864
charlesmn	0:0be0bd219e72	5865	uint16_t zero_distance_phase;
charlesmn	0:0be0bd219e72	5866
charlesmn	0:0be0bd219e72	5867	uint8_t number_of_ambient_samples;
charlesmn	0:0be0bd219e72	5868
charlesmn	0:0be0bd219e72	5869	int32_t ambient_events_sum;
charlesmn	0:0be0bd219e72	5870
charlesmn	0:0be0bd219e72	5871	int32_t VL53LX_p_028;
charlesmn	0:0be0bd219e72	5872
charlesmn	0:0be0bd219e72	5873
charlesmn	0:0be0bd219e72	5874	uint8_t roi_config__user_roi_centre_spad;
charlesmn	0:0be0bd219e72	5875
charlesmn	0:0be0bd219e72	5876	uint8_t roi_config__user_roi_requested_global_xy_size;
charlesmn	0:0be0bd219e72	5877
charlesmn	0:0be0bd219e72	5878
charlesmn	0:0be0bd219e72	5879	} VL53LX_histogram_bin_data_t;
charlesmn	0:0be0bd219e72	5880
charlesmn	0:0be0bd219e72	5881
charlesmn	0:0be0bd219e72	5882
charlesmn	0:0be0bd219e72	5883
charlesmn	0:0be0bd219e72	5884	typedef struct {
charlesmn	0:0be0bd219e72	5885
charlesmn	0:0be0bd219e72	5886
charlesmn	0:0be0bd219e72	5887	uint8_t zone_id;
charlesmn	0:0be0bd219e72	5888
charlesmn	0:0be0bd219e72	5889	uint32_t time_stamp;
charlesmn	0:0be0bd219e72	5890
charlesmn	0:0be0bd219e72	5891
charlesmn	0:0be0bd219e72	5892	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	5893
charlesmn	0:0be0bd219e72	5894	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	5895
charlesmn	0:0be0bd219e72	5896	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	5897
charlesmn	0:0be0bd219e72	5898	uint32_t bin_data[VL53LX_XTALK_HISTO_BINS];
charlesmn	0:0be0bd219e72	5899
charlesmn	0:0be0bd219e72	5900
charlesmn	0:0be0bd219e72	5901
charlesmn	0:0be0bd219e72	5902	uint16_t phasecal_result__reference_phase;
charlesmn	0:0be0bd219e72	5903
charlesmn	0:0be0bd219e72	5904	uint8_t phasecal_result__vcsel_start;
charlesmn	0:0be0bd219e72	5905
charlesmn	0:0be0bd219e72	5906	uint8_t cal_config__vcsel_start;
charlesmn	0:0be0bd219e72	5907
charlesmn	0:0be0bd219e72	5908	uint16_t vcsel_width;
charlesmn	0:0be0bd219e72	5909
charlesmn	0:0be0bd219e72	5910	uint16_t VL53LX_p_015;
charlesmn	0:0be0bd219e72	5911
charlesmn	0:0be0bd219e72	5912	uint16_t zero_distance_phase;
charlesmn	0:0be0bd219e72	5913
charlesmn	0:0be0bd219e72	5914
charlesmn	0:0be0bd219e72	5915	} VL53LX_xtalk_histogram_shape_t;
charlesmn	0:0be0bd219e72	5916
charlesmn	0:0be0bd219e72	5917
charlesmn	0:0be0bd219e72	5918
charlesmn	0:0be0bd219e72	5919
charlesmn	0:0be0bd219e72	5920	typedef struct {
charlesmn	0:0be0bd219e72	5921
charlesmn	0:0be0bd219e72	5922
charlesmn	0:0be0bd219e72	5923	VL53LX_xtalk_histogram_shape_t xtalk_shape;
charlesmn	0:0be0bd219e72	5924
charlesmn	0:0be0bd219e72	5925	VL53LX_histogram_bin_data_t xtalk_hist_removed;
charlesmn	0:0be0bd219e72	5926
charlesmn	0:0be0bd219e72	5927	} VL53LX_xtalk_histogram_data_t;
charlesmn	0:0be0bd219e72	5928
charlesmn	0:0be0bd219e72	5929
charlesmn	0:0be0bd219e72	5930	/* vl53lx_hist_private_structs.h */
charlesmn	0:0be0bd219e72	5931
charlesmn	0:0be0bd219e72	5932	#define VL53LX_D_001 8
charlesmn	0:0be0bd219e72	5933
charlesmn	0:0be0bd219e72	5934
charlesmn	0:0be0bd219e72	5935
charlesmn	0:0be0bd219e72	5936
charlesmn	0:0be0bd219e72	5937
charlesmn	0:0be0bd219e72	5938	typedef struct {
charlesmn	0:0be0bd219e72	5939
charlesmn	0:0be0bd219e72	5940	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	5941
charlesmn	0:0be0bd219e72	5942
charlesmn	0:0be0bd219e72	5943	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	5944
charlesmn	0:0be0bd219e72	5945
charlesmn	0:0be0bd219e72	5946	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	5947
charlesmn	0:0be0bd219e72	5948
charlesmn	0:0be0bd219e72	5949	uint8_t VL53LX_p_029;
charlesmn	0:0be0bd219e72	5950
charlesmn	0:0be0bd219e72	5951
charlesmn	0:0be0bd219e72	5952	int32_t VL53LX_p_016;
charlesmn	0:0be0bd219e72	5953
charlesmn	0:0be0bd219e72	5954
charlesmn	0:0be0bd219e72	5955
charlesmn	0:0be0bd219e72	5956	int32_t VL53LX_p_043[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5957
charlesmn	0:0be0bd219e72	5958	int32_t VL53LX_p_068[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5959
charlesmn	0:0be0bd219e72	5960
charlesmn	0:0be0bd219e72	5961	uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5962
charlesmn	0:0be0bd219e72	5963
charlesmn	0:0be0bd219e72	5964	int32_t VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5965
charlesmn	0:0be0bd219e72	5966	uint16_t VL53LX_p_014[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5967
charlesmn	0:0be0bd219e72	5968	uint16_t VL53LX_p_008[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	5969
charlesmn	0:0be0bd219e72	5970
charlesmn	0:0be0bd219e72	5971	} VL53LX_hist_gen1_algo_private_data_t;
charlesmn	0:0be0bd219e72	5972
charlesmn	0:0be0bd219e72	5973
charlesmn	0:0be0bd219e72	5974
charlesmn	0:0be0bd219e72	5975
charlesmn	0:0be0bd219e72	5976
charlesmn	0:0be0bd219e72	5977
charlesmn	0:0be0bd219e72	5978
charlesmn	0:0be0bd219e72	5979
charlesmn	0:0be0bd219e72	5980
charlesmn	0:0be0bd219e72	5981
charlesmn	0:0be0bd219e72	5982	typedef struct {
charlesmn	0:0be0bd219e72	5983
charlesmn	0:0be0bd219e72	5984	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	5985
charlesmn	0:0be0bd219e72	5986
charlesmn	0:0be0bd219e72	5987	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	5988
charlesmn	0:0be0bd219e72	5989
charlesmn	0:0be0bd219e72	5990	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	5991
charlesmn	0:0be0bd219e72	5992
charlesmn	0:0be0bd219e72	5993	uint16_t VL53LX_p_015;
charlesmn	0:0be0bd219e72	5994
charlesmn	0:0be0bd219e72	5995
charlesmn	0:0be0bd219e72	5996	uint8_t VL53LX_p_005;
charlesmn	0:0be0bd219e72	5997
charlesmn	0:0be0bd219e72	5998
charlesmn	0:0be0bd219e72	5999	uint8_t VL53LX_p_029;
charlesmn	0:0be0bd219e72	6000
charlesmn	0:0be0bd219e72	6001
charlesmn	0:0be0bd219e72	6002	int32_t VL53LX_p_028;
charlesmn	0:0be0bd219e72	6003
charlesmn	0:0be0bd219e72	6004
charlesmn	0:0be0bd219e72	6005	int32_t VL53LX_p_016;
charlesmn	0:0be0bd219e72	6006
charlesmn	0:0be0bd219e72	6007
charlesmn	0:0be0bd219e72	6008
charlesmn	0:0be0bd219e72	6009	int32_t VL53LX_p_007[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6010
charlesmn	0:0be0bd219e72	6011
charlesmn	0:0be0bd219e72	6012	int32_t VL53LX_p_032[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6013
charlesmn	0:0be0bd219e72	6014
charlesmn	0:0be0bd219e72	6015	int32_t VL53LX_p_001[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6016
charlesmn	0:0be0bd219e72	6017
charlesmn	0:0be0bd219e72	6018
charlesmn	0:0be0bd219e72	6019	int32_t VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6020
charlesmn	0:0be0bd219e72	6021
charlesmn	0:0be0bd219e72	6022	int32_t VL53LX_p_055[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6023
charlesmn	0:0be0bd219e72	6024
charlesmn	0:0be0bd219e72	6025	int32_t VL53LX_p_053[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6026
charlesmn	0:0be0bd219e72	6027
charlesmn	0:0be0bd219e72	6028	int32_t VL53LX_p_054[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6029
charlesmn	0:0be0bd219e72	6030
charlesmn	0:0be0bd219e72	6031
charlesmn	0:0be0bd219e72	6032	} VL53LX_hist_gen2_algo_filtered_data_t;
charlesmn	0:0be0bd219e72	6033
charlesmn	0:0be0bd219e72	6034
charlesmn	0:0be0bd219e72	6035
charlesmn	0:0be0bd219e72	6036
charlesmn	0:0be0bd219e72	6037
charlesmn	0:0be0bd219e72	6038
charlesmn	0:0be0bd219e72	6039
charlesmn	0:0be0bd219e72	6040
charlesmn	0:0be0bd219e72	6041
charlesmn	0:0be0bd219e72	6042
charlesmn	0:0be0bd219e72	6043	typedef struct {
charlesmn	0:0be0bd219e72	6044
charlesmn	0:0be0bd219e72	6045	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	6046
charlesmn	0:0be0bd219e72	6047
charlesmn	0:0be0bd219e72	6048	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	6049
charlesmn	0:0be0bd219e72	6050
charlesmn	0:0be0bd219e72	6051	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	6052
charlesmn	0:0be0bd219e72	6053
charlesmn	0:0be0bd219e72	6054	int32_t VL53LX_p_031;
charlesmn	0:0be0bd219e72	6055
charlesmn	0:0be0bd219e72	6056
charlesmn	0:0be0bd219e72	6057
charlesmn	0:0be0bd219e72	6058	uint8_t VL53LX_p_069[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6059
charlesmn	0:0be0bd219e72	6060
charlesmn	0:0be0bd219e72	6061	uint8_t VL53LX_p_070[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6062
charlesmn	0:0be0bd219e72	6063
charlesmn	0:0be0bd219e72	6064
charlesmn	0:0be0bd219e72	6065	uint32_t VL53LX_p_014[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6066
charlesmn	0:0be0bd219e72	6067
charlesmn	0:0be0bd219e72	6068	uint16_t VL53LX_p_008[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6069
charlesmn	0:0be0bd219e72	6070
charlesmn	0:0be0bd219e72	6071
charlesmn	0:0be0bd219e72	6072	uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6073
charlesmn	0:0be0bd219e72	6074
charlesmn	0:0be0bd219e72	6075
charlesmn	0:0be0bd219e72	6076	} VL53LX_hist_gen2_algo_detection_data_t;
charlesmn	0:0be0bd219e72	6077
charlesmn	0:0be0bd219e72	6078
charlesmn	0:0be0bd219e72	6079
charlesmn	0:0be0bd219e72	6080
charlesmn	0:0be0bd219e72	6081
charlesmn	0:0be0bd219e72	6082
charlesmn	0:0be0bd219e72	6083
charlesmn	0:0be0bd219e72	6084
charlesmn	0:0be0bd219e72	6085
charlesmn	0:0be0bd219e72	6086
charlesmn	0:0be0bd219e72	6087	typedef struct {
charlesmn	0:0be0bd219e72	6088
charlesmn	0:0be0bd219e72	6089	uint8_t VL53LX_p_012;
charlesmn	0:0be0bd219e72	6090
charlesmn	0:0be0bd219e72	6091
charlesmn	0:0be0bd219e72	6092	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	6093
charlesmn	0:0be0bd219e72	6094
charlesmn	0:0be0bd219e72	6095	uint8_t VL53LX_p_023;
charlesmn	0:0be0bd219e72	6096
charlesmn	0:0be0bd219e72	6097
charlesmn	0:0be0bd219e72	6098	uint8_t VL53LX_p_024;
charlesmn	0:0be0bd219e72	6099
charlesmn	0:0be0bd219e72	6100
charlesmn	0:0be0bd219e72	6101	uint8_t VL53LX_p_013;
charlesmn	0:0be0bd219e72	6102
charlesmn	0:0be0bd219e72	6103
charlesmn	0:0be0bd219e72	6104
charlesmn	0:0be0bd219e72	6105	uint8_t VL53LX_p_025;
charlesmn	0:0be0bd219e72	6106
charlesmn	0:0be0bd219e72	6107
charlesmn	0:0be0bd219e72	6108	uint8_t VL53LX_p_051;
charlesmn	0:0be0bd219e72	6109
charlesmn	0:0be0bd219e72	6110
charlesmn	0:0be0bd219e72	6111
charlesmn	0:0be0bd219e72	6112	int32_t VL53LX_p_016;
charlesmn	0:0be0bd219e72	6113
charlesmn	0:0be0bd219e72	6114
charlesmn	0:0be0bd219e72	6115	int32_t VL53LX_p_017;
charlesmn	0:0be0bd219e72	6116
charlesmn	0:0be0bd219e72	6117
charlesmn	0:0be0bd219e72	6118	int32_t VL53LX_p_010;
charlesmn	0:0be0bd219e72	6119
charlesmn	0:0be0bd219e72	6120
charlesmn	0:0be0bd219e72	6121
charlesmn	0:0be0bd219e72	6122	uint32_t VL53LX_p_026;
charlesmn	0:0be0bd219e72	6123
charlesmn	0:0be0bd219e72	6124
charlesmn	0:0be0bd219e72	6125	uint32_t VL53LX_p_011;
charlesmn	0:0be0bd219e72	6126
charlesmn	0:0be0bd219e72	6127
charlesmn	0:0be0bd219e72	6128	uint32_t VL53LX_p_027;
charlesmn	0:0be0bd219e72	6129
charlesmn	0:0be0bd219e72	6130
charlesmn	0:0be0bd219e72	6131
charlesmn	0:0be0bd219e72	6132	uint16_t VL53LX_p_002;
charlesmn	0:0be0bd219e72	6133
charlesmn	0:0be0bd219e72	6134
charlesmn	0:0be0bd219e72	6135
charlesmn	0:0be0bd219e72	6136	} VL53LX_hist_pulse_data_t;
charlesmn	0:0be0bd219e72	6137
charlesmn	0:0be0bd219e72	6138
charlesmn	0:0be0bd219e72	6139
charlesmn	0:0be0bd219e72	6140
charlesmn	0:0be0bd219e72	6141
charlesmn	0:0be0bd219e72	6142
charlesmn	0:0be0bd219e72	6143
charlesmn	0:0be0bd219e72	6144
charlesmn	0:0be0bd219e72	6145
charlesmn	0:0be0bd219e72	6146
charlesmn	0:0be0bd219e72	6147	typedef struct {
charlesmn	0:0be0bd219e72	6148
charlesmn	0:0be0bd219e72	6149	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	6150
charlesmn	0:0be0bd219e72	6151
charlesmn	0:0be0bd219e72	6152	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	6153
charlesmn	0:0be0bd219e72	6154
charlesmn	0:0be0bd219e72	6155	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	6156
charlesmn	0:0be0bd219e72	6157
charlesmn	0:0be0bd219e72	6158	uint8_t VL53LX_p_030;
charlesmn	0:0be0bd219e72	6159
charlesmn	0:0be0bd219e72	6160
charlesmn	0:0be0bd219e72	6161	uint8_t VL53LX_p_039;
charlesmn	0:0be0bd219e72	6162
charlesmn	0:0be0bd219e72	6163
charlesmn	0:0be0bd219e72	6164	int32_t VL53LX_p_028;
charlesmn	0:0be0bd219e72	6165
charlesmn	0:0be0bd219e72	6166
charlesmn	0:0be0bd219e72	6167	int32_t VL53LX_p_031;
charlesmn	0:0be0bd219e72	6168
charlesmn	0:0be0bd219e72	6169
charlesmn	0:0be0bd219e72	6170
charlesmn	0:0be0bd219e72	6171	uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6172
charlesmn	0:0be0bd219e72	6173
charlesmn	0:0be0bd219e72	6174	uint8_t VL53LX_p_041[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6175
charlesmn	0:0be0bd219e72	6176
charlesmn	0:0be0bd219e72	6177	uint8_t VL53LX_p_042[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6178
charlesmn	0:0be0bd219e72	6179
charlesmn	0:0be0bd219e72	6180
charlesmn	0:0be0bd219e72	6181	int32_t VL53LX_p_052[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6182
charlesmn	0:0be0bd219e72	6183
charlesmn	0:0be0bd219e72	6184	int32_t VL53LX_p_043[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6185
charlesmn	0:0be0bd219e72	6186
charlesmn	0:0be0bd219e72	6187	int32_t VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6188
charlesmn	0:0be0bd219e72	6189
charlesmn	0:0be0bd219e72	6190
charlesmn	0:0be0bd219e72	6191	uint8_t VL53LX_p_044;
charlesmn	0:0be0bd219e72	6192
charlesmn	0:0be0bd219e72	6193
charlesmn	0:0be0bd219e72	6194	uint8_t VL53LX_p_045;
charlesmn	0:0be0bd219e72	6195
charlesmn	0:0be0bd219e72	6196
charlesmn	0:0be0bd219e72	6197	uint8_t VL53LX_p_046;
charlesmn	0:0be0bd219e72	6198
charlesmn	0:0be0bd219e72	6199
charlesmn	0:0be0bd219e72	6200
charlesmn	0:0be0bd219e72	6201	VL53LX_hist_pulse_data_t VL53LX_p_003[VL53LX_D_001];
charlesmn	0:0be0bd219e72	6202
charlesmn	0:0be0bd219e72	6203
charlesmn	0:0be0bd219e72	6204
charlesmn	0:0be0bd219e72	6205
charlesmn	0:0be0bd219e72	6206
charlesmn	0:0be0bd219e72	6207
charlesmn	0:0be0bd219e72	6208	VL53LX_histogram_bin_data_t VL53LX_p_006;
charlesmn	0:0be0bd219e72	6209
charlesmn	0:0be0bd219e72	6210
charlesmn	0:0be0bd219e72	6211	VL53LX_histogram_bin_data_t VL53LX_p_047;
charlesmn	0:0be0bd219e72	6212
charlesmn	0:0be0bd219e72	6213
charlesmn	0:0be0bd219e72	6214	VL53LX_histogram_bin_data_t VL53LX_p_048;
charlesmn	0:0be0bd219e72	6215
charlesmn	0:0be0bd219e72	6216
charlesmn	0:0be0bd219e72	6217	VL53LX_histogram_bin_data_t VL53LX_p_049;
charlesmn	0:0be0bd219e72	6218
charlesmn	0:0be0bd219e72	6219
charlesmn	0:0be0bd219e72	6220	VL53LX_histogram_bin_data_t VL53LX_p_050;
charlesmn	0:0be0bd219e72	6221
charlesmn	0:0be0bd219e72	6222
charlesmn	0:0be0bd219e72	6223
charlesmn	0:0be0bd219e72	6224
charlesmn	0:0be0bd219e72	6225
charlesmn	0:0be0bd219e72	6226
charlesmn	0:0be0bd219e72	6227	} VL53LX_hist_gen3_algo_private_data_t;
charlesmn	0:0be0bd219e72	6228
charlesmn	0:0be0bd219e72	6229
charlesmn	0:0be0bd219e72	6230
charlesmn	0:0be0bd219e72	6231
charlesmn	0:0be0bd219e72	6232
charlesmn	0:0be0bd219e72	6233
charlesmn	0:0be0bd219e72	6234
charlesmn	0:0be0bd219e72	6235
charlesmn	0:0be0bd219e72	6236
charlesmn	0:0be0bd219e72	6237
charlesmn	0:0be0bd219e72	6238	typedef struct {
charlesmn	0:0be0bd219e72	6239
charlesmn	0:0be0bd219e72	6240	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	6241
charlesmn	0:0be0bd219e72	6242
charlesmn	0:0be0bd219e72	6243	uint8_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	6244
charlesmn	0:0be0bd219e72	6245
charlesmn	0:0be0bd219e72	6246	uint8_t VL53LX_p_021;
charlesmn	0:0be0bd219e72	6247
charlesmn	0:0be0bd219e72	6248
charlesmn	0:0be0bd219e72	6249
charlesmn	0:0be0bd219e72	6250	int32_t VL53LX_p_007[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6251
charlesmn	0:0be0bd219e72	6252
charlesmn	0:0be0bd219e72	6253	int32_t VL53LX_p_032[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6254
charlesmn	0:0be0bd219e72	6255
charlesmn	0:0be0bd219e72	6256	int32_t VL53LX_p_001[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6257
charlesmn	0:0be0bd219e72	6258
charlesmn	0:0be0bd219e72	6259
charlesmn	0:0be0bd219e72	6260	int32_t VL53LX_p_053[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6261
charlesmn	0:0be0bd219e72	6262
charlesmn	0:0be0bd219e72	6263	int32_t VL53LX_p_054[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6264
charlesmn	0:0be0bd219e72	6265
charlesmn	0:0be0bd219e72	6266
charlesmn	0:0be0bd219e72	6267	uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	6268
charlesmn	0:0be0bd219e72	6269
charlesmn	0:0be0bd219e72	6270
charlesmn	0:0be0bd219e72	6271	} VL53LX_hist_gen4_algo_filtered_data_t;
charlesmn	0:0be0bd219e72	6272
charlesmn	0:0be0bd219e72	6273
charlesmn	0:0be0bd219e72	6274
charlesmn	0:0be0bd219e72	6275	// define & typedef from VL53Lx_ll_def.h
charlesmn	0:0be0bd219e72	6276
charlesmn	0:0be0bd219e72	6277
charlesmn	0:0be0bd219e72	6278
charlesmn	0:0be0bd219e72	6279
charlesmn	0:0be0bd219e72	6280	#define VL53LX_LL_API_IMPLEMENTATION_VER_MAJOR 1
charlesmn	0:0be0bd219e72	6281
charlesmn	0:0be0bd219e72	6282	#define VL53LX_LL_API_IMPLEMENTATION_VER_MINOR 1
charlesmn	0:0be0bd219e72	6283
charlesmn	0:0be0bd219e72	6284	#define VL53LX_LL_API_IMPLEMENTATION_VER_SUB 1
charlesmn	0:0be0bd219e72	6285
charlesmn	0:0be0bd219e72	6286	#define VL53LX_LL_API_IMPLEMENTATION_VER_REVISION 0
charlesmn	0:0be0bd219e72	6287
charlesmn	0:0be0bd219e72	6288	#define VL53LX_LL_API_IMPLEMENTATION_VER_STRING "1.1.1"
charlesmn	0:0be0bd219e72	6289
charlesmn	0:0be0bd219e72	6290
charlesmn	0:0be0bd219e72	6291	#define VL53LX_FIRMWARE_VER_MINIMUM 398
charlesmn	0:0be0bd219e72	6292	#define VL53LX_FIRMWARE_VER_MAXIMUM 400
charlesmn	0:0be0bd219e72	6293
charlesmn	0:0be0bd219e72	6294
charlesmn	0:0be0bd219e72	6295
charlesmn	0:0be0bd219e72	6296
charlesmn	0:0be0bd219e72	6297	#define VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION 0xECAB0102
charlesmn	0:0be0bd219e72	6298
charlesmn	0:0be0bd219e72	6299
charlesmn	0:0be0bd219e72	6300
charlesmn	0:0be0bd219e72	6301
charlesmn	0:0be0bd219e72	6302	#define VL53LX_LL_ZONE_CALIBRATION_DATA_STRUCT_VERSION 0xECAE0101
charlesmn	0:0be0bd219e72	6303
charlesmn	0:0be0bd219e72	6304
charlesmn	0:0be0bd219e72	6305
charlesmn	0:0be0bd219e72	6306
charlesmn	0:0be0bd219e72	6307
charlesmn	0:0be0bd219e72	6308	#define VL53LX_BIN_REC_SIZE 6
charlesmn	0:0be0bd219e72	6309
charlesmn	0:0be0bd219e72	6310	#define VL53LX_TIMING_CONF_A_B_SIZE 2
charlesmn	0:0be0bd219e72	6311
charlesmn	0:0be0bd219e72	6312	#define VL53LX_FRAME_WAIT_EVENT 6
charlesmn	0:0be0bd219e72	6313
charlesmn	0:0be0bd219e72	6314
charlesmn	0:0be0bd219e72	6315
charlesmn	0:0be0bd219e72	6316
charlesmn	0:0be0bd219e72	6317	#define VL53LX_MAX_XTALK_RANGE_RESULTS 5
charlesmn	0:0be0bd219e72	6318
charlesmn	0:0be0bd219e72	6319
charlesmn	0:0be0bd219e72	6320	#define VL53LX_MAX_OFFSET_RANGE_RESULTS 3
charlesmn	0:0be0bd219e72	6321
charlesmn	0:0be0bd219e72	6322
charlesmn	0:0be0bd219e72	6323	#define VL53LX_NVM_MAX_FMT_RANGE_DATA 4
charlesmn	0:0be0bd219e72	6324
charlesmn	0:0be0bd219e72	6325
charlesmn	0:0be0bd219e72	6326	#define VL53LX_NVM_PEAK_RATE_MAP_SAMPLES 25
charlesmn	0:0be0bd219e72	6327
charlesmn	0:0be0bd219e72	6328	#define VL53LX_NVM_PEAK_RATE_MAP_WIDTH 5
charlesmn	0:0be0bd219e72	6329
charlesmn	0:0be0bd219e72	6330	#define VL53LX_NVM_PEAK_RATE_MAP_HEIGHT 5
charlesmn	0:0be0bd219e72	6331
charlesmn	0:0be0bd219e72	6332
charlesmn	0:0be0bd219e72	6333
charlesmn	0:0be0bd219e72	6334
charlesmn	0:0be0bd219e72	6335	#define VL53LX_ERROR_DEVICE_FIRMWARE_TOO_OLD ((VL53LX_Error) - 80)
charlesmn	0:0be0bd219e72	6336
charlesmn	0:0be0bd219e72	6337	#define VL53LX_ERROR_DEVICE_FIRMWARE_TOO_NEW ((VL53LX_Error) - 85)
charlesmn	0:0be0bd219e72	6338
charlesmn	0:0be0bd219e72	6339	#define VL53LX_ERROR_UNIT_TEST_FAIL ((VL53LX_Error) - 90)
charlesmn	0:0be0bd219e72	6340
charlesmn	0:0be0bd219e72	6341	#define VL53LX_ERROR_FILE_READ_FAIL ((VL53LX_Error) - 95)
charlesmn	0:0be0bd219e72	6342
charlesmn	0:0be0bd219e72	6343	#define VL53LX_ERROR_FILE_WRITE_FAIL ((VL53LX_Error) - 96)
charlesmn	0:0be0bd219e72	6344
charlesmn	0:0be0bd219e72	6345
charlesmn	0:0be0bd219e72	6346
charlesmn	0:0be0bd219e72	6347
charlesmn	0:0be0bd219e72	6348
charlesmn	0:0be0bd219e72	6349
charlesmn	0:0be0bd219e72	6350	typedef struct {
charlesmn	0:0be0bd219e72	6351	uint32_t ll_revision;
charlesmn	0:0be0bd219e72	6352	uint8_t ll_major;
charlesmn	0:0be0bd219e72	6353	uint8_t ll_minor;
charlesmn	0:0be0bd219e72	6354	uint8_t ll_build;
charlesmn	0:0be0bd219e72	6355	} VL53LX_ll_version_t;
charlesmn	0:0be0bd219e72	6356
charlesmn	0:0be0bd219e72	6357
charlesmn	0:0be0bd219e72	6358
charlesmn	0:0be0bd219e72	6359
charlesmn	0:0be0bd219e72	6360	typedef struct {
charlesmn	0:0be0bd219e72	6361
charlesmn	0:0be0bd219e72	6362	uint8_t device_test_mode;
charlesmn	0:0be0bd219e72	6363	uint8_t VL53LX_p_005;
charlesmn	0:0be0bd219e72	6364	uint32_t timeout_us;
charlesmn	0:0be0bd219e72	6365	uint16_t target_count_rate_mcps;
charlesmn	0:0be0bd219e72	6366
charlesmn	0:0be0bd219e72	6367	uint16_t min_count_rate_limit_mcps;
charlesmn	0:0be0bd219e72	6368
charlesmn	0:0be0bd219e72	6369	uint16_t max_count_rate_limit_mcps;
charlesmn	0:0be0bd219e72	6370
charlesmn	0:0be0bd219e72	6371
charlesmn	0:0be0bd219e72	6372	} VL53LX_refspadchar_config_t;
charlesmn	0:0be0bd219e72	6373
charlesmn	0:0be0bd219e72	6374
charlesmn	0:0be0bd219e72	6375
charlesmn	0:0be0bd219e72	6376
charlesmn	0:0be0bd219e72	6377	typedef struct {
charlesmn	0:0be0bd219e72	6378
charlesmn	0:0be0bd219e72	6379	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	6380
charlesmn	0:0be0bd219e72	6381	uint32_t phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	6382
charlesmn	0:0be0bd219e72	6383	uint32_t mm_config_timeout_us;
charlesmn	0:0be0bd219e72	6384
charlesmn	0:0be0bd219e72	6385	uint32_t range_config_timeout_us;
charlesmn	0:0be0bd219e72	6386
charlesmn	0:0be0bd219e72	6387	uint8_t num_of_samples;
charlesmn	0:0be0bd219e72	6388
charlesmn	0:0be0bd219e72	6389	int16_t algo__crosstalk_extract_min_valid_range_mm;
charlesmn	0:0be0bd219e72	6390
charlesmn	0:0be0bd219e72	6391	int16_t algo__crosstalk_extract_max_valid_range_mm;
charlesmn	0:0be0bd219e72	6392
charlesmn	0:0be0bd219e72	6393	uint16_t algo__crosstalk_extract_max_valid_rate_kcps;
charlesmn	0:0be0bd219e72	6394
charlesmn	0:0be0bd219e72	6395	uint16_t algo__crosstalk_extract_max_sigma_mm;
charlesmn	0:0be0bd219e72	6396
charlesmn	0:0be0bd219e72	6397
charlesmn	0:0be0bd219e72	6398	} VL53LX_xtalkextract_config_t;
charlesmn	0:0be0bd219e72	6399
charlesmn	0:0be0bd219e72	6400
charlesmn	0:0be0bd219e72	6401
charlesmn	0:0be0bd219e72	6402
charlesmn	0:0be0bd219e72	6403	typedef struct {
charlesmn	0:0be0bd219e72	6404
charlesmn	0:0be0bd219e72	6405	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	6406
charlesmn	0:0be0bd219e72	6407	uint32_t phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	6408
charlesmn	0:0be0bd219e72	6409	uint32_t range_config_timeout_us;
charlesmn	0:0be0bd219e72	6410
charlesmn	0:0be0bd219e72	6411	uint32_t mm_config_timeout_us;
charlesmn	0:0be0bd219e72	6412
charlesmn	0:0be0bd219e72	6413	uint8_t pre_num_of_samples;
charlesmn	0:0be0bd219e72	6414
charlesmn	0:0be0bd219e72	6415	uint8_t mm1_num_of_samples;
charlesmn	0:0be0bd219e72	6416
charlesmn	0:0be0bd219e72	6417	uint8_t mm2_num_of_samples;
charlesmn	0:0be0bd219e72	6418
charlesmn	0:0be0bd219e72	6419
charlesmn	0:0be0bd219e72	6420	} VL53LX_offsetcal_config_t;
charlesmn	0:0be0bd219e72	6421
charlesmn	0:0be0bd219e72	6422
charlesmn	0:0be0bd219e72	6423
charlesmn	0:0be0bd219e72	6424
charlesmn	0:0be0bd219e72	6425	typedef struct {
charlesmn	0:0be0bd219e72	6426
charlesmn	0:0be0bd219e72	6427	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	6428
charlesmn	0:0be0bd219e72	6429	uint32_t phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	6430
charlesmn	0:0be0bd219e72	6431	uint32_t mm_config_timeout_us;
charlesmn	0:0be0bd219e72	6432
charlesmn	0:0be0bd219e72	6433	uint32_t range_config_timeout_us;
charlesmn	0:0be0bd219e72	6434
charlesmn	0:0be0bd219e72	6435	uint16_t phasecal_num_of_samples;
charlesmn	0:0be0bd219e72	6436
charlesmn	0:0be0bd219e72	6437	uint16_t zone_num_of_samples;
charlesmn	0:0be0bd219e72	6438
charlesmn	0:0be0bd219e72	6439
charlesmn	0:0be0bd219e72	6440	} VL53LX_zonecal_config_t;
charlesmn	0:0be0bd219e72	6441
charlesmn	0:0be0bd219e72	6442
charlesmn	0:0be0bd219e72	6443
charlesmn	0:0be0bd219e72	6444
charlesmn	0:0be0bd219e72	6445
charlesmn	0:0be0bd219e72	6446	typedef struct {
charlesmn	0:0be0bd219e72	6447
charlesmn	0:0be0bd219e72	6448	VL53LX_DeviceSscArray array_select;
charlesmn	0:0be0bd219e72	6449
charlesmn	0:0be0bd219e72	6450	uint8_t VL53LX_p_005;
charlesmn	0:0be0bd219e72	6451
charlesmn	0:0be0bd219e72	6452	uint8_t vcsel_start;
charlesmn	0:0be0bd219e72	6453
charlesmn	0:0be0bd219e72	6454	uint8_t vcsel_width;
charlesmn	0:0be0bd219e72	6455
charlesmn	0:0be0bd219e72	6456	uint32_t timeout_us;
charlesmn	0:0be0bd219e72	6457
charlesmn	0:0be0bd219e72	6458	uint16_t rate_limit_mcps;
charlesmn	0:0be0bd219e72	6459
charlesmn	0:0be0bd219e72	6460
charlesmn	0:0be0bd219e72	6461	} VL53LX_ssc_config_t;
charlesmn	0:0be0bd219e72	6462
charlesmn	0:0be0bd219e72	6463
charlesmn	0:0be0bd219e72	6464
charlesmn	0:0be0bd219e72	6465
charlesmn	0:0be0bd219e72	6466	typedef struct {
charlesmn	0:0be0bd219e72	6467
charlesmn	0:0be0bd219e72	6468
charlesmn	0:0be0bd219e72	6469	uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	6470
charlesmn	0:0be0bd219e72	6471	int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	6472
charlesmn	0:0be0bd219e72	6473	int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	6474
charlesmn	0:0be0bd219e72	6475	uint32_t nvm_default__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	6476
charlesmn	0:0be0bd219e72	6477	int16_t nvm_default__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	6478
charlesmn	0:0be0bd219e72	6479	int16_t nvm_default__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	6480
charlesmn	0:0be0bd219e72	6481	uint8_t global_crosstalk_compensation_enable;
charlesmn	0:0be0bd219e72	6482
charlesmn	0:0be0bd219e72	6483	int16_t histogram_mode_crosstalk_margin_kcps;
charlesmn	0:0be0bd219e72	6484
charlesmn	0:0be0bd219e72	6485	int16_t lite_mode_crosstalk_margin_kcps;
charlesmn	0:0be0bd219e72	6486
charlesmn	0:0be0bd219e72	6487	uint8_t crosstalk_range_ignore_threshold_mult;
charlesmn	0:0be0bd219e72	6488
charlesmn	0:0be0bd219e72	6489	uint16_t crosstalk_range_ignore_threshold_rate_mcps;
charlesmn	0:0be0bd219e72	6490
charlesmn	0:0be0bd219e72	6491	int16_t algo__crosstalk_detect_min_valid_range_mm;
charlesmn	0:0be0bd219e72	6492
charlesmn	0:0be0bd219e72	6493	int16_t algo__crosstalk_detect_max_valid_range_mm;
charlesmn	0:0be0bd219e72	6494
charlesmn	0:0be0bd219e72	6495	uint16_t algo__crosstalk_detect_max_valid_rate_kcps;
charlesmn	0:0be0bd219e72	6496
charlesmn	0:0be0bd219e72	6497	uint16_t algo__crosstalk_detect_max_sigma_mm;
charlesmn	0:0be0bd219e72	6498
charlesmn	0:0be0bd219e72	6499
charlesmn	0:0be0bd219e72	6500
charlesmn	0:0be0bd219e72	6501	} VL53LX_xtalk_config_t;
charlesmn	0:0be0bd219e72	6502
charlesmn	0:0be0bd219e72	6503
charlesmn	0:0be0bd219e72	6504
charlesmn	0:0be0bd219e72	6505
charlesmn	0:0be0bd219e72	6506	typedef struct {
charlesmn	0:0be0bd219e72	6507
charlesmn	0:0be0bd219e72	6508
charlesmn	0:0be0bd219e72	6509	uint16_t tp_tuning_parm_version;
charlesmn	0:0be0bd219e72	6510
charlesmn	0:0be0bd219e72	6511	uint16_t tp_tuning_parm_key_table_version;
charlesmn	0:0be0bd219e72	6512
charlesmn	0:0be0bd219e72	6513	uint16_t tp_tuning_parm_lld_version;
charlesmn	0:0be0bd219e72	6514
charlesmn	0:0be0bd219e72	6515	uint8_t tp_init_phase_rtn_lite_long;
charlesmn	0:0be0bd219e72	6516
charlesmn	0:0be0bd219e72	6517	uint8_t tp_init_phase_rtn_lite_med;
charlesmn	0:0be0bd219e72	6518
charlesmn	0:0be0bd219e72	6519	uint8_t tp_init_phase_rtn_lite_short;
charlesmn	0:0be0bd219e72	6520
charlesmn	0:0be0bd219e72	6521	uint8_t tp_init_phase_ref_lite_long;
charlesmn	0:0be0bd219e72	6522
charlesmn	0:0be0bd219e72	6523	uint8_t tp_init_phase_ref_lite_med;
charlesmn	0:0be0bd219e72	6524
charlesmn	0:0be0bd219e72	6525	uint8_t tp_init_phase_ref_lite_short;
charlesmn	0:0be0bd219e72	6526
charlesmn	0:0be0bd219e72	6527
charlesmn	0:0be0bd219e72	6528	uint8_t tp_init_phase_rtn_hist_long;
charlesmn	0:0be0bd219e72	6529
charlesmn	0:0be0bd219e72	6530	uint8_t tp_init_phase_rtn_hist_med;
charlesmn	0:0be0bd219e72	6531
charlesmn	0:0be0bd219e72	6532	uint8_t tp_init_phase_rtn_hist_short;
charlesmn	0:0be0bd219e72	6533
charlesmn	0:0be0bd219e72	6534	uint8_t tp_init_phase_ref_hist_long;
charlesmn	0:0be0bd219e72	6535
charlesmn	0:0be0bd219e72	6536	uint8_t tp_init_phase_ref_hist_med;
charlesmn	0:0be0bd219e72	6537
charlesmn	0:0be0bd219e72	6538	uint8_t tp_init_phase_ref_hist_short;
charlesmn	0:0be0bd219e72	6539
charlesmn	0:0be0bd219e72	6540
charlesmn	0:0be0bd219e72	6541	uint8_t tp_consistency_lite_phase_tolerance;
charlesmn	0:0be0bd219e72	6542
charlesmn	0:0be0bd219e72	6543	uint8_t tp_phasecal_target;
charlesmn	0:0be0bd219e72	6544
charlesmn	0:0be0bd219e72	6545	uint16_t tp_cal_repeat_rate;
charlesmn	0:0be0bd219e72	6546
charlesmn	0:0be0bd219e72	6547	uint8_t tp_lite_min_clip;
charlesmn	0:0be0bd219e72	6548
charlesmn	0:0be0bd219e72	6549
charlesmn	0:0be0bd219e72	6550	uint16_t tp_lite_long_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	6551
charlesmn	0:0be0bd219e72	6552	uint16_t tp_lite_med_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	6553
charlesmn	0:0be0bd219e72	6554	uint16_t tp_lite_short_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	6555
charlesmn	0:0be0bd219e72	6556
charlesmn	0:0be0bd219e72	6557	uint16_t tp_lite_long_min_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	6558
charlesmn	0:0be0bd219e72	6559	uint16_t tp_lite_med_min_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	6560
charlesmn	0:0be0bd219e72	6561	uint16_t tp_lite_short_min_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	6562
charlesmn	0:0be0bd219e72	6563
charlesmn	0:0be0bd219e72	6564	uint8_t tp_lite_sigma_est_pulse_width_ns;
charlesmn	0:0be0bd219e72	6565
charlesmn	0:0be0bd219e72	6566	uint8_t tp_lite_sigma_est_amb_width_ns;
charlesmn	0:0be0bd219e72	6567
charlesmn	0:0be0bd219e72	6568	uint8_t tp_lite_sigma_ref_mm;
charlesmn	0:0be0bd219e72	6569
charlesmn	0:0be0bd219e72	6570	uint8_t tp_lite_seed_cfg;
charlesmn	0:0be0bd219e72	6571
charlesmn	0:0be0bd219e72	6572	uint8_t tp_timed_seed_cfg;
charlesmn	0:0be0bd219e72	6573
charlesmn	0:0be0bd219e72	6574
charlesmn	0:0be0bd219e72	6575	uint8_t tp_lite_quantifier;
charlesmn	0:0be0bd219e72	6576
charlesmn	0:0be0bd219e72	6577	uint8_t tp_lite_first_order_select;
charlesmn	0:0be0bd219e72	6578
charlesmn	0:0be0bd219e72	6579
charlesmn	0:0be0bd219e72	6580	uint16_t tp_dss_target_lite_mcps;
charlesmn	0:0be0bd219e72	6581
charlesmn	0:0be0bd219e72	6582	uint16_t tp_dss_target_histo_mcps;
charlesmn	0:0be0bd219e72	6583
charlesmn	0:0be0bd219e72	6584	uint16_t tp_dss_target_histo_mz_mcps;
charlesmn	0:0be0bd219e72	6585
charlesmn	0:0be0bd219e72	6586	uint16_t tp_dss_target_timed_mcps;
charlesmn	0:0be0bd219e72	6587
charlesmn	0:0be0bd219e72	6588	uint16_t tp_dss_target_very_short_mcps;
charlesmn	0:0be0bd219e72	6589
charlesmn	0:0be0bd219e72	6590
charlesmn	0:0be0bd219e72	6591	uint32_t tp_phasecal_timeout_lite_us;
charlesmn	0:0be0bd219e72	6592
charlesmn	0:0be0bd219e72	6593	uint32_t tp_phasecal_timeout_hist_long_us;
charlesmn	0:0be0bd219e72	6594
charlesmn	0:0be0bd219e72	6595	uint32_t tp_phasecal_timeout_hist_med_us;
charlesmn	0:0be0bd219e72	6596
charlesmn	0:0be0bd219e72	6597	uint32_t tp_phasecal_timeout_hist_short_us;
charlesmn	0:0be0bd219e72	6598
charlesmn	0:0be0bd219e72	6599
charlesmn	0:0be0bd219e72	6600	uint32_t tp_phasecal_timeout_mz_long_us;
charlesmn	0:0be0bd219e72	6601
charlesmn	0:0be0bd219e72	6602	uint32_t tp_phasecal_timeout_mz_med_us;
charlesmn	0:0be0bd219e72	6603
charlesmn	0:0be0bd219e72	6604	uint32_t tp_phasecal_timeout_mz_short_us;
charlesmn	0:0be0bd219e72	6605
charlesmn	0:0be0bd219e72	6606	uint32_t tp_phasecal_timeout_timed_us;
charlesmn	0:0be0bd219e72	6607
charlesmn	0:0be0bd219e72	6608
charlesmn	0:0be0bd219e72	6609	uint32_t tp_mm_timeout_lite_us;
charlesmn	0:0be0bd219e72	6610
charlesmn	0:0be0bd219e72	6611	uint32_t tp_mm_timeout_histo_us;
charlesmn	0:0be0bd219e72	6612
charlesmn	0:0be0bd219e72	6613	uint32_t tp_mm_timeout_mz_us;
charlesmn	0:0be0bd219e72	6614
charlesmn	0:0be0bd219e72	6615	uint32_t tp_mm_timeout_timed_us;
charlesmn	0:0be0bd219e72	6616
charlesmn	0:0be0bd219e72	6617	uint32_t tp_mm_timeout_lpa_us;
charlesmn	0:0be0bd219e72	6618
charlesmn	0:0be0bd219e72	6619
charlesmn	0:0be0bd219e72	6620	uint32_t tp_range_timeout_lite_us;
charlesmn	0:0be0bd219e72	6621
charlesmn	0:0be0bd219e72	6622	uint32_t tp_range_timeout_histo_us;
charlesmn	0:0be0bd219e72	6623
charlesmn	0:0be0bd219e72	6624	uint32_t tp_range_timeout_mz_us;
charlesmn	0:0be0bd219e72	6625
charlesmn	0:0be0bd219e72	6626	uint32_t tp_range_timeout_timed_us;
charlesmn	0:0be0bd219e72	6627
charlesmn	0:0be0bd219e72	6628	uint32_t tp_range_timeout_lpa_us;
charlesmn	0:0be0bd219e72	6629
charlesmn	0:0be0bd219e72	6630	uint32_t tp_phasecal_patch_power;
charlesmn	0:0be0bd219e72	6631
charlesmn	0:0be0bd219e72	6632	uint32_t tp_hist_merge;
charlesmn	0:0be0bd219e72	6633
charlesmn	0:0be0bd219e72	6634	uint32_t tp_reset_merge_threshold;
charlesmn	0:0be0bd219e72	6635
charlesmn	0:0be0bd219e72	6636	uint32_t tp_hist_merge_max_size;
charlesmn	0:0be0bd219e72	6637
charlesmn	0:0be0bd219e72	6638
charlesmn	0:0be0bd219e72	6639	} VL53LX_tuning_parm_storage_t;
charlesmn	0:0be0bd219e72	6640
charlesmn	0:0be0bd219e72	6641
charlesmn	0:0be0bd219e72	6642
charlesmn	0:0be0bd219e72	6643
charlesmn	0:0be0bd219e72	6644
charlesmn	0:0be0bd219e72	6645	typedef struct {
charlesmn	0:0be0bd219e72	6646
charlesmn	0:0be0bd219e72	6647	uint8_t x_centre;
charlesmn	0:0be0bd219e72	6648	uint8_t y_centre;
charlesmn	0:0be0bd219e72	6649
charlesmn	0:0be0bd219e72	6650	} VL53LX_optical_centre_t;
charlesmn	0:0be0bd219e72	6651
charlesmn	0:0be0bd219e72	6652
charlesmn	0:0be0bd219e72	6653
charlesmn	0:0be0bd219e72	6654
charlesmn	0:0be0bd219e72	6655	typedef struct {
charlesmn	0:0be0bd219e72	6656
charlesmn	0:0be0bd219e72	6657	uint8_t x_centre;
charlesmn	0:0be0bd219e72	6658	uint8_t y_centre;
charlesmn	0:0be0bd219e72	6659	uint8_t width;
charlesmn	0:0be0bd219e72	6660	uint8_t height;
charlesmn	0:0be0bd219e72	6661
charlesmn	0:0be0bd219e72	6662	} VL53LX_user_zone_t;
charlesmn	0:0be0bd219e72	6663
charlesmn	0:0be0bd219e72	6664
charlesmn	0:0be0bd219e72	6665
charlesmn	0:0be0bd219e72	6666
charlesmn	0:0be0bd219e72	6667	typedef struct {
charlesmn	0:0be0bd219e72	6668
charlesmn	0:0be0bd219e72	6669	uint8_t max_zones;
charlesmn	0:0be0bd219e72	6670	uint8_t active_zones;
charlesmn	0:0be0bd219e72	6671
charlesmn	0:0be0bd219e72	6672
charlesmn	0:0be0bd219e72	6673
charlesmn	0:0be0bd219e72	6674	VL53LX_histogram_config_t multizone_hist_cfg;
charlesmn	0:0be0bd219e72	6675
charlesmn	0:0be0bd219e72	6676	VL53LX_user_zone_t user_zones[VL53LX_MAX_USER_ZONES];
charlesmn	0:0be0bd219e72	6677
charlesmn	0:0be0bd219e72	6678
charlesmn	0:0be0bd219e72	6679	uint8_t bin_config[VL53LX_MAX_USER_ZONES];
charlesmn	0:0be0bd219e72	6680
charlesmn	0:0be0bd219e72	6681
charlesmn	0:0be0bd219e72	6682	} VL53LX_zone_config_t;
charlesmn	0:0be0bd219e72	6683
charlesmn	0:0be0bd219e72	6684
charlesmn	0:0be0bd219e72	6685
charlesmn	0:0be0bd219e72	6686	typedef struct {
charlesmn	0:0be0bd219e72	6687
charlesmn	0:0be0bd219e72	6688
charlesmn	0:0be0bd219e72	6689	VL53LX_GPIO_Interrupt_Mode intr_mode_distance;
charlesmn	0:0be0bd219e72	6690
charlesmn	0:0be0bd219e72	6691
charlesmn	0:0be0bd219e72	6692	VL53LX_GPIO_Interrupt_Mode intr_mode_rate;
charlesmn	0:0be0bd219e72	6693
charlesmn	0:0be0bd219e72	6694
charlesmn	0:0be0bd219e72	6695	uint8_t intr_new_measure_ready;
charlesmn	0:0be0bd219e72	6696
charlesmn	0:0be0bd219e72	6697
charlesmn	0:0be0bd219e72	6698	uint8_t intr_no_target;
charlesmn	0:0be0bd219e72	6699
charlesmn	0:0be0bd219e72	6700
charlesmn	0:0be0bd219e72	6701	uint8_t intr_combined_mode;
charlesmn	0:0be0bd219e72	6702
charlesmn	0:0be0bd219e72	6703
charlesmn	0:0be0bd219e72	6704
charlesmn	0:0be0bd219e72	6705
charlesmn	0:0be0bd219e72	6706
charlesmn	0:0be0bd219e72	6707	uint16_t threshold_distance_high;
charlesmn	0:0be0bd219e72	6708
charlesmn	0:0be0bd219e72	6709
charlesmn	0:0be0bd219e72	6710	uint16_t threshold_distance_low;
charlesmn	0:0be0bd219e72	6711
charlesmn	0:0be0bd219e72	6712
charlesmn	0:0be0bd219e72	6713	uint16_t threshold_rate_high;
charlesmn	0:0be0bd219e72	6714
charlesmn	0:0be0bd219e72	6715
charlesmn	0:0be0bd219e72	6716	uint16_t threshold_rate_low;
charlesmn	0:0be0bd219e72	6717
charlesmn	0:0be0bd219e72	6718	} VL53LX_GPIO_interrupt_config_t;
charlesmn	0:0be0bd219e72	6719
charlesmn	0:0be0bd219e72	6720
charlesmn	0:0be0bd219e72	6721
charlesmn	0:0be0bd219e72	6722
charlesmn	0:0be0bd219e72	6723	typedef struct {
charlesmn	0:0be0bd219e72	6724
charlesmn	0:0be0bd219e72	6725
charlesmn	0:0be0bd219e72	6726	uint8_t vhv_loop_bound;
charlesmn	0:0be0bd219e72	6727
charlesmn	0:0be0bd219e72	6728
charlesmn	0:0be0bd219e72	6729	uint8_t is_low_power_auto_mode;
charlesmn	0:0be0bd219e72	6730
charlesmn	0:0be0bd219e72	6731
charlesmn	0:0be0bd219e72	6732	uint8_t low_power_auto_range_count;
charlesmn	0:0be0bd219e72	6733
charlesmn	0:0be0bd219e72	6734
charlesmn	0:0be0bd219e72	6735	uint8_t saved_interrupt_config;
charlesmn	0:0be0bd219e72	6736
charlesmn	0:0be0bd219e72	6737
charlesmn	0:0be0bd219e72	6738	uint8_t saved_vhv_init;
charlesmn	0:0be0bd219e72	6739
charlesmn	0:0be0bd219e72	6740
charlesmn	0:0be0bd219e72	6741	uint8_t saved_vhv_timeout;
charlesmn	0:0be0bd219e72	6742
charlesmn	0:0be0bd219e72	6743
charlesmn	0:0be0bd219e72	6744	uint8_t first_run_phasecal_result;
charlesmn	0:0be0bd219e72	6745
charlesmn	0:0be0bd219e72	6746
charlesmn	0:0be0bd219e72	6747	uint32_t dss__total_rate_per_spad_mcps;
charlesmn	0:0be0bd219e72	6748
charlesmn	0:0be0bd219e72	6749
charlesmn	0:0be0bd219e72	6750	uint16_t dss__required_spads;
charlesmn	0:0be0bd219e72	6751
charlesmn	0:0be0bd219e72	6752	} VL53LX_low_power_auto_data_t;
charlesmn	0:0be0bd219e72	6753
charlesmn	0:0be0bd219e72	6754
charlesmn	0:0be0bd219e72	6755
charlesmn	0:0be0bd219e72	6756
charlesmn	0:0be0bd219e72	6757
charlesmn	0:0be0bd219e72	6758
charlesmn	0:0be0bd219e72	6759
charlesmn	0:0be0bd219e72	6760	typedef struct {
charlesmn	0:0be0bd219e72	6761
charlesmn	0:0be0bd219e72	6762
charlesmn	0:0be0bd219e72	6763	uint8_t smudge_corr_enabled;
charlesmn	0:0be0bd219e72	6764
charlesmn	0:0be0bd219e72	6765
charlesmn	0:0be0bd219e72	6766	uint8_t smudge_corr_apply_enabled;
charlesmn	0:0be0bd219e72	6767
charlesmn	0:0be0bd219e72	6768
charlesmn	0:0be0bd219e72	6769	uint8_t smudge_corr_single_apply;
charlesmn	0:0be0bd219e72	6770
charlesmn	0:0be0bd219e72	6771
charlesmn	0:0be0bd219e72	6772
charlesmn	0:0be0bd219e72	6773
charlesmn	0:0be0bd219e72	6774	uint16_t smudge_margin;
charlesmn	0:0be0bd219e72	6775
charlesmn	0:0be0bd219e72	6776
charlesmn	0:0be0bd219e72	6777	uint32_t noise_margin;
charlesmn	0:0be0bd219e72	6778
charlesmn	0:0be0bd219e72	6779
charlesmn	0:0be0bd219e72	6780	uint32_t user_xtalk_offset_limit;
charlesmn	0:0be0bd219e72	6781
charlesmn	0:0be0bd219e72	6782
charlesmn	0:0be0bd219e72	6783	uint8_t user_xtalk_offset_limit_hi;
charlesmn	0:0be0bd219e72	6784
charlesmn	0:0be0bd219e72	6785
charlesmn	0:0be0bd219e72	6786	uint32_t sample_limit;
charlesmn	0:0be0bd219e72	6787
charlesmn	0:0be0bd219e72	6788
charlesmn	0:0be0bd219e72	6789	uint32_t single_xtalk_delta;
charlesmn	0:0be0bd219e72	6790
charlesmn	0:0be0bd219e72	6791
charlesmn	0:0be0bd219e72	6792	uint32_t averaged_xtalk_delta;
charlesmn	0:0be0bd219e72	6793
charlesmn	0:0be0bd219e72	6794
charlesmn	0:0be0bd219e72	6795	uint32_t smudge_corr_clip_limit;
charlesmn	0:0be0bd219e72	6796
charlesmn	0:0be0bd219e72	6797
charlesmn	0:0be0bd219e72	6798	uint32_t smudge_corr_ambient_threshold;
charlesmn	0:0be0bd219e72	6799
charlesmn	0:0be0bd219e72	6800
charlesmn	0:0be0bd219e72	6801	uint8_t scaler_calc_method;
charlesmn	0:0be0bd219e72	6802
charlesmn	0:0be0bd219e72	6803
charlesmn	0:0be0bd219e72	6804	int16_t x_gradient_scaler;
charlesmn	0:0be0bd219e72	6805
charlesmn	0:0be0bd219e72	6806
charlesmn	0:0be0bd219e72	6807	int16_t y_gradient_scaler;
charlesmn	0:0be0bd219e72	6808
charlesmn	0:0be0bd219e72	6809
charlesmn	0:0be0bd219e72	6810	uint8_t user_scaler_set;
charlesmn	0:0be0bd219e72	6811
charlesmn	0:0be0bd219e72	6812
charlesmn	0:0be0bd219e72	6813	uint32_t nodetect_ambient_threshold;
charlesmn	0:0be0bd219e72	6814
charlesmn	0:0be0bd219e72	6815
charlesmn	0:0be0bd219e72	6816	uint32_t nodetect_sample_limit;
charlesmn	0:0be0bd219e72	6817
charlesmn	0:0be0bd219e72	6818
charlesmn	0:0be0bd219e72	6819	uint32_t nodetect_xtalk_offset;
charlesmn	0:0be0bd219e72	6820
charlesmn	0:0be0bd219e72	6821
charlesmn	0:0be0bd219e72	6822	uint16_t nodetect_min_range_mm;
charlesmn	0:0be0bd219e72	6823
charlesmn	0:0be0bd219e72	6824
charlesmn	0:0be0bd219e72	6825	uint32_t max_smudge_factor;
charlesmn	0:0be0bd219e72	6826
charlesmn	0:0be0bd219e72	6827	} VL53LX_smudge_corrector_config_t;
charlesmn	0:0be0bd219e72	6828
charlesmn	0:0be0bd219e72	6829
charlesmn	0:0be0bd219e72	6830
charlesmn	0:0be0bd219e72	6831	typedef struct {
charlesmn	0:0be0bd219e72	6832
charlesmn	0:0be0bd219e72	6833
charlesmn	0:0be0bd219e72	6834	uint32_t current_samples;
charlesmn	0:0be0bd219e72	6835
charlesmn	0:0be0bd219e72	6836
charlesmn	0:0be0bd219e72	6837	uint32_t required_samples;
charlesmn	0:0be0bd219e72	6838
charlesmn	0:0be0bd219e72	6839
charlesmn	0:0be0bd219e72	6840	uint64_t accumulator;
charlesmn	0:0be0bd219e72	6841
charlesmn	0:0be0bd219e72	6842
charlesmn	0:0be0bd219e72	6843	uint32_t nodetect_counter;
charlesmn	0:0be0bd219e72	6844
charlesmn	0:0be0bd219e72	6845	} VL53LX_smudge_corrector_internals_t;
charlesmn	0:0be0bd219e72	6846
charlesmn	0:0be0bd219e72	6847
charlesmn	0:0be0bd219e72	6848
charlesmn	0:0be0bd219e72	6849	typedef struct {
charlesmn	0:0be0bd219e72	6850
charlesmn	0:0be0bd219e72	6851
charlesmn	0:0be0bd219e72	6852	uint8_t smudge_corr_valid;
charlesmn	0:0be0bd219e72	6853
charlesmn	0:0be0bd219e72	6854
charlesmn	0:0be0bd219e72	6855	uint8_t smudge_corr_clipped;
charlesmn	0:0be0bd219e72	6856
charlesmn	0:0be0bd219e72	6857
charlesmn	0:0be0bd219e72	6858	uint8_t single_xtalk_delta_flag;
charlesmn	0:0be0bd219e72	6859
charlesmn	0:0be0bd219e72	6860
charlesmn	0:0be0bd219e72	6861	uint8_t averaged_xtalk_delta_flag;
charlesmn	0:0be0bd219e72	6862
charlesmn	0:0be0bd219e72	6863
charlesmn	0:0be0bd219e72	6864	uint8_t sample_limit_exceeded_flag;
charlesmn	0:0be0bd219e72	6865
charlesmn	0:0be0bd219e72	6866
charlesmn	0:0be0bd219e72	6867	uint8_t gradient_zero_flag;
charlesmn	0:0be0bd219e72	6868
charlesmn	0:0be0bd219e72	6869
charlesmn	0:0be0bd219e72	6870	uint8_t new_xtalk_applied_flag;
charlesmn	0:0be0bd219e72	6871
charlesmn	0:0be0bd219e72	6872
charlesmn	0:0be0bd219e72	6873	uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	6874
charlesmn	0:0be0bd219e72	6875
charlesmn	0:0be0bd219e72	6876	int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	6877
charlesmn	0:0be0bd219e72	6878
charlesmn	0:0be0bd219e72	6879	int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	6880
charlesmn	0:0be0bd219e72	6881
charlesmn	0:0be0bd219e72	6882	} VL53LX_smudge_corrector_data_t;
charlesmn	0:0be0bd219e72	6883
charlesmn	0:0be0bd219e72	6884
charlesmn	0:0be0bd219e72	6885
charlesmn	0:0be0bd219e72	6886
charlesmn	0:0be0bd219e72	6887
charlesmn	0:0be0bd219e72	6888	typedef struct {
charlesmn	0:0be0bd219e72	6889
charlesmn	0:0be0bd219e72	6890
charlesmn	0:0be0bd219e72	6891
charlesmn	0:0be0bd219e72	6892	uint8_t range_id;
charlesmn	0:0be0bd219e72	6893
charlesmn	0:0be0bd219e72	6894	uint32_t time_stamp;
charlesmn	0:0be0bd219e72	6895
charlesmn	0:0be0bd219e72	6896	uint8_t VL53LX_p_012;
charlesmn	0:0be0bd219e72	6897
charlesmn	0:0be0bd219e72	6898	uint8_t VL53LX_p_019;
charlesmn	0:0be0bd219e72	6899
charlesmn	0:0be0bd219e72	6900	uint8_t VL53LX_p_023;
charlesmn	0:0be0bd219e72	6901
charlesmn	0:0be0bd219e72	6902	uint8_t VL53LX_p_024;
charlesmn	0:0be0bd219e72	6903
charlesmn	0:0be0bd219e72	6904	uint8_t VL53LX_p_013;
charlesmn	0:0be0bd219e72	6905
charlesmn	0:0be0bd219e72	6906	uint8_t VL53LX_p_025;
charlesmn	0:0be0bd219e72	6907
charlesmn	0:0be0bd219e72	6908
charlesmn	0:0be0bd219e72	6909	uint16_t width;
charlesmn	0:0be0bd219e72	6910
charlesmn	0:0be0bd219e72	6911	uint8_t VL53LX_p_029;
charlesmn	0:0be0bd219e72	6912
charlesmn	0:0be0bd219e72	6913
charlesmn	0:0be0bd219e72	6914	uint16_t fast_osc_frequency;
charlesmn	0:0be0bd219e72	6915
charlesmn	0:0be0bd219e72	6916	uint16_t zero_distance_phase;
charlesmn	0:0be0bd219e72	6917
charlesmn	0:0be0bd219e72	6918	uint16_t VL53LX_p_004;
charlesmn	0:0be0bd219e72	6919
charlesmn	0:0be0bd219e72	6920
charlesmn	0:0be0bd219e72	6921	uint32_t total_periods_elapsed;
charlesmn	0:0be0bd219e72	6922
charlesmn	0:0be0bd219e72	6923
charlesmn	0:0be0bd219e72	6924	uint32_t peak_duration_us;
charlesmn	0:0be0bd219e72	6925
charlesmn	0:0be0bd219e72	6926
charlesmn	0:0be0bd219e72	6927	uint32_t woi_duration_us;
charlesmn	0:0be0bd219e72	6928
charlesmn	0:0be0bd219e72	6929
charlesmn	0:0be0bd219e72	6930
charlesmn	0:0be0bd219e72	6931
charlesmn	0:0be0bd219e72	6932
charlesmn	0:0be0bd219e72	6933	uint32_t VL53LX_p_016;
charlesmn	0:0be0bd219e72	6934
charlesmn	0:0be0bd219e72	6935	uint32_t VL53LX_p_017;
charlesmn	0:0be0bd219e72	6936
charlesmn	0:0be0bd219e72	6937	int32_t VL53LX_p_010;
charlesmn	0:0be0bd219e72	6938
charlesmn	0:0be0bd219e72	6939
charlesmn	0:0be0bd219e72	6940
charlesmn	0:0be0bd219e72	6941
charlesmn	0:0be0bd219e72	6942	uint16_t peak_signal_count_rate_mcps;
charlesmn	0:0be0bd219e72	6943
charlesmn	0:0be0bd219e72	6944	uint16_t avg_signal_count_rate_mcps;
charlesmn	0:0be0bd219e72	6945
charlesmn	0:0be0bd219e72	6946	uint16_t ambient_count_rate_mcps;
charlesmn	0:0be0bd219e72	6947
charlesmn	0:0be0bd219e72	6948	uint16_t total_rate_per_spad_mcps;
charlesmn	0:0be0bd219e72	6949
charlesmn	0:0be0bd219e72	6950	uint32_t VL53LX_p_009;
charlesmn	0:0be0bd219e72	6951
charlesmn	0:0be0bd219e72	6952
charlesmn	0:0be0bd219e72	6953
charlesmn	0:0be0bd219e72	6954
charlesmn	0:0be0bd219e72	6955	uint16_t VL53LX_p_002;
charlesmn	0:0be0bd219e72	6956
charlesmn	0:0be0bd219e72	6957
charlesmn	0:0be0bd219e72	6958
charlesmn	0:0be0bd219e72	6959
charlesmn	0:0be0bd219e72	6960	uint16_t VL53LX_p_026;
charlesmn	0:0be0bd219e72	6961
charlesmn	0:0be0bd219e72	6962	uint16_t VL53LX_p_011;
charlesmn	0:0be0bd219e72	6963
charlesmn	0:0be0bd219e72	6964	uint16_t VL53LX_p_027;
charlesmn	0:0be0bd219e72	6965
charlesmn	0:0be0bd219e72	6966
charlesmn	0:0be0bd219e72	6967
charlesmn	0:0be0bd219e72	6968
charlesmn	0:0be0bd219e72	6969	int16_t min_range_mm;
charlesmn	0:0be0bd219e72	6970
charlesmn	0:0be0bd219e72	6971	int16_t median_range_mm;
charlesmn	0:0be0bd219e72	6972
charlesmn	0:0be0bd219e72	6973	int16_t max_range_mm;
charlesmn	0:0be0bd219e72	6974
charlesmn	0:0be0bd219e72	6975
charlesmn	0:0be0bd219e72	6976
charlesmn	0:0be0bd219e72	6977
charlesmn	0:0be0bd219e72	6978	uint8_t range_status;
charlesmn	0:0be0bd219e72	6979
charlesmn	0:0be0bd219e72	6980	} VL53LX_range_data_t;
charlesmn	0:0be0bd219e72	6981
charlesmn	0:0be0bd219e72	6982
charlesmn	0:0be0bd219e72	6983
charlesmn	0:0be0bd219e72	6984
charlesmn	0:0be0bd219e72	6985	typedef struct {
charlesmn	0:0be0bd219e72	6986
charlesmn	0:0be0bd219e72	6987	VL53LX_DeviceState cfg_device_state;
charlesmn	0:0be0bd219e72	6988
charlesmn	0:0be0bd219e72	6989	VL53LX_DeviceState rd_device_state;
charlesmn	0:0be0bd219e72	6990
charlesmn	0:0be0bd219e72	6991	uint8_t zone_id;
charlesmn	0:0be0bd219e72	6992
charlesmn	0:0be0bd219e72	6993	uint8_t stream_count;
charlesmn	0:0be0bd219e72	6994
charlesmn	0:0be0bd219e72	6995
charlesmn	0:0be0bd219e72	6996	int16_t VL53LX_p_022[VL53LX_MAX_AMBIENT_DMAX_VALUES];
charlesmn	0:0be0bd219e72	6997
charlesmn	0:0be0bd219e72	6998	int16_t wrap_dmax_mm;
charlesmn	0:0be0bd219e72	6999
charlesmn	0:0be0bd219e72	7000
charlesmn	0:0be0bd219e72	7001	uint8_t device_status;
charlesmn	0:0be0bd219e72	7002
charlesmn	0:0be0bd219e72	7003
charlesmn	0:0be0bd219e72	7004	uint8_t max_results;
charlesmn	0:0be0bd219e72	7005
charlesmn	0:0be0bd219e72	7006	uint8_t active_results;
charlesmn	0:0be0bd219e72	7007
charlesmn	0:0be0bd219e72	7008	VL53LX_range_data_t VL53LX_p_003[VL53LX_MAX_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7009
charlesmn	0:0be0bd219e72	7010	VL53LX_range_data_t xmonitor;
charlesmn	0:0be0bd219e72	7011
charlesmn	0:0be0bd219e72	7012	VL53LX_smudge_corrector_data_t smudge_corrector_data;
charlesmn	0:0be0bd219e72	7013
charlesmn	0:0be0bd219e72	7014
charlesmn	0:0be0bd219e72	7015
charlesmn	0:0be0bd219e72	7016	} VL53LX_range_results_t;
charlesmn	0:0be0bd219e72	7017
charlesmn	0:0be0bd219e72	7018
charlesmn	0:0be0bd219e72	7019
charlesmn	0:0be0bd219e72	7020
charlesmn	0:0be0bd219e72	7021	typedef struct {
charlesmn	0:0be0bd219e72	7022
charlesmn	0:0be0bd219e72	7023	uint8_t no_of_samples;
charlesmn	0:0be0bd219e72	7024
charlesmn	0:0be0bd219e72	7025	uint32_t rate_per_spad_kcps_sum;
charlesmn	0:0be0bd219e72	7026
charlesmn	0:0be0bd219e72	7027	uint32_t rate_per_spad_kcps_avg;
charlesmn	0:0be0bd219e72	7028
charlesmn	0:0be0bd219e72	7029	int32_t signal_total_events_sum;
charlesmn	0:0be0bd219e72	7030
charlesmn	0:0be0bd219e72	7031	int32_t signal_total_events_avg;
charlesmn	0:0be0bd219e72	7032
charlesmn	0:0be0bd219e72	7033	uint32_t sigma_mm_sum;
charlesmn	0:0be0bd219e72	7034
charlesmn	0:0be0bd219e72	7035	uint32_t sigma_mm_avg;
charlesmn	0:0be0bd219e72	7036
charlesmn	0:0be0bd219e72	7037	uint32_t median_phase_sum;
charlesmn	0:0be0bd219e72	7038
charlesmn	0:0be0bd219e72	7039	uint32_t median_phase_avg;
charlesmn	0:0be0bd219e72	7040
charlesmn	0:0be0bd219e72	7041
charlesmn	0:0be0bd219e72	7042	} VL53LX_xtalk_range_data_t;
charlesmn	0:0be0bd219e72	7043
charlesmn	0:0be0bd219e72	7044
charlesmn	0:0be0bd219e72	7045
charlesmn	0:0be0bd219e72	7046
charlesmn	0:0be0bd219e72	7047	typedef struct {
charlesmn	0:0be0bd219e72	7048
charlesmn	0:0be0bd219e72	7049	VL53LX_Error cal_status;
charlesmn	0:0be0bd219e72	7050
charlesmn	0:0be0bd219e72	7051	uint8_t num_of_samples_status;
charlesmn	0:0be0bd219e72	7052
charlesmn	0:0be0bd219e72	7053	uint8_t zero_samples_status;
charlesmn	0:0be0bd219e72	7054
charlesmn	0:0be0bd219e72	7055	uint8_t max_sigma_status;
charlesmn	0:0be0bd219e72	7056
charlesmn	0:0be0bd219e72	7057	uint8_t max_results;
charlesmn	0:0be0bd219e72	7058
charlesmn	0:0be0bd219e72	7059	uint8_t active_results;
charlesmn	0:0be0bd219e72	7060
charlesmn	0:0be0bd219e72	7061
charlesmn	0:0be0bd219e72	7062	VL53LX_xtalk_range_data_t
charlesmn	0:0be0bd219e72	7063	VL53LX_p_003[VL53LX_MAX_XTALK_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7064
charlesmn	0:0be0bd219e72	7065	VL53LX_histogram_bin_data_t central_histogram_sum;
charlesmn	0:0be0bd219e72	7066
charlesmn	0:0be0bd219e72	7067	VL53LX_histogram_bin_data_t central_histogram_avg;
charlesmn	0:0be0bd219e72	7068
charlesmn	0:0be0bd219e72	7069	uint8_t central_histogram__window_start;
charlesmn	0:0be0bd219e72	7070
charlesmn	0:0be0bd219e72	7071	uint8_t central_histogram__window_end;
charlesmn	0:0be0bd219e72	7072
charlesmn	0:0be0bd219e72	7073	VL53LX_histogram_bin_data_t
charlesmn	0:0be0bd219e72	7074	histogram_avg_1[VL53LX_MAX_XTALK_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7075
charlesmn	0:0be0bd219e72	7076	VL53LX_histogram_bin_data_t
charlesmn	0:0be0bd219e72	7077	histogram_avg_2[VL53LX_MAX_XTALK_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7078
charlesmn	0:0be0bd219e72	7079	VL53LX_histogram_bin_data_t
charlesmn	0:0be0bd219e72	7080	xtalk_avg[VL53LX_MAX_XTALK_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7081
charlesmn	0:0be0bd219e72	7082
charlesmn	0:0be0bd219e72	7083	} VL53LX_xtalk_range_results_t;
charlesmn	0:0be0bd219e72	7084
charlesmn	0:0be0bd219e72	7085
charlesmn	0:0be0bd219e72	7086
charlesmn	0:0be0bd219e72	7087
charlesmn	0:0be0bd219e72	7088	typedef struct {
charlesmn	0:0be0bd219e72	7089
charlesmn	0:0be0bd219e72	7090	uint8_t preset_mode;
charlesmn	0:0be0bd219e72	7091
charlesmn	0:0be0bd219e72	7092	uint8_t dss_config__roi_mode_control;
charlesmn	0:0be0bd219e72	7093
charlesmn	0:0be0bd219e72	7094	uint16_t dss_config__manual_effective_spads_select;
charlesmn	0:0be0bd219e72	7095
charlesmn	0:0be0bd219e72	7096	uint8_t no_of_samples;
charlesmn	0:0be0bd219e72	7097
charlesmn	0:0be0bd219e72	7098	uint32_t effective_spads;
charlesmn	0:0be0bd219e72	7099
charlesmn	0:0be0bd219e72	7100	uint32_t peak_rate_mcps;
charlesmn	0:0be0bd219e72	7101
charlesmn	0:0be0bd219e72	7102	uint32_t VL53LX_p_002;
charlesmn	0:0be0bd219e72	7103
charlesmn	0:0be0bd219e72	7104	int32_t median_range_mm;
charlesmn	0:0be0bd219e72	7105
charlesmn	0:0be0bd219e72	7106	int32_t range_mm_offset;
charlesmn	0:0be0bd219e72	7107
charlesmn	0:0be0bd219e72	7108
charlesmn	0:0be0bd219e72	7109	} VL53LX_offset_range_data_t;
charlesmn	0:0be0bd219e72	7110
charlesmn	0:0be0bd219e72	7111
charlesmn	0:0be0bd219e72	7112
charlesmn	0:0be0bd219e72	7113
charlesmn	0:0be0bd219e72	7114	typedef struct {
charlesmn	0:0be0bd219e72	7115
charlesmn	0:0be0bd219e72	7116	int16_t cal_distance_mm;
charlesmn	0:0be0bd219e72	7117
charlesmn	0:0be0bd219e72	7118	uint16_t cal_reflectance_pc;
charlesmn	0:0be0bd219e72	7119
charlesmn	0:0be0bd219e72	7120	VL53LX_Error cal_status;
charlesmn	0:0be0bd219e72	7121
charlesmn	0:0be0bd219e72	7122	uint8_t cal_report;
charlesmn	0:0be0bd219e72	7123
charlesmn	0:0be0bd219e72	7124	uint8_t max_results;
charlesmn	0:0be0bd219e72	7125
charlesmn	0:0be0bd219e72	7126	uint8_t active_results;
charlesmn	0:0be0bd219e72	7127
charlesmn	0:0be0bd219e72	7128	VL53LX_offset_range_data_t
charlesmn	0:0be0bd219e72	7129	VL53LX_p_003[VL53LX_MAX_OFFSET_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7130
charlesmn	0:0be0bd219e72	7131
charlesmn	0:0be0bd219e72	7132	} VL53LX_offset_range_results_t;
charlesmn	0:0be0bd219e72	7133
charlesmn	0:0be0bd219e72	7134
charlesmn	0:0be0bd219e72	7135
charlesmn	0:0be0bd219e72	7136
charlesmn	0:0be0bd219e72	7137	typedef struct {
charlesmn	0:0be0bd219e72	7138
charlesmn	0:0be0bd219e72	7139	uint16_t result__mm_inner_actual_effective_spads;
charlesmn	0:0be0bd219e72	7140
charlesmn	0:0be0bd219e72	7141	uint16_t result__mm_outer_actual_effective_spads;
charlesmn	0:0be0bd219e72	7142
charlesmn	0:0be0bd219e72	7143	uint16_t result__mm_inner_peak_signal_count_rtn_mcps;
charlesmn	0:0be0bd219e72	7144
charlesmn	0:0be0bd219e72	7145	uint16_t result__mm_outer_peak_signal_count_rtn_mcps;
charlesmn	0:0be0bd219e72	7146
charlesmn	0:0be0bd219e72	7147
charlesmn	0:0be0bd219e72	7148	} VL53LX_additional_offset_cal_data_t;
charlesmn	0:0be0bd219e72	7149
charlesmn	0:0be0bd219e72	7150
charlesmn	0:0be0bd219e72	7151
charlesmn	0:0be0bd219e72	7152	typedef struct {
charlesmn	0:0be0bd219e72	7153	int16_t short_a_offset_mm;
charlesmn	0:0be0bd219e72	7154	int16_t short_b_offset_mm;
charlesmn	0:0be0bd219e72	7155	int16_t medium_a_offset_mm;
charlesmn	0:0be0bd219e72	7156	int16_t medium_b_offset_mm;
charlesmn	0:0be0bd219e72	7157	int16_t long_a_offset_mm;
charlesmn	0:0be0bd219e72	7158	int16_t long_b_offset_mm;
charlesmn	0:0be0bd219e72	7159	} VL53LX_per_vcsel_period_offset_cal_data_t;
charlesmn	0:0be0bd219e72	7160
charlesmn	0:0be0bd219e72	7161
charlesmn	0:0be0bd219e72	7162
charlesmn	0:0be0bd219e72	7163
charlesmn	0:0be0bd219e72	7164
charlesmn	0:0be0bd219e72	7165	typedef struct {
charlesmn	0:0be0bd219e72	7166
charlesmn	0:0be0bd219e72	7167	uint32_t VL53LX_p_016;
charlesmn	0:0be0bd219e72	7168
charlesmn	0:0be0bd219e72	7169	uint32_t VL53LX_p_017;
charlesmn	0:0be0bd219e72	7170
charlesmn	0:0be0bd219e72	7171	uint16_t VL53LX_p_011;
charlesmn	0:0be0bd219e72	7172
charlesmn	0:0be0bd219e72	7173	uint8_t range_status;
charlesmn	0:0be0bd219e72	7174
charlesmn	0:0be0bd219e72	7175
charlesmn	0:0be0bd219e72	7176	} VL53LX_object_data_t;
charlesmn	0:0be0bd219e72	7177
charlesmn	0:0be0bd219e72	7178
charlesmn	0:0be0bd219e72	7179
charlesmn	0:0be0bd219e72	7180
charlesmn	0:0be0bd219e72	7181	typedef struct {
charlesmn	0:0be0bd219e72	7182
charlesmn	0:0be0bd219e72	7183	VL53LX_DeviceState cfg_device_state;
charlesmn	0:0be0bd219e72	7184
charlesmn	0:0be0bd219e72	7185	VL53LX_DeviceState rd_device_state;
charlesmn	0:0be0bd219e72	7186
charlesmn	0:0be0bd219e72	7187	uint8_t zone_id;
charlesmn	0:0be0bd219e72	7188
charlesmn	0:0be0bd219e72	7189	uint8_t stream_count;
charlesmn	0:0be0bd219e72	7190
charlesmn	0:0be0bd219e72	7191	uint8_t max_objects;
charlesmn	0:0be0bd219e72	7192
charlesmn	0:0be0bd219e72	7193	uint8_t active_objects;
charlesmn	0:0be0bd219e72	7194
charlesmn	0:0be0bd219e72	7195	VL53LX_object_data_t VL53LX_p_003[VL53LX_MAX_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	7196
charlesmn	0:0be0bd219e72	7197
charlesmn	0:0be0bd219e72	7198	VL53LX_object_data_t xmonitor;
charlesmn	0:0be0bd219e72	7199
charlesmn	0:0be0bd219e72	7200
charlesmn	0:0be0bd219e72	7201	} VL53LX_zone_objects_t;
charlesmn	0:0be0bd219e72	7202
charlesmn	0:0be0bd219e72	7203
charlesmn	0:0be0bd219e72	7204
charlesmn	0:0be0bd219e72	7205
charlesmn	0:0be0bd219e72	7206
charlesmn	0:0be0bd219e72	7207
charlesmn	0:0be0bd219e72	7208	typedef struct {
charlesmn	0:0be0bd219e72	7209
charlesmn	0:0be0bd219e72	7210	uint8_t max_zones;
charlesmn	0:0be0bd219e72	7211
charlesmn	0:0be0bd219e72	7212	uint8_t active_zones;
charlesmn	0:0be0bd219e72	7213
charlesmn	0:0be0bd219e72	7214	VL53LX_zone_objects_t VL53LX_p_003[VL53LX_MAX_USER_ZONES];
charlesmn	0:0be0bd219e72	7215
charlesmn	0:0be0bd219e72	7216
charlesmn	0:0be0bd219e72	7217	} VL53LX_zone_results_t;
charlesmn	0:0be0bd219e72	7218
charlesmn	0:0be0bd219e72	7219
charlesmn	0:0be0bd219e72	7220
charlesmn	0:0be0bd219e72	7221
charlesmn	0:0be0bd219e72	7222	typedef struct {
charlesmn	0:0be0bd219e72	7223
charlesmn	0:0be0bd219e72	7224	VL53LX_DeviceState rd_device_state;
charlesmn	0:0be0bd219e72	7225
charlesmn	0:0be0bd219e72	7226
charlesmn	0:0be0bd219e72	7227	uint8_t number_of_ambient_bins;
charlesmn	0:0be0bd219e72	7228
charlesmn	0:0be0bd219e72	7229
charlesmn	0:0be0bd219e72	7230	uint16_t result__dss_actual_effective_spads;
charlesmn	0:0be0bd219e72	7231
charlesmn	0:0be0bd219e72	7232	uint8_t VL53LX_p_005;
charlesmn	0:0be0bd219e72	7233
charlesmn	0:0be0bd219e72	7234	uint32_t total_periods_elapsed;
charlesmn	0:0be0bd219e72	7235
charlesmn	0:0be0bd219e72	7236
charlesmn	0:0be0bd219e72	7237	int32_t ambient_events_sum;
charlesmn	0:0be0bd219e72	7238
charlesmn	0:0be0bd219e72	7239
charlesmn	0:0be0bd219e72	7240	} VL53LX_zone_hist_info_t;
charlesmn	0:0be0bd219e72	7241
charlesmn	0:0be0bd219e72	7242
charlesmn	0:0be0bd219e72	7243
charlesmn	0:0be0bd219e72	7244
charlesmn	0:0be0bd219e72	7245	typedef struct {
charlesmn	0:0be0bd219e72	7246
charlesmn	0:0be0bd219e72	7247	uint8_t max_zones;
charlesmn	0:0be0bd219e72	7248
charlesmn	0:0be0bd219e72	7249	uint8_t active_zones;
charlesmn	0:0be0bd219e72	7250
charlesmn	0:0be0bd219e72	7251	VL53LX_zone_hist_info_t VL53LX_p_003[VL53LX_MAX_USER_ZONES];
charlesmn	0:0be0bd219e72	7252
charlesmn	0:0be0bd219e72	7253
charlesmn	0:0be0bd219e72	7254	} VL53LX_zone_histograms_t;
charlesmn	0:0be0bd219e72	7255
charlesmn	0:0be0bd219e72	7256
charlesmn	0:0be0bd219e72	7257
charlesmn	0:0be0bd219e72	7258
charlesmn	0:0be0bd219e72	7259	typedef struct {
charlesmn	0:0be0bd219e72	7260
charlesmn	0:0be0bd219e72	7261	uint32_t no_of_samples;
charlesmn	0:0be0bd219e72	7262
charlesmn	0:0be0bd219e72	7263	uint32_t effective_spads;
charlesmn	0:0be0bd219e72	7264
charlesmn	0:0be0bd219e72	7265	uint32_t peak_rate_mcps;
charlesmn	0:0be0bd219e72	7266
charlesmn	0:0be0bd219e72	7267	uint32_t VL53LX_p_011;
charlesmn	0:0be0bd219e72	7268
charlesmn	0:0be0bd219e72	7269	uint32_t VL53LX_p_002;
charlesmn	0:0be0bd219e72	7270
charlesmn	0:0be0bd219e72	7271	int32_t median_range_mm;
charlesmn	0:0be0bd219e72	7272
charlesmn	0:0be0bd219e72	7273	int32_t range_mm_offset;
charlesmn	0:0be0bd219e72	7274
charlesmn	0:0be0bd219e72	7275
charlesmn	0:0be0bd219e72	7276	} VL53LX_zone_calibration_data_t;
charlesmn	0:0be0bd219e72	7277
charlesmn	0:0be0bd219e72	7278
charlesmn	0:0be0bd219e72	7279
charlesmn	0:0be0bd219e72	7280
charlesmn	0:0be0bd219e72	7281
charlesmn	0:0be0bd219e72	7282
charlesmn	0:0be0bd219e72	7283	typedef struct {
charlesmn	0:0be0bd219e72	7284
charlesmn	0:0be0bd219e72	7285	uint32_t struct_version;
charlesmn	0:0be0bd219e72	7286
charlesmn	0:0be0bd219e72	7287	VL53LX_DevicePresetModes preset_mode;
charlesmn	0:0be0bd219e72	7288
charlesmn	0:0be0bd219e72	7289	VL53LX_DeviceZonePreset zone_preset;
charlesmn	0:0be0bd219e72	7290
charlesmn	0:0be0bd219e72	7291	int16_t cal_distance_mm;
charlesmn	0:0be0bd219e72	7292
charlesmn	0:0be0bd219e72	7293	uint16_t cal_reflectance_pc;
charlesmn	0:0be0bd219e72	7294
charlesmn	0:0be0bd219e72	7295	uint16_t phasecal_result__reference_phase;
charlesmn	0:0be0bd219e72	7296
charlesmn	0:0be0bd219e72	7297	uint16_t zero_distance_phase;
charlesmn	0:0be0bd219e72	7298
charlesmn	0:0be0bd219e72	7299	VL53LX_Error cal_status;
charlesmn	0:0be0bd219e72	7300
charlesmn	0:0be0bd219e72	7301	uint8_t max_zones;
charlesmn	0:0be0bd219e72	7302
charlesmn	0:0be0bd219e72	7303	uint8_t active_zones;
charlesmn	0:0be0bd219e72	7304
charlesmn	0:0be0bd219e72	7305	VL53LX_zone_calibration_data_t VL53LX_p_003[VL53LX_MAX_USER_ZONES];
charlesmn	0:0be0bd219e72	7306
charlesmn	0:0be0bd219e72	7307
charlesmn	0:0be0bd219e72	7308	} VL53LX_zone_calibration_results_t;
charlesmn	0:0be0bd219e72	7309
charlesmn	0:0be0bd219e72	7310
charlesmn	0:0be0bd219e72	7311
charlesmn	0:0be0bd219e72	7312
charlesmn	0:0be0bd219e72	7313
charlesmn	0:0be0bd219e72	7314	typedef struct {
charlesmn	0:0be0bd219e72	7315
charlesmn	0:0be0bd219e72	7316	int16_t cal_distance_mm;
charlesmn	0:0be0bd219e72	7317
charlesmn	0:0be0bd219e72	7318	uint16_t cal_reflectance_pc;
charlesmn	0:0be0bd219e72	7319
charlesmn	0:0be0bd219e72	7320	uint16_t max_samples;
charlesmn	0:0be0bd219e72	7321
charlesmn	0:0be0bd219e72	7322	uint16_t width;
charlesmn	0:0be0bd219e72	7323
charlesmn	0:0be0bd219e72	7324	uint16_t height;
charlesmn	0:0be0bd219e72	7325
charlesmn	0:0be0bd219e72	7326	uint16_t peak_rate_mcps[VL53LX_NVM_PEAK_RATE_MAP_SAMPLES];
charlesmn	0:0be0bd219e72	7327
charlesmn	0:0be0bd219e72	7328
charlesmn	0:0be0bd219e72	7329	} VL53LX_cal_peak_rate_map_t;
charlesmn	0:0be0bd219e72	7330
charlesmn	0:0be0bd219e72	7331
charlesmn	0:0be0bd219e72	7332
charlesmn	0:0be0bd219e72	7333
charlesmn	0:0be0bd219e72	7334	typedef struct {
charlesmn	0:0be0bd219e72	7335
charlesmn	0:0be0bd219e72	7336	uint8_t expected_stream_count;
charlesmn	0:0be0bd219e72	7337
charlesmn	0:0be0bd219e72	7338	uint8_t expected_gph_id;
charlesmn	0:0be0bd219e72	7339
charlesmn	0:0be0bd219e72	7340	uint8_t dss_mode;
charlesmn	0:0be0bd219e72	7341
charlesmn	0:0be0bd219e72	7342	uint16_t dss_requested_effective_spad_count;
charlesmn	0:0be0bd219e72	7343
charlesmn	0:0be0bd219e72	7344	uint8_t seed_cfg;
charlesmn	0:0be0bd219e72	7345
charlesmn	0:0be0bd219e72	7346	uint8_t initial_phase_seed;
charlesmn	0:0be0bd219e72	7347
charlesmn	0:0be0bd219e72	7348
charlesmn	0:0be0bd219e72	7349	uint8_t roi_config__user_roi_centre_spad;
charlesmn	0:0be0bd219e72	7350
charlesmn	0:0be0bd219e72	7351	uint8_t roi_config__user_roi_requested_global_xy_size;
charlesmn	0:0be0bd219e72	7352
charlesmn	0:0be0bd219e72	7353
charlesmn	0:0be0bd219e72	7354	} VL53LX_zone_private_dyn_cfg_t;
charlesmn	0:0be0bd219e72	7355
charlesmn	0:0be0bd219e72	7356
charlesmn	0:0be0bd219e72	7357
charlesmn	0:0be0bd219e72	7358
charlesmn	0:0be0bd219e72	7359	typedef struct {
charlesmn	0:0be0bd219e72	7360
charlesmn	0:0be0bd219e72	7361	uint8_t max_zones;
charlesmn	0:0be0bd219e72	7362
charlesmn	0:0be0bd219e72	7363	uint8_t active_zones;
charlesmn	0:0be0bd219e72	7364
charlesmn	0:0be0bd219e72	7365	VL53LX_zone_private_dyn_cfg_t VL53LX_p_003[VL53LX_MAX_USER_ZONES];
charlesmn	0:0be0bd219e72	7366
charlesmn	0:0be0bd219e72	7367
charlesmn	0:0be0bd219e72	7368	} VL53LX_zone_private_dyn_cfgs_t;
charlesmn	0:0be0bd219e72	7369
charlesmn	0:0be0bd219e72	7370
charlesmn	0:0be0bd219e72	7371
charlesmn	0:0be0bd219e72	7372	typedef struct {
charlesmn	0:0be0bd219e72	7373
charlesmn	0:0be0bd219e72	7374	uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	7375
charlesmn	0:0be0bd219e72	7376	int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	7377
charlesmn	0:0be0bd219e72	7378	int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	7379
charlesmn	0:0be0bd219e72	7380	uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53LX_BIN_REC_SIZE];
charlesmn	0:0be0bd219e72	7381
charlesmn	0:0be0bd219e72	7382
charlesmn	0:0be0bd219e72	7383	} VL53LX_xtalk_calibration_results_t;
charlesmn	0:0be0bd219e72	7384
charlesmn	0:0be0bd219e72	7385
charlesmn	0:0be0bd219e72	7386
charlesmn	0:0be0bd219e72	7387
charlesmn	0:0be0bd219e72	7388	typedef struct {
charlesmn	0:0be0bd219e72	7389
charlesmn	0:0be0bd219e72	7390
charlesmn	0:0be0bd219e72	7391	uint32_t sample_count;
charlesmn	0:0be0bd219e72	7392
charlesmn	0:0be0bd219e72	7393
charlesmn	0:0be0bd219e72	7394	uint32_t pll_period_mm;
charlesmn	0:0be0bd219e72	7395
charlesmn	0:0be0bd219e72	7396
charlesmn	0:0be0bd219e72	7397	uint32_t peak_duration_us_sum;
charlesmn	0:0be0bd219e72	7398
charlesmn	0:0be0bd219e72	7399
charlesmn	0:0be0bd219e72	7400	uint32_t effective_spad_count_sum;
charlesmn	0:0be0bd219e72	7401
charlesmn	0:0be0bd219e72	7402
charlesmn	0:0be0bd219e72	7403	uint32_t zero_distance_phase_sum;
charlesmn	0:0be0bd219e72	7404
charlesmn	0:0be0bd219e72	7405
charlesmn	0:0be0bd219e72	7406	uint32_t zero_distance_phase_avg;
charlesmn	0:0be0bd219e72	7407
charlesmn	0:0be0bd219e72	7408
charlesmn	0:0be0bd219e72	7409	int32_t event_scaler_sum;
charlesmn	0:0be0bd219e72	7410
charlesmn	0:0be0bd219e72	7411
charlesmn	0:0be0bd219e72	7412	int32_t event_scaler_avg;
charlesmn	0:0be0bd219e72	7413
charlesmn	0:0be0bd219e72	7414
charlesmn	0:0be0bd219e72	7415	int32_t signal_events_sum;
charlesmn	0:0be0bd219e72	7416
charlesmn	0:0be0bd219e72	7417
charlesmn	0:0be0bd219e72	7418	uint32_t xtalk_rate_kcps_per_spad;
charlesmn	0:0be0bd219e72	7419
charlesmn	0:0be0bd219e72	7420
charlesmn	0:0be0bd219e72	7421	int32_t xtalk_start_phase;
charlesmn	0:0be0bd219e72	7422
charlesmn	0:0be0bd219e72	7423
charlesmn	0:0be0bd219e72	7424	int32_t xtalk_end_phase;
charlesmn	0:0be0bd219e72	7425
charlesmn	0:0be0bd219e72	7426
charlesmn	0:0be0bd219e72	7427	int32_t xtalk_width_phase;
charlesmn	0:0be0bd219e72	7428
charlesmn	0:0be0bd219e72	7429
charlesmn	0:0be0bd219e72	7430	int32_t target_start_phase;
charlesmn	0:0be0bd219e72	7431
charlesmn	0:0be0bd219e72	7432
charlesmn	0:0be0bd219e72	7433	int32_t target_end_phase;
charlesmn	0:0be0bd219e72	7434
charlesmn	0:0be0bd219e72	7435
charlesmn	0:0be0bd219e72	7436	int32_t target_width_phase;
charlesmn	0:0be0bd219e72	7437
charlesmn	0:0be0bd219e72	7438
charlesmn	0:0be0bd219e72	7439	int32_t effective_width;
charlesmn	0:0be0bd219e72	7440
charlesmn	0:0be0bd219e72	7441
charlesmn	0:0be0bd219e72	7442	int32_t event_scaler;
charlesmn	0:0be0bd219e72	7443
charlesmn	0:0be0bd219e72	7444
charlesmn	0:0be0bd219e72	7445	uint8_t VL53LX_p_012;
charlesmn	0:0be0bd219e72	7446
charlesmn	0:0be0bd219e72	7447
charlesmn	0:0be0bd219e72	7448	uint8_t VL53LX_p_013;
charlesmn	0:0be0bd219e72	7449
charlesmn	0:0be0bd219e72	7450
charlesmn	0:0be0bd219e72	7451	uint8_t target_start;
charlesmn	0:0be0bd219e72	7452
charlesmn	0:0be0bd219e72	7453
charlesmn	0:0be0bd219e72	7454	int32_t max_shape_value;
charlesmn	0:0be0bd219e72	7455
charlesmn	0:0be0bd219e72	7456
charlesmn	0:0be0bd219e72	7457	int32_t bin_data_sums[VL53LX_XTALK_HISTO_BINS];
charlesmn	0:0be0bd219e72	7458
charlesmn	0:0be0bd219e72	7459	} VL53LX_hist_xtalk_extract_data_t;
charlesmn	0:0be0bd219e72	7460
charlesmn	0:0be0bd219e72	7461
charlesmn	0:0be0bd219e72	7462
charlesmn	0:0be0bd219e72	7463
charlesmn	0:0be0bd219e72	7464	typedef struct {
charlesmn	0:0be0bd219e72	7465
charlesmn	0:0be0bd219e72	7466	uint16_t standard_ranging_gain_factor;
charlesmn	0:0be0bd219e72	7467
charlesmn	0:0be0bd219e72	7468	uint16_t histogram_ranging_gain_factor;
charlesmn	0:0be0bd219e72	7469
charlesmn	0:0be0bd219e72	7470
charlesmn	0:0be0bd219e72	7471	} VL53LX_gain_calibration_data_t;
charlesmn	0:0be0bd219e72	7472
charlesmn	0:0be0bd219e72	7473
charlesmn	0:0be0bd219e72	7474
charlesmn	0:0be0bd219e72	7475
charlesmn	0:0be0bd219e72	7476	typedef struct {
charlesmn	0:0be0bd219e72	7477
charlesmn	0:0be0bd219e72	7478	VL53LX_DeviceState cfg_device_state;
charlesmn	0:0be0bd219e72	7479
charlesmn	0:0be0bd219e72	7480	uint8_t cfg_stream_count;
charlesmn	0:0be0bd219e72	7481
charlesmn	0:0be0bd219e72	7482	uint8_t cfg_internal_stream_count;
charlesmn	0:0be0bd219e72	7483
charlesmn	0:0be0bd219e72	7484	uint8_t cfg_internal_stream_count_val;
charlesmn	0:0be0bd219e72	7485
charlesmn	0:0be0bd219e72	7486	uint8_t cfg_gph_id;
charlesmn	0:0be0bd219e72	7487
charlesmn	0:0be0bd219e72	7488	uint8_t cfg_timing_status;
charlesmn	0:0be0bd219e72	7489
charlesmn	0:0be0bd219e72	7490	uint8_t cfg_zone_id;
charlesmn	0:0be0bd219e72	7491
charlesmn	0:0be0bd219e72	7492
charlesmn	0:0be0bd219e72	7493	VL53LX_DeviceState rd_device_state;
charlesmn	0:0be0bd219e72	7494
charlesmn	0:0be0bd219e72	7495	uint8_t rd_stream_count;
charlesmn	0:0be0bd219e72	7496
charlesmn	0:0be0bd219e72	7497	uint8_t rd_internal_stream_count;
charlesmn	0:0be0bd219e72	7498
charlesmn	0:0be0bd219e72	7499	uint8_t rd_internal_stream_count_val;
charlesmn	0:0be0bd219e72	7500
charlesmn	0:0be0bd219e72	7501	uint8_t rd_gph_id;
charlesmn	0:0be0bd219e72	7502
charlesmn	0:0be0bd219e72	7503	uint8_t rd_timing_status;
charlesmn	0:0be0bd219e72	7504
charlesmn	0:0be0bd219e72	7505	uint8_t rd_zone_id;
charlesmn	0:0be0bd219e72	7506
charlesmn	0:0be0bd219e72	7507
charlesmn	0:0be0bd219e72	7508	} VL53LX_ll_driver_state_t;
charlesmn	0:0be0bd219e72	7509
charlesmn	0:0be0bd219e72	7510
charlesmn	0:0be0bd219e72	7511
charlesmn	0:0be0bd219e72	7512
charlesmn	0:0be0bd219e72	7513	typedef struct {
charlesmn	0:0be0bd219e72	7514
charlesmn	0:0be0bd219e72	7515	uint8_t wait_method;
charlesmn	0:0be0bd219e72	7516
charlesmn	0:0be0bd219e72	7517	VL53LX_DevicePresetModes preset_mode;
charlesmn	0:0be0bd219e72	7518
charlesmn	0:0be0bd219e72	7519	VL53LX_DeviceZonePreset zone_preset;
charlesmn	0:0be0bd219e72	7520
charlesmn	0:0be0bd219e72	7521	VL53LX_DeviceMeasurementModes measurement_mode;
charlesmn	0:0be0bd219e72	7522
charlesmn	0:0be0bd219e72	7523	VL53LX_OffsetCalibrationMode offset_calibration_mode;
charlesmn	0:0be0bd219e72	7524
charlesmn	0:0be0bd219e72	7525	VL53LX_OffsetCorrectionMode offset_correction_mode;
charlesmn	0:0be0bd219e72	7526
charlesmn	0:0be0bd219e72	7527	VL53LX_DeviceDmaxMode dmax_mode;
charlesmn	0:0be0bd219e72	7528
charlesmn	0:0be0bd219e72	7529	uint32_t phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7530
charlesmn	0:0be0bd219e72	7531	uint32_t mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7532
charlesmn	0:0be0bd219e72	7533	uint32_t range_config_timeout_us;
charlesmn	0:0be0bd219e72	7534
charlesmn	0:0be0bd219e72	7535	uint32_t inter_measurement_period_ms;
charlesmn	0:0be0bd219e72	7536
charlesmn	0:0be0bd219e72	7537	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	7538
charlesmn	0:0be0bd219e72	7539	uint32_t fw_ready_poll_duration_ms;
charlesmn	0:0be0bd219e72	7540
charlesmn	0:0be0bd219e72	7541	uint8_t fw_ready;
charlesmn	0:0be0bd219e72	7542
charlesmn	0:0be0bd219e72	7543	uint8_t debug_mode;
charlesmn	0:0be0bd219e72	7544
charlesmn	0:0be0bd219e72	7545
charlesmn	0:0be0bd219e72	7546
charlesmn	0:0be0bd219e72	7547	VL53LX_ll_version_t version;
charlesmn	0:0be0bd219e72	7548
charlesmn	0:0be0bd219e72	7549
charlesmn	0:0be0bd219e72	7550	VL53LX_ll_driver_state_t ll_state;
charlesmn	0:0be0bd219e72	7551
charlesmn	0:0be0bd219e72	7552
charlesmn	0:0be0bd219e72	7553	VL53LX_GPIO_interrupt_config_t gpio_interrupt_config;
charlesmn	0:0be0bd219e72	7554
charlesmn	0:0be0bd219e72	7555
charlesmn	0:0be0bd219e72	7556	VL53LX_customer_nvm_managed_t customer;
charlesmn	0:0be0bd219e72	7557	VL53LX_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn	0:0be0bd219e72	7558	VL53LX_additional_offset_cal_data_t add_off_cal_data;
charlesmn	0:0be0bd219e72	7559	VL53LX_dmax_calibration_data_t fmt_dmax_cal;
charlesmn	0:0be0bd219e72	7560	VL53LX_dmax_calibration_data_t cust_dmax_cal;
charlesmn	0:0be0bd219e72	7561	VL53LX_gain_calibration_data_t gain_cal;
charlesmn	0:0be0bd219e72	7562	VL53LX_user_zone_t mm_roi;
charlesmn	0:0be0bd219e72	7563	VL53LX_optical_centre_t optical_centre;
charlesmn	0:0be0bd219e72	7564	VL53LX_zone_config_t zone_cfg;
charlesmn	0:0be0bd219e72	7565
charlesmn	0:0be0bd219e72	7566
charlesmn	0:0be0bd219e72	7567	VL53LX_tuning_parm_storage_t tuning_parms;
charlesmn	0:0be0bd219e72	7568
charlesmn	0:0be0bd219e72	7569
charlesmn	0:0be0bd219e72	7570	uint8_t rtn_good_spads[VL53LX_RTN_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	7571
charlesmn	0:0be0bd219e72	7572
charlesmn	0:0be0bd219e72	7573	VL53LX_refspadchar_config_t refspadchar;
charlesmn	0:0be0bd219e72	7574	VL53LX_ssc_config_t ssc_cfg;
charlesmn	0:0be0bd219e72	7575	VL53LX_hist_post_process_config_t histpostprocess;
charlesmn	0:0be0bd219e72	7576	VL53LX_hist_gen3_dmax_config_t dmax_cfg;
charlesmn	0:0be0bd219e72	7577	VL53LX_xtalkextract_config_t xtalk_extract_cfg;
charlesmn	0:0be0bd219e72	7578	VL53LX_xtalk_config_t xtalk_cfg;
charlesmn	0:0be0bd219e72	7579	VL53LX_offsetcal_config_t offsetcal_cfg;
charlesmn	0:0be0bd219e72	7580	VL53LX_zonecal_config_t zonecal_cfg;
charlesmn	0:0be0bd219e72	7581
charlesmn	0:0be0bd219e72	7582
charlesmn	0:0be0bd219e72	7583	VL53LX_static_nvm_managed_t stat_nvm;
charlesmn	0:0be0bd219e72	7584	VL53LX_histogram_config_t hist_cfg;
charlesmn	0:0be0bd219e72	7585	VL53LX_static_config_t stat_cfg;
charlesmn	0:0be0bd219e72	7586	VL53LX_general_config_t gen_cfg;
charlesmn	0:0be0bd219e72	7587	VL53LX_timing_config_t tim_cfg;
charlesmn	0:0be0bd219e72	7588	VL53LX_dynamic_config_t dyn_cfg;
charlesmn	0:0be0bd219e72	7589	VL53LX_system_control_t sys_ctrl;
charlesmn	0:0be0bd219e72	7590	VL53LX_system_results_t sys_results;
charlesmn	0:0be0bd219e72	7591	VL53LX_nvm_copy_data_t nvm_copy_data;
charlesmn	0:0be0bd219e72	7592
charlesmn	0:0be0bd219e72	7593
charlesmn	0:0be0bd219e72	7594	VL53LX_histogram_bin_data_t hist_data;
charlesmn	0:0be0bd219e72	7595	VL53LX_histogram_bin_data_t hist_xtalk;
charlesmn	0:0be0bd219e72	7596
charlesmn	0:0be0bd219e72	7597
charlesmn	0:0be0bd219e72	7598	VL53LX_xtalk_histogram_data_t xtalk_shapes;
charlesmn	0:0be0bd219e72	7599	VL53LX_xtalk_range_results_t xtalk_results;
charlesmn	0:0be0bd219e72	7600	VL53LX_xtalk_calibration_results_t xtalk_cal;
charlesmn	0:0be0bd219e72	7601	VL53LX_hist_xtalk_extract_data_t xtalk_extract;
charlesmn	0:0be0bd219e72	7602
charlesmn	0:0be0bd219e72	7603
charlesmn	0:0be0bd219e72	7604	VL53LX_offset_range_results_t offset_results;
charlesmn	0:0be0bd219e72	7605
charlesmn	0:0be0bd219e72	7606
charlesmn	0:0be0bd219e72	7607	VL53LX_core_results_t core_results;
charlesmn	0:0be0bd219e72	7608	VL53LX_debug_results_t dbg_results;
charlesmn	0:0be0bd219e72	7609
charlesmn	0:0be0bd219e72	7610	VL53LX_smudge_corrector_config_t smudge_correct_config;
charlesmn	0:0be0bd219e72	7611
charlesmn	0:0be0bd219e72	7612	VL53LX_smudge_corrector_internals_t smudge_corrector_internals;
charlesmn	0:0be0bd219e72	7613
charlesmn	0:0be0bd219e72	7614
charlesmn	0:0be0bd219e72	7615
charlesmn	0:0be0bd219e72	7616
charlesmn	0:0be0bd219e72	7617	VL53LX_low_power_auto_data_t low_power_auto_data;
charlesmn	0:0be0bd219e72	7618
charlesmn	0:0be0bd219e72	7619	uint8_t wArea1[1536];
charlesmn	0:0be0bd219e72	7620	uint8_t wArea2[512];
charlesmn	0:0be0bd219e72	7621	VL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn	0:0be0bd219e72	7622
charlesmn	0:0be0bd219e72	7623	uint8_t bin_rec_pos;
charlesmn	0:0be0bd219e72	7624
charlesmn	0:0be0bd219e72	7625	uint8_t pos_before_next_recom;
charlesmn	0:0be0bd219e72	7626
charlesmn	0:0be0bd219e72	7627	int32_t multi_bins_rec[VL53LX_BIN_REC_SIZE]
charlesmn	0:0be0bd219e72	7628	[VL53LX_TIMING_CONF_A_B_SIZE][VL53LX_HISTOGRAM_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	7629
charlesmn	0:0be0bd219e72	7630	} VL53LX_LLDriverData_t;
charlesmn	0:0be0bd219e72	7631
charlesmn	0:0be0bd219e72	7632
charlesmn	0:0be0bd219e72	7633
charlesmn	0:0be0bd219e72	7634
charlesmn	0:0be0bd219e72	7635	typedef struct {
charlesmn	0:0be0bd219e72	7636
charlesmn	0:0be0bd219e72	7637
charlesmn	0:0be0bd219e72	7638	VL53LX_range_results_t range_results;
charlesmn	0:0be0bd219e72	7639
charlesmn	0:0be0bd219e72	7640
charlesmn	0:0be0bd219e72	7641	VL53LX_zone_private_dyn_cfgs_t zone_dyn_cfgs;
charlesmn	0:0be0bd219e72	7642
charlesmn	0:0be0bd219e72	7643
charlesmn	0:0be0bd219e72	7644	VL53LX_zone_results_t zone_results;
charlesmn	0:0be0bd219e72	7645	VL53LX_zone_histograms_t zone_hists;
charlesmn	0:0be0bd219e72	7646	VL53LX_zone_calibration_results_t zone_cal;
charlesmn	0:0be0bd219e72	7647
charlesmn	0:0be0bd219e72	7648	} VL53LX_LLDriverResults_t;
charlesmn	0:0be0bd219e72	7649
charlesmn	0:0be0bd219e72	7650
charlesmn	0:0be0bd219e72	7651
charlesmn	0:0be0bd219e72	7652
charlesmn	0:0be0bd219e72	7653	typedef struct {
charlesmn	0:0be0bd219e72	7654
charlesmn	0:0be0bd219e72	7655	uint32_t struct_version;
charlesmn	0:0be0bd219e72	7656	VL53LX_customer_nvm_managed_t customer;
charlesmn	0:0be0bd219e72	7657	VL53LX_dmax_calibration_data_t fmt_dmax_cal;
charlesmn	0:0be0bd219e72	7658	VL53LX_dmax_calibration_data_t cust_dmax_cal;
charlesmn	0:0be0bd219e72	7659	VL53LX_additional_offset_cal_data_t add_off_cal_data;
charlesmn	0:0be0bd219e72	7660	VL53LX_optical_centre_t optical_centre;
charlesmn	0:0be0bd219e72	7661	VL53LX_xtalk_histogram_data_t xtalkhisto;
charlesmn	0:0be0bd219e72	7662	VL53LX_gain_calibration_data_t gain_cal;
charlesmn	0:0be0bd219e72	7663	VL53LX_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn	0:0be0bd219e72	7664	VL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn	0:0be0bd219e72	7665
charlesmn	0:0be0bd219e72	7666	} VL53LX_calibration_data_t;
charlesmn	0:0be0bd219e72	7667
charlesmn	0:0be0bd219e72	7668
charlesmn	0:0be0bd219e72	7669
charlesmn	0:0be0bd219e72	7670
charlesmn	0:0be0bd219e72	7671	typedef struct {
charlesmn	0:0be0bd219e72	7672
charlesmn	0:0be0bd219e72	7673	VL53LX_customer_nvm_managed_t customer;
charlesmn	0:0be0bd219e72	7674	VL53LX_xtalkextract_config_t xtalk_extract_cfg;
charlesmn	0:0be0bd219e72	7675	VL53LX_xtalk_config_t xtalk_cfg;
charlesmn	0:0be0bd219e72	7676	VL53LX_histogram_bin_data_t hist_data;
charlesmn	0:0be0bd219e72	7677	VL53LX_xtalk_histogram_data_t xtalk_shapes;
charlesmn	0:0be0bd219e72	7678	VL53LX_xtalk_range_results_t xtalk_results;
charlesmn	0:0be0bd219e72	7679
charlesmn	0:0be0bd219e72	7680	} VL53LX_xtalk_debug_data_t;
charlesmn	0:0be0bd219e72	7681
charlesmn	0:0be0bd219e72	7682
charlesmn	0:0be0bd219e72	7683
charlesmn	0:0be0bd219e72	7684
charlesmn	0:0be0bd219e72	7685	typedef struct {
charlesmn	0:0be0bd219e72	7686
charlesmn	0:0be0bd219e72	7687	VL53LX_customer_nvm_managed_t customer;
charlesmn	0:0be0bd219e72	7688	VL53LX_dmax_calibration_data_t fmt_dmax_cal;
charlesmn	0:0be0bd219e72	7689	VL53LX_dmax_calibration_data_t cust_dmax_cal;
charlesmn	0:0be0bd219e72	7690	VL53LX_additional_offset_cal_data_t add_off_cal_data;
charlesmn	0:0be0bd219e72	7691	VL53LX_offset_range_results_t offset_results;
charlesmn	0:0be0bd219e72	7692
charlesmn	0:0be0bd219e72	7693	} VL53LX_offset_debug_data_t;
charlesmn	0:0be0bd219e72	7694
charlesmn	0:0be0bd219e72	7695
charlesmn	0:0be0bd219e72	7696
charlesmn	0:0be0bd219e72	7697
charlesmn	0:0be0bd219e72	7698	typedef struct {
charlesmn	0:0be0bd219e72	7699	uint16_t vl53lx_tuningparm_version;
charlesmn	0:0be0bd219e72	7700	uint16_t vl53lx_tuningparm_key_table_version;
charlesmn	0:0be0bd219e72	7701	uint16_t vl53lx_tuningparm_lld_version;
charlesmn	0:0be0bd219e72	7702	uint8_t vl53lx_tuningparm_hist_algo_select;
charlesmn	0:0be0bd219e72	7703	uint8_t vl53lx_tuningparm_hist_target_order;
charlesmn	0:0be0bd219e72	7704	uint8_t vl53lx_tuningparm_hist_filter_woi_0;
charlesmn	0:0be0bd219e72	7705	uint8_t vl53lx_tuningparm_hist_filter_woi_1;
charlesmn	0:0be0bd219e72	7706	uint8_t vl53lx_tuningparm_hist_amb_est_method;
charlesmn	0:0be0bd219e72	7707	uint8_t vl53lx_tuningparm_hist_amb_thresh_sigma_0;
charlesmn	0:0be0bd219e72	7708	uint8_t vl53lx_tuningparm_hist_amb_thresh_sigma_1;
charlesmn	0:0be0bd219e72	7709	int32_t vl53lx_tuningparm_hist_min_amb_thresh_events;
charlesmn	0:0be0bd219e72	7710	uint16_t vl53lx_tuningparm_hist_amb_events_scaler;
charlesmn	0:0be0bd219e72	7711	uint16_t vl53lx_tuningparm_hist_noise_threshold;
charlesmn	0:0be0bd219e72	7712	int32_t vl53lx_tuningparm_hist_signal_total_events_limit;
charlesmn	0:0be0bd219e72	7713	uint8_t vl53lx_tuningparm_hist_sigma_est_ref_mm;
charlesmn	0:0be0bd219e72	7714	uint16_t vl53lx_tuningparm_hist_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	7715	uint16_t vl53lx_tuningparm_hist_gain_factor;
charlesmn	0:0be0bd219e72	7716	uint8_t vl53lx_tuningparm_consistency_hist_phase_tolerance;
charlesmn	0:0be0bd219e72	7717	uint16_t vl53lx_tuningparm_consistency_hist_min_max_tolerance_mm;
charlesmn	0:0be0bd219e72	7718	uint8_t vl53lx_tuningparm_consistency_hist_event_sigma;
charlesmn	0:0be0bd219e72	7719	uint16_t vl53lx_tuningparm_consistency_hist_event_sigma_min_spad_limit;
charlesmn	0:0be0bd219e72	7720	uint8_t vl53lx_tuningparm_initial_phase_rtn_histo_long_range;
charlesmn	0:0be0bd219e72	7721	uint8_t vl53lx_tuningparm_initial_phase_rtn_histo_med_range;
charlesmn	0:0be0bd219e72	7722	uint8_t vl53lx_tuningparm_initial_phase_rtn_histo_short_range;
charlesmn	0:0be0bd219e72	7723	uint8_t vl53lx_tuningparm_initial_phase_ref_histo_long_range;
charlesmn	0:0be0bd219e72	7724	uint8_t vl53lx_tuningparm_initial_phase_ref_histo_med_range;
charlesmn	0:0be0bd219e72	7725	uint8_t vl53lx_tuningparm_initial_phase_ref_histo_short_range;
charlesmn	0:0be0bd219e72	7726	int16_t vl53lx_tuningparm_xtalk_detect_min_valid_range_mm;
charlesmn	0:0be0bd219e72	7727	int16_t vl53lx_tuningparm_xtalk_detect_max_valid_range_mm;
charlesmn	0:0be0bd219e72	7728	uint16_t vl53lx_tuningparm_xtalk_detect_max_sigma_mm;
charlesmn	0:0be0bd219e72	7729	uint16_t vl53lx_tuningparm_xtalk_detect_min_max_tolerance;
charlesmn	0:0be0bd219e72	7730	uint16_t vl53lx_tuningparm_xtalk_detect_max_valid_rate_kcps;
charlesmn	0:0be0bd219e72	7731	uint8_t vl53lx_tuningparm_xtalk_detect_event_sigma;
charlesmn	0:0be0bd219e72	7732	int16_t vl53lx_tuningparm_hist_xtalk_margin_kcps;
charlesmn	0:0be0bd219e72	7733	uint8_t vl53lx_tuningparm_consistency_lite_phase_tolerance;
charlesmn	0:0be0bd219e72	7734	uint8_t vl53lx_tuningparm_phasecal_target;
charlesmn	0:0be0bd219e72	7735	uint16_t vl53lx_tuningparm_lite_cal_repeat_rate;
charlesmn	0:0be0bd219e72	7736	uint16_t vl53lx_tuningparm_lite_ranging_gain_factor;
charlesmn	0:0be0bd219e72	7737	uint8_t vl53lx_tuningparm_lite_min_clip_mm;
charlesmn	0:0be0bd219e72	7738	uint16_t vl53lx_tuningparm_lite_long_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	7739	uint16_t vl53lx_tuningparm_lite_med_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	7740	uint16_t vl53lx_tuningparm_lite_short_sigma_thresh_mm;
charlesmn	0:0be0bd219e72	7741	uint16_t vl53lx_tuningparm_lite_long_min_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	7742	uint16_t vl53lx_tuningparm_lite_med_min_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	7743	uint16_t vl53lx_tuningparm_lite_short_min_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	7744	uint8_t vl53lx_tuningparm_lite_sigma_est_pulse_width;
charlesmn	0:0be0bd219e72	7745	uint8_t vl53lx_tuningparm_lite_sigma_est_amb_width_ns;
charlesmn	0:0be0bd219e72	7746	uint8_t vl53lx_tuningparm_lite_sigma_ref_mm;
charlesmn	0:0be0bd219e72	7747	uint8_t vl53lx_tuningparm_lite_rit_mult;
charlesmn	0:0be0bd219e72	7748	uint8_t vl53lx_tuningparm_lite_seed_config;
charlesmn	0:0be0bd219e72	7749	uint8_t vl53lx_tuningparm_lite_quantifier;
charlesmn	0:0be0bd219e72	7750	uint8_t vl53lx_tuningparm_lite_first_order_select;
charlesmn	0:0be0bd219e72	7751	int16_t vl53lx_tuningparm_lite_xtalk_margin_kcps;
charlesmn	0:0be0bd219e72	7752	uint8_t vl53lx_tuningparm_initial_phase_rtn_lite_long_range;
charlesmn	0:0be0bd219e72	7753	uint8_t vl53lx_tuningparm_initial_phase_rtn_lite_med_range;
charlesmn	0:0be0bd219e72	7754	uint8_t vl53lx_tuningparm_initial_phase_rtn_lite_short_range;
charlesmn	0:0be0bd219e72	7755	uint8_t vl53lx_tuningparm_initial_phase_ref_lite_long_range;
charlesmn	0:0be0bd219e72	7756	uint8_t vl53lx_tuningparm_initial_phase_ref_lite_med_range;
charlesmn	0:0be0bd219e72	7757	uint8_t vl53lx_tuningparm_initial_phase_ref_lite_short_range;
charlesmn	0:0be0bd219e72	7758	uint8_t vl53lx_tuningparm_timed_seed_config;
charlesmn	0:0be0bd219e72	7759	uint8_t vl53lx_tuningparm_dmax_cfg_signal_thresh_sigma;
charlesmn	0:0be0bd219e72	7760	uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_0;
charlesmn	0:0be0bd219e72	7761	uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_1;
charlesmn	0:0be0bd219e72	7762	uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_2;
charlesmn	0:0be0bd219e72	7763	uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_3;
charlesmn	0:0be0bd219e72	7764	uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_4;
charlesmn	0:0be0bd219e72	7765	uint8_t vl53lx_tuningparm_vhv_loopbound;
charlesmn	0:0be0bd219e72	7766	uint8_t vl53lx_tuningparm_refspadchar_device_test_mode;
charlesmn	0:0be0bd219e72	7767	uint8_t vl53lx_tuningparm_refspadchar_vcsel_period;
charlesmn	0:0be0bd219e72	7768	uint32_t vl53lx_tuningparm_refspadchar_phasecal_timeout_us;
charlesmn	0:0be0bd219e72	7769	uint16_t vl53lx_tuningparm_refspadchar_target_count_rate_mcps;
charlesmn	0:0be0bd219e72	7770	uint16_t vl53lx_tuningparm_refspadchar_min_countrate_limit_mcps;
charlesmn	0:0be0bd219e72	7771	uint16_t vl53lx_tuningparm_refspadchar_max_countrate_limit_mcps;
charlesmn	0:0be0bd219e72	7772	uint8_t vl53lx_tuningparm_xtalk_extract_num_of_samples;
charlesmn	0:0be0bd219e72	7773	int16_t vl53lx_tuningparm_xtalk_extract_min_filter_thresh_mm;
charlesmn	0:0be0bd219e72	7774	int16_t vl53lx_tuningparm_xtalk_extract_max_filter_thresh_mm;
charlesmn	0:0be0bd219e72	7775	uint16_t vl53lx_tuningparm_xtalk_extract_dss_rate_mcps;
charlesmn	0:0be0bd219e72	7776	uint32_t vl53lx_tuningparm_xtalk_extract_phasecal_timeout_us;
charlesmn	0:0be0bd219e72	7777	uint16_t vl53lx_tuningparm_xtalk_extract_max_valid_rate_kcps;
charlesmn	0:0be0bd219e72	7778	uint16_t vl53lx_tuningparm_xtalk_extract_sigma_threshold_mm;
charlesmn	0:0be0bd219e72	7779	uint32_t vl53lx_tuningparm_xtalk_extract_dss_timeout_us;
charlesmn	0:0be0bd219e72	7780	uint32_t vl53lx_tuningparm_xtalk_extract_bin_timeout_us;
charlesmn	0:0be0bd219e72	7781	uint16_t vl53lx_tuningparm_offset_cal_dss_rate_mcps;
charlesmn	0:0be0bd219e72	7782	uint32_t vl53lx_tuningparm_offset_cal_phasecal_timeout_us;
charlesmn	0:0be0bd219e72	7783	uint32_t vl53lx_tuningparm_offset_cal_mm_timeout_us;
charlesmn	0:0be0bd219e72	7784	uint32_t vl53lx_tuningparm_offset_cal_range_timeout_us;
charlesmn	0:0be0bd219e72	7785	uint8_t vl53lx_tuningparm_offset_cal_pre_samples;
charlesmn	0:0be0bd219e72	7786	uint8_t vl53lx_tuningparm_offset_cal_mm1_samples;
charlesmn	0:0be0bd219e72	7787	uint8_t vl53lx_tuningparm_offset_cal_mm2_samples;
charlesmn	0:0be0bd219e72	7788	uint16_t vl53lx_tuningparm_zone_cal_dss_rate_mcps;
charlesmn	0:0be0bd219e72	7789	uint32_t vl53lx_tuningparm_zone_cal_phasecal_timeout_us;
charlesmn	0:0be0bd219e72	7790	uint32_t vl53lx_tuningparm_zone_cal_dss_timeout_us;
charlesmn	0:0be0bd219e72	7791	uint16_t vl53lx_tuningparm_zone_cal_phasecal_num_samples;
charlesmn	0:0be0bd219e72	7792	uint32_t vl53lx_tuningparm_zone_cal_range_timeout_us;
charlesmn	0:0be0bd219e72	7793	uint16_t vl53lx_tuningparm_zone_cal_zone_num_samples;
charlesmn	0:0be0bd219e72	7794	uint8_t vl53lx_tuningparm_spadmap_vcsel_period;
charlesmn	0:0be0bd219e72	7795	uint8_t vl53lx_tuningparm_spadmap_vcsel_start;
charlesmn	0:0be0bd219e72	7796	uint16_t vl53lx_tuningparm_spadmap_rate_limit_mcps;
charlesmn	0:0be0bd219e72	7797	uint16_t vl53lx_tuningparm_lite_dss_config_target_total_rate_mcps;
charlesmn	0:0be0bd219e72	7798	uint16_t vl53lx_tuningparm_ranging_dss_config_target_total_rate_mcps;
charlesmn	0:0be0bd219e72	7799	uint16_t vl53lx_tuningparm_mz_dss_config_target_total_rate_mcps;
charlesmn	0:0be0bd219e72	7800	uint16_t vl53lx_tuningparm_timed_dss_config_target_total_rate_mcps;
charlesmn	0:0be0bd219e72	7801	uint32_t vl53lx_tuningparm_lite_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7802	uint32_t vl53lx_tuningparm_ranging_long_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7803	uint32_t vl53lx_tuningparm_ranging_med_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7804	uint32_t vl53lx_tuningparm_ranging_short_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7805	uint32_t vl53lx_tuningparm_mz_long_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7806	uint32_t vl53lx_tuningparm_mz_med_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7807	uint32_t vl53lx_tuningparm_mz_short_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7808	uint32_t vl53lx_tuningparm_timed_phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7809	uint32_t vl53lx_tuningparm_lite_mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7810	uint32_t vl53lx_tuningparm_ranging_mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7811	uint32_t vl53lx_tuningparm_mz_mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7812	uint32_t vl53lx_tuningparm_timed_mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7813	uint32_t vl53lx_tuningparm_lite_range_config_timeout_us;
charlesmn	0:0be0bd219e72	7814	uint32_t vl53lx_tuningparm_ranging_range_config_timeout_us;
charlesmn	0:0be0bd219e72	7815	uint32_t vl53lx_tuningparm_mz_range_config_timeout_us;
charlesmn	0:0be0bd219e72	7816	uint32_t vl53lx_tuningparm_timed_range_config_timeout_us;
charlesmn	0:0be0bd219e72	7817	uint16_t vl53lx_tuningparm_dynxtalk_smudge_margin;
charlesmn	0:0be0bd219e72	7818	uint32_t vl53lx_tuningparm_dynxtalk_noise_margin;
charlesmn	0:0be0bd219e72	7819	uint32_t vl53lx_tuningparm_dynxtalk_xtalk_offset_limit;
charlesmn	0:0be0bd219e72	7820	uint8_t vl53lx_tuningparm_dynxtalk_xtalk_offset_limit_hi;
charlesmn	0:0be0bd219e72	7821	uint32_t vl53lx_tuningparm_dynxtalk_sample_limit;
charlesmn	0:0be0bd219e72	7822	uint32_t vl53lx_tuningparm_dynxtalk_single_xtalk_delta;
charlesmn	0:0be0bd219e72	7823	uint32_t vl53lx_tuningparm_dynxtalk_averaged_xtalk_delta;
charlesmn	0:0be0bd219e72	7824	uint32_t vl53lx_tuningparm_dynxtalk_clip_limit;
charlesmn	0:0be0bd219e72	7825	uint8_t vl53lx_tuningparm_dynxtalk_scaler_calc_method;
charlesmn	0:0be0bd219e72	7826	int16_t vl53lx_tuningparm_dynxtalk_xgradient_scaler;
charlesmn	0:0be0bd219e72	7827	int16_t vl53lx_tuningparm_dynxtalk_ygradient_scaler;
charlesmn	0:0be0bd219e72	7828	uint8_t vl53lx_tuningparm_dynxtalk_user_scaler_set;
charlesmn	0:0be0bd219e72	7829	uint8_t vl53lx_tuningparm_dynxtalk_smudge_cor_single_apply;
charlesmn	0:0be0bd219e72	7830	uint32_t vl53lx_tuningparm_dynxtalk_xtalk_amb_threshold;
charlesmn	0:0be0bd219e72	7831	uint32_t vl53lx_tuningparm_dynxtalk_nodetect_amb_threshold_kcps;
charlesmn	0:0be0bd219e72	7832	uint32_t vl53lx_tuningparm_dynxtalk_nodetect_sample_limit;
charlesmn	0:0be0bd219e72	7833	uint32_t vl53lx_tuningparm_dynxtalk_nodetect_xtalk_offset_kcps;
charlesmn	0:0be0bd219e72	7834	uint16_t vl53lx_tuningparm_dynxtalk_nodetect_min_range_mm;
charlesmn	0:0be0bd219e72	7835	uint8_t vl53lx_tuningparm_lowpowerauto_vhv_loop_bound;
charlesmn	0:0be0bd219e72	7836	uint32_t vl53lx_tuningparm_lowpowerauto_mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7837	uint32_t vl53lx_tuningparm_lowpowerauto_range_config_timeout_us;
charlesmn	0:0be0bd219e72	7838	uint16_t vl53lx_tuningparm_very_short_dss_rate_mcps;
charlesmn	0:0be0bd219e72	7839	uint32_t vl53lx_tuningparm_phasecal_patch_power;
charlesmn	0:0be0bd219e72	7840	} VL53LX_tuning_parameters_t;
charlesmn	0:0be0bd219e72	7841
charlesmn	0:0be0bd219e72	7842
charlesmn	0:0be0bd219e72	7843
charlesmn	0:0be0bd219e72	7844
charlesmn	0:0be0bd219e72	7845
charlesmn	0:0be0bd219e72	7846	typedef struct {
charlesmn	0:0be0bd219e72	7847
charlesmn	0:0be0bd219e72	7848	uint16_t target_reflectance_for_dmax[VL53LX_MAX_AMBIENT_DMAX_VALUES];
charlesmn	0:0be0bd219e72	7849
charlesmn	0:0be0bd219e72	7850	} VL53LX_dmax_reflectance_array_t;
charlesmn	0:0be0bd219e72	7851
charlesmn	0:0be0bd219e72	7852
charlesmn	0:0be0bd219e72	7853
charlesmn	0:0be0bd219e72	7854
charlesmn	0:0be0bd219e72	7855	typedef struct {
charlesmn	0:0be0bd219e72	7856
charlesmn	0:0be0bd219e72	7857	uint8_t spad_type;
charlesmn	0:0be0bd219e72	7858
charlesmn	0:0be0bd219e72	7859	uint16_t VL53LX_p_020;
charlesmn	0:0be0bd219e72	7860
charlesmn	0:0be0bd219e72	7861	uint16_t rate_data[VL53LX_NO_OF_SPAD_ENABLES];
charlesmn	0:0be0bd219e72	7862
charlesmn	0:0be0bd219e72	7863	uint16_t no_of_values;
charlesmn	0:0be0bd219e72	7864
charlesmn	0:0be0bd219e72	7865	uint8_t fractional_bits;
charlesmn	0:0be0bd219e72	7866
charlesmn	0:0be0bd219e72	7867	uint8_t error_status;
charlesmn	0:0be0bd219e72	7868
charlesmn	0:0be0bd219e72	7869
charlesmn	0:0be0bd219e72	7870	} VL53LX_spad_rate_data_t;
charlesmn	0:0be0bd219e72	7871
charlesmn	0:0be0bd219e72	7872
charlesmn	0:0be0bd219e72	7873
charlesmn	0:0be0bd219e72	7874
charlesmn	0:0be0bd219e72	7875
charlesmn	0:0be0bd219e72	7876
charlesmn	0:0be0bd219e72	7877	typedef struct {
charlesmn	0:0be0bd219e72	7878
charlesmn	0:0be0bd219e72	7879	VL53LX_DevicePresetModes preset_mode;
charlesmn	0:0be0bd219e72	7880
charlesmn	0:0be0bd219e72	7881	VL53LX_DeviceZonePreset zone_preset;
charlesmn	0:0be0bd219e72	7882
charlesmn	0:0be0bd219e72	7883	VL53LX_DeviceMeasurementModes measurement_mode;
charlesmn	0:0be0bd219e72	7884
charlesmn	0:0be0bd219e72	7885	VL53LX_OffsetCalibrationMode offset_calibration_mode;
charlesmn	0:0be0bd219e72	7886
charlesmn	0:0be0bd219e72	7887	VL53LX_OffsetCorrectionMode offset_correction_mode;
charlesmn	0:0be0bd219e72	7888
charlesmn	0:0be0bd219e72	7889	VL53LX_DeviceDmaxMode dmax_mode;
charlesmn	0:0be0bd219e72	7890
charlesmn	0:0be0bd219e72	7891
charlesmn	0:0be0bd219e72	7892	uint32_t phasecal_config_timeout_us;
charlesmn	0:0be0bd219e72	7893
charlesmn	0:0be0bd219e72	7894	uint32_t mm_config_timeout_us;
charlesmn	0:0be0bd219e72	7895
charlesmn	0:0be0bd219e72	7896	uint32_t range_config_timeout_us;
charlesmn	0:0be0bd219e72	7897
charlesmn	0:0be0bd219e72	7898	uint32_t inter_measurement_period_ms;
charlesmn	0:0be0bd219e72	7899
charlesmn	0:0be0bd219e72	7900	uint16_t dss_config__target_total_rate_mcps;
charlesmn	0:0be0bd219e72	7901
charlesmn	0:0be0bd219e72	7902
charlesmn	0:0be0bd219e72	7903	VL53LX_histogram_bin_data_t VL53LX_p_006;
charlesmn	0:0be0bd219e72	7904
charlesmn	0:0be0bd219e72	7905
charlesmn	0:0be0bd219e72	7906	} VL53LX_additional_data_t;
charlesmn	0:0be0bd219e72	7907
charlesmn	0:0be0bd219e72	7908
charlesmn	0:0be0bd219e72	7909
charlesmn	0:0be0bd219e72	7910	/* vl53lx_def.h */
charlesmn	0:0be0bd219e72	7911
charlesmn	0:0be0bd219e72	7912
charlesmn	0:0be0bd219e72	7913	/** @defgroup VL53LX_globaldefine_group VL53LX Defines
charlesmn	0:0be0bd219e72	7914	* @brief VL53LX Defines
charlesmn	0:0be0bd219e72	7915	* @{
charlesmn	0:0be0bd219e72	7916	*/
charlesmn	0:0be0bd219e72	7917
charlesmn	0:0be0bd219e72	7918
charlesmn	0:0be0bd219e72	7919	/** VL53LX IMPLEMENTATION major version */
charlesmn	0:0be0bd219e72	7920	#define VL53LX_IMPLEMENTATION_VER_MAJOR 1
charlesmn	0:0be0bd219e72	7921	/** VL53LX IMPLEMENTATION minor version */
charlesmn	0:0be0bd219e72	7922	#define VL53LX_IMPLEMENTATION_VER_MINOR 1
charlesmn	0:0be0bd219e72	7923	/** VL53LX IMPLEMENTATION sub version */
charlesmn	0:0be0bd219e72	7924	#define VL53LX_IMPLEMENTATION_VER_SUB 4
charlesmn	0:0be0bd219e72	7925	/** VL53LX IMPLEMENTATION sub version */
charlesmn	0:0be0bd219e72	7926	#define VL53LX_IMPLEMENTATION_VER_REVISION 2352
charlesmn	0:0be0bd219e72	7927
charlesmn	0:0be0bd219e72	7928	/****************************************
charlesmn	0:0be0bd219e72	7929	* PRIVATE define do not edit
charlesmn	0:0be0bd219e72	7930	****************************************/
charlesmn	0:0be0bd219e72	7931
charlesmn	0:0be0bd219e72	7932	/** @brief Defines the parameters of the Get Version Functions
charlesmn	0:0be0bd219e72	7933	*/
charlesmn	0:0be0bd219e72	7934	typedef struct {
charlesmn	0:0be0bd219e72	7935	uint32_t revision; /!< revision number /
charlesmn	0:0be0bd219e72	7936	uint8_t major; /!< major number /
charlesmn	0:0be0bd219e72	7937	uint8_t minor; /!< minor number /
charlesmn	0:0be0bd219e72	7938	uint8_t build; /!< build number /
charlesmn	0:0be0bd219e72	7939	} VL53LX_Version_t;
charlesmn	0:0be0bd219e72	7940
charlesmn	0:0be0bd219e72	7941
charlesmn	0:0be0bd219e72	7942	/** @brief Defines the parameters of the Get Device Info Functions
charlesmn	0:0be0bd219e72	7943	*/
charlesmn	0:0be0bd219e72	7944	typedef struct {
charlesmn	0:0be0bd219e72	7945	uint8_t ProductType;
charlesmn	0:0be0bd219e72	7946	/*!< Product Type, VL53LX = 0xAA
charlesmn	0:0be0bd219e72	7947	* Stands as module_type in the datasheet
charlesmn	0:0be0bd219e72	7948	*/
charlesmn	0:0be0bd219e72	7949	uint8_t ProductRevisionMajor;
charlesmn	0:0be0bd219e72	7950	/!< Product revision major /
charlesmn	0:0be0bd219e72	7951	uint8_t ProductRevisionMinor;
charlesmn	0:0be0bd219e72	7952	/!< Product revision minor /
charlesmn	0:0be0bd219e72	7953	} VL53LX_DeviceInfo_t;
charlesmn	0:0be0bd219e72	7954
charlesmn	0:0be0bd219e72	7955	/** @defgroup VL53LX_define_DistanceModes_group Defines Distance modes
charlesmn	0:0be0bd219e72	7956	* Defines all possible Distance modes for the device
charlesmn	0:0be0bd219e72	7957	* @{
charlesmn	0:0be0bd219e72	7958	*/
charlesmn	0:0be0bd219e72	7959	typedef uint8_t VL53LX_DistanceModes;
charlesmn	0:0be0bd219e72	7960
charlesmn	0:0be0bd219e72	7961	#define VL53LX_DISTANCEMODE_SHORT ((VL53LX_DistanceModes) 1)
charlesmn	0:0be0bd219e72	7962	#define VL53LX_DISTANCEMODE_MEDIUM ((VL53LX_DistanceModes) 2)
charlesmn	0:0be0bd219e72	7963	#define VL53LX_DISTANCEMODE_LONG ((VL53LX_DistanceModes) 3)
charlesmn	0:0be0bd219e72	7964	/** @} VL53LX_define_DistanceModes_group */
charlesmn	0:0be0bd219e72	7965
charlesmn	0:0be0bd219e72	7966	/** @defgroup VL53LX_define_OffsetCorrectionModes_group Defines Offset Correction modes
charlesmn	0:0be0bd219e72	7967	* Device Offset Correction Mode
charlesmn	0:0be0bd219e72	7968	*
charlesmn	0:0be0bd219e72	7969	* @brief Defines all possible offset correction modes for the device
charlesmn	0:0be0bd219e72	7970	* @{
charlesmn	0:0be0bd219e72	7971	*/
charlesmn	0:0be0bd219e72	7972	typedef uint8_t VL53LX_OffsetCorrectionModes;
charlesmn	0:0be0bd219e72	7973
charlesmn	0:0be0bd219e72	7974	#define VL53LX_OFFSETCORRECTIONMODE_STANDARD ((VL53LX_OffsetCorrectionModes) 1)
charlesmn	0:0be0bd219e72	7975	#define VL53LX_OFFSETCORRECTIONMODE_PERVCSEL ((VL53LX_OffsetCorrectionModes) 3)
charlesmn	0:0be0bd219e72	7976
charlesmn	0:0be0bd219e72	7977	/** @} VL53LX_define_OffsetCorrectionModes_group */
charlesmn	0:0be0bd219e72	7978
charlesmn	0:0be0bd219e72	7979	/** @brief Defines all parameters for the device
charlesmn	0:0be0bd219e72	7980	*/
charlesmn	0:0be0bd219e72	7981	typedef struct {
charlesmn	0:0be0bd219e72	7982	VL53LX_DistanceModes DistanceMode;
charlesmn	0:0be0bd219e72	7983	/!< Defines the operating mode to be used for the next measure /
charlesmn	0:0be0bd219e72	7984	uint32_t MeasurementTimingBudgetMicroSeconds;
charlesmn	0:0be0bd219e72	7985	/!< Defines the allowed total time for a single measurement /
charlesmn	0:0be0bd219e72	7986	} VL53LX_DeviceParameters_t;
charlesmn	0:0be0bd219e72	7987
charlesmn	0:0be0bd219e72	7988
charlesmn	0:0be0bd219e72	7989	/** @defgroup VL53LX_define_Smudge_Mode_group Defines smudge correction modes
charlesmn	0:0be0bd219e72	7990	* Defines the smudge correction modes
charlesmn	0:0be0bd219e72	7991	* @{
charlesmn	0:0be0bd219e72	7992	*/
charlesmn	0:0be0bd219e72	7993
charlesmn	0:0be0bd219e72	7994	typedef uint8_t VL53LX_SmudgeCorrectionModes;
charlesmn	0:0be0bd219e72	7995
charlesmn	0:0be0bd219e72	7996	#define VL53LX_SMUDGE_CORRECTION_NONE ((VL53LX_SmudgeCorrectionModes) 0)
charlesmn	0:0be0bd219e72	7997	/!< Smudge correction is applied continuously across the rangings /
charlesmn	0:0be0bd219e72	7998	#define VL53LX_SMUDGE_CORRECTION_CONTINUOUS ((VL53LX_SmudgeCorrectionModes) 1)
charlesmn	0:0be0bd219e72	7999	/!< Smudge correction is applied continuously across the rangings /
charlesmn	0:0be0bd219e72	8000	#define VL53LX_SMUDGE_CORRECTION_SINGLE ((VL53LX_SmudgeCorrectionModes) 2)
charlesmn	0:0be0bd219e72	8001	/!< Smudge correction is applied only once across the rangings /
charlesmn	0:0be0bd219e72	8002	#define VL53LX_SMUDGE_CORRECTION_DEBUG ((VL53LX_SmudgeCorrectionModes) 3)
charlesmn	0:0be0bd219e72	8003	/*!< Smudge detection is applied continuously but Xtalk values are not
charlesmn	0:0be0bd219e72	8004	* updated automatically within the driver
charlesmn	0:0be0bd219e72	8005	*/
charlesmn	0:0be0bd219e72	8006
charlesmn	0:0be0bd219e72	8007	/** @} VL53LX_define_Smudge_Correction_Mode_group */
charlesmn	0:0be0bd219e72	8008
charlesmn	0:0be0bd219e72	8009	/**
charlesmn	0:0be0bd219e72	8010	* @struct VL53LX_TargetRangeData_t
charlesmn	0:0be0bd219e72	8011	* @brief One Range measurement data for each target.
charlesmn	0:0be0bd219e72	8012	*/
charlesmn	0:0be0bd219e72	8013	typedef struct {
charlesmn	0:0be0bd219e72	8014	int16_t RangeMaxMilliMeter;
charlesmn	0:0be0bd219e72	8015	/*!< Tells what is the maximum detection distance of the object
charlesmn	0:0be0bd219e72	8016	* in current setup and environment conditions (Filled when
charlesmn	0:0be0bd219e72	8017	* applicable)
charlesmn	0:0be0bd219e72	8018	*/
charlesmn	0:0be0bd219e72	8019
charlesmn	0:0be0bd219e72	8020	int16_t RangeMinMilliMeter;
charlesmn	0:0be0bd219e72	8021	/*!< Tells what is the minimum detection distance of the object
charlesmn	0:0be0bd219e72	8022	* in current setup and environment conditions (Filled when
charlesmn	0:0be0bd219e72	8023	* applicable)
charlesmn	0:0be0bd219e72	8024	*/
charlesmn	0:0be0bd219e72	8025
charlesmn	0:0be0bd219e72	8026	FixPoint1616_t SignalRateRtnMegaCps;
charlesmn	0:0be0bd219e72	8027	/*!< Return signal rate (MCPS)\n these is a 16.16 fix point
charlesmn	0:0be0bd219e72	8028	* value, which is effectively a measure of target
charlesmn	0:0be0bd219e72	8029	* reflectance.
charlesmn	0:0be0bd219e72	8030	*/
charlesmn	0:0be0bd219e72	8031
charlesmn	0:0be0bd219e72	8032	FixPoint1616_t AmbientRateRtnMegaCps;
charlesmn	0:0be0bd219e72	8033	/*!< Return ambient rate (MCPS)\n these is a 16.16 fix point
charlesmn	0:0be0bd219e72	8034	* value, which is effectively a measure of the ambien
charlesmn	0:0be0bd219e72	8035	* t light.
charlesmn	0:0be0bd219e72	8036	*/
charlesmn	0:0be0bd219e72	8037
charlesmn	0:0be0bd219e72	8038	FixPoint1616_t SigmaMilliMeter;
charlesmn	0:0be0bd219e72	8039	/!< Return the Sigma value in millimeter /
charlesmn	0:0be0bd219e72	8040
charlesmn	0:0be0bd219e72	8041	int16_t RangeMilliMeter;
charlesmn	0:0be0bd219e72	8042	/*!< range distance in millimeter. This should be between
charlesmn	0:0be0bd219e72	8043	* RangeMinMilliMeter and RangeMaxMilliMeter
charlesmn	0:0be0bd219e72	8044	*/
charlesmn	0:0be0bd219e72	8045
charlesmn	0:0be0bd219e72	8046	uint8_t RangeStatus;
charlesmn	0:0be0bd219e72	8047	/*!< Range Status for the current measurement. This is device
charlesmn	0:0be0bd219e72	8048	* dependent. Value = 0 means value is valid.
charlesmn	0:0be0bd219e72	8049	*/
charlesmn	0:0be0bd219e72	8050	} VL53LX_TargetRangeData_t;
charlesmn	0:0be0bd219e72	8051	/**
charlesmn	0:0be0bd219e72	8052	* @struct VL53LX_MultiRangingData_t
charlesmn	0:0be0bd219e72	8053	* @brief Structure for storing the set of range results
charlesmn	0:0be0bd219e72	8054	*
charlesmn	0:0be0bd219e72	8055	*/
charlesmn	0:0be0bd219e72	8056	typedef struct {
charlesmn	0:0be0bd219e72	8057	uint32_t TimeStamp;
charlesmn	0:0be0bd219e72	8058	/*!< 32-bit time stamp.
charlesmn	0:0be0bd219e72	8059	* @warning Not yet implemented
charlesmn	0:0be0bd219e72	8060	*/
charlesmn	0:0be0bd219e72	8061
charlesmn	0:0be0bd219e72	8062	uint8_t StreamCount;
charlesmn	0:0be0bd219e72	8063	/!< 8-bit Stream Count. /
charlesmn	0:0be0bd219e72	8064
charlesmn	0:0be0bd219e72	8065	uint8_t NumberOfObjectsFound;
charlesmn	0:0be0bd219e72	8066	/*!< Indicate the number of objects found.
charlesmn	0:0be0bd219e72	8067	* This is used to know how many ranging data should be get.
charlesmn	0:0be0bd219e72	8068	* NumberOfObjectsFound is in the range 0 to
charlesmn	0:0be0bd219e72	8069	* VL53LX_MAX_RANGE_RESULTS.
charlesmn	0:0be0bd219e72	8070	*/
charlesmn	0:0be0bd219e72	8071	VL53LX_TargetRangeData_t RangeData[VL53LX_MAX_RANGE_RESULTS];
charlesmn	0:0be0bd219e72	8072	/!< Range data each target distance /
charlesmn	0:0be0bd219e72	8073	uint8_t HasXtalkValueChanged;
charlesmn	0:0be0bd219e72	8074	/*!< set to 1 if a new Xtalk value has been computed whilst
charlesmn	0:0be0bd219e72	8075	* smudge correction mode enable by with
charlesmn	0:0be0bd219e72	8076	* VL53LX_SmudgeCorrectionEnable() function is either
charlesmn	0:0be0bd219e72	8077	* VL53LX_SMUDGE_CORRECTION_CONTINUOUS or
charlesmn	0:0be0bd219e72	8078	* VL53LX_SMUDGE_CORRECTION_SINGLE.
charlesmn	0:0be0bd219e72	8079	*/
charlesmn	0:0be0bd219e72	8080	uint16_t EffectiveSpadRtnCount;
charlesmn	0:0be0bd219e72	8081	/*!< Return the effective SPAD count for the return signal.
charlesmn	0:0be0bd219e72	8082	* To obtain Real value it should be divided by 256
charlesmn	0:0be0bd219e72	8083	*/
charlesmn	0:0be0bd219e72	8084	} VL53LX_MultiRangingData_t;
charlesmn	0:0be0bd219e72	8085
charlesmn	0:0be0bd219e72	8086
charlesmn	0:0be0bd219e72	8087
charlesmn	0:0be0bd219e72	8088	/**
charlesmn	0:0be0bd219e72	8089	* @struct VL53LX_CustomerNvmManaged_t
charlesmn	0:0be0bd219e72	8090	*
charlesmn	0:0be0bd219e72	8091	*/
charlesmn	0:0be0bd219e72	8092
charlesmn	0:0be0bd219e72	8093	typedef struct {
charlesmn	0:0be0bd219e72	8094	uint8_t global_config__spad_enables_ref_0;
charlesmn	0:0be0bd219e72	8095	uint8_t global_config__spad_enables_ref_1;
charlesmn	0:0be0bd219e72	8096	uint8_t global_config__spad_enables_ref_2;
charlesmn	0:0be0bd219e72	8097	uint8_t global_config__spad_enables_ref_3;
charlesmn	0:0be0bd219e72	8098	uint8_t global_config__spad_enables_ref_4;
charlesmn	0:0be0bd219e72	8099	uint8_t global_config__spad_enables_ref_5;
charlesmn	0:0be0bd219e72	8100	uint8_t global_config__ref_en_start_select;
charlesmn	0:0be0bd219e72	8101	uint8_t ref_spad_man__num_requested_ref_spads;
charlesmn	0:0be0bd219e72	8102	uint8_t ref_spad_man__ref_location;
charlesmn	0:0be0bd219e72	8103	uint32_t algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	8104	int16_t algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	8105	int16_t algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	8106	uint16_t ref_spad_char__total_rate_target_mcps;
charlesmn	0:0be0bd219e72	8107	int16_t algo__part_to_part_range_offset_mm;
charlesmn	0:0be0bd219e72	8108	int16_t mm_config__inner_offset_mm;
charlesmn	0:0be0bd219e72	8109	int16_t mm_config__outer_offset_mm;
charlesmn	0:0be0bd219e72	8110	} VL53LX_CustomerNvmManaged_t;
charlesmn	0:0be0bd219e72	8111
charlesmn	0:0be0bd219e72	8112	/**
charlesmn	0:0be0bd219e72	8113	* @struct VL53LX_CalibrationData_t
charlesmn	0:0be0bd219e72	8114	* @brief Structure for storing the Calibration Data
charlesmn	0:0be0bd219e72	8115	*
charlesmn	0:0be0bd219e72	8116	*/
charlesmn	0:0be0bd219e72	8117
charlesmn	0:0be0bd219e72	8118	typedef struct {
charlesmn	0:0be0bd219e72	8119
charlesmn	0:0be0bd219e72	8120	uint32_t struct_version;
charlesmn	0:0be0bd219e72	8121	VL53LX_CustomerNvmManaged_t customer;
charlesmn	0:0be0bd219e72	8122	VL53LX_additional_offset_cal_data_t add_off_cal_data;
charlesmn	0:0be0bd219e72	8123	VL53LX_optical_centre_t optical_centre;
charlesmn	0:0be0bd219e72	8124	VL53LX_xtalk_histogram_data_t xtalkhisto;
charlesmn	0:0be0bd219e72	8125	VL53LX_gain_calibration_data_t gain_cal;
charlesmn	0:0be0bd219e72	8126	VL53LX_cal_peak_rate_map_t cal_peak_rate_map;
charlesmn	0:0be0bd219e72	8127	VL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;
charlesmn	0:0be0bd219e72	8128	uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53LX_BIN_REC_SIZE];
charlesmn	0:0be0bd219e72	8129	} VL53LX_CalibrationData_t;
charlesmn	0:0be0bd219e72	8130
charlesmn	0:0be0bd219e72	8131	#define VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION 0x20
charlesmn	0:0be0bd219e72	8132	/** VL53LX additional Calibration Data struct version final struct version
charlesmn	0:0be0bd219e72	8133	* is given by adding it to VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION
charlesmn	0:0be0bd219e72	8134	*/
charlesmn	0:0be0bd219e72	8135
charlesmn	0:0be0bd219e72	8136	#define VL53LX_CALIBRATION_DATA_STRUCT_VERSION \
charlesmn	0:0be0bd219e72	8137	(VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION + \
charlesmn	0:0be0bd219e72	8138	VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION)
charlesmn	0:0be0bd219e72	8139	/* VL53LX Calibration Data struct version */
charlesmn	0:0be0bd219e72	8140
charlesmn	0:0be0bd219e72	8141	/**
charlesmn	0:0be0bd219e72	8142	* @struct VL53LX_AdditionalData_t
charlesmn	0:0be0bd219e72	8143	* @brief Structure for storing the Additional Data
charlesmn	0:0be0bd219e72	8144	*
charlesmn	0:0be0bd219e72	8145	*/
charlesmn	0:0be0bd219e72	8146	typedef VL53LX_additional_data_t VL53LX_AdditionalData_t;
charlesmn	0:0be0bd219e72	8147
charlesmn	0:0be0bd219e72	8148
charlesmn	0:0be0bd219e72	8149	/** @defgroup VL53LX_define_RangeStatus_group Defines the Range Status
charlesmn	0:0be0bd219e72	8150	* @{
charlesmn	0:0be0bd219e72	8151	*/
charlesmn	0:0be0bd219e72	8152	#define VL53LX_RANGESTATUS_RANGE_VALID 0
charlesmn	0:0be0bd219e72	8153	/!<The Range is valid. /
charlesmn	0:0be0bd219e72	8154	#define VL53LX_RANGESTATUS_SIGMA_FAIL 1
charlesmn	0:0be0bd219e72	8155	/!<Sigma Fail. /
charlesmn	0:0be0bd219e72	8156	#define VL53LX_RANGESTATUS_SIGNAL_FAIL 2
charlesmn	0:0be0bd219e72	8157	/!<Signal fail. /
charlesmn	0:0be0bd219e72	8158	#define VL53LX_RANGESTATUS_RANGE_VALID_MIN_RANGE_CLIPPED 3
charlesmn	0:0be0bd219e72	8159	/!<Target is below minimum detection threshold. /
charlesmn	0:0be0bd219e72	8160	#define VL53LX_RANGESTATUS_OUTOFBOUNDS_FAIL 4
charlesmn	0:0be0bd219e72	8161	/!<Phase out of valid limits - different to a wrap exit. /
charlesmn	0:0be0bd219e72	8162	#define VL53LX_RANGESTATUS_HARDWARE_FAIL 5
charlesmn	0:0be0bd219e72	8163	/!<Hardware fail. /
charlesmn	0:0be0bd219e72	8164	#define VL53LX_RANGESTATUS_RANGE_VALID_NO_WRAP_CHECK_FAIL 6
charlesmn	0:0be0bd219e72	8165	/!<The Range is valid but the wraparound check has not been done. /
charlesmn	0:0be0bd219e72	8166	#define VL53LX_RANGESTATUS_WRAP_TARGET_FAIL 7
charlesmn	0:0be0bd219e72	8167	/!<Wrapped target - no matching phase in other VCSEL period timing. /
charlesmn	0:0be0bd219e72	8168	#define VL53LX_RANGESTATUS_PROCESSING_FAIL 8
charlesmn	0:0be0bd219e72	8169	/!<Internal algo underflow or overflow in lite ranging. /
charlesmn	0:0be0bd219e72	8170	#define VL53LX_RANGESTATUS_XTALK_SIGNAL_FAIL 9
charlesmn	0:0be0bd219e72	8171	/!<Specific to lite ranging. /
charlesmn	0:0be0bd219e72	8172	#define VL53LX_RANGESTATUS_SYNCRONISATION_INT 10
charlesmn	0:0be0bd219e72	8173	/!<1st interrupt when starting ranging in back to back mode. Ignore data. /
charlesmn	0:0be0bd219e72	8174	#define VL53LX_RANGESTATUS_RANGE_VALID_MERGED_PULSE 11
charlesmn	0:0be0bd219e72	8175	/*!<All Range ok but object is result of multiple pulses merging together.
charlesmn	0:0be0bd219e72	8176	* Used by RQL for merged pulse detection
charlesmn	0:0be0bd219e72	8177	*/
charlesmn	0:0be0bd219e72	8178	#define VL53LX_RANGESTATUS_TARGET_PRESENT_LACK_OF_SIGNAL 12
charlesmn	0:0be0bd219e72	8179	/!<Used by RQL as different to phase fail. /
charlesmn	0:0be0bd219e72	8180	#define VL53LX_RANGESTATUS_MIN_RANGE_FAIL 13
charlesmn	0:0be0bd219e72	8181	/!<Unexpected error in SPAD Array./
charlesmn	0:0be0bd219e72	8182	#define VL53LX_RANGESTATUS_RANGE_INVALID 14
charlesmn	0:0be0bd219e72	8183	/!<lld returned valid range but negative value ! /
charlesmn	0:0be0bd219e72	8184	#define VL53LX_RANGESTATUS_NONE 255
charlesmn	0:0be0bd219e72	8185	/!<No Update. /
charlesmn	0:0be0bd219e72	8186
charlesmn	0:0be0bd219e72	8187	/** @} VL53LX_define_RangeStatus_group */
charlesmn	0:0be0bd219e72	8188
charlesmn	0:0be0bd219e72	8189
charlesmn	0:0be0bd219e72	8190	/** @brief Contains the Internal data of the Bare Driver
charlesmn	0:0be0bd219e72	8191	*/
charlesmn	0:0be0bd219e72	8192
charlesmn	0:0be0bd219e72	8193	typedef struct {
charlesmn	0:0be0bd219e72	8194	VL53LX_LLDriverData_t LLData;
charlesmn	0:0be0bd219e72	8195	/!< Low Level Driver data structure /
charlesmn	0:0be0bd219e72	8196
charlesmn	0:0be0bd219e72	8197	VL53LX_LLDriverResults_t llresults;
charlesmn	0:0be0bd219e72	8198	/!< Low Level Driver data structure /
charlesmn	0:0be0bd219e72	8199
charlesmn	0:0be0bd219e72	8200	VL53LX_DeviceParameters_t CurrentParameters;
charlesmn	0:0be0bd219e72	8201	/!< Current Device Parameter /
charlesmn	0:0be0bd219e72	8202
charlesmn	0:0be0bd219e72	8203	} VL53LX_DevData_t;
charlesmn	0:0be0bd219e72	8204
charlesmn	0:0be0bd219e72	8205
charlesmn	0:0be0bd219e72	8206	/* MACRO Definitions */
charlesmn	0:0be0bd219e72	8207	/** @defgroup VL53LX_define_GeneralMacro_group General Macro Defines
charlesmn	0:0be0bd219e72	8208	* General Macro Defines
charlesmn	0:0be0bd219e72	8209	* @{
charlesmn	0:0be0bd219e72	8210	*/
charlesmn	0:0be0bd219e72	8211
charlesmn	0:0be0bd219e72	8212	/* Defines */
charlesmn	0:0be0bd219e72	8213	#define VL53LX_SETPARAMETERFIELD(Dev, field, value) \
charlesmn	0:0be0bd219e72	8214	(VL53LXDevDataSet(Dev, CurrentParameters.field, value))
charlesmn	0:0be0bd219e72	8215
charlesmn	0:0be0bd219e72	8216	#define VL53LX_GETPARAMETERFIELD(Dev, field, variable) \
charlesmn	0:0be0bd219e72	8217	(variable = VL53LXDevDataGet(Dev, CurrentParameters).field)
charlesmn	0:0be0bd219e72	8218
charlesmn	0:0be0bd219e72	8219	#define VL53LX_SETARRAYPARAMETERFIELD(Dev, field, index, value) \
charlesmn	0:0be0bd219e72	8220	(VL53LXDevDataSet(Dev, CurrentParameters.field[index], value))
charlesmn	0:0be0bd219e72	8221
charlesmn	0:0be0bd219e72	8222	#define VL53LX_GETARRAYPARAMETERFIELD(Dev, field, index, variable) \
charlesmn	0:0be0bd219e72	8223	(variable = VL53LXDevDataGet(Dev, CurrentParameters).field[index])
charlesmn	0:0be0bd219e72	8224
charlesmn	0:0be0bd219e72	8225	#define VL53LX_SETDEVICESPECIFICPARAMETER(Dev, field, value) \
charlesmn	0:0be0bd219e72	8226	(VL53LXDevDataSet(Dev, DeviceSpecificParameters.field, value))
charlesmn	0:0be0bd219e72	8227
charlesmn	0:0be0bd219e72	8228	#define VL53LX_GETDEVICESPECIFICPARAMETER(Dev, field) \
charlesmn	0:0be0bd219e72	8229	(VL53LXDevDataGet(Dev, DeviceSpecificParameters).field)
charlesmn	0:0be0bd219e72	8230
charlesmn	0:0be0bd219e72	8231
charlesmn	0:0be0bd219e72	8232	#define VL53LX_FIXPOINT1616TOFIXPOINT44(Value) \
charlesmn	0:0be0bd219e72	8233	(uint16_t)((Value>>12)&0xFFFF)
charlesmn	0:0be0bd219e72	8234	#define VL53LX_FIXPOINT44TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8235	(FixPoint1616_t)((uint32_t)Value<<12)
charlesmn	0:0be0bd219e72	8236
charlesmn	0:0be0bd219e72	8237	#define VL53LX_FIXPOINT1616TOFIXPOINT72(Value) \
charlesmn	0:0be0bd219e72	8238	(uint16_t)((Value>>14)&0xFFFF)
charlesmn	0:0be0bd219e72	8239	#define VL53LX_FIXPOINT72TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8240	(FixPoint1616_t)((uint32_t)Value<<14)
charlesmn	0:0be0bd219e72	8241
charlesmn	0:0be0bd219e72	8242	#define VL53LX_FIXPOINT1616TOFIXPOINT97(Value) \
charlesmn	0:0be0bd219e72	8243	(uint16_t)((Value>>9)&0xFFFF)
charlesmn	0:0be0bd219e72	8244	#define VL53LX_FIXPOINT97TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8245	(FixPoint1616_t)((uint32_t)Value<<9)
charlesmn	0:0be0bd219e72	8246
charlesmn	0:0be0bd219e72	8247	#define VL53LX_FIXPOINT1616TOFIXPOINT88(Value) \
charlesmn	0:0be0bd219e72	8248	(uint16_t)((Value>>8)&0xFFFF)
charlesmn	0:0be0bd219e72	8249	#define VL53LX_FIXPOINT88TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8250	(FixPoint1616_t)((uint32_t)Value<<8)
charlesmn	0:0be0bd219e72	8251
charlesmn	0:0be0bd219e72	8252	#define VL53LX_FIXPOINT1616TOFIXPOINT412(Value) \
charlesmn	0:0be0bd219e72	8253	(uint16_t)((Value>>4)&0xFFFF)
charlesmn	0:0be0bd219e72	8254	#define VL53LX_FIXPOINT412TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8255	(FixPoint1616_t)((uint32_t)Value<<4)
charlesmn	0:0be0bd219e72	8256
charlesmn	0:0be0bd219e72	8257	#define VL53LX_FIXPOINT1616TOFIXPOINT313(Value) \
charlesmn	0:0be0bd219e72	8258	(uint16_t)((Value>>3)&0xFFFF)
charlesmn	0:0be0bd219e72	8259	#define VL53LX_FIXPOINT313TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8260	(FixPoint1616_t)((uint32_t)Value<<3)
charlesmn	0:0be0bd219e72	8261
charlesmn	0:0be0bd219e72	8262	#define VL53LX_FIXPOINT1616TOFIXPOINT08(Value) \
charlesmn	0:0be0bd219e72	8263	(uint8_t)((Value>>8)&0x00FF)
charlesmn	0:0be0bd219e72	8264	#define VL53LX_FIXPOINT08TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8265	(FixPoint1616_t)((uint32_t)Value<<8)
charlesmn	0:0be0bd219e72	8266
charlesmn	0:0be0bd219e72	8267	#define VL53LX_FIXPOINT1616TOFIXPOINT53(Value) \
charlesmn	0:0be0bd219e72	8268	(uint8_t)((Value>>13)&0x00FF)
charlesmn	0:0be0bd219e72	8269	#define VL53LX_FIXPOINT53TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8270	(FixPoint1616_t)((uint32_t)Value<<13)
charlesmn	0:0be0bd219e72	8271
charlesmn	0:0be0bd219e72	8272	#define VL53LX_FIXPOINT1616TOFIXPOINT102(Value) \
charlesmn	0:0be0bd219e72	8273	(uint16_t)((Value>>14)&0x0FFF)
charlesmn	0:0be0bd219e72	8274	#define VL53LX_FIXPOINT102TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8275	(FixPoint1616_t)((uint32_t)Value<<14)
charlesmn	0:0be0bd219e72	8276
charlesmn	0:0be0bd219e72	8277	#define VL53LX_FIXPOINT1616TOFIXPOINT142(Value) \
charlesmn	0:0be0bd219e72	8278	(uint16_t)((Value>>14)&0xFFFF)
charlesmn	0:0be0bd219e72	8279	#define VL53LX_FIXPOINT142TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8280	(FixPoint1616_t)((uint32_t)Value<<14)
charlesmn	0:0be0bd219e72	8281
charlesmn	0:0be0bd219e72	8282	#define VL53LX_FIXPOINT1616TOFIXPOINT160(Value) \
charlesmn	0:0be0bd219e72	8283	(uint16_t)((Value>>16)&0xFFFF)
charlesmn	0:0be0bd219e72	8284	#define VL53LX_FIXPOINT160TOFIXPOINT1616(Value) \
charlesmn	0:0be0bd219e72	8285	(FixPoint1616_t)((uint32_t)Value<<16)
charlesmn	0:0be0bd219e72	8286
charlesmn	0:0be0bd219e72	8287	#define VL53LX_MAKEUINT16(lsb, msb) (uint16_t)((((uint16_t)msb)<<8) + \
charlesmn	0:0be0bd219e72	8288	(uint16_t)lsb)
charlesmn	0:0be0bd219e72	8289
charlesmn	0:0be0bd219e72	8290	#ifndef SUPPRESS_UNUSED_WARNING
charlesmn	0:0be0bd219e72	8291	#define SUPPRESS_UNUSED_WARNING(x) ((void) (x))
charlesmn	0:0be0bd219e72	8292	#endif
charlesmn	0:0be0bd219e72	8293
charlesmn	0:0be0bd219e72	8294	/** @} VL53LX_define_GeneralMacro_group */
charlesmn	0:0be0bd219e72	8295
charlesmn	0:0be0bd219e72	8296	/** @} VL53LX_globaldefine_group */
charlesmn	0:0be0bd219e72	8297
charlesmn	0:0be0bd219e72	8298
charlesmn	0:0be0bd219e72	8299
charlesmn	0:0be0bd219e72	8300
charlesmn	0:0be0bd219e72	8301	/* vl53lx_xtalk_private_structs.h */
charlesmn	0:0be0bd219e72	8302
charlesmn	0:0be0bd219e72	8303
charlesmn	0:0be0bd219e72	8304	#define VL53LX_D_012 4
charlesmn	0:0be0bd219e72	8305
charlesmn	0:0be0bd219e72	8306
charlesmn	0:0be0bd219e72	8307
charlesmn	0:0be0bd219e72	8308
charlesmn	0:0be0bd219e72	8309
charlesmn	0:0be0bd219e72	8310
charlesmn	0:0be0bd219e72	8311
charlesmn	0:0be0bd219e72	8312
charlesmn	0:0be0bd219e72	8313
charlesmn	0:0be0bd219e72	8314	typedef struct {
charlesmn	0:0be0bd219e72	8315
charlesmn	0:0be0bd219e72	8316
charlesmn	0:0be0bd219e72	8317
charlesmn	0:0be0bd219e72	8318
charlesmn	0:0be0bd219e72	8319
charlesmn	0:0be0bd219e72	8320	uint32_t VL53LX_p_061[VL53LX_D_012];
charlesmn	0:0be0bd219e72	8321
charlesmn	0:0be0bd219e72	8322
charlesmn	0:0be0bd219e72	8323
charlesmn	0:0be0bd219e72	8324	int16_t VL53LX_p_059;
charlesmn	0:0be0bd219e72	8325
charlesmn	0:0be0bd219e72	8326
charlesmn	0:0be0bd219e72	8327	int16_t VL53LX_p_060;
charlesmn	0:0be0bd219e72	8328
charlesmn	0:0be0bd219e72	8329
charlesmn	0:0be0bd219e72	8330
charlesmn	0:0be0bd219e72	8331	VL53LX_histogram_bin_data_t VL53LX_p_056;
charlesmn	0:0be0bd219e72	8332
charlesmn	0:0be0bd219e72	8333
charlesmn	0:0be0bd219e72	8334	VL53LX_histogram_bin_data_t VL53LX_p_057;
charlesmn	0:0be0bd219e72	8335
charlesmn	0:0be0bd219e72	8336
charlesmn	0:0be0bd219e72	8337
charlesmn	0:0be0bd219e72	8338
charlesmn	0:0be0bd219e72	8339	uint32_t VL53LX_p_058;
charlesmn	0:0be0bd219e72	8340
charlesmn	0:0be0bd219e72	8341
charlesmn	0:0be0bd219e72	8342
charlesmn	0:0be0bd219e72	8343	uint32_t VL53LX_p_062[VL53LX_XTALK_HISTO_BINS];
charlesmn	0:0be0bd219e72	8344
charlesmn	0:0be0bd219e72	8345
charlesmn	0:0be0bd219e72	8346
charlesmn	0:0be0bd219e72	8347	} VL53LX_xtalk_algo_data_t;
charlesmn	0:0be0bd219e72	8348
charlesmn	0:0be0bd219e72	8349
charlesmn	0:0be0bd219e72	8350	/vl53lx_platform_user_data/
charlesmn	0:0be0bd219e72	8351
charlesmn	0:0be0bd219e72	8352	#include <stdlib.h>
charlesmn	0:0be0bd219e72	8353	//#include "Wire.h"
charlesmn	0:0be0bd219e72	8354	/*
charlesmn	0:0be0bd219e72	8355
charlesmn	0:0be0bd219e72	8356	typedef struct {
charlesmn	0:0be0bd219e72	8357	VL53LX_DevData_t Data;
charlesmn	0:0be0bd219e72	8358	//!< Low Level Driver data structure
charlesmn	0:0be0bd219e72	8359	uint8_t i2c_slave_address;
charlesmn	0:0be0bd219e72	8360	uint8_t comms_type;
charlesmn	0:0be0bd219e72	8361	uint16_t comms_speed_khz;
charlesmn	0:0be0bd219e72	8362	vl53L1X_DevI2C *I2cHandle;
charlesmn	0:0be0bd219e72	8363	uint8_t I2cDevAddr;
charlesmn	0:0be0bd219e72	8364	int Present;
charlesmn	0:0be0bd219e72	8365	int Enabled;
charlesmn	0:0be0bd219e72	8366	int LoopState;
charlesmn	0:0be0bd219e72	8367	int FirstStreamCountZero;
charlesmn	0:0be0bd219e72	8368	int Idle;
charlesmn	0:0be0bd219e72	8369	int Ready;
charlesmn	0:0be0bd219e72	8370	uint8_t RangeStatus;
charlesmn	0:0be0bd219e72	8371	FixPoint1616_t SignalRateRtnMegaCps;
charlesmn	0:0be0bd219e72	8372	VL53LX_DeviceState device_state; //!< Device State
charlesmn	0:0be0bd219e72	8373	} VL53LX_Dev_t;
charlesmn	0:0be0bd219e72	8374
charlesmn	0:0be0bd219e72	8375	typedef VL53LX_Dev_t *VL53LX_DEV;
charlesmn	0:0be0bd219e72	8376	*/
charlesmn	0:0be0bd219e72	8377	/**
charlesmn	0:0be0bd219e72	8378	* @def VL53LXDevDataGet
charlesmn	0:0be0bd219e72	8379	* @brief Get ST private structure @a VL53LX_DevData_t data access
charlesmn	0:0be0bd219e72	8380	*
charlesmn	0:0be0bd219e72	8381	* @param Dev Device Handle
charlesmn	0:0be0bd219e72	8382	* @param field ST structure field name
charlesmn	0:0be0bd219e72	8383	* It maybe used and as real data "ref" not just as "get" for sub-structure item
charlesmn	0:0be0bd219e72	8384	* like VL53L1DevDataGet(FilterData.field)[i] or
charlesmn	0:0be0bd219e72	8385	* VL53L1DevDataGet(FilterData.MeasurementIndex)++
charlesmn	0:0be0bd219e72	8386	*/
charlesmn	0:0be0bd219e72	8387	#define VL53LXDevDataGet(Dev, field) (Dev->Data.field)
charlesmn	0:0be0bd219e72	8388
charlesmn	0:0be0bd219e72	8389	/**
charlesmn	0:0be0bd219e72	8390	* @def VL53LXDevDataSet(Dev, field, data)
charlesmn	0:0be0bd219e72	8391	* @brief Set ST private structure @a VL53LX_DevData_t data field
charlesmn	0:0be0bd219e72	8392	* @param Dev Device Handle
charlesmn	0:0be0bd219e72	8393	* @param field ST structure field name
charlesmn	0:0be0bd219e72	8394	* @param data Data to be set
charlesmn	0:0be0bd219e72	8395	*/
charlesmn	0:0be0bd219e72	8396	#define VL53LXDevDataSet(Dev, field, data) ((Dev->Data.field) = (data))
charlesmn	0:0be0bd219e72	8397
charlesmn	0:0be0bd219e72	8398	#define PALDevDataGet(Dev, field) (Dev->Data.field)
charlesmn	0:0be0bd219e72	8399
charlesmn	0:0be0bd219e72	8400	#define PALDevDataSet(Dev, field, VL53LX_PRM_00005) (Dev->Data.field)=(VL53LX_PRM_00005)
charlesmn	0:0be0bd219e72	8401
charlesmn	0:0be0bd219e72	8402	#define VL53LXDevStructGetLLDriverHandle(Dev) (&Dev -> Data.LLData)
charlesmn	0:0be0bd219e72	8403
charlesmn	0:0be0bd219e72	8404	#define VL53LXDevStructGetLLResultsHandle(Dev) (&Dev -> Data.llresults)
charlesmn	0:0be0bd219e72	8405
charlesmn	0:0be0bd219e72	8406
charlesmn	0:0be0bd219e72	8407	/* vl53lx_hist_map.h */
charlesmn	0:0be0bd219e72	8408
charlesmn	0:0be0bd219e72	8409
charlesmn	0:0be0bd219e72	8410	#define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_0 \
charlesmn	0:0be0bd219e72	8411	VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS
charlesmn	0:0be0bd219e72	8412
charlesmn	0:0be0bd219e72	8413	#define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_1 \
charlesmn	0:0be0bd219e72	8414	VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS
charlesmn	0:0be0bd219e72	8415
charlesmn	0:0be0bd219e72	8416	#define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_2 \
charlesmn	0:0be0bd219e72	8417	VL53LX_SIGMA_ESTIMATOR__SIGMA_REF_MM
charlesmn	0:0be0bd219e72	8418
charlesmn	0:0be0bd219e72	8419	#define VL53LX_HISTOGRAM_CONFIG__AMB_THRESH_HIGH \
charlesmn	0:0be0bd219e72	8420	VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS
charlesmn	0:0be0bd219e72	8421
charlesmn	0:0be0bd219e72	8422
charlesmn	0:0be0bd219e72	8423
charlesmn	0:0be0bd219e72	8424
charlesmn	0:0be0bd219e72	8425	#define VL53LX_RESULT__HISTOGRAM_BIN_0_2 0x008E
charlesmn	0:0be0bd219e72	8426	#define VL53LX_RESULT__HISTOGRAM_BIN_0_1 0x008F
charlesmn	0:0be0bd219e72	8427	#define VL53LX_RESULT__HISTOGRAM_BIN_0_0 0x0090
charlesmn	0:0be0bd219e72	8428
charlesmn	0:0be0bd219e72	8429	#define VL53LX_RESULT__HISTOGRAM_BIN_23_2 0x00D3
charlesmn	0:0be0bd219e72	8430	#define VL53LX_RESULT__HISTOGRAM_BIN_23_1 0x00D4
charlesmn	0:0be0bd219e72	8431	#define VL53LX_RESULT__HISTOGRAM_BIN_23_0 0x00D5
charlesmn	0:0be0bd219e72	8432
charlesmn	0:0be0bd219e72	8433	#define VL53LX_RESULT__HISTOGRAM_BIN_23_0_MSB 0x00D9
charlesmn	0:0be0bd219e72	8434	#define VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB 0x00DA
charlesmn	0:0be0bd219e72	8435
charlesmn	0:0be0bd219e72	8436
charlesmn	0:0be0bd219e72	8437
charlesmn	0:0be0bd219e72	8438	#define VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX \
charlesmn	0:0be0bd219e72	8439	VL53LX_RESULT__INTERRUPT_STATUS
charlesmn	0:0be0bd219e72	8440	#define VL53LX_HISTOGRAM_BIN_DATA_I2C_SIZE_BYTES \
charlesmn	0:0be0bd219e72	8441	(VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB - \
charlesmn	0:0be0bd219e72	8442	VL53LX_RESULT__INTERRUPT_STATUS + 1)
charlesmn	0:0be0bd219e72	8443
charlesmn	0:0be0bd219e72	8444
charlesmn	0:0be0bd219e72	8445	/* vl53lx_nvm_structs.h */
charlesmn	0:0be0bd219e72	8446
charlesmn	0:0be0bd219e72	8447	typedef struct {
charlesmn	0:0be0bd219e72	8448
charlesmn	0:0be0bd219e72	8449	uint16_t result__actual_effective_rtn_spads;
charlesmn	0:0be0bd219e72	8450	uint8_t ref_spad_array__num_requested_ref_spads;
charlesmn	0:0be0bd219e72	8451	uint8_t ref_spad_array__ref_location;
charlesmn	0:0be0bd219e72	8452	uint16_t result__peak_signal_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	8453	uint16_t result__ambient_count_rate_rtn_mcps;
charlesmn	0:0be0bd219e72	8454	uint16_t result__peak_signal_count_rate_ref_mcps;
charlesmn	0:0be0bd219e72	8455	uint16_t result__ambient_count_rate_ref_mcps;
charlesmn	0:0be0bd219e72	8456	uint16_t measured_distance_mm;
charlesmn	0:0be0bd219e72	8457	uint16_t measured_distance_stdev_mm;
charlesmn	0:0be0bd219e72	8458	} VL53LX_decoded_nvm_fmt_range_data_t;
charlesmn	0:0be0bd219e72	8459
charlesmn	0:0be0bd219e72	8460
charlesmn	0:0be0bd219e72	8461	typedef struct {
charlesmn	0:0be0bd219e72	8462
charlesmn	0:0be0bd219e72	8463	char nvm__fmt__fgc[19];
charlesmn	0:0be0bd219e72	8464	uint8_t nvm__fmt__test_program_major;
charlesmn	0:0be0bd219e72	8465	uint8_t nvm__fmt__test_program_minor;
charlesmn	0:0be0bd219e72	8466	uint8_t nvm__fmt__map_major;
charlesmn	0:0be0bd219e72	8467	uint8_t nvm__fmt__map_minor;
charlesmn	0:0be0bd219e72	8468	uint8_t nvm__fmt__year;
charlesmn	0:0be0bd219e72	8469	uint8_t nvm__fmt__month;
charlesmn	0:0be0bd219e72	8470	uint8_t nvm__fmt__day;
charlesmn	0:0be0bd219e72	8471	uint8_t nvm__fmt__module_date_phase;
charlesmn	0:0be0bd219e72	8472	uint16_t nvm__fmt__time;
charlesmn	0:0be0bd219e72	8473	uint8_t nvm__fmt__tester_id;
charlesmn	0:0be0bd219e72	8474	uint8_t nvm__fmt__site_id;
charlesmn	0:0be0bd219e72	8475	uint8_t nvm__ews__test_program_major;
charlesmn	0:0be0bd219e72	8476	uint8_t nvm__ews__test_program_minor;
charlesmn	0:0be0bd219e72	8477	uint8_t nvm__ews__probe_card_major;
charlesmn	0:0be0bd219e72	8478	uint8_t nvm__ews__probe_card_minor;
charlesmn	0:0be0bd219e72	8479	uint8_t nvm__ews__tester_id;
charlesmn	0:0be0bd219e72	8480	char nvm__ews__lot[8];
charlesmn	0:0be0bd219e72	8481	uint8_t nvm__ews__wafer;
charlesmn	0:0be0bd219e72	8482	uint8_t nvm__ews__xcoord;
charlesmn	0:0be0bd219e72	8483	uint8_t nvm__ews__ycoord;
charlesmn	0:0be0bd219e72	8484	} VL53LX_decoded_nvm_fmt_info_t;
charlesmn	0:0be0bd219e72	8485
charlesmn	0:0be0bd219e72	8486
charlesmn	0:0be0bd219e72	8487	typedef struct {
charlesmn	0:0be0bd219e72	8488
charlesmn	0:0be0bd219e72	8489	uint8_t nvm__ews__test_program_major;
charlesmn	0:0be0bd219e72	8490	uint8_t nvm__ews__test_program_minor;
charlesmn	0:0be0bd219e72	8491	uint8_t nvm__ews__probe_card_major;
charlesmn	0:0be0bd219e72	8492	uint8_t nvm__ews__probe_card_minor;
charlesmn	0:0be0bd219e72	8493	uint8_t nvm__ews__tester_id;
charlesmn	0:0be0bd219e72	8494	char nvm__ews__lot[8];
charlesmn	0:0be0bd219e72	8495	uint8_t nvm__ews__wafer;
charlesmn	0:0be0bd219e72	8496	uint8_t nvm__ews__xcoord;
charlesmn	0:0be0bd219e72	8497	uint8_t nvm__ews__ycoord;
charlesmn	0:0be0bd219e72	8498	} VL53LX_decoded_nvm_ews_info_t;
charlesmn	0:0be0bd219e72	8499
charlesmn	0:0be0bd219e72	8500
charlesmn	0:0be0bd219e72	8501	typedef struct {
charlesmn	0:0be0bd219e72	8502	uint8_t nvm__identification_model_id;
charlesmn	0:0be0bd219e72	8503	uint8_t nvm__identification_module_type;
charlesmn	0:0be0bd219e72	8504	uint8_t nvm__identification_revision_id;
charlesmn	0:0be0bd219e72	8505	uint16_t nvm__identification_module_id;
charlesmn	0:0be0bd219e72	8506	uint8_t nvm__i2c_valid;
charlesmn	0:0be0bd219e72	8507	uint8_t nvm__i2c_device_address_ews;
charlesmn	0:0be0bd219e72	8508	uint16_t nvm__ews__fast_osc_frequency;
charlesmn	0:0be0bd219e72	8509	uint8_t nvm__ews__fast_osc_trim_max;
charlesmn	0:0be0bd219e72	8510	uint8_t nvm__ews__fast_osc_freq_set;
charlesmn	0:0be0bd219e72	8511	uint16_t nvm__ews__slow_osc_calibration;
charlesmn	0:0be0bd219e72	8512	uint16_t nvm__fmt__fast_osc_frequency;
charlesmn	0:0be0bd219e72	8513	uint8_t nvm__fmt__fast_osc_trim_max;
charlesmn	0:0be0bd219e72	8514	uint8_t nvm__fmt__fast_osc_freq_set;
charlesmn	0:0be0bd219e72	8515	uint16_t nvm__fmt__slow_osc_calibration;
charlesmn	0:0be0bd219e72	8516	uint8_t nvm__vhv_config_unlock;
charlesmn	0:0be0bd219e72	8517	uint8_t nvm__ref_selvddpix;
charlesmn	0:0be0bd219e72	8518	uint8_t nvm__ref_selvquench;
charlesmn	0:0be0bd219e72	8519	uint8_t nvm__regavdd1v2_sel;
charlesmn	0:0be0bd219e72	8520	uint8_t nvm__regdvdd1v2_sel;
charlesmn	0:0be0bd219e72	8521	uint8_t nvm__vhv_timeout__macrop;
charlesmn	0:0be0bd219e72	8522	uint8_t nvm__vhv_loop_bound;
charlesmn	0:0be0bd219e72	8523	uint8_t nvm__vhv_count_threshold;
charlesmn	0:0be0bd219e72	8524	uint8_t nvm__vhv_offset;
charlesmn	0:0be0bd219e72	8525	uint8_t nvm__vhv_init_enable;
charlesmn	0:0be0bd219e72	8526	uint8_t nvm__vhv_init_value;
charlesmn	0:0be0bd219e72	8527	uint8_t nvm__laser_safety_vcsel_trim_ll;
charlesmn	0:0be0bd219e72	8528	uint8_t nvm__laser_safety_vcsel_selion_ll;
charlesmn	0:0be0bd219e72	8529	uint8_t nvm__laser_safety_vcsel_selion_max_ll;
charlesmn	0:0be0bd219e72	8530	uint8_t nvm__laser_safety_mult_ll;
charlesmn	0:0be0bd219e72	8531	uint8_t nvm__laser_safety_clip_ll;
charlesmn	0:0be0bd219e72	8532	uint8_t nvm__laser_safety_vcsel_trim_ld;
charlesmn	0:0be0bd219e72	8533	uint8_t nvm__laser_safety_vcsel_selion_ld;
charlesmn	0:0be0bd219e72	8534	uint8_t nvm__laser_safety_vcsel_selion_max_ld;
charlesmn	0:0be0bd219e72	8535	uint8_t nvm__laser_safety_mult_ld;
charlesmn	0:0be0bd219e72	8536	uint8_t nvm__laser_safety_clip_ld;
charlesmn	0:0be0bd219e72	8537	uint8_t nvm__laser_safety_lock_byte;
charlesmn	0:0be0bd219e72	8538	uint8_t nvm__laser_safety_unlock_byte;
charlesmn	0:0be0bd219e72	8539	uint8_t nvm__ews__spad_enables_rtn[VL53LX_RTN_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8540	uint8_t nvm__ews__spad_enables_ref__loc1[VL53LX_REF_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8541	uint8_t nvm__ews__spad_enables_ref__loc2[VL53LX_REF_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8542	uint8_t nvm__ews__spad_enables_ref__loc3[VL53LX_REF_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8543	uint8_t nvm__fmt__spad_enables_rtn[VL53LX_RTN_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8544	uint8_t nvm__fmt__spad_enables_ref__loc1[VL53LX_REF_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8545	uint8_t nvm__fmt__spad_enables_ref__loc2[VL53LX_REF_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8546	uint8_t nvm__fmt__spad_enables_ref__loc3[VL53LX_REF_SPAD_BUFFER_SIZE];
charlesmn	0:0be0bd219e72	8547	uint8_t nvm__fmt__roi_config__mode_roi_centre_spad;
charlesmn	0:0be0bd219e72	8548	uint8_t nvm__fmt__roi_config__mode_roi_x_size;
charlesmn	0:0be0bd219e72	8549	uint8_t nvm__fmt__roi_config__mode_roi_y_size;
charlesmn	0:0be0bd219e72	8550	uint8_t nvm__fmt__ref_spad_apply__num_requested_ref_spad;
charlesmn	0:0be0bd219e72	8551	uint8_t nvm__fmt__ref_spad_man__ref_location;
charlesmn	0:0be0bd219e72	8552	uint16_t nvm__fmt__mm_config__inner_offset_mm;
charlesmn	0:0be0bd219e72	8553	uint16_t nvm__fmt__mm_config__outer_offset_mm;
charlesmn	0:0be0bd219e72	8554	uint16_t nvm__fmt__algo_part_to_part_range_offset_mm;
charlesmn	0:0be0bd219e72	8555	uint16_t nvm__fmt__algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	8556	uint16_t nvm__fmt__algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	8557	uint16_t nvm__fmt__algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	8558	uint8_t nvm__fmt__spare__host_config__nvm_config_spare_0;
charlesmn	0:0be0bd219e72	8559	uint8_t nvm__fmt__spare__host_config__nvm_config_spare_1;
charlesmn	0:0be0bd219e72	8560	uint8_t nvm__customer_space_programmed;
charlesmn	0:0be0bd219e72	8561	uint8_t nvm__cust__i2c_device_address;
charlesmn	0:0be0bd219e72	8562	uint8_t nvm__cust__ref_spad_apply__num_requested_ref_spad;
charlesmn	0:0be0bd219e72	8563	uint8_t nvm__cust__ref_spad_man__ref_location;
charlesmn	0:0be0bd219e72	8564	uint16_t nvm__cust__mm_config__inner_offset_mm;
charlesmn	0:0be0bd219e72	8565	uint16_t nvm__cust__mm_config__outer_offset_mm;
charlesmn	0:0be0bd219e72	8566	uint16_t nvm__cust__algo_part_to_part_range_offset_mm;
charlesmn	0:0be0bd219e72	8567	uint16_t nvm__cust__algo__crosstalk_compensation_plane_offset_kcps;
charlesmn	0:0be0bd219e72	8568	uint16_t nvm__cust__algo__crosstalk_compensation_x_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	8569	uint16_t nvm__cust__algo__crosstalk_compensation_y_plane_gradient_kcps;
charlesmn	0:0be0bd219e72	8570	uint8_t nvm__cust__spare__host_config__nvm_config_spare_0;
charlesmn	0:0be0bd219e72	8571	uint8_t nvm__cust__spare__host_config__nvm_config_spare_1;
charlesmn	0:0be0bd219e72	8572	VL53LX_optical_centre_t fmt_optical_centre;
charlesmn	0:0be0bd219e72	8573	VL53LX_cal_peak_rate_map_t fmt_peak_rate_map;
charlesmn	0:0be0bd219e72	8574	VL53LX_additional_offset_cal_data_t fmt_add_offset_data;
charlesmn	0:0be0bd219e72	8575
charlesmn	0:0be0bd219e72	8576	VL53LX_decoded_nvm_fmt_range_data_t
charlesmn	0:0be0bd219e72	8577	fmt_range_data[VL53LX_NVM_MAX_FMT_RANGE_DATA];
charlesmn	0:0be0bd219e72	8578
charlesmn	0:0be0bd219e72	8579	VL53LX_decoded_nvm_fmt_info_t fmt_info;
charlesmn	0:0be0bd219e72	8580	VL53LX_decoded_nvm_ews_info_t ews_info;
charlesmn	0:0be0bd219e72	8581
charlesmn	0:0be0bd219e72	8582	} VL53LX_decoded_nvm_data_t;
charlesmn	0:0be0bd219e72	8583
charlesmn	0:0be0bd219e72	8584
charlesmn	0:0be0bd219e72	8585
charlesmn	0:0be0bd219e72	8586	#ifdef __cplusplus
charlesmn	0:0be0bd219e72	8587	}
charlesmn	0:0be0bd219e72	8588	#endif
charlesmn	0:0be0bd219e72	8589
charlesmn	0:0be0bd219e72	8590	#endif /* _VL53LX_DEF_H_ */

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	03 Nov 2020
Imports:	1
Forks:	0
Commits:	4
Dependents:	1
Dependencies:	2
Followers:	2

Developers

John Alexander

charles macneill

vl53lx_def.h@3:316175f392f7, 2020-11-03 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Developers

Important Information for this Arm website

Access Warning