Joaquin Verastegui / jro

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Dependents:   JRO_CR2 frdm_test

Fork of jro by Miguel Urco

JroDDS.h@3:f0e6c145b075, 2015-02-05 (annotated)

Committer:
miguelcordero191
Date:
Thu Feb 05 21:31:37 2015 +0000
Revision:
3:f0e6c145b075
Parent:
2:3d8d52e9751c
Child:
4:de495ce256b8
jroEthernet and jroSerial modules were deleted

Who changed what in which revision?

UserRevisionLine numberNew contents of line
miguelcordero191 2:3d8d52e9751c 1 #include "mbed.h"
miguelcordero191 2:3d8d52e9751c 2 #include "SerialDriver.h"
miguelcordero191 2:3d8d52e9751c 3
miguelcordero191 2:3d8d52e9751c 4 #define SPI_BITS 8
miguelcordero191 2:3d8d52e9751c 5 #define SPI_MODE 0
miguelcordero191 2:3d8d52e9751c 6 #define SPI_FREQ 10000
miguelcordero191 2:3d8d52e9751c 7
miguelcordero191 3:f0e6c145b075 8 #define DDS_CMD_RESET 0X10
miguelcordero191 3:f0e6c145b075 9 #define DDS_CMD_ENABLE_RF 0x11
miguelcordero191 3:f0e6c145b075 10 #define DDS_CMD_MULTIPLIER 0X12
miguelcordero191 3:f0e6c145b075 11 #define DDS_CMD_MODE 0x13
miguelcordero191 3:f0e6c145b075 12 #define DDS_CMD_FREQUENCY1 0X14
miguelcordero191 3:f0e6c145b075 13 #define DDS_CMD_FREQUENCY2 0x15
miguelcordero191 3:f0e6c145b075 14 #define DDS_CMD_PHASE1 0X16
miguelcordero191 3:f0e6c145b075 15 #define DDS_CMD_PHASE2 0x17
miguelcordero191 3:f0e6c145b075 16 #define DDS_CMD_AMPLITUDEI 0X18
miguelcordero191 3:f0e6c145b075 17 #define DDS_CMD_AMPLITUDEQ 0x19
miguelcordero191 3:f0e6c145b075 18 #define DDS_CMD_READ 0x8000
miguelcordero191 2:3d8d52e9751c 19
miguelcordero191 2:3d8d52e9751c 20 class DDS{
miguelcordero191 2:3d8d52e9751c 21 private:
miguelcordero191 2:3d8d52e9751c 22 float frequency; // Work frequency in MHz
miguelcordero191 2:3d8d52e9751c 23 char cr_multiplier; // Multiplier 4- 20
miguelcordero191 2:3d8d52e9751c 24 char cr_mode; // Single, FSK, Ramped FSK, Chirp, BPSK
miguelcordero191 2:3d8d52e9751c 25 bool cr_qdac_pwdn; // Q DAC power down enable: 0 -> disable
miguelcordero191 2:3d8d52e9751c 26 bool cr_ioupdclk; // IO Update clock enable: 0 -> input
miguelcordero191 2:3d8d52e9751c 27 bool cr_inv_sinc; // Inverse sinc filter enable: 0 -> enable
miguelcordero191 2:3d8d52e9751c 28 bool cr_osk_en; // Enable AM: 0 -> disabled
miguelcordero191 2:3d8d52e9751c 29 bool cr_osk_int; // ext/int output shaped control: 0 -> external
miguelcordero191 2:3d8d52e9751c 30 bool cr_msb_lsb; // msb/lsb bit first: 0 -> MSB
miguelcordero191 2:3d8d52e9751c 31 bool cr_sdo; // SDO pin active: 0 -> inactive
miguelcordero191 2:3d8d52e9751c 32
miguelcordero191 2:3d8d52e9751c 33 SPI *spi_device;
miguelcordero191 2:3d8d52e9751c 34 //DDS I/O
miguelcordero191 2:3d8d52e9751c 35 DigitalOut *dds_mreset;
miguelcordero191 2:3d8d52e9751c 36 DigitalOut *dds_outramp;
miguelcordero191 2:3d8d52e9751c 37 DigitalOut *dds_sp_mode;
miguelcordero191 2:3d8d52e9751c 38 DigitalOut *dds_cs;
miguelcordero191 2:3d8d52e9751c 39 DigitalOut *dds_io_reset;
miguelcordero191 2:3d8d52e9751c 40 DigitalInOut *dds_updclk;
miguelcordero191 2:3d8d52e9751c 41
miguelcordero191 2:3d8d52e9751c 42 char frequency1[6];
miguelcordero191 2:3d8d52e9751c 43 char frequency2[6];
miguelcordero191 2:3d8d52e9751c 44 char phase1[2];
miguelcordero191 2:3d8d52e9751c 45 char phase2[2];
miguelcordero191 2:3d8d52e9751c 46 char amplitudeI[2];
miguelcordero191 2:3d8d52e9751c 47 char amplitudeQ[2];
miguelcordero191 2:3d8d52e9751c 48 bool rf_enabled;
miguelcordero191 2:3d8d52e9751c 49
miguelcordero191 2:3d8d52e9751c 50 char* cmd_answer;
miguelcordero191 2:3d8d52e9751c 51 unsigned long cmd_answer_len;
miguelcordero191 2:3d8d52e9751c 52
miguelcordero191 2:3d8d52e9751c 53 int __writeData(char addr, char ndata, const char* data);
miguelcordero191 2:3d8d52e9751c 54 char* __readData(char addr, char ndata);
miguelcordero191 2:3d8d52e9751c 55 int __writeDataAndVerify(char addr, char ndata, const char* wr_spi_data, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 56 char* __getControlRegister();
miguelcordero191 2:3d8d52e9751c 57 int __writeControlRegister();
miguelcordero191 2:3d8d52e9751c 58
miguelcordero191 2:3d8d52e9751c 59 public:
miguelcordero191 2:3d8d52e9751c 60 bool isConfig;
miguelcordero191 2:3d8d52e9751c 61
miguelcordero191 2:3d8d52e9751c 62 DDS(SPI *spi_dev, DigitalOut *mreset, DigitalOut *outramp, DigitalOut *spmode, DigitalOut *cs, DigitalOut *ioreset, DigitalInOut *updclk);
miguelcordero191 2:3d8d52e9751c 63 int init();
miguelcordero191 2:3d8d52e9751c 64 int reset();
miguelcordero191 2:3d8d52e9751c 65 int scanIOUpdate();
miguelcordero191 2:3d8d52e9751c 66 int find();
miguelcordero191 2:3d8d52e9751c 67 char* rdMode();
miguelcordero191 2:3d8d52e9751c 68 char* rdMultiplier();
miguelcordero191 2:3d8d52e9751c 69 char* rdPhase1();
miguelcordero191 2:3d8d52e9751c 70 char* rdPhase2();
miguelcordero191 2:3d8d52e9751c 71 char* rdFrequency1();
miguelcordero191 2:3d8d52e9751c 72 char* rdFrequency2();
miguelcordero191 2:3d8d52e9751c 73 char* rdAmplitudeI();
miguelcordero191 2:3d8d52e9751c 74 char* rdAmplitudeQ();
miguelcordero191 2:3d8d52e9751c 75 int wrMode(char mode);
miguelcordero191 2:3d8d52e9751c 76 int wrMultiplier(char multiplier, float clock);
miguelcordero191 2:3d8d52e9751c 77 int wrPhase1(char* phase, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 78 int wrPhase2(char* phase, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 79 int wrFrequency1(char* freq, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 80 int wrFrequency2(char* freq, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 81 int wrAmplitudeI(char* amplitude, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 82 int wrAmplitudeQ(char* amplitude, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 83 int enableRF();
miguelcordero191 2:3d8d52e9751c 84 int disableRF();
miguelcordero191 2:3d8d52e9751c 85 int defaultSettings(SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 86 char* setCommand(unsigned short cmd, char* payload, unsigned long payload_len);
miguelcordero191 2:3d8d52e9751c 87 char* getCmdAnswer();
miguelcordero191 2:3d8d52e9751c 88 unsigned long getCmdAnswerLen();
miguelcordero191 2:3d8d52e9751c 89 int setAllDevice(char* payload, SerialDriver *screen=NULL);
miguelcordero191 2:3d8d52e9751c 90
miguelcordero191 2:3d8d52e9751c 91 };