Joaquin Verastegui / CR2

Library for the JRO Radar Controller

Dependents:   JRO_CR2 frdm_test

CR2.h@0:e3f3fe2e689b, 2016-03-14 (annotated)

Committer:
joaquinbvw
Date:
Mon Mar 14 19:38:54 2016 +0000
Revision:
0:e3f3fe2e689b
CR2 first attempt.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
joaquinbvw 0:e3f3fe2e689b 1 #ifndef CR2_SER_DRIVER
joaquinbvw 0:e3f3fe2e689b 2 #define CR2_SER_DRIVER
joaquinbvw 0:e3f3fe2e689b 3
joaquinbvw 0:e3f3fe2e689b 4 #include "mbed.h"
joaquinbvw 0:e3f3fe2e689b 5 #include "SerialDriver.h"
joaquinbvw 0:e3f3fe2e689b 6
joaquinbvw 0:e3f3fe2e689b 7 #define SPI_BITS 8
joaquinbvw 0:e3f3fe2e689b 8 #define SPI_MODE 0
joaquinbvw 0:e3f3fe2e689b 9 #define SPI_FREQ 4000000
joaquinbvw 0:e3f3fe2e689b 10
joaquinbvw 0:e3f3fe2e689b 11 #define CR2_RESET 0X00
joaquinbvw 0:e3f3fe2e689b 12 #define CR2_ENABLE 0X01
joaquinbvw 0:e3f3fe2e689b 13 #define CR2_IO 0X02
joaquinbvw 0:e3f3fe2e689b 14 #define CR2_FREQ 0X03
joaquinbvw 0:e3f3fe2e689b 15 #define CR2_MW_BUF_L 0X04
joaquinbvw 0:e3f3fe2e689b 16 #define CR2_MW_BUF_H 0X05
joaquinbvw 0:e3f3fe2e689b 17 #define CR2_MR_BUF_L 0X06
joaquinbvw 0:e3f3fe2e689b 18 #define CR2_MR_BUF_H 0X07
joaquinbvw 0:e3f3fe2e689b 19 #define CR2_MEM_A_0 0X08
joaquinbvw 0:e3f3fe2e689b 20 #define CR2_MEM_A_1 0X09
joaquinbvw 0:e3f3fe2e689b 21 #define CR2_MEM_A_2 0X0A
joaquinbvw 0:e3f3fe2e689b 22 #define CR2_MEM_CONF 0X0B
joaquinbvw 0:e3f3fe2e689b 23 #define CR2_SAMP_L 0X0C
joaquinbvw 0:e3f3fe2e689b 24 #define CR2_SAMP_H 0X0D
joaquinbvw 0:e3f3fe2e689b 25 #define CR2_SAMP_CONT 0X0E
joaquinbvw 0:e3f3fe2e689b 26 #define CR2_MON_DAT_L 0X0F
joaquinbvw 0:e3f3fe2e689b 27 #define CR2_MON_DAT_H 0X10
joaquinbvw 0:e3f3fe2e689b 28 #define CR2_MON_CONT_L 0X11
joaquinbvw 0:e3f3fe2e689b 29 #define CR2_MON_CONT_H 0X12
joaquinbvw 0:e3f3fe2e689b 30 #define CR2_FRT_SEL_1 0X13
joaquinbvw 0:e3f3fe2e689b 31 #define CR2_FRT_SEL_2 0X14
joaquinbvw 0:e3f3fe2e689b 32 #define CR2_ACK_KEY 0X15
joaquinbvw 0:e3f3fe2e689b 33
joaquinbvw 0:e3f3fe2e689b 34 #define CR2_CMD_RESET 0X10
joaquinbvw 0:e3f3fe2e689b 35 #define CR2_CMD_ENABLE_RF 0x11
joaquinbvw 0:e3f3fe2e689b 36 #define CR2_CMD_MULTIPLIER 0X12
joaquinbvw 0:e3f3fe2e689b 37 #define CR2_CMD_MODE 0x13
joaquinbvw 0:e3f3fe2e689b 38 #define CR2_CMD_FREQUENCYA 0X14
joaquinbvw 0:e3f3fe2e689b 39 #define CR2_CMD_FREQUENCYB 0x15
joaquinbvw 0:e3f3fe2e689b 40 #define CR2_CMD_PHASEA 0X16
joaquinbvw 0:e3f3fe2e689b 41 #define CR2_CMD_PHASEB 0x17
joaquinbvw 0:e3f3fe2e689b 42 #define CR2_CMD_AMPLITUDE1 0X18
joaquinbvw 0:e3f3fe2e689b 43 #define CR2_CMD_AMPLITUDE2 0x19
joaquinbvw 0:e3f3fe2e689b 44 #define CR2_CMD_READ 0x8000
joaquinbvw 0:e3f3fe2e689b 45
joaquinbvw 0:e3f3fe2e689b 46 class CR2{
joaquinbvw 0:e3f3fe2e689b 47 private:
joaquinbvw 0:e3f3fe2e689b 48 float clock; // Work frequency in MHz
joaquinbvw 0:e3f3fe2e689b 49 char cr2_multiplier; // Multiplier 4- 20
joaquinbvw 0:e3f3fe2e689b 50 char cr2_mode; // Single, FSK, Ramped FSK, Chirp, BPSK
joaquinbvw 0:e3f3fe2e689b 51 bool cr2_qdac_pwdn; // Q DAC power down enable: 0 -> disable
joaquinbvw 0:e3f3fe2e689b 52 bool cr2_ioupdclk; // IO Update clock enable: 0 -> input
joaquinbvw 0:e3f3fe2e689b 53 bool cr2_inv_sinc; // Inverse sinc filter enable: 0 -> enable
joaquinbvw 0:e3f3fe2e689b 54 bool cr2_osk_en; // Enable AM: 0 -> disabled
joaquinbvw 0:e3f3fe2e689b 55 bool cr2_osk_int; // ext/int output shaped control: 0 -> external
joaquinbvw 0:e3f3fe2e689b 56 bool cr2_msb_lsb; // msb/lsb bit first: 0 -> MSB
joaquinbvw 0:e3f3fe2e689b 57 bool cr2_sdo; // SDO pin active: 0 -> inactive
joaquinbvw 0:e3f3fe2e689b 58
joaquinbvw 0:e3f3fe2e689b 59 char frequency1[6];
joaquinbvw 0:e3f3fe2e689b 60 char frequency2[6];
joaquinbvw 0:e3f3fe2e689b 61 char phase1[2];
joaquinbvw 0:e3f3fe2e689b 62 char phase2[2];
joaquinbvw 0:e3f3fe2e689b 63 char amplitudeI[2];
joaquinbvw 0:e3f3fe2e689b 64 char amplitudeQ[2];
joaquinbvw 0:e3f3fe2e689b 65 bool rf_enabled;
joaquinbvw 0:e3f3fe2e689b 66
joaquinbvw 0:e3f3fe2e689b 67 double factor_freq1;
joaquinbvw 0:e3f3fe2e689b 68 double factor_freq2;
joaquinbvw 0:e3f3fe2e689b 69
joaquinbvw 0:e3f3fe2e689b 70 SPI *spi_device;
joaquinbvw 0:e3f3fe2e689b 71 //CR2 I/O
joaquinbvw 0:e3f3fe2e689b 72 DigitalOut *cr2_mreset;
joaquinbvw 0:e3f3fe2e689b 73 DigitalOut *cr2_outramp;
joaquinbvw 0:e3f3fe2e689b 74 DigitalOut *cr2_sp_mode;
joaquinbvw 0:e3f3fe2e689b 75 DigitalOut *cr2_cs;
joaquinbvw 0:e3f3fe2e689b 76 DigitalOut *cr2_io_reset;
joaquinbvw 0:e3f3fe2e689b 77 DigitalInOut *cr2_updclk;
joaquinbvw 0:e3f3fe2e689b 78
joaquinbvw 0:e3f3fe2e689b 79 char* cmd_answer;
joaquinbvw 0:e3f3fe2e689b 80 unsigned long cmd_answer_len;
joaquinbvw 0:e3f3fe2e689b 81
joaquinbvw 0:e3f3fe2e689b 82 int __writeData(char addr, char data);
joaquinbvw 0:e3f3fe2e689b 83 char __readData(char addr);
joaquinbvw 0:e3f3fe2e689b 84 int __writeDataAndVerify(char addr, char wr_spi_data, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 85 //char* __getControlRegister();
joaquinbvw 0:e3f3fe2e689b 86 //int __writeControlRegister();
joaquinbvw 0:e3f3fe2e689b 87
joaquinbvw 0:e3f3fe2e689b 88 public:
joaquinbvw 0:e3f3fe2e689b 89 bool isConfig;
joaquinbvw 0:e3f3fe2e689b 90
joaquinbvw 0:e3f3fe2e689b 91
joaquinbvw 0:e3f3fe2e689b 92 CR2(SPI *spi_dev, DigitalOut *mreset, DigitalOut *outramp, DigitalOut *spmode, DigitalOut *cs, DigitalOut *ioreset, DigitalInOut *updclk);
joaquinbvw 0:e3f3fe2e689b 93 int init();
joaquinbvw 0:e3f3fe2e689b 94 int reset();
joaquinbvw 0:e3f3fe2e689b 95 int scanIOUpdate();
joaquinbvw 0:e3f3fe2e689b 96 int find();
joaquinbvw 0:e3f3fe2e689b 97 int writeBlock(char ndata, const char* data);
joaquinbvw 0:e3f3fe2e689b 98 /*
joaquinbvw 0:e3f3fe2e689b 99 char* rdMode();
joaquinbvw 0:e3f3fe2e689b 100 char* rdMultiplier();
joaquinbvw 0:e3f3fe2e689b 101 char* rdPhase1();
joaquinbvw 0:e3f3fe2e689b 102 char* rdPhase2();
joaquinbvw 0:e3f3fe2e689b 103 char* rdFrequency1();
joaquinbvw 0:e3f3fe2e689b 104 char* rdFrequency2();
joaquinbvw 0:e3f3fe2e689b 105 char* rdAmplitudeI();
joaquinbvw 0:e3f3fe2e689b 106 char* rdAmplitudeQ();
joaquinbvw 0:e3f3fe2e689b 107 int isRFEnabled();
joaquinbvw 0:e3f3fe2e689b 108 int wrMode(char mode);
joaquinbvw 0:e3f3fe2e689b 109 int wrMultiplier(char multiplier, float clock=200.0);
joaquinbvw 0:e3f3fe2e689b 110 int wrPhase1(char* phase, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 111 int wrPhase2(char* phase, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 112 int wrFrequency1(char* freq, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 113 int wrFrequency2(char* freq, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 114 int wrAmplitudeI(char* amplitude, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 115 int wrAmplitudeQ(char* amplitude, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 116 int enableRF();
joaquinbvw 0:e3f3fe2e689b 117 int disableRF();
joaquinbvw 0:e3f3fe2e689b 118 int defaultSettings(SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 119 */
joaquinbvw 0:e3f3fe2e689b 120 char* setCommand(unsigned short cmd, char* payload, unsigned long payload_len);
joaquinbvw 0:e3f3fe2e689b 121 char* getCmdAnswer();
joaquinbvw 0:e3f3fe2e689b 122 unsigned long getCmdAnswerLen();
joaquinbvw 0:e3f3fe2e689b 123 //int setAllDevice(char* payload, SerialDriver *screen=NULL);
joaquinbvw 0:e3f3fe2e689b 124 bool wasInitialized();
joaquinbvw 0:e3f3fe2e689b 125 char getMultiplier();
joaquinbvw 0:e3f3fe2e689b 126 double getFreqFactor1();
joaquinbvw 0:e3f3fe2e689b 127 double getFreqFactor2();
joaquinbvw 0:e3f3fe2e689b 128 char getMode();
joaquinbvw 0:e3f3fe2e689b 129 char* getModeStr();
joaquinbvw 0:e3f3fe2e689b 130
joaquinbvw 0:e3f3fe2e689b 131 };
joaquinbvw 0:e3f3fe2e689b 132
joaquinbvw 0:e3f3fe2e689b 133 #endif