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CC1101/CC1101-Defines.h@2:c42a035d71ed, 2014-12-31 (annotated)

Committer:
jjones646
Date:
Wed Dec 31 22:16:01 2014 +0000
Revision:
2:c42a035d71ed
Parent:
1:05a48c038381 
adding dummy cc1101 support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jjones646 0:c5afea7b9057 1 #ifndef CC1101_DEFINES_H
jjones646 0:c5afea7b9057 2 #define CC1101_DEFINES_H
jjones646 0:c5afea7b9057 3
jjones646 0:c5afea7b9057 4
jjones646 0:c5afea7b9057 5 /**
jjones646 0:c5afea7b9057 6 * Defines for TI CCXXX0 Radio Transceivers
jjones646 0:c5afea7b9057 7 */
jjones646 0:c5afea7b9057 8
jjones646 0:c5afea7b9057 9 // REGISTERS
jjones646 0:c5afea7b9057 10 #define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
jjones646 0:c5afea7b9057 11 #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
jjones646 0:c5afea7b9057 12 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
jjones646 0:c5afea7b9057 13 #define CCxxx0_SYNC1 0x04 // Sync word, high byte
jjones646 0:c5afea7b9057 14 #define CCxxx0_SYNC0 0x05 // Sync word, low byte
jjones646 0:c5afea7b9057 15 #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
jjones646 0:c5afea7b9057 16 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
jjones646 0:c5afea7b9057 17 #define CCxxx0_SYNC1 0x04 // Sync word, high byte
jjones646 0:c5afea7b9057 18 #define CCxxx0_SYNC0 0x05 // Sync word, low byte
jjones646 0:c5afea7b9057 19 #define CCxxx0_PCKLEN 0x06 // Packet length
jjones646 0:c5afea7b9057 20 #define CCxxx0_PCKCTRL1 0x07 // Packet automation control
jjones646 0:c5afea7b9057 21 #define CCxxx0_PCKCTRL0 0x08 // Packet automation control
jjones646 0:c5afea7b9057 22 #define CCxxx0_ADDR 0x09 // Device address
jjones646 0:c5afea7b9057 23 #define CCxxx0_CHANNR 0x0A // Channel number
jjones646 0:c5afea7b9057 24 #define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
jjones646 0:c5afea7b9057 25 #define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
jjones646 0:c5afea7b9057 26 #define CCxxx0_FREQ2 0x0D // Frequency control word, high byte
jjones646 0:c5afea7b9057 27 #define CCxxx0_FREQ1 0x0E // Frequency control word, middle byte
jjones646 0:c5afea7b9057 28 #define CCxxx0_FREQ0 0x0F // Frequency control word, low byte
jjones646 0:c5afea7b9057 29 #define CCxxx0_MDMCFG4 0x10 // Modem configuration
jjones646 0:c5afea7b9057 30 #define CCxxx0_MDMCFG3 0x11 // Modem configuration
jjones646 0:c5afea7b9057 31 #define CCxxx0_MDMCFG2 0x12 // Modem configuration
jjones646 0:c5afea7b9057 32 #define CCxxx0_MDMCFG1 0x13 // Modem configuration
jjones646 0:c5afea7b9057 33 #define CCxxx0_MDMCFG0 0x14 // Modem configuration
jjones646 0:c5afea7b9057 34 #define CCxxx0_DEVIATN 0x15 // Modem deviation setting
jjones646 0:c5afea7b9057 35 #define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
jjones646 0:c5afea7b9057 36 #define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
jjones646 0:c5afea7b9057 37 #define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
jjones646 0:c5afea7b9057 38 #define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
jjones646 0:c5afea7b9057 39 #define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
jjones646 0:c5afea7b9057 40 #define CCxxx0_AGCCTRL2 0x1B // AGC control
jjones646 0:c5afea7b9057 41 #define CCxxx0_AGCCTRL1 0x1C // AGC control
jjones646 0:c5afea7b9057 42 #define CCxxx0_AGCCTRL0 0x1D // AGC control
jjones646 0:c5afea7b9057 43 #define CCxxx0_WOREVT1 0x1E // High byte Event 0 timeout
jjones646 0:c5afea7b9057 44 #define CCxxx0_WOREVT0 0x1F // Low byte Event 0 timeout
jjones646 0:c5afea7b9057 45 #define CCxxx0_WORCTRL 0x20 // Wake On Radio control
jjones646 0:c5afea7b9057 46 #define CCxxx0_FREND1 0x21 // Front end RX configuration
jjones646 0:c5afea7b9057 47 #define CCxxx0_FREND0 0x22 // Front end TX configuration
jjones646 0:c5afea7b9057 48 #define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
jjones646 0:c5afea7b9057 49 #define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
jjones646 0:c5afea7b9057 50 #define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
jjones646 0:c5afea7b9057 51 #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
jjones646 0:c5afea7b9057 52 #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
jjones646 0:c5afea7b9057 53 #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
jjones646 0:c5afea7b9057 54 #define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
jjones646 0:c5afea7b9057 55 #define CCxxx0_PTEST 0x2A // Production test
jjones646 0:c5afea7b9057 56 #define CCxxx0_AGCTEST 0x2B // AGC test
jjones646 0:c5afea7b9057 57 #define CCxxx0_TEST2 0x2C // Various test settings
jjones646 0:c5afea7b9057 58 #define CCxxx0_TEST1 0x2D // Various test settings
jjones646 0:c5afea7b9057 59 #define CCxxx0_TEST0 0x2E // Various test settings
jjones646 0:c5afea7b9057 60
jjones646 0:c5afea7b9057 61 // STROBE COMMANDS
jjones646 0:c5afea7b9057 62 #define CCxxx0_SRES 0x30 // Reset chip.
jjones646 0:c5afea7b9057 63 #define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
jjones646 0:c5afea7b9057 64 #define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
jjones646 0:c5afea7b9057 65 #define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
jjones646 0:c5afea7b9057 66 #define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
jjones646 0:c5afea7b9057 67 #define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
jjones646 0:c5afea7b9057 68 #define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
jjones646 0:c5afea7b9057 69 #define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
jjones646 0:c5afea7b9057 70 #define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
jjones646 0:c5afea7b9057 71 #define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
jjones646 0:c5afea7b9057 72 #define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
jjones646 0:c5afea7b9057 73 #define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
jjones646 0:c5afea7b9057 74 #define CCxxx0_SWORRST 0x3C // Reset real time clock.
jjones646 0:c5afea7b9057 75
jjones646 0:c5afea7b9057 76 // READ ONLY REGISTERS
jjones646 0:c5afea7b9057 77 #define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two bytes for simpler software.
jjones646 0:c5afea7b9057 78 #define CCxxx0_PARTNUM 0x30
jjones646 0:c5afea7b9057 79 #define CCxxx0_VERSION 0x31
jjones646 0:c5afea7b9057 80 #define CCxxx0_FREQEST 0x32
jjones646 0:c5afea7b9057 81 #define CCxxx0_LQI 0x33
jjones646 0:c5afea7b9057 82 #define CCxxx0_RSSI 0x34
jjones646 0:c5afea7b9057 83 #define CCxxx0_MARCSTATE 0x35
jjones646 0:c5afea7b9057 84 #define CCxxx0_WORTIME1 0x36
jjones646 0:c5afea7b9057 85 #define CCxxx0_WORTIME0 0x37
jjones646 0:c5afea7b9057 86 #define CCxxx0_PKTSTATUS 0x38
jjones646 0:c5afea7b9057 87 #define CCxxx0_VCO_VC_DAC 0x39
jjones646 0:c5afea7b9057 88 #define CCxxx0_TXBYTES 0x3A
jjones646 0:c5afea7b9057 89 #define CCxxx0_RXBYTES 0x3B
jjones646 0:c5afea7b9057 90 #define CCxxx0_RCCTRL1_STATUS 0x3C
jjones646 0:c5afea7b9057 91 #define CCxxx0_RCCTRL0_STATUS 0x3D
jjones646 0:c5afea7b9057 92
jjones646 0:c5afea7b9057 93 // POWER REGISTERS
jjones646 0:c5afea7b9057 94 #define CCxxx0_PATABLE 0x3E
jjones646 0:c5afea7b9057 95 #define CCxxx0_TXFIFO 0x3F
jjones646 0:c5afea7b9057 96 #define CCxxx0_RXFIFO 0x3F
jjones646 0:c5afea7b9057 97
jjones646 0:c5afea7b9057 98 // BURST/SINGLE MODIFIERS
jjones646 0:c5afea7b9057 99 #define WRITE_BURST 0x40
jjones646 0:c5afea7b9057 100 #define READ_SINGLE 0x80
jjones646 0:c5afea7b9057 101 #define READ_BURST 0xC0
jjones646 0:c5afea7b9057 102
jjones646 0:c5afea7b9057 103 // GENERAL DEFINES
jjones646 0:c5afea7b9057 104 #define CRC_OK 0x80
jjones646 0:c5afea7b9057 105 #define RSSI 0
jjones646 0:c5afea7b9057 106 #define LQI 1
jjones646 0:c5afea7b9057 107 #define BYTES_IN_RXFIFO 0x7F
jjones646 0:c5afea7b9057 108
jjones646 0:c5afea7b9057 109 // CHIP STATUS
jjones646 0:c5afea7b9057 110 #define CHIP_RDY 0x80
jjones646 0:c5afea7b9057 111 #define CHIP_STATE_MASK 0x70
jjones646 0:c5afea7b9057 112 #define CHIP_STATE_IDLE 0x00
jjones646 0:c5afea7b9057 113 #define CHIP_STATE_RX 0x10
jjones646 0:c5afea7b9057 114 #define CHIP_STATE_TX 0x20
jjones646 0:c5afea7b9057 115 #define CHIP_STATE_FSTON 0x30
jjones646 0:c5afea7b9057 116 #define CHIP_STATE_CALIBRATE 0x40
jjones646 0:c5afea7b9057 117 #define CHIP_STATE_SETTLING 0x50
jjones646 0:c5afea7b9057 118 #define CHIP_STATE_RXFIFO_OVERFLOW 0x60
jjones646 0:c5afea7b9057 119 #define CHIP_STATE_TXFIFO_UNDERFLOW 0x70
jjones646 0:c5afea7b9057 120 #define FIFO_BYTES_MASK 0x0F
jjones646 0:c5afea7b9057 121
jjones646 0:c5afea7b9057 122 // FREQUENCY DEFINITIONS
jjones646 0:c5afea7b9057 123 #define _902MHZ_ 901833462
jjones646 0:c5afea7b9057 124 #define _316KHZ_ 316406
jjones646 0:c5afea7b9057 125
jjones646 0:c5afea7b9057 126
jjones646 0:c5afea7b9057 127 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
jjones646 0:c5afea7b9057 128 typedef struct rf_settings_t {
jjones646 0:c5afea7b9057 129 uint8_t FSCTRL1; // Frequency synthesizer control.
jjones646 0:c5afea7b9057 130 uint8_t IOCFG0; // GDO0 output pin configuration
jjones646 0:c5afea7b9057 131 uint8_t FSCTRL0; // Frequency synthesizer control.
jjones646 0:c5afea7b9057 132 uint8_t FREQ2; // Frequency control word, high byte.
jjones646 0:c5afea7b9057 133 uint8_t FREQ1; // Frequency control word, middle byte.
jjones646 0:c5afea7b9057 134 uint8_t FREQ0; // Frequency control word, low byte.
jjones646 0:c5afea7b9057 135 uint8_t MDMCFG4; // Modem configuration.
jjones646 0:c5afea7b9057 136 uint8_t MDMCFG3; // Modem configuration.
jjones646 0:c5afea7b9057 137 uint8_t MDMCFG2; // Modem configuration.
jjones646 0:c5afea7b9057 138 uint8_t MDMCFG1; // Modem configuration.
jjones646 0:c5afea7b9057 139 uint8_t MDMCFG0; // Modem configuration.
jjones646 0:c5afea7b9057 140 uint8_t CHANNR; // Channel number.
jjones646 0:c5afea7b9057 141 uint8_t DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
jjones646 0:c5afea7b9057 142 uint8_t FREND1; // Front end RX configuration.
jjones646 0:c5afea7b9057 143 uint8_t FREND0; // Front end RX configuration.
jjones646 0:c5afea7b9057 144 uint8_t MCSM0; // Main Radio Control State Machine configuration.
jjones646 0:c5afea7b9057 145 uint8_t MCSM1; // Main Radio Control State Machine configuration.
jjones646 0:c5afea7b9057 146 uint8_t MCSM2; // Main Radio Control State Machine configuration.
jjones646 0:c5afea7b9057 147 uint8_t FOCCFG; // Frequency Offset Compensation Configuration.
jjones646 0:c5afea7b9057 148 uint8_t BSCFG; // Bit synchronization Configuration.
jjones646 0:c5afea7b9057 149 uint8_t AGCCTRL2; // AGC control.
jjones646 0:c5afea7b9057 150 uint8_t AGCCTRL1; // AGC control.
jjones646 0:c5afea7b9057 151 uint8_t AGCCTRL0; // AGC control.
jjones646 0:c5afea7b9057 152 uint8_t FSCAL3; // Frequency synthesizer calibration.
jjones646 0:c5afea7b9057 153 uint8_t FSCAL2; // Frequency synthesizer calibration.
jjones646 0:c5afea7b9057 154 uint8_t FSCAL1; // Frequency synthesizer calibration.
jjones646 0:c5afea7b9057 155 uint8_t FSCAL0; // Frequency synthesizer calibration.
jjones646 0:c5afea7b9057 156 uint8_t FSTEST; // Frequency synthesizer calibration control
jjones646 0:c5afea7b9057 157 uint8_t TEST2; // Various test settings.
jjones646 0:c5afea7b9057 158 uint8_t TEST1; // Various test settings.
jjones646 0:c5afea7b9057 159 uint8_t TEST0; // Various test settings.
jjones646 0:c5afea7b9057 160 uint8_t FIFOTHR; // RXFIFO and TXFIFO thresholds.
jjones646 0:c5afea7b9057 161 uint8_t IOCFG2; // GDO2 output pin configuration
jjones646 0:c5afea7b9057 162 uint8_t IOCFG1; // GDO1 output pin configuration
jjones646 0:c5afea7b9057 163 uint8_t PCKCTRL1; // Packet automation control.
jjones646 0:c5afea7b9057 164 uint8_t PCKCTRL0; // Packet automation control.
jjones646 0:c5afea7b9057 165 uint8_t ADDR; // Device address.
jjones646 0:c5afea7b9057 166 uint8_t PCKLEN; // Packet length.
jjones646 0:c5afea7b9057 167 } rf_settings_t;
jjones646 0:c5afea7b9057 168
jjones646 0:c5afea7b9057 169 /** Enumerations for state types of the CC1101 */
jjones646 0:c5afea7b9057 170 enum radio_state_t {
jjones646 0:c5afea7b9057 171 RADIO_IDLE = 0,
jjones646 0:c5afea7b9057 172 RADIO_RX = 1,
jjones646 0:c5afea7b9057 173 RADIO_TX = 2,
jjones646 0:c5afea7b9057 174 RADIO_FSTXON = 3,
jjones646 0:c5afea7b9057 175 RADIO_CALIBRATE = 4,
jjones646 0:c5afea7b9057 176 RADIO_SETTLING = 5,
jjones646 0:c5afea7b9057 177 RADIO_RXFIFO_OVERFLOW = 6,
jjones646 0:c5afea7b9057 178 RADIO_TXFIFO_OVERFLOW = 7
jjones646 0:c5afea7b9057 179 };
jjones646 0:c5afea7b9057 180
jjones646 0:c5afea7b9057 181 /** Enumerations for packet format settings of the CC1101 */
jjones646 0:c5afea7b9057 182 enum pck_format_t {
jjones646 0:c5afea7b9057 183 FORMAT_DEFAULT = 0,
jjones646 0:c5afea7b9057 184 FORMAT_SYNC_SERIAL = 1,
jjones646 0:c5afea7b9057 185 FORMAT_RAND_TX = 2,
jjones646 0:c5afea7b9057 186 FORMAT_ASYC_SERIAL = 3
jjones646 0:c5afea7b9057 187 };
jjones646 0:c5afea7b9057 188
jjones646 0:c5afea7b9057 189 /** Enumerations for packet length types of the CC1101 */
jjones646 0:c5afea7b9057 190 enum pck_length_type_t {
jjones646 0:c5afea7b9057 191 PACKET_FIXED = 0,
jjones646 0:c5afea7b9057 192 PACKET_VARIABLE = 1,
jjones646 0:c5afea7b9057 193 PACKET_INFINITE = 2
jjones646 0:c5afea7b9057 194 };
jjones646 0:c5afea7b9057 195
jjones646 0:c5afea7b9057 196 /** Enumerations for packet address checking types of the CC1101 */
jjones646 0:c5afea7b9057 197 enum pck_addr_chk_t {
jjones646 0:c5afea7b9057 198 ADDR_OFF = 0,
jjones646 0:c5afea7b9057 199 ADDR_CHK = 1,
jjones646 0:c5afea7b9057 200 ADDR_CHK_AND_BCAST = 2,
jjones646 0:c5afea7b9057 201 ADDR_CHK_AND_BCAST_ALL = 3
jjones646 0:c5afea7b9057 202 };
jjones646 0:c5afea7b9057 203
jjones646 0:c5afea7b9057 204 /** Data structure for managing how the CC1101 handels packets */
jjones646 0:c5afea7b9057 205 typedef struct pck_ctrl_t {
jjones646 0:c5afea7b9057 206 bool whitening_en;
jjones646 0:c5afea7b9057 207 bool crc_en;
jjones646 0:c5afea7b9057 208 bool autoflush_en;
jjones646 0:c5afea7b9057 209 bool status_field_en;
jjones646 0:c5afea7b9057 210 uint8_t preamble_thresh;
jjones646 0:c5afea7b9057 211 uint8_t size;
jjones646 0:c5afea7b9057 212 pck_format_t format_type;
jjones646 0:c5afea7b9057 213 pck_length_type_t length_type;
jjones646 0:c5afea7b9057 214 pck_addr_chk_t addr_check;
jjones646 0:c5afea7b9057 215 } pck_ctrl_t;
jjones646 0:c5afea7b9057 216
jjones646 0:c5afea7b9057 217 /** Enumerations for modulation types of the CC1101 */
jjones646 0:c5afea7b9057 218 enum mod_format_t {
jjones646 0:c5afea7b9057 219 MOD_TWO_FSK = 0,
jjones646 0:c5afea7b9057 220 MOD_GFSK = 1,
jjones646 0:c5afea7b9057 221 MOD_ASK = 3,
jjones646 0:c5afea7b9057 222 MOD_FOUR_FSK = 4,
jjones646 0:c5afea7b9057 223 MOD_MSK = 7
jjones646 0:c5afea7b9057 224 };
jjones646 0:c5afea7b9057 225
jjones646 0:c5afea7b9057 226 /** Enumerations for signal syncronization of the CC1101 */
jjones646 0:c5afea7b9057 227 enum sync_mode_t {
jjones646 0:c5afea7b9057 228 SYNC_NONE = 0,
jjones646 0:c5afea7b9057 229 SYNC_LOW_ALLOW_ONE = 1,
jjones646 0:c5afea7b9057 230 SYNC_LOW_ALLOW_NONE = 2,
jjones646 0:c5afea7b9057 231 SYNC_HIGH_ALLOW_TWO = 3,
jjones646 0:c5afea7b9057 232 SYNC_JUST_CARRIER_SENSE = 4,
jjones646 0:c5afea7b9057 233 SYNC_LOW_ALLOW_ONE_CS = 5,
jjones646 0:c5afea7b9057 234 SYNC_LOW_ALLOW_NONE_CS = 6,
jjones646 0:c5afea7b9057 235 SYNC_HIGH_ALLOW_TWO_CS = 7
jjones646 0:c5afea7b9057 236 };
jjones646 0:c5afea7b9057 237
jjones646 0:c5afea7b9057 238 /** Enumerations for preamble byte sizes of the CC1101 */
jjones646 0:c5afea7b9057 239 enum pream_bytes_t {
jjones646 0:c5afea7b9057 240 PREAM_TWO = 0,
jjones646 0:c5afea7b9057 241 PREAM_THREE = 1,
jjones646 0:c5afea7b9057 242 PREAM_FOUR = 2,
jjones646 0:c5afea7b9057 243 PREAM_SIX = 3,
jjones646 0:c5afea7b9057 244 PREAM_EIGHT = 4,
jjones646 0:c5afea7b9057 245 PREAM_TWELVE = 5,
jjones646 0:c5afea7b9057 246 PREAM_SIXTEEN = 6,
jjones646 0:c5afea7b9057 247 PREAM_TWENTY_FOUR = 7
jjones646 0:c5afea7b9057 248 };
jjones646 0:c5afea7b9057 249
jjones646 0:c5afea7b9057 250 /** Data structure for managing how the CC1101 modulates/demodulates signals */
jjones646 0:c5afea7b9057 251 typedef struct modem_t {
jjones646 0:c5afea7b9057 252 bool dc_filter_off_en;
jjones646 0:c5afea7b9057 253 bool manchester_encode_en;
jjones646 0:c5afea7b9057 254 bool fec_en;
jjones646 0:c5afea7b9057 255 uint8_t data_rate_exp;
jjones646 0:c5afea7b9057 256 uint8_t data_rate_mtsa;
jjones646 0:c5afea7b9057 257 uint8_t channel_bw;
jjones646 0:c5afea7b9057 258 uint8_t channel_bw_exp;
jjones646 0:c5afea7b9057 259 uint8_t channel_space_exp;
jjones646 0:c5afea7b9057 260 uint8_t channel_space_mtsa;
jjones646 0:c5afea7b9057 261 mod_format_t mod_type;
jjones646 0:c5afea7b9057 262 sync_mode_t sync_mode;
jjones646 0:c5afea7b9057 263 pream_bytes_t preamble_bytes;
jjones646 0:c5afea7b9057 264 } modem_t;
jjones646 0:c5afea7b9057 265
jjones646 0:c5afea7b9057 266 #endif // CC1101_DEFINES_H