Seunghee Jeong / Mbed 2 deprecated Dronequadrotor

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Dependencies:   mbed

RF24.cpp@0:56ba69e447e3, 23 months ago (annotated)

Committer:
jjeong
Date:
Mon Jul 18 06:37:14 2022 +0000
Revision:
0:56ba69e447e3
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jjeong 0:56ba69e447e3 1 /*
jjeong 0:56ba69e447e3 2 Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
jjeong 0:56ba69e447e3 3
jjeong 0:56ba69e447e3 4 This program is free software; you can redistribute it and/or
jjeong 0:56ba69e447e3 5 modify it under the terms of the GNU General Public License
jjeong 0:56ba69e447e3 6 version 2 as published by the Free Software Foundation.
jjeong 0:56ba69e447e3 7 */
jjeong 0:56ba69e447e3 8
jjeong 0:56ba69e447e3 9 /*
jjeong 0:56ba69e447e3 10 * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
jjeong 0:56ba69e447e3 11 * Porting completed on Nov/05/2015
jjeong 0:56ba69e447e3 12 *
jjeong 0:56ba69e447e3 13 * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
jjeong 0:56ba69e447e3 14 * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
jjeong 0:56ba69e447e3 15 *
jjeong 0:56ba69e447e3 16 */
jjeong 0:56ba69e447e3 17
jjeong 0:56ba69e447e3 18 #include "nRF24L01.h"
jjeong 0:56ba69e447e3 19 #include "RF24_config.h"
jjeong 0:56ba69e447e3 20 #include "RF24.h"
jjeong 0:56ba69e447e3 21
jjeong 0:56ba69e447e3 22 /****************************************************************************/
jjeong 0:56ba69e447e3 23
jjeong 0:56ba69e447e3 24 void RF24::csn(bool mode)
jjeong 0:56ba69e447e3 25 {
jjeong 0:56ba69e447e3 26
jjeong 0:56ba69e447e3 27 csn_pin = mode;
jjeong 0:56ba69e447e3 28
jjeong 0:56ba69e447e3 29
jjeong 0:56ba69e447e3 30 }
jjeong 0:56ba69e447e3 31
jjeong 0:56ba69e447e3 32 /****************************************************************************/
jjeong 0:56ba69e447e3 33
jjeong 0:56ba69e447e3 34 void RF24::ce(bool level)
jjeong 0:56ba69e447e3 35 {
jjeong 0:56ba69e447e3 36 ce_pin = level;
jjeong 0:56ba69e447e3 37
jjeong 0:56ba69e447e3 38 }
jjeong 0:56ba69e447e3 39
jjeong 0:56ba69e447e3 40 /****************************************************************************/
jjeong 0:56ba69e447e3 41
jjeong 0:56ba69e447e3 42 inline void RF24::beginTransaction() {
jjeong 0:56ba69e447e3 43
jjeong 0:56ba69e447e3 44
jjeong 0:56ba69e447e3 45 csn(LOW);
jjeong 0:56ba69e447e3 46 }
jjeong 0:56ba69e447e3 47
jjeong 0:56ba69e447e3 48 /****************************************************************************/
jjeong 0:56ba69e447e3 49
jjeong 0:56ba69e447e3 50 inline void RF24::endTransaction() {
jjeong 0:56ba69e447e3 51 csn(HIGH);
jjeong 0:56ba69e447e3 52
jjeong 0:56ba69e447e3 53
jjeong 0:56ba69e447e3 54
jjeong 0:56ba69e447e3 55 }
jjeong 0:56ba69e447e3 56
jjeong 0:56ba69e447e3 57 /****************************************************************************/
jjeong 0:56ba69e447e3 58
jjeong 0:56ba69e447e3 59 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
jjeong 0:56ba69e447e3 60 {
jjeong 0:56ba69e447e3 61 uint8_t status;
jjeong 0:56ba69e447e3 62
jjeong 0:56ba69e447e3 63
jjeong 0:56ba69e447e3 64
jjeong 0:56ba69e447e3 65 beginTransaction();
jjeong 0:56ba69e447e3 66 status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:56ba69e447e3 67 while ( len-- ){
jjeong 0:56ba69e447e3 68 *buf++ = spi.write(0xff);
jjeong 0:56ba69e447e3 69 }
jjeong 0:56ba69e447e3 70 endTransaction();
jjeong 0:56ba69e447e3 71
jjeong 0:56ba69e447e3 72
jjeong 0:56ba69e447e3 73
jjeong 0:56ba69e447e3 74 return status;
jjeong 0:56ba69e447e3 75 }
jjeong 0:56ba69e447e3 76
jjeong 0:56ba69e447e3 77 /****************************************************************************/
jjeong 0:56ba69e447e3 78
jjeong 0:56ba69e447e3 79 uint8_t RF24::read_register(uint8_t reg)
jjeong 0:56ba69e447e3 80 {
jjeong 0:56ba69e447e3 81 uint8_t result;
jjeong 0:56ba69e447e3 82
jjeong 0:56ba69e447e3 83
jjeong 0:56ba69e447e3 84 beginTransaction();
jjeong 0:56ba69e447e3 85 spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:56ba69e447e3 86 result = spi.write(0xff);
jjeong 0:56ba69e447e3 87 endTransaction();
jjeong 0:56ba69e447e3 88
jjeong 0:56ba69e447e3 89
jjeong 0:56ba69e447e3 90
jjeong 0:56ba69e447e3 91 return result;
jjeong 0:56ba69e447e3 92 }
jjeong 0:56ba69e447e3 93
jjeong 0:56ba69e447e3 94 /****************************************************************************/
jjeong 0:56ba69e447e3 95
jjeong 0:56ba69e447e3 96 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
jjeong 0:56ba69e447e3 97 {
jjeong 0:56ba69e447e3 98 uint8_t status;
jjeong 0:56ba69e447e3 99
jjeong 0:56ba69e447e3 100
jjeong 0:56ba69e447e3 101 beginTransaction();
jjeong 0:56ba69e447e3 102 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:56ba69e447e3 103 while ( len-- )
jjeong 0:56ba69e447e3 104 spi.write(*buf++);
jjeong 0:56ba69e447e3 105 endTransaction();
jjeong 0:56ba69e447e3 106
jjeong 0:56ba69e447e3 107
jjeong 0:56ba69e447e3 108
jjeong 0:56ba69e447e3 109 return status;
jjeong 0:56ba69e447e3 110 }
jjeong 0:56ba69e447e3 111
jjeong 0:56ba69e447e3 112 /****************************************************************************/
jjeong 0:56ba69e447e3 113
jjeong 0:56ba69e447e3 114 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
jjeong 0:56ba69e447e3 115 {
jjeong 0:56ba69e447e3 116 uint8_t status;
jjeong 0:56ba69e447e3 117
jjeong 0:56ba69e447e3 118 IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
jjeong 0:56ba69e447e3 119
jjeong 0:56ba69e447e3 120
jjeong 0:56ba69e447e3 121 beginTransaction();
jjeong 0:56ba69e447e3 122 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
jjeong 0:56ba69e447e3 123 spi.write(value);
jjeong 0:56ba69e447e3 124 endTransaction();
jjeong 0:56ba69e447e3 125
jjeong 0:56ba69e447e3 126
jjeong 0:56ba69e447e3 127
jjeong 0:56ba69e447e3 128 return status;
jjeong 0:56ba69e447e3 129 }
jjeong 0:56ba69e447e3 130
jjeong 0:56ba69e447e3 131 /****************************************************************************/
jjeong 0:56ba69e447e3 132
jjeong 0:56ba69e447e3 133 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
jjeong 0:56ba69e447e3 134 {
jjeong 0:56ba69e447e3 135 uint8_t status;
jjeong 0:56ba69e447e3 136 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
jjeong 0:56ba69e447e3 137
jjeong 0:56ba69e447e3 138 data_len = rf24_min(data_len, payload_size);
jjeong 0:56ba69e447e3 139 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
jjeong 0:56ba69e447e3 140
jjeong 0:56ba69e447e3 141 //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
jjeong 0:56ba69e447e3 142 IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
jjeong 0:56ba69e447e3 143
jjeong 0:56ba69e447e3 144
jjeong 0:56ba69e447e3 145 beginTransaction();
jjeong 0:56ba69e447e3 146 status = spi.write( writeType );
jjeong 0:56ba69e447e3 147 while ( data_len-- ) {
jjeong 0:56ba69e447e3 148 spi.write(*current++);
jjeong 0:56ba69e447e3 149 }
jjeong 0:56ba69e447e3 150 while ( blank_len-- ) {
jjeong 0:56ba69e447e3 151 spi.write(0);
jjeong 0:56ba69e447e3 152 }
jjeong 0:56ba69e447e3 153 endTransaction();
jjeong 0:56ba69e447e3 154
jjeong 0:56ba69e447e3 155
jjeong 0:56ba69e447e3 156
jjeong 0:56ba69e447e3 157 return status;
jjeong 0:56ba69e447e3 158 }
jjeong 0:56ba69e447e3 159
jjeong 0:56ba69e447e3 160 /****************************************************************************/
jjeong 0:56ba69e447e3 161
jjeong 0:56ba69e447e3 162 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
jjeong 0:56ba69e447e3 163 {
jjeong 0:56ba69e447e3 164 uint8_t status;
jjeong 0:56ba69e447e3 165 uint8_t* current = reinterpret_cast<uint8_t*>(buf);
jjeong 0:56ba69e447e3 166
jjeong 0:56ba69e447e3 167 if(data_len > payload_size) data_len = payload_size;
jjeong 0:56ba69e447e3 168 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
jjeong 0:56ba69e447e3 169
jjeong 0:56ba69e447e3 170 //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
jjeong 0:56ba69e447e3 171
jjeong 0:56ba69e447e3 172 IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
jjeong 0:56ba69e447e3 173
jjeong 0:56ba69e447e3 174
jjeong 0:56ba69e447e3 175
jjeong 0:56ba69e447e3 176 beginTransaction();
jjeong 0:56ba69e447e3 177 status = spi.write( R_RX_PAYLOAD );
jjeong 0:56ba69e447e3 178 while ( data_len-- ) {
jjeong 0:56ba69e447e3 179 *current++ = spi.write(0xFF);
jjeong 0:56ba69e447e3 180 }
jjeong 0:56ba69e447e3 181 while ( blank_len-- ) {
jjeong 0:56ba69e447e3 182 spi.write(0xff);
jjeong 0:56ba69e447e3 183 }
jjeong 0:56ba69e447e3 184 endTransaction();
jjeong 0:56ba69e447e3 185
jjeong 0:56ba69e447e3 186
jjeong 0:56ba69e447e3 187
jjeong 0:56ba69e447e3 188 return status;
jjeong 0:56ba69e447e3 189 }
jjeong 0:56ba69e447e3 190
jjeong 0:56ba69e447e3 191 /****************************************************************************/
jjeong 0:56ba69e447e3 192
jjeong 0:56ba69e447e3 193 uint8_t RF24::flush_rx(void)
jjeong 0:56ba69e447e3 194 {
jjeong 0:56ba69e447e3 195 return spiTrans( FLUSH_RX );
jjeong 0:56ba69e447e3 196 }
jjeong 0:56ba69e447e3 197
jjeong 0:56ba69e447e3 198 /****************************************************************************/
jjeong 0:56ba69e447e3 199
jjeong 0:56ba69e447e3 200 uint8_t RF24::flush_tx(void)
jjeong 0:56ba69e447e3 201 {
jjeong 0:56ba69e447e3 202 return spiTrans( FLUSH_TX );
jjeong 0:56ba69e447e3 203 }
jjeong 0:56ba69e447e3 204
jjeong 0:56ba69e447e3 205 /****************************************************************************/
jjeong 0:56ba69e447e3 206
jjeong 0:56ba69e447e3 207 uint8_t RF24::spiTrans(uint8_t cmd){
jjeong 0:56ba69e447e3 208
jjeong 0:56ba69e447e3 209 uint8_t status;
jjeong 0:56ba69e447e3 210
jjeong 0:56ba69e447e3 211 beginTransaction();
jjeong 0:56ba69e447e3 212 status = spi.write( cmd );
jjeong 0:56ba69e447e3 213 endTransaction();
jjeong 0:56ba69e447e3 214
jjeong 0:56ba69e447e3 215 return status;
jjeong 0:56ba69e447e3 216 }
jjeong 0:56ba69e447e3 217
jjeong 0:56ba69e447e3 218 /****************************************************************************/
jjeong 0:56ba69e447e3 219
jjeong 0:56ba69e447e3 220 uint8_t RF24::get_status(void)
jjeong 0:56ba69e447e3 221 {
jjeong 0:56ba69e447e3 222 return spiTrans(NOP);
jjeong 0:56ba69e447e3 223 }
jjeong 0:56ba69e447e3 224
jjeong 0:56ba69e447e3 225 /****************************************************************************/
jjeong 0:56ba69e447e3 226 #if !defined (MINIMAL)
jjeong 0:56ba69e447e3 227 void RF24::print_status(uint8_t status)
jjeong 0:56ba69e447e3 228 {
jjeong 0:56ba69e447e3 229 printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
jjeong 0:56ba69e447e3 230 status,
jjeong 0:56ba69e447e3 231 (status & _BV(RX_DR))?1:0,
jjeong 0:56ba69e447e3 232 (status & _BV(TX_DS))?1:0,
jjeong 0:56ba69e447e3 233 (status & _BV(MAX_RT))?1:0,
jjeong 0:56ba69e447e3 234 ((status >> RX_P_NO) & 0b111),
jjeong 0:56ba69e447e3 235 (status & _BV(TX_FULL))?1:0
jjeong 0:56ba69e447e3 236 );
jjeong 0:56ba69e447e3 237 }
jjeong 0:56ba69e447e3 238
jjeong 0:56ba69e447e3 239 /****************************************************************************/
jjeong 0:56ba69e447e3 240
jjeong 0:56ba69e447e3 241 void RF24::print_observe_tx(uint8_t value)
jjeong 0:56ba69e447e3 242 {
jjeong 0:56ba69e447e3 243 printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
jjeong 0:56ba69e447e3 244 value,
jjeong 0:56ba69e447e3 245 (value >> PLOS_CNT) & 0b1111,
jjeong 0:56ba69e447e3 246 (value >> ARC_CNT) & 0b1111
jjeong 0:56ba69e447e3 247 );
jjeong 0:56ba69e447e3 248 }
jjeong 0:56ba69e447e3 249
jjeong 0:56ba69e447e3 250 /****************************************************************************/
jjeong 0:56ba69e447e3 251
jjeong 0:56ba69e447e3 252 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
jjeong 0:56ba69e447e3 253 {
jjeong 0:56ba69e447e3 254 //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
jjeong 0:56ba69e447e3 255 //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
jjeong 0:56ba69e447e3 256
jjeong 0:56ba69e447e3 257
jjeong 0:56ba69e447e3 258
jjeong 0:56ba69e447e3 259 printf_P(PSTR(PRIPSTR"\t ="),name);
jjeong 0:56ba69e447e3 260
jjeong 0:56ba69e447e3 261 while (qty--)
jjeong 0:56ba69e447e3 262 printf_P(PSTR(" 0x%02x"),read_register(reg++));
jjeong 0:56ba69e447e3 263 printf_P(PSTR("\r\n"));
jjeong 0:56ba69e447e3 264 }
jjeong 0:56ba69e447e3 265
jjeong 0:56ba69e447e3 266 /****************************************************************************/
jjeong 0:56ba69e447e3 267
jjeong 0:56ba69e447e3 268 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
jjeong 0:56ba69e447e3 269 {
jjeong 0:56ba69e447e3 270
jjeong 0:56ba69e447e3 271
jjeong 0:56ba69e447e3 272
jjeong 0:56ba69e447e3 273
jjeong 0:56ba69e447e3 274 printf_P(PSTR(PRIPSTR"\t ="),name);
jjeong 0:56ba69e447e3 275
jjeong 0:56ba69e447e3 276 while (qty--)
jjeong 0:56ba69e447e3 277 {
jjeong 0:56ba69e447e3 278 uint8_t buffer[addr_width];
jjeong 0:56ba69e447e3 279 read_register(reg++,buffer,sizeof buffer);
jjeong 0:56ba69e447e3 280
jjeong 0:56ba69e447e3 281 printf_P(PSTR(" 0x"));
jjeong 0:56ba69e447e3 282 uint8_t* bufptr = buffer + sizeof buffer;
jjeong 0:56ba69e447e3 283 while( --bufptr >= buffer )
jjeong 0:56ba69e447e3 284 printf_P(PSTR("%02x"),*bufptr);
jjeong 0:56ba69e447e3 285 }
jjeong 0:56ba69e447e3 286
jjeong 0:56ba69e447e3 287 printf_P(PSTR("\r\n"));
jjeong 0:56ba69e447e3 288 }
jjeong 0:56ba69e447e3 289 #endif
jjeong 0:56ba69e447e3 290 /****************************************************************************/
jjeong 0:56ba69e447e3 291 RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin):
jjeong 0:56ba69e447e3 292 spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true),
jjeong 0:56ba69e447e3 293 payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
jjeong 0:56ba69e447e3 294 {
jjeong 0:56ba69e447e3 295 pipe0_reading_address[0]=0;
jjeong 0:56ba69e447e3 296
jjeong 0:56ba69e447e3 297 //spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus
jjeong 0:56ba69e447e3 298 spi.frequency(10000000/5);
jjeong 0:56ba69e447e3 299 //spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
jjeong 0:56ba69e447e3 300 spi.format(8,0);
jjeong 0:56ba69e447e3 301 wait_ms(10);
jjeong 0:56ba69e447e3 302 }
jjeong 0:56ba69e447e3 303
jjeong 0:56ba69e447e3 304
jjeong 0:56ba69e447e3 305
jjeong 0:56ba69e447e3 306
jjeong 0:56ba69e447e3 307
jjeong 0:56ba69e447e3 308
jjeong 0:56ba69e447e3 309
jjeong 0:56ba69e447e3 310
jjeong 0:56ba69e447e3 311 /****************************************************************************/
jjeong 0:56ba69e447e3 312
jjeong 0:56ba69e447e3 313 void RF24::setChannel(uint8_t channel)
jjeong 0:56ba69e447e3 314 {
jjeong 0:56ba69e447e3 315 const uint8_t max_channel = 125;
jjeong 0:56ba69e447e3 316 write_register(RF_CH,rf24_min(channel,max_channel));
jjeong 0:56ba69e447e3 317 }
jjeong 0:56ba69e447e3 318
jjeong 0:56ba69e447e3 319 uint8_t RF24::getChannel()
jjeong 0:56ba69e447e3 320 {
jjeong 0:56ba69e447e3 321
jjeong 0:56ba69e447e3 322 return read_register(RF_CH);
jjeong 0:56ba69e447e3 323 }
jjeong 0:56ba69e447e3 324 /****************************************************************************/
jjeong 0:56ba69e447e3 325
jjeong 0:56ba69e447e3 326 void RF24::setPayloadSize(uint8_t size)
jjeong 0:56ba69e447e3 327 {
jjeong 0:56ba69e447e3 328 payload_size = rf24_min(size,32);
jjeong 0:56ba69e447e3 329 }
jjeong 0:56ba69e447e3 330
jjeong 0:56ba69e447e3 331 /****************************************************************************/
jjeong 0:56ba69e447e3 332
jjeong 0:56ba69e447e3 333 uint8_t RF24::getPayloadSize(void)
jjeong 0:56ba69e447e3 334 {
jjeong 0:56ba69e447e3 335 return payload_size;
jjeong 0:56ba69e447e3 336 }
jjeong 0:56ba69e447e3 337
jjeong 0:56ba69e447e3 338 /****************************************************************************/
jjeong 0:56ba69e447e3 339
jjeong 0:56ba69e447e3 340 #if !defined (MINIMAL)
jjeong 0:56ba69e447e3 341
jjeong 0:56ba69e447e3 342 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
jjeong 0:56ba69e447e3 343 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
jjeong 0:56ba69e447e3 344 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
jjeong 0:56ba69e447e3 345 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
jjeong 0:56ba69e447e3 346 rf24_datarate_e_str_0,
jjeong 0:56ba69e447e3 347 rf24_datarate_e_str_1,
jjeong 0:56ba69e447e3 348 rf24_datarate_e_str_2,
jjeong 0:56ba69e447e3 349 };
jjeong 0:56ba69e447e3 350 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
jjeong 0:56ba69e447e3 351 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
jjeong 0:56ba69e447e3 352 static const char * const rf24_model_e_str_P[] PROGMEM = {
jjeong 0:56ba69e447e3 353 rf24_model_e_str_0,
jjeong 0:56ba69e447e3 354 rf24_model_e_str_1,
jjeong 0:56ba69e447e3 355 };
jjeong 0:56ba69e447e3 356 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
jjeong 0:56ba69e447e3 357 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
jjeong 0:56ba69e447e3 358 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
jjeong 0:56ba69e447e3 359 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
jjeong 0:56ba69e447e3 360 rf24_crclength_e_str_0,
jjeong 0:56ba69e447e3 361 rf24_crclength_e_str_1,
jjeong 0:56ba69e447e3 362 rf24_crclength_e_str_2,
jjeong 0:56ba69e447e3 363 };
jjeong 0:56ba69e447e3 364 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
jjeong 0:56ba69e447e3 365 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
jjeong 0:56ba69e447e3 366 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
jjeong 0:56ba69e447e3 367 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
jjeong 0:56ba69e447e3 368 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
jjeong 0:56ba69e447e3 369 rf24_pa_dbm_e_str_0,
jjeong 0:56ba69e447e3 370 rf24_pa_dbm_e_str_1,
jjeong 0:56ba69e447e3 371 rf24_pa_dbm_e_str_2,
jjeong 0:56ba69e447e3 372 rf24_pa_dbm_e_str_3,
jjeong 0:56ba69e447e3 373 };
jjeong 0:56ba69e447e3 374
jjeong 0:56ba69e447e3 375
jjeong 0:56ba69e447e3 376
jjeong 0:56ba69e447e3 377
jjeong 0:56ba69e447e3 378
jjeong 0:56ba69e447e3 379
jjeong 0:56ba69e447e3 380
jjeong 0:56ba69e447e3 381
jjeong 0:56ba69e447e3 382
jjeong 0:56ba69e447e3 383
jjeong 0:56ba69e447e3 384
jjeong 0:56ba69e447e3 385
jjeong 0:56ba69e447e3 386
jjeong 0:56ba69e447e3 387
jjeong 0:56ba69e447e3 388 void RF24::printDetails(void)
jjeong 0:56ba69e447e3 389 {
jjeong 0:56ba69e447e3 390
jjeong 0:56ba69e447e3 391
jjeong 0:56ba69e447e3 392 print_status(get_status());
jjeong 0:56ba69e447e3 393
jjeong 0:56ba69e447e3 394 print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
jjeong 0:56ba69e447e3 395 print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
jjeong 0:56ba69e447e3 396 print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
jjeong 0:56ba69e447e3 397
jjeong 0:56ba69e447e3 398 print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
jjeong 0:56ba69e447e3 399 print_byte_register(PSTR("EN_AA\t"),EN_AA);
jjeong 0:56ba69e447e3 400 print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
jjeong 0:56ba69e447e3 401 print_byte_register(PSTR("RF_CH\t"),RF_CH);
jjeong 0:56ba69e447e3 402 print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
jjeong 0:56ba69e447e3 403 print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
jjeong 0:56ba69e447e3 404 print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
jjeong 0:56ba69e447e3 405
jjeong 0:56ba69e447e3 406 printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
jjeong 0:56ba69e447e3 407 printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
jjeong 0:56ba69e447e3 408 printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
jjeong 0:56ba69e447e3 409 printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
jjeong 0:56ba69e447e3 410
jjeong 0:56ba69e447e3 411 }
jjeong 0:56ba69e447e3 412
jjeong 0:56ba69e447e3 413 #endif
jjeong 0:56ba69e447e3 414 /****************************************************************************/
jjeong 0:56ba69e447e3 415
jjeong 0:56ba69e447e3 416 bool RF24::begin(void)
jjeong 0:56ba69e447e3 417 {
jjeong 0:56ba69e447e3 418
jjeong 0:56ba69e447e3 419 uint8_t setup=0;
jjeong 0:56ba69e447e3 420
jjeong 0:56ba69e447e3 421 mainTimer.start();
jjeong 0:56ba69e447e3 422
jjeong 0:56ba69e447e3 423 ce(LOW);
jjeong 0:56ba69e447e3 424 csn(HIGH);
jjeong 0:56ba69e447e3 425
jjeong 0:56ba69e447e3 426 wait_ms(100);
jjeong 0:56ba69e447e3 427
jjeong 0:56ba69e447e3 428
jjeong 0:56ba69e447e3 429
jjeong 0:56ba69e447e3 430
jjeong 0:56ba69e447e3 431 // Must allow the radio time to settle else configuration bits will not necessarily stick.
jjeong 0:56ba69e447e3 432 // This is actually only required following power up but some settling time also appears to
jjeong 0:56ba69e447e3 433 // be required after resets too. For full coverage, we'll always assume the worst.
jjeong 0:56ba69e447e3 434 // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
jjeong 0:56ba69e447e3 435 // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
jjeong 0:56ba69e447e3 436 // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
jjeong 0:56ba69e447e3 437 wait_ms( 5 ) ;
jjeong 0:56ba69e447e3 438
jjeong 0:56ba69e447e3 439 // Reset NRF_CONFIG and enable 16-bit CRC.
jjeong 0:56ba69e447e3 440 write_register( NRF_CONFIG, 0b00001100 ) ;
jjeong 0:56ba69e447e3 441
jjeong 0:56ba69e447e3 442 // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
jjeong 0:56ba69e447e3 443 // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
jjeong 0:56ba69e447e3 444 // sizes must never be used. See documentation for a more complete explanation.
jjeong 0:56ba69e447e3 445 setRetries(5,15);
jjeong 0:56ba69e447e3 446
jjeong 0:56ba69e447e3 447 // Reset value is MAX
jjeong 0:56ba69e447e3 448 //setPALevel( RF24_PA_MAX ) ;
jjeong 0:56ba69e447e3 449
jjeong 0:56ba69e447e3 450 // check for connected module and if this is a p nRF24l01 variant
jjeong 0:56ba69e447e3 451 //
jjeong 0:56ba69e447e3 452 if( setDataRate( RF24_250KBPS ) )
jjeong 0:56ba69e447e3 453 {
jjeong 0:56ba69e447e3 454 p_variant = true ;
jjeong 0:56ba69e447e3 455 }
jjeong 0:56ba69e447e3 456 setup = read_register(RF_SETUP);
jjeong 0:56ba69e447e3 457 /*if( setup == 0b00001110 ) // register default for nRF24L01P
jjeong 0:56ba69e447e3 458 {
jjeong 0:56ba69e447e3 459 p_variant = true ;
jjeong 0:56ba69e447e3 460 }*/
jjeong 0:56ba69e447e3 461
jjeong 0:56ba69e447e3 462 // Then set the data rate to the slowest (and most reliable) speed supported by all
jjeong 0:56ba69e447e3 463 // hardware.
jjeong 0:56ba69e447e3 464 //setDataRate( RF24_1MBPS ) ;
jjeong 0:56ba69e447e3 465 setDataRate( RF24_1MBPS ) ;
jjeong 0:56ba69e447e3 466
jjeong 0:56ba69e447e3 467 // Initialize CRC and request 2-byte (16bit) CRC
jjeong 0:56ba69e447e3 468 setCRCLength( RF24_CRC_16 ) ;
jjeong 0:56ba69e447e3 469
jjeong 0:56ba69e447e3 470 // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
jjeong 0:56ba69e447e3 471 toggle_features();
jjeong 0:56ba69e447e3 472 write_register(FEATURE,0 );
jjeong 0:56ba69e447e3 473 write_register(DYNPD,0);
jjeong 0:56ba69e447e3 474
jjeong 0:56ba69e447e3 475 // Reset current status
jjeong 0:56ba69e447e3 476 // Notice reset and flush is the last thing we do
jjeong 0:56ba69e447e3 477 write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:56ba69e447e3 478
jjeong 0:56ba69e447e3 479 // Set up default configuration. Callers can always change it later.
jjeong 0:56ba69e447e3 480 // This channel should be universally safe and not bleed over into adjacent
jjeong 0:56ba69e447e3 481 // spectrum.
jjeong 0:56ba69e447e3 482 setChannel(76);
jjeong 0:56ba69e447e3 483
jjeong 0:56ba69e447e3 484 // Flush buffers
jjeong 0:56ba69e447e3 485 flush_rx();
jjeong 0:56ba69e447e3 486 flush_tx();
jjeong 0:56ba69e447e3 487
jjeong 0:56ba69e447e3 488 powerUp(); //Power up by default when begin() is called
jjeong 0:56ba69e447e3 489
jjeong 0:56ba69e447e3 490 // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
jjeong 0:56ba69e447e3 491 // PTX should use only 22uA of power
jjeong 0:56ba69e447e3 492 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
jjeong 0:56ba69e447e3 493 printDetails();
jjeong 0:56ba69e447e3 494 // if setup is 0 or ff then there was no response from module
jjeong 0:56ba69e447e3 495 return ( setup != 0 && setup != 0xff );
jjeong 0:56ba69e447e3 496 }
jjeong 0:56ba69e447e3 497
jjeong 0:56ba69e447e3 498 /****************************************************************************/
jjeong 0:56ba69e447e3 499
jjeong 0:56ba69e447e3 500 void RF24::startListening(void)
jjeong 0:56ba69e447e3 501 {
jjeong 0:56ba69e447e3 502
jjeong 0:56ba69e447e3 503
jjeong 0:56ba69e447e3 504
jjeong 0:56ba69e447e3 505 write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
jjeong 0:56ba69e447e3 506 write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:56ba69e447e3 507 ce(HIGH);
jjeong 0:56ba69e447e3 508 // Restore the pipe0 adddress, if exists
jjeong 0:56ba69e447e3 509 if (pipe0_reading_address[0] > 0){
jjeong 0:56ba69e447e3 510 write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
jjeong 0:56ba69e447e3 511 }else{
jjeong 0:56ba69e447e3 512 closeReadingPipe(0);
jjeong 0:56ba69e447e3 513 }
jjeong 0:56ba69e447e3 514
jjeong 0:56ba69e447e3 515 // Flush buffers
jjeong 0:56ba69e447e3 516 //flush_rx();
jjeong 0:56ba69e447e3 517 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
jjeong 0:56ba69e447e3 518 flush_tx();
jjeong 0:56ba69e447e3 519 }
jjeong 0:56ba69e447e3 520
jjeong 0:56ba69e447e3 521 // Go!
jjeong 0:56ba69e447e3 522 //delayMicroseconds(100);
jjeong 0:56ba69e447e3 523 }
jjeong 0:56ba69e447e3 524
jjeong 0:56ba69e447e3 525 /****************************************************************************/
jjeong 0:56ba69e447e3 526 static const uint8_t child_pipe_enable[] PROGMEM =
jjeong 0:56ba69e447e3 527 {
jjeong 0:56ba69e447e3 528 ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
jjeong 0:56ba69e447e3 529 };
jjeong 0:56ba69e447e3 530
jjeong 0:56ba69e447e3 531 void RF24::stopListening(void)
jjeong 0:56ba69e447e3 532 {
jjeong 0:56ba69e447e3 533 ce(LOW);
jjeong 0:56ba69e447e3 534
jjeong 0:56ba69e447e3 535 wait_us(txRxDelay);
jjeong 0:56ba69e447e3 536
jjeong 0:56ba69e447e3 537 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
jjeong 0:56ba69e447e3 538 wait_us(txRxDelay); //200
jjeong 0:56ba69e447e3 539 flush_tx();
jjeong 0:56ba69e447e3 540 }
jjeong 0:56ba69e447e3 541 //flush_rx();
jjeong 0:56ba69e447e3 542 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
jjeong 0:56ba69e447e3 543
jjeong 0:56ba69e447e3 544
jjeong 0:56ba69e447e3 545 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
jjeong 0:56ba69e447e3 546
jjeong 0:56ba69e447e3 547 //delayMicroseconds(100);
jjeong 0:56ba69e447e3 548
jjeong 0:56ba69e447e3 549 }
jjeong 0:56ba69e447e3 550
jjeong 0:56ba69e447e3 551 /****************************************************************************/
jjeong 0:56ba69e447e3 552
jjeong 0:56ba69e447e3 553 void RF24::powerDown(void)
jjeong 0:56ba69e447e3 554 {
jjeong 0:56ba69e447e3 555 ce(LOW); // Guarantee CE is low on powerDown
jjeong 0:56ba69e447e3 556 write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
jjeong 0:56ba69e447e3 557 }
jjeong 0:56ba69e447e3 558
jjeong 0:56ba69e447e3 559 /****************************************************************************/
jjeong 0:56ba69e447e3 560
jjeong 0:56ba69e447e3 561 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
jjeong 0:56ba69e447e3 562 void RF24::powerUp(void)
jjeong 0:56ba69e447e3 563 {
jjeong 0:56ba69e447e3 564 uint8_t cfg = read_register(NRF_CONFIG);
jjeong 0:56ba69e447e3 565
jjeong 0:56ba69e447e3 566 // if not powered up then power up and wait for the radio to initialize
jjeong 0:56ba69e447e3 567 if (!(cfg & _BV(PWR_UP))){
jjeong 0:56ba69e447e3 568 write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
jjeong 0:56ba69e447e3 569
jjeong 0:56ba69e447e3 570 // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
jjeong 0:56ba69e447e3 571 // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
jjeong 0:56ba69e447e3 572 // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
jjeong 0:56ba69e447e3 573 wait_ms(5);
jjeong 0:56ba69e447e3 574 }
jjeong 0:56ba69e447e3 575 }
jjeong 0:56ba69e447e3 576
jjeong 0:56ba69e447e3 577 /******************************************************************/
jjeong 0:56ba69e447e3 578 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 579 void RF24::errNotify(){
jjeong 0:56ba69e447e3 580 #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 581 printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
jjeong 0:56ba69e447e3 582 #endif
jjeong 0:56ba69e447e3 583 #if defined (FAILURE_HANDLING)
jjeong 0:56ba69e447e3 584 failureDetected = 1;
jjeong 0:56ba69e447e3 585 #else
jjeong 0:56ba69e447e3 586 wait_ms(5000);
jjeong 0:56ba69e447e3 587 #endif
jjeong 0:56ba69e447e3 588 }
jjeong 0:56ba69e447e3 589 #endif
jjeong 0:56ba69e447e3 590 /******************************************************************/
jjeong 0:56ba69e447e3 591
jjeong 0:56ba69e447e3 592 //Similar to the previous write, clears the interrupt flags
jjeong 0:56ba69e447e3 593 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
jjeong 0:56ba69e447e3 594 {
jjeong 0:56ba69e447e3 595 //Start Writing
jjeong 0:56ba69e447e3 596 startFastWrite(buf,len,multicast);
jjeong 0:56ba69e447e3 597
jjeong 0:56ba69e447e3 598 //Wait until complete or failed
jjeong 0:56ba69e447e3 599 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 600 uint32_t timer = mainTimer.read_ms();
jjeong 0:56ba69e447e3 601 #endif
jjeong 0:56ba69e447e3 602
jjeong 0:56ba69e447e3 603 while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
jjeong 0:56ba69e447e3 604 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 605 if(mainTimer.read_ms() - timer > 95){
jjeong 0:56ba69e447e3 606 errNotify();
jjeong 0:56ba69e447e3 607 #if defined (FAILURE_HANDLING)
jjeong 0:56ba69e447e3 608 return 0;
jjeong 0:56ba69e447e3 609 #else
jjeong 0:56ba69e447e3 610 wait_ms(100);
jjeong 0:56ba69e447e3 611 #endif
jjeong 0:56ba69e447e3 612 }
jjeong 0:56ba69e447e3 613 #endif
jjeong 0:56ba69e447e3 614 }
jjeong 0:56ba69e447e3 615
jjeong 0:56ba69e447e3 616 ce(LOW);
jjeong 0:56ba69e447e3 617
jjeong 0:56ba69e447e3 618 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:56ba69e447e3 619
jjeong 0:56ba69e447e3 620 //Max retries exceeded
jjeong 0:56ba69e447e3 621 if( status & _BV(MAX_RT)){
jjeong 0:56ba69e447e3 622 flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
jjeong 0:56ba69e447e3 623 return 0;
jjeong 0:56ba69e447e3 624 }
jjeong 0:56ba69e447e3 625 //TX OK 1 or 0
jjeong 0:56ba69e447e3 626 return 1;
jjeong 0:56ba69e447e3 627 }
jjeong 0:56ba69e447e3 628
jjeong 0:56ba69e447e3 629 bool RF24::write( const void* buf, uint8_t len ){
jjeong 0:56ba69e447e3 630 return write(buf,len,0);
jjeong 0:56ba69e447e3 631 }
jjeong 0:56ba69e447e3 632 /****************************************************************************/
jjeong 0:56ba69e447e3 633
jjeong 0:56ba69e447e3 634 //For general use, the interrupt flags are not important to clear
jjeong 0:56ba69e447e3 635 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
jjeong 0:56ba69e447e3 636 {
jjeong 0:56ba69e447e3 637 //Block until the FIFO is NOT full.
jjeong 0:56ba69e447e3 638 //Keep track of the MAX retries and set auto-retry if seeing failures
jjeong 0:56ba69e447e3 639 //This way the FIFO will fill up and allow blocking until packets go through
jjeong 0:56ba69e447e3 640 //The radio will auto-clear everything in the FIFO as long as CE remains high
jjeong 0:56ba69e447e3 641
jjeong 0:56ba69e447e3 642 uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started
jjeong 0:56ba69e447e3 643
jjeong 0:56ba69e447e3 644 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
jjeong 0:56ba69e447e3 645
jjeong 0:56ba69e447e3 646 if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached
jjeong 0:56ba69e447e3 647 reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
jjeong 0:56ba69e447e3 648 if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0
jjeong 0:56ba69e447e3 649 }
jjeong 0:56ba69e447e3 650 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 651 if(mainTimer.read_ms() - timer > (timeout+95) ){
jjeong 0:56ba69e447e3 652 errNotify();
jjeong 0:56ba69e447e3 653 #if defined (FAILURE_HANDLING)
jjeong 0:56ba69e447e3 654 return 0;
jjeong 0:56ba69e447e3 655 #endif
jjeong 0:56ba69e447e3 656 }
jjeong 0:56ba69e447e3 657 #endif
jjeong 0:56ba69e447e3 658
jjeong 0:56ba69e447e3 659 }
jjeong 0:56ba69e447e3 660
jjeong 0:56ba69e447e3 661 //Start Writing
jjeong 0:56ba69e447e3 662 startFastWrite(buf,len,0); //Write the payload if a buffer is clear
jjeong 0:56ba69e447e3 663
jjeong 0:56ba69e447e3 664 return 1; //Return 1 to indicate successful transmission
jjeong 0:56ba69e447e3 665 }
jjeong 0:56ba69e447e3 666
jjeong 0:56ba69e447e3 667 /****************************************************************************/
jjeong 0:56ba69e447e3 668
jjeong 0:56ba69e447e3 669 void RF24::reUseTX(){
jjeong 0:56ba69e447e3 670 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
jjeong 0:56ba69e447e3 671 spiTrans( REUSE_TX_PL );
jjeong 0:56ba69e447e3 672 ce(LOW); //Re-Transfer packet
jjeong 0:56ba69e447e3 673 ce(HIGH);
jjeong 0:56ba69e447e3 674 }
jjeong 0:56ba69e447e3 675
jjeong 0:56ba69e447e3 676 /****************************************************************************/
jjeong 0:56ba69e447e3 677
jjeong 0:56ba69e447e3 678 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
jjeong 0:56ba69e447e3 679 {
jjeong 0:56ba69e447e3 680 //Block until the FIFO is NOT full.
jjeong 0:56ba69e447e3 681 //Keep track of the MAX retries and set auto-retry if seeing failures
jjeong 0:56ba69e447e3 682 //Return 0 so the user can control the retrys and set a timer or failure counter if required
jjeong 0:56ba69e447e3 683 //The radio will auto-clear everything in the FIFO as long as CE remains high
jjeong 0:56ba69e447e3 684
jjeong 0:56ba69e447e3 685 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 686 uint32_t timer = mainTimer.read_ms();
jjeong 0:56ba69e447e3 687 #endif
jjeong 0:56ba69e447e3 688
jjeong 0:56ba69e447e3 689 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
jjeong 0:56ba69e447e3 690
jjeong 0:56ba69e447e3 691 if( get_status() & _BV(MAX_RT)){
jjeong 0:56ba69e447e3 692 //reUseTX(); //Set re-transmit
jjeong 0:56ba69e447e3 693 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
jjeong 0:56ba69e447e3 694 return 0; //Return 0. The previous payload has been retransmitted
jjeong 0:56ba69e447e3 695 //From the user perspective, if you get a 0, just keep trying to send the same payload
jjeong 0:56ba69e447e3 696 }
jjeong 0:56ba69e447e3 697 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 698 if(mainTimer.read_ms() - timer > 95 ){
jjeong 0:56ba69e447e3 699 errNotify();
jjeong 0:56ba69e447e3 700 #if defined (FAILURE_HANDLING)
jjeong 0:56ba69e447e3 701 return 0;
jjeong 0:56ba69e447e3 702 #endif
jjeong 0:56ba69e447e3 703 }
jjeong 0:56ba69e447e3 704 #endif
jjeong 0:56ba69e447e3 705 }
jjeong 0:56ba69e447e3 706 //Start Writing
jjeong 0:56ba69e447e3 707 startFastWrite(buf,len,multicast);
jjeong 0:56ba69e447e3 708
jjeong 0:56ba69e447e3 709 return 1;
jjeong 0:56ba69e447e3 710 }
jjeong 0:56ba69e447e3 711
jjeong 0:56ba69e447e3 712 bool RF24::writeFast( const void* buf, uint8_t len ){
jjeong 0:56ba69e447e3 713 return writeFast(buf,len,0);
jjeong 0:56ba69e447e3 714 }
jjeong 0:56ba69e447e3 715
jjeong 0:56ba69e447e3 716 /****************************************************************************/
jjeong 0:56ba69e447e3 717
jjeong 0:56ba69e447e3 718 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
jjeong 0:56ba69e447e3 719 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
jjeong 0:56ba69e447e3 720 //Otherwise we enter Standby-II mode, which is still faster than standby mode
jjeong 0:56ba69e447e3 721 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
jjeong 0:56ba69e447e3 722
jjeong 0:56ba69e447e3 723 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
jjeong 0:56ba69e447e3 724
jjeong 0:56ba69e447e3 725 //write_payload( buf,len);
jjeong 0:56ba69e447e3 726 write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
jjeong 0:56ba69e447e3 727 if(startTx){
jjeong 0:56ba69e447e3 728 ce(HIGH);
jjeong 0:56ba69e447e3 729 }
jjeong 0:56ba69e447e3 730
jjeong 0:56ba69e447e3 731 }
jjeong 0:56ba69e447e3 732
jjeong 0:56ba69e447e3 733 /****************************************************************************/
jjeong 0:56ba69e447e3 734
jjeong 0:56ba69e447e3 735 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
jjeong 0:56ba69e447e3 736 //Allows the library to pass all tests
jjeong 0:56ba69e447e3 737 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
jjeong 0:56ba69e447e3 738
jjeong 0:56ba69e447e3 739 // Send the payload
jjeong 0:56ba69e447e3 740
jjeong 0:56ba69e447e3 741 //write_payload( buf, len );
jjeong 0:56ba69e447e3 742 write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
jjeong 0:56ba69e447e3 743 ce(HIGH);
jjeong 0:56ba69e447e3 744
jjeong 0:56ba69e447e3 745 wait_us(10);
jjeong 0:56ba69e447e3 746
jjeong 0:56ba69e447e3 747 ce(LOW);
jjeong 0:56ba69e447e3 748
jjeong 0:56ba69e447e3 749
jjeong 0:56ba69e447e3 750 }
jjeong 0:56ba69e447e3 751
jjeong 0:56ba69e447e3 752 /****************************************************************************/
jjeong 0:56ba69e447e3 753
jjeong 0:56ba69e447e3 754 bool RF24::rxFifoFull(){
jjeong 0:56ba69e447e3 755 return read_register(FIFO_STATUS) & _BV(RX_FULL);
jjeong 0:56ba69e447e3 756 }
jjeong 0:56ba69e447e3 757 /****************************************************************************/
jjeong 0:56ba69e447e3 758
jjeong 0:56ba69e447e3 759 bool RF24::txStandBy(){
jjeong 0:56ba69e447e3 760
jjeong 0:56ba69e447e3 761 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 762 uint32_t timeout = mainTimer.read_ms();
jjeong 0:56ba69e447e3 763 #endif
jjeong 0:56ba69e447e3 764 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
jjeong 0:56ba69e447e3 765 if( get_status() & _BV(MAX_RT)){
jjeong 0:56ba69e447e3 766 write_register(NRF_STATUS,_BV(MAX_RT) );
jjeong 0:56ba69e447e3 767 ce(LOW);
jjeong 0:56ba69e447e3 768 flush_tx(); //Non blocking, flush the data
jjeong 0:56ba69e447e3 769 return 0;
jjeong 0:56ba69e447e3 770 }
jjeong 0:56ba69e447e3 771 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 772 if( mainTimer.read_ms() - timeout > 95){
jjeong 0:56ba69e447e3 773 errNotify();
jjeong 0:56ba69e447e3 774 #if defined (FAILURE_HANDLING)
jjeong 0:56ba69e447e3 775 return 0;
jjeong 0:56ba69e447e3 776 #endif
jjeong 0:56ba69e447e3 777 }
jjeong 0:56ba69e447e3 778 #endif
jjeong 0:56ba69e447e3 779 }
jjeong 0:56ba69e447e3 780
jjeong 0:56ba69e447e3 781 ce(LOW); //Set STANDBY-I mode
jjeong 0:56ba69e447e3 782 return 1;
jjeong 0:56ba69e447e3 783 }
jjeong 0:56ba69e447e3 784
jjeong 0:56ba69e447e3 785 /****************************************************************************/
jjeong 0:56ba69e447e3 786
jjeong 0:56ba69e447e3 787 bool RF24::txStandBy(uint32_t timeout, bool startTx){
jjeong 0:56ba69e447e3 788
jjeong 0:56ba69e447e3 789 if(startTx){
jjeong 0:56ba69e447e3 790 stopListening();
jjeong 0:56ba69e447e3 791 ce(HIGH);
jjeong 0:56ba69e447e3 792 }
jjeong 0:56ba69e447e3 793 uint32_t start = mainTimer.read_ms();
jjeong 0:56ba69e447e3 794
jjeong 0:56ba69e447e3 795 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
jjeong 0:56ba69e447e3 796 if( get_status() & _BV(MAX_RT)){
jjeong 0:56ba69e447e3 797 write_register(NRF_STATUS,_BV(MAX_RT) );
jjeong 0:56ba69e447e3 798 ce(LOW); //Set re-transmit
jjeong 0:56ba69e447e3 799 ce(HIGH);
jjeong 0:56ba69e447e3 800 if(mainTimer.read_ms() - start >= timeout){
jjeong 0:56ba69e447e3 801 ce(LOW); flush_tx(); return 0;
jjeong 0:56ba69e447e3 802 }
jjeong 0:56ba69e447e3 803 }
jjeong 0:56ba69e447e3 804 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
jjeong 0:56ba69e447e3 805 if( mainTimer.read_ms() - start > (timeout+95)){
jjeong 0:56ba69e447e3 806 errNotify();
jjeong 0:56ba69e447e3 807 #if defined (FAILURE_HANDLING)
jjeong 0:56ba69e447e3 808 return 0;
jjeong 0:56ba69e447e3 809 #endif
jjeong 0:56ba69e447e3 810 }
jjeong 0:56ba69e447e3 811 #endif
jjeong 0:56ba69e447e3 812 }
jjeong 0:56ba69e447e3 813
jjeong 0:56ba69e447e3 814
jjeong 0:56ba69e447e3 815 ce(LOW); //Set STANDBY-I mode
jjeong 0:56ba69e447e3 816 return 1;
jjeong 0:56ba69e447e3 817
jjeong 0:56ba69e447e3 818 }
jjeong 0:56ba69e447e3 819
jjeong 0:56ba69e447e3 820 /****************************************************************************/
jjeong 0:56ba69e447e3 821
jjeong 0:56ba69e447e3 822 void RF24::maskIRQ(bool tx, bool fail, bool rx){
jjeong 0:56ba69e447e3 823
jjeong 0:56ba69e447e3 824 uint8_t config = read_register(NRF_CONFIG);
jjeong 0:56ba69e447e3 825 /* clear the interrupt flags */
jjeong 0:56ba69e447e3 826 config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
jjeong 0:56ba69e447e3 827 /* set the specified interrupt flags */
jjeong 0:56ba69e447e3 828 config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
jjeong 0:56ba69e447e3 829 write_register(NRF_CONFIG, config);
jjeong 0:56ba69e447e3 830 }
jjeong 0:56ba69e447e3 831
jjeong 0:56ba69e447e3 832 /****************************************************************************/
jjeong 0:56ba69e447e3 833
jjeong 0:56ba69e447e3 834 uint8_t RF24::getDynamicPayloadSize(void)
jjeong 0:56ba69e447e3 835 {
jjeong 0:56ba69e447e3 836 uint8_t result = 0;
jjeong 0:56ba69e447e3 837
jjeong 0:56ba69e447e3 838
jjeong 0:56ba69e447e3 839 beginTransaction();
jjeong 0:56ba69e447e3 840 spi.write( R_RX_PL_WID );
jjeong 0:56ba69e447e3 841 result = spi.write(0xff);
jjeong 0:56ba69e447e3 842 endTransaction();
jjeong 0:56ba69e447e3 843
jjeong 0:56ba69e447e3 844
jjeong 0:56ba69e447e3 845 if(result > 32) { flush_rx(); wait_ms(2); return 0; }
jjeong 0:56ba69e447e3 846 return result;
jjeong 0:56ba69e447e3 847 }
jjeong 0:56ba69e447e3 848
jjeong 0:56ba69e447e3 849 /****************************************************************************/
jjeong 0:56ba69e447e3 850
jjeong 0:56ba69e447e3 851 bool RF24::available(void)
jjeong 0:56ba69e447e3 852 {
jjeong 0:56ba69e447e3 853 return available(NULL);
jjeong 0:56ba69e447e3 854 }
jjeong 0:56ba69e447e3 855
jjeong 0:56ba69e447e3 856 /****************************************************************************/
jjeong 0:56ba69e447e3 857
jjeong 0:56ba69e447e3 858 bool RF24::available(uint8_t* pipe_num)
jjeong 0:56ba69e447e3 859 {
jjeong 0:56ba69e447e3 860 if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
jjeong 0:56ba69e447e3 861
jjeong 0:56ba69e447e3 862 // If the caller wants the pipe number, include that
jjeong 0:56ba69e447e3 863 if ( pipe_num ){
jjeong 0:56ba69e447e3 864 uint8_t status = get_status();
jjeong 0:56ba69e447e3 865 *pipe_num = ( status >> RX_P_NO ) & 0b111;
jjeong 0:56ba69e447e3 866 }
jjeong 0:56ba69e447e3 867 return 1;
jjeong 0:56ba69e447e3 868 }
jjeong 0:56ba69e447e3 869
jjeong 0:56ba69e447e3 870
jjeong 0:56ba69e447e3 871 return 0;
jjeong 0:56ba69e447e3 872
jjeong 0:56ba69e447e3 873
jjeong 0:56ba69e447e3 874 }
jjeong 0:56ba69e447e3 875
jjeong 0:56ba69e447e3 876 /****************************************************************************/
jjeong 0:56ba69e447e3 877
jjeong 0:56ba69e447e3 878 void RF24::read( void* buf, uint8_t len ){
jjeong 0:56ba69e447e3 879
jjeong 0:56ba69e447e3 880 // Fetch the payload
jjeong 0:56ba69e447e3 881 read_payload( buf, len );
jjeong 0:56ba69e447e3 882
jjeong 0:56ba69e447e3 883 //Clear the two possible interrupt flags with one command
jjeong 0:56ba69e447e3 884 write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
jjeong 0:56ba69e447e3 885
jjeong 0:56ba69e447e3 886 }
jjeong 0:56ba69e447e3 887
jjeong 0:56ba69e447e3 888 /****************************************************************************/
jjeong 0:56ba69e447e3 889
jjeong 0:56ba69e447e3 890 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
jjeong 0:56ba69e447e3 891 {
jjeong 0:56ba69e447e3 892 // Read the status & reset the status in one easy call
jjeong 0:56ba69e447e3 893 // Or is that such a good idea?
jjeong 0:56ba69e447e3 894 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
jjeong 0:56ba69e447e3 895
jjeong 0:56ba69e447e3 896 // Report to the user what happened
jjeong 0:56ba69e447e3 897 tx_ok = status & _BV(TX_DS);
jjeong 0:56ba69e447e3 898 tx_fail = status & _BV(MAX_RT);
jjeong 0:56ba69e447e3 899 rx_ready = status & _BV(RX_DR);
jjeong 0:56ba69e447e3 900 }
jjeong 0:56ba69e447e3 901
jjeong 0:56ba69e447e3 902 /****************************************************************************/
jjeong 0:56ba69e447e3 903
jjeong 0:56ba69e447e3 904 void RF24::openWritingPipe(uint64_t value)
jjeong 0:56ba69e447e3 905 {
jjeong 0:56ba69e447e3 906 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
jjeong 0:56ba69e447e3 907 // expects it LSB first too, so we're good.
jjeong 0:56ba69e447e3 908
jjeong 0:56ba69e447e3 909 write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
jjeong 0:56ba69e447e3 910 write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
jjeong 0:56ba69e447e3 911
jjeong 0:56ba69e447e3 912
jjeong 0:56ba69e447e3 913 //const uint8_t max_payload_size = 32;
jjeong 0:56ba69e447e3 914 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
jjeong 0:56ba69e447e3 915 write_register(RX_PW_P0,payload_size);
jjeong 0:56ba69e447e3 916 }
jjeong 0:56ba69e447e3 917
jjeong 0:56ba69e447e3 918 /****************************************************************************/
jjeong 0:56ba69e447e3 919 void RF24::openWritingPipe(const uint8_t *address)
jjeong 0:56ba69e447e3 920 {
jjeong 0:56ba69e447e3 921 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
jjeong 0:56ba69e447e3 922 // expects it LSB first too, so we're good.
jjeong 0:56ba69e447e3 923
jjeong 0:56ba69e447e3 924 write_register(RX_ADDR_P0,address, addr_width);
jjeong 0:56ba69e447e3 925 write_register(TX_ADDR, address, addr_width);
jjeong 0:56ba69e447e3 926
jjeong 0:56ba69e447e3 927 //const uint8_t max_payload_size = 32;
jjeong 0:56ba69e447e3 928 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
jjeong 0:56ba69e447e3 929 write_register(RX_PW_P0,payload_size);
jjeong 0:56ba69e447e3 930 }
jjeong 0:56ba69e447e3 931
jjeong 0:56ba69e447e3 932 /****************************************************************************/
jjeong 0:56ba69e447e3 933 static const uint8_t child_pipe[] PROGMEM =
jjeong 0:56ba69e447e3 934 {
jjeong 0:56ba69e447e3 935 RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
jjeong 0:56ba69e447e3 936 };
jjeong 0:56ba69e447e3 937 static const uint8_t child_payload_size[] PROGMEM =
jjeong 0:56ba69e447e3 938 {
jjeong 0:56ba69e447e3 939 RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
jjeong 0:56ba69e447e3 940 };
jjeong 0:56ba69e447e3 941
jjeong 0:56ba69e447e3 942
jjeong 0:56ba69e447e3 943 void RF24::openReadingPipe(uint8_t child, uint64_t address)
jjeong 0:56ba69e447e3 944 {
jjeong 0:56ba69e447e3 945 // If this is pipe 0, cache the address. This is needed because
jjeong 0:56ba69e447e3 946 // openWritingPipe() will overwrite the pipe 0 address, so
jjeong 0:56ba69e447e3 947 // startListening() will have to restore it.
jjeong 0:56ba69e447e3 948 if (child == 0){
jjeong 0:56ba69e447e3 949 memcpy(pipe0_reading_address,&address,addr_width);
jjeong 0:56ba69e447e3 950 }
jjeong 0:56ba69e447e3 951
jjeong 0:56ba69e447e3 952 if (child <= 6)
jjeong 0:56ba69e447e3 953 {
jjeong 0:56ba69e447e3 954 // For pipes 2-5, only write the LSB
jjeong 0:56ba69e447e3 955 if ( child < 2 )
jjeong 0:56ba69e447e3 956 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
jjeong 0:56ba69e447e3 957 else
jjeong 0:56ba69e447e3 958 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
jjeong 0:56ba69e447e3 959
jjeong 0:56ba69e447e3 960 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
jjeong 0:56ba69e447e3 961
jjeong 0:56ba69e447e3 962 // Note it would be more efficient to set all of the bits for all open
jjeong 0:56ba69e447e3 963 // pipes at once. However, I thought it would make the calling code
jjeong 0:56ba69e447e3 964 // more simple to do it this way.
jjeong 0:56ba69e447e3 965 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
jjeong 0:56ba69e447e3 966 }
jjeong 0:56ba69e447e3 967 }
jjeong 0:56ba69e447e3 968
jjeong 0:56ba69e447e3 969 /****************************************************************************/
jjeong 0:56ba69e447e3 970 void RF24::setAddressWidth(uint8_t a_width){
jjeong 0:56ba69e447e3 971
jjeong 0:56ba69e447e3 972 if(a_width -= 2){
jjeong 0:56ba69e447e3 973 write_register(SETUP_AW,a_width%4);
jjeong 0:56ba69e447e3 974 addr_width = (a_width%4) + 2;
jjeong 0:56ba69e447e3 975 }
jjeong 0:56ba69e447e3 976
jjeong 0:56ba69e447e3 977 }
jjeong 0:56ba69e447e3 978
jjeong 0:56ba69e447e3 979 /****************************************************************************/
jjeong 0:56ba69e447e3 980
jjeong 0:56ba69e447e3 981 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
jjeong 0:56ba69e447e3 982 {
jjeong 0:56ba69e447e3 983 // If this is pipe 0, cache the address. This is needed because
jjeong 0:56ba69e447e3 984 // openWritingPipe() will overwrite the pipe 0 address, so
jjeong 0:56ba69e447e3 985 // startListening() will have to restore it.
jjeong 0:56ba69e447e3 986 if (child == 0){
jjeong 0:56ba69e447e3 987 memcpy(pipe0_reading_address,address,addr_width);
jjeong 0:56ba69e447e3 988 }
jjeong 0:56ba69e447e3 989 if (child <= 6)
jjeong 0:56ba69e447e3 990 {
jjeong 0:56ba69e447e3 991 // For pipes 2-5, only write the LSB
jjeong 0:56ba69e447e3 992 if ( child < 2 ){
jjeong 0:56ba69e447e3 993 write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
jjeong 0:56ba69e447e3 994 }else{
jjeong 0:56ba69e447e3 995 write_register(pgm_read_byte(&child_pipe[child]), address, 1);
jjeong 0:56ba69e447e3 996 }
jjeong 0:56ba69e447e3 997 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
jjeong 0:56ba69e447e3 998
jjeong 0:56ba69e447e3 999 // Note it would be more efficient to set all of the bits for all open
jjeong 0:56ba69e447e3 1000 // pipes at once. However, I thought it would make the calling code
jjeong 0:56ba69e447e3 1001 // more simple to do it this way.
jjeong 0:56ba69e447e3 1002 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
jjeong 0:56ba69e447e3 1003
jjeong 0:56ba69e447e3 1004 }
jjeong 0:56ba69e447e3 1005 }
jjeong 0:56ba69e447e3 1006
jjeong 0:56ba69e447e3 1007 /****************************************************************************/
jjeong 0:56ba69e447e3 1008
jjeong 0:56ba69e447e3 1009 void RF24::closeReadingPipe( uint8_t pipe )
jjeong 0:56ba69e447e3 1010 {
jjeong 0:56ba69e447e3 1011 write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
jjeong 0:56ba69e447e3 1012 }
jjeong 0:56ba69e447e3 1013
jjeong 0:56ba69e447e3 1014 /****************************************************************************/
jjeong 0:56ba69e447e3 1015
jjeong 0:56ba69e447e3 1016 void RF24::toggle_features(void)
jjeong 0:56ba69e447e3 1017 {
jjeong 0:56ba69e447e3 1018 beginTransaction();
jjeong 0:56ba69e447e3 1019 spi.write( ACTIVATE );
jjeong 0:56ba69e447e3 1020 spi.write( 0x73 );
jjeong 0:56ba69e447e3 1021 endTransaction();
jjeong 0:56ba69e447e3 1022 }
jjeong 0:56ba69e447e3 1023
jjeong 0:56ba69e447e3 1024 /****************************************************************************/
jjeong 0:56ba69e447e3 1025
jjeong 0:56ba69e447e3 1026 void RF24::enableDynamicPayloads(void)
jjeong 0:56ba69e447e3 1027 {
jjeong 0:56ba69e447e3 1028 // Enable dynamic payload throughout the system
jjeong 0:56ba69e447e3 1029
jjeong 0:56ba69e447e3 1030 //toggle_features();
jjeong 0:56ba69e447e3 1031 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
jjeong 0:56ba69e447e3 1032
jjeong 0:56ba69e447e3 1033
jjeong 0:56ba69e447e3 1034 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
jjeong 0:56ba69e447e3 1035
jjeong 0:56ba69e447e3 1036 // Enable dynamic payload on all pipes
jjeong 0:56ba69e447e3 1037 //
jjeong 0:56ba69e447e3 1038 // Not sure the use case of only having dynamic payload on certain
jjeong 0:56ba69e447e3 1039 // pipes, so the library does not support it.
jjeong 0:56ba69e447e3 1040 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
jjeong 0:56ba69e447e3 1041
jjeong 0:56ba69e447e3 1042 dynamic_payloads_enabled = true;
jjeong 0:56ba69e447e3 1043 }
jjeong 0:56ba69e447e3 1044
jjeong 0:56ba69e447e3 1045 /****************************************************************************/
jjeong 0:56ba69e447e3 1046
jjeong 0:56ba69e447e3 1047 void RF24::enableAckPayload(void)
jjeong 0:56ba69e447e3 1048 {
jjeong 0:56ba69e447e3 1049 //
jjeong 0:56ba69e447e3 1050 // enable ack payload and dynamic payload features
jjeong 0:56ba69e447e3 1051 //
jjeong 0:56ba69e447e3 1052
jjeong 0:56ba69e447e3 1053 //toggle_features();
jjeong 0:56ba69e447e3 1054 write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
jjeong 0:56ba69e447e3 1055
jjeong 0:56ba69e447e3 1056 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
jjeong 0:56ba69e447e3 1057
jjeong 0:56ba69e447e3 1058 //
jjeong 0:56ba69e447e3 1059 // Enable dynamic payload on pipes 0 & 1
jjeong 0:56ba69e447e3 1060 //
jjeong 0:56ba69e447e3 1061
jjeong 0:56ba69e447e3 1062 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
jjeong 0:56ba69e447e3 1063 dynamic_payloads_enabled = true;
jjeong 0:56ba69e447e3 1064 }
jjeong 0:56ba69e447e3 1065
jjeong 0:56ba69e447e3 1066 /****************************************************************************/
jjeong 0:56ba69e447e3 1067
jjeong 0:56ba69e447e3 1068 void RF24::enableDynamicAck(void){
jjeong 0:56ba69e447e3 1069 //
jjeong 0:56ba69e447e3 1070 // enable dynamic ack features
jjeong 0:56ba69e447e3 1071 //
jjeong 0:56ba69e447e3 1072 //toggle_features();
jjeong 0:56ba69e447e3 1073 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
jjeong 0:56ba69e447e3 1074
jjeong 0:56ba69e447e3 1075 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
jjeong 0:56ba69e447e3 1076
jjeong 0:56ba69e447e3 1077
jjeong 0:56ba69e447e3 1078 }
jjeong 0:56ba69e447e3 1079
jjeong 0:56ba69e447e3 1080 /****************************************************************************/
jjeong 0:56ba69e447e3 1081
jjeong 0:56ba69e447e3 1082 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
jjeong 0:56ba69e447e3 1083 {
jjeong 0:56ba69e447e3 1084 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
jjeong 0:56ba69e447e3 1085
jjeong 0:56ba69e447e3 1086 uint8_t data_len = rf24_min(len,32);
jjeong 0:56ba69e447e3 1087
jjeong 0:56ba69e447e3 1088
jjeong 0:56ba69e447e3 1089
jjeong 0:56ba69e447e3 1090 beginTransaction();
jjeong 0:56ba69e447e3 1091 spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
jjeong 0:56ba69e447e3 1092
jjeong 0:56ba69e447e3 1093 while ( data_len-- )
jjeong 0:56ba69e447e3 1094 spi.write(*current++);
jjeong 0:56ba69e447e3 1095 endTransaction();
jjeong 0:56ba69e447e3 1096
jjeong 0:56ba69e447e3 1097
jjeong 0:56ba69e447e3 1098
jjeong 0:56ba69e447e3 1099 }
jjeong 0:56ba69e447e3 1100
jjeong 0:56ba69e447e3 1101 /****************************************************************************/
jjeong 0:56ba69e447e3 1102
jjeong 0:56ba69e447e3 1103 bool RF24::isAckPayloadAvailable(void)
jjeong 0:56ba69e447e3 1104 {
jjeong 0:56ba69e447e3 1105 return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
jjeong 0:56ba69e447e3 1106 }
jjeong 0:56ba69e447e3 1107
jjeong 0:56ba69e447e3 1108 /****************************************************************************/
jjeong 0:56ba69e447e3 1109
jjeong 0:56ba69e447e3 1110 bool RF24::isPVariant(void)
jjeong 0:56ba69e447e3 1111 {
jjeong 0:56ba69e447e3 1112 return p_variant ;
jjeong 0:56ba69e447e3 1113 }
jjeong 0:56ba69e447e3 1114
jjeong 0:56ba69e447e3 1115 /****************************************************************************/
jjeong 0:56ba69e447e3 1116
jjeong 0:56ba69e447e3 1117 void RF24::setAutoAck(bool enable)
jjeong 0:56ba69e447e3 1118 {
jjeong 0:56ba69e447e3 1119 if ( enable )
jjeong 0:56ba69e447e3 1120 write_register(EN_AA, 0b111111);
jjeong 0:56ba69e447e3 1121 else
jjeong 0:56ba69e447e3 1122 write_register(EN_AA, 0);
jjeong 0:56ba69e447e3 1123 }
jjeong 0:56ba69e447e3 1124
jjeong 0:56ba69e447e3 1125 /****************************************************************************/
jjeong 0:56ba69e447e3 1126
jjeong 0:56ba69e447e3 1127 void RF24::setAutoAck( uint8_t pipe, bool enable )
jjeong 0:56ba69e447e3 1128 {
jjeong 0:56ba69e447e3 1129 if ( pipe <= 6 )
jjeong 0:56ba69e447e3 1130 {
jjeong 0:56ba69e447e3 1131 uint8_t en_aa = read_register( EN_AA ) ;
jjeong 0:56ba69e447e3 1132 if( enable )
jjeong 0:56ba69e447e3 1133 {
jjeong 0:56ba69e447e3 1134 en_aa |= _BV(pipe) ;
jjeong 0:56ba69e447e3 1135 }
jjeong 0:56ba69e447e3 1136 else
jjeong 0:56ba69e447e3 1137 {
jjeong 0:56ba69e447e3 1138 en_aa &= ~_BV(pipe) ;
jjeong 0:56ba69e447e3 1139 }
jjeong 0:56ba69e447e3 1140 write_register( EN_AA, en_aa ) ;
jjeong 0:56ba69e447e3 1141 }
jjeong 0:56ba69e447e3 1142 }
jjeong 0:56ba69e447e3 1143
jjeong 0:56ba69e447e3 1144 /****************************************************************************/
jjeong 0:56ba69e447e3 1145
jjeong 0:56ba69e447e3 1146 bool RF24::testCarrier(void)
jjeong 0:56ba69e447e3 1147 {
jjeong 0:56ba69e447e3 1148 return ( read_register(CD) & 1 );
jjeong 0:56ba69e447e3 1149 }
jjeong 0:56ba69e447e3 1150
jjeong 0:56ba69e447e3 1151 /****************************************************************************/
jjeong 0:56ba69e447e3 1152
jjeong 0:56ba69e447e3 1153 bool RF24::testRPD(void)
jjeong 0:56ba69e447e3 1154 {
jjeong 0:56ba69e447e3 1155 return ( read_register(RPD) & 1 ) ;
jjeong 0:56ba69e447e3 1156 }
jjeong 0:56ba69e447e3 1157
jjeong 0:56ba69e447e3 1158 /****************************************************************************/
jjeong 0:56ba69e447e3 1159
jjeong 0:56ba69e447e3 1160 void RF24::setPALevel(uint8_t level)
jjeong 0:56ba69e447e3 1161 {
jjeong 0:56ba69e447e3 1162
jjeong 0:56ba69e447e3 1163 uint8_t setup = read_register(RF_SETUP) & 0b11111000;
jjeong 0:56ba69e447e3 1164
jjeong 0:56ba69e447e3 1165 if(level > 3){ // If invalid level, go to max PA
jjeong 0:56ba69e447e3 1166 level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
jjeong 0:56ba69e447e3 1167 }else{
jjeong 0:56ba69e447e3 1168 level = (level << 1) + 1; // Else set level as requested
jjeong 0:56ba69e447e3 1169 }
jjeong 0:56ba69e447e3 1170
jjeong 0:56ba69e447e3 1171
jjeong 0:56ba69e447e3 1172 write_register( RF_SETUP, setup |= level ) ; // Write it to the chip
jjeong 0:56ba69e447e3 1173 }
jjeong 0:56ba69e447e3 1174
jjeong 0:56ba69e447e3 1175 /****************************************************************************/
jjeong 0:56ba69e447e3 1176
jjeong 0:56ba69e447e3 1177 uint8_t RF24::getPALevel(void)
jjeong 0:56ba69e447e3 1178 {
jjeong 0:56ba69e447e3 1179
jjeong 0:56ba69e447e3 1180 return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
jjeong 0:56ba69e447e3 1181 }
jjeong 0:56ba69e447e3 1182
jjeong 0:56ba69e447e3 1183 /****************************************************************************/
jjeong 0:56ba69e447e3 1184
jjeong 0:56ba69e447e3 1185 bool RF24::setDataRate(rf24_datarate_e speed)
jjeong 0:56ba69e447e3 1186 {
jjeong 0:56ba69e447e3 1187 bool result = false;
jjeong 0:56ba69e447e3 1188 uint8_t setup = read_register(RF_SETUP) ;
jjeong 0:56ba69e447e3 1189
jjeong 0:56ba69e447e3 1190 // HIGH and LOW '00' is 1Mbs - our default
jjeong 0:56ba69e447e3 1191 setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
jjeong 0:56ba69e447e3 1192
jjeong 0:56ba69e447e3 1193
jjeong 0:56ba69e447e3 1194
jjeong 0:56ba69e447e3 1195
jjeong 0:56ba69e447e3 1196 txRxDelay=85;
jjeong 0:56ba69e447e3 1197
jjeong 0:56ba69e447e3 1198 if( speed == RF24_250KBPS )
jjeong 0:56ba69e447e3 1199 {
jjeong 0:56ba69e447e3 1200 // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
jjeong 0:56ba69e447e3 1201 // Making it '10'.
jjeong 0:56ba69e447e3 1202 setup |= _BV( RF_DR_LOW ) ;
jjeong 0:56ba69e447e3 1203
jjeong 0:56ba69e447e3 1204
jjeong 0:56ba69e447e3 1205
jjeong 0:56ba69e447e3 1206 txRxDelay=155;
jjeong 0:56ba69e447e3 1207
jjeong 0:56ba69e447e3 1208 }
jjeong 0:56ba69e447e3 1209 else
jjeong 0:56ba69e447e3 1210 {
jjeong 0:56ba69e447e3 1211 // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
jjeong 0:56ba69e447e3 1212 // Making it '01'
jjeong 0:56ba69e447e3 1213 if ( speed == RF24_2MBPS )
jjeong 0:56ba69e447e3 1214 {
jjeong 0:56ba69e447e3 1215 setup |= _BV(RF_DR_HIGH);
jjeong 0:56ba69e447e3 1216
jjeong 0:56ba69e447e3 1217
jjeong 0:56ba69e447e3 1218 //txRxDelay=65;
jjeong 0:56ba69e447e3 1219 txRxDelay=15; //mbed works fine with this latency
jjeong 0:56ba69e447e3 1220
jjeong 0:56ba69e447e3 1221 }
jjeong 0:56ba69e447e3 1222 }
jjeong 0:56ba69e447e3 1223 write_register(RF_SETUP,setup);
jjeong 0:56ba69e447e3 1224
jjeong 0:56ba69e447e3 1225 // Verify our result
jjeong 0:56ba69e447e3 1226 if ( read_register(RF_SETUP) == setup )
jjeong 0:56ba69e447e3 1227 {
jjeong 0:56ba69e447e3 1228 result = true;
jjeong 0:56ba69e447e3 1229 }
jjeong 0:56ba69e447e3 1230 return result;
jjeong 0:56ba69e447e3 1231 }
jjeong 0:56ba69e447e3 1232
jjeong 0:56ba69e447e3 1233 /****************************************************************************/
jjeong 0:56ba69e447e3 1234
jjeong 0:56ba69e447e3 1235 rf24_datarate_e RF24::getDataRate( void )
jjeong 0:56ba69e447e3 1236 {
jjeong 0:56ba69e447e3 1237 rf24_datarate_e result ;
jjeong 0:56ba69e447e3 1238 uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
jjeong 0:56ba69e447e3 1239
jjeong 0:56ba69e447e3 1240 // switch uses RAM (evil!)
jjeong 0:56ba69e447e3 1241 // Order matters in our case below
jjeong 0:56ba69e447e3 1242 if ( dr == _BV(RF_DR_LOW) )
jjeong 0:56ba69e447e3 1243 {
jjeong 0:56ba69e447e3 1244 // '10' = 250KBPS
jjeong 0:56ba69e447e3 1245 result = RF24_250KBPS ;
jjeong 0:56ba69e447e3 1246 }
jjeong 0:56ba69e447e3 1247 else if ( dr == _BV(RF_DR_HIGH) )
jjeong 0:56ba69e447e3 1248 {
jjeong 0:56ba69e447e3 1249 // '01' = 2MBPS
jjeong 0:56ba69e447e3 1250 result = RF24_2MBPS ;
jjeong 0:56ba69e447e3 1251 }
jjeong 0:56ba69e447e3 1252 else
jjeong 0:56ba69e447e3 1253 {
jjeong 0:56ba69e447e3 1254 // '00' = 1MBPS
jjeong 0:56ba69e447e3 1255 result = RF24_1MBPS ;
jjeong 0:56ba69e447e3 1256 }
jjeong 0:56ba69e447e3 1257 return result ;
jjeong 0:56ba69e447e3 1258 }
jjeong 0:56ba69e447e3 1259
jjeong 0:56ba69e447e3 1260 /****************************************************************************/
jjeong 0:56ba69e447e3 1261
jjeong 0:56ba69e447e3 1262 void RF24::setCRCLength(rf24_crclength_e length)
jjeong 0:56ba69e447e3 1263 {
jjeong 0:56ba69e447e3 1264 uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
jjeong 0:56ba69e447e3 1265
jjeong 0:56ba69e447e3 1266 // switch uses RAM (evil!)
jjeong 0:56ba69e447e3 1267 if ( length == RF24_CRC_DISABLED )
jjeong 0:56ba69e447e3 1268 {
jjeong 0:56ba69e447e3 1269 // Do nothing, we turned it off above.
jjeong 0:56ba69e447e3 1270 }
jjeong 0:56ba69e447e3 1271 else if ( length == RF24_CRC_8 )
jjeong 0:56ba69e447e3 1272 {
jjeong 0:56ba69e447e3 1273 config |= _BV(EN_CRC);
jjeong 0:56ba69e447e3 1274 }
jjeong 0:56ba69e447e3 1275 else
jjeong 0:56ba69e447e3 1276 {
jjeong 0:56ba69e447e3 1277 config |= _BV(EN_CRC);
jjeong 0:56ba69e447e3 1278 config |= _BV( CRCO );
jjeong 0:56ba69e447e3 1279 }
jjeong 0:56ba69e447e3 1280 write_register( NRF_CONFIG, config ) ;
jjeong 0:56ba69e447e3 1281 }
jjeong 0:56ba69e447e3 1282
jjeong 0:56ba69e447e3 1283 /****************************************************************************/
jjeong 0:56ba69e447e3 1284
jjeong 0:56ba69e447e3 1285 rf24_crclength_e RF24::getCRCLength(void)
jjeong 0:56ba69e447e3 1286 {
jjeong 0:56ba69e447e3 1287 rf24_crclength_e result = RF24_CRC_DISABLED;
jjeong 0:56ba69e447e3 1288
jjeong 0:56ba69e447e3 1289 uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
jjeong 0:56ba69e447e3 1290 uint8_t AA = read_register(EN_AA);
jjeong 0:56ba69e447e3 1291
jjeong 0:56ba69e447e3 1292 if ( config & _BV(EN_CRC ) || AA)
jjeong 0:56ba69e447e3 1293 {
jjeong 0:56ba69e447e3 1294 if ( config & _BV(CRCO) )
jjeong 0:56ba69e447e3 1295 result = RF24_CRC_16;
jjeong 0:56ba69e447e3 1296 else
jjeong 0:56ba69e447e3 1297 result = RF24_CRC_8;
jjeong 0:56ba69e447e3 1298 }
jjeong 0:56ba69e447e3 1299
jjeong 0:56ba69e447e3 1300 return result;
jjeong 0:56ba69e447e3 1301 }
jjeong 0:56ba69e447e3 1302
jjeong 0:56ba69e447e3 1303 /****************************************************************************/
jjeong 0:56ba69e447e3 1304
jjeong 0:56ba69e447e3 1305 void RF24::disableCRC( void )
jjeong 0:56ba69e447e3 1306 {
jjeong 0:56ba69e447e3 1307 uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
jjeong 0:56ba69e447e3 1308 write_register( NRF_CONFIG, disable ) ;
jjeong 0:56ba69e447e3 1309 }
jjeong 0:56ba69e447e3 1310
jjeong 0:56ba69e447e3 1311 /****************************************************************************/
jjeong 0:56ba69e447e3 1312 void RF24::setRetries(uint8_t delay, uint8_t count)
jjeong 0:56ba69e447e3 1313 {
jjeong 0:56ba69e447e3 1314 write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
jjeong 0:56ba69e447e3 1315 }
jjeong 0:56ba69e447e3 1316