Jhon Plantikow / mbed

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Dependents:   RTC

TARGET_NUCLEO_F072RB/core_caFunc.h@0:88e313c910d0, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:20:09 2015 +0000
Revision:
0:88e313c910d0
RTC Example

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jhon309 0:88e313c910d0 1 /**************************************************************************//**
jhon309 0:88e313c910d0 2 * @file core_caFunc.h
jhon309 0:88e313c910d0 3 * @brief CMSIS Cortex-A Core Function Access Header File
jhon309 0:88e313c910d0 4 * @version V3.10
jhon309 0:88e313c910d0 5 * @date 9 May 2013
jhon309 0:88e313c910d0 6 *
jhon309 0:88e313c910d0 7 * @note
jhon309 0:88e313c910d0 8 *
jhon309 0:88e313c910d0 9 ******************************************************************************/
jhon309 0:88e313c910d0 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
jhon309 0:88e313c910d0 11
jhon309 0:88e313c910d0 12 All rights reserved.
jhon309 0:88e313c910d0 13 Redistribution and use in source and binary forms, with or without
jhon309 0:88e313c910d0 14 modification, are permitted provided that the following conditions are met:
jhon309 0:88e313c910d0 15 - Redistributions of source code must retain the above copyright
jhon309 0:88e313c910d0 16 notice, this list of conditions and the following disclaimer.
jhon309 0:88e313c910d0 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:88e313c910d0 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:88e313c910d0 19 documentation and/or other materials provided with the distribution.
jhon309 0:88e313c910d0 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:88e313c910d0 21 to endorse or promote products derived from this software without
jhon309 0:88e313c910d0 22 specific prior written permission.
jhon309 0:88e313c910d0 23 *
jhon309 0:88e313c910d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:88e313c910d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:88e313c910d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:88e313c910d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:88e313c910d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:88e313c910d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:88e313c910d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:88e313c910d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:88e313c910d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:88e313c910d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:88e313c910d0 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:88e313c910d0 35 ---------------------------------------------------------------------------*/
jhon309 0:88e313c910d0 36
jhon309 0:88e313c910d0 37
jhon309 0:88e313c910d0 38 #ifndef __CORE_CAFUNC_H__
jhon309 0:88e313c910d0 39 #define __CORE_CAFUNC_H__
jhon309 0:88e313c910d0 40
jhon309 0:88e313c910d0 41
jhon309 0:88e313c910d0 42 /* ########################### Core Function Access ########################### */
jhon309 0:88e313c910d0 43 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:88e313c910d0 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
jhon309 0:88e313c910d0 45 @{
jhon309 0:88e313c910d0 46 */
jhon309 0:88e313c910d0 47
jhon309 0:88e313c910d0 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jhon309 0:88e313c910d0 49 /* ARM armcc specific functions */
jhon309 0:88e313c910d0 50
jhon309 0:88e313c910d0 51 #if (__ARMCC_VERSION < 400677)
jhon309 0:88e313c910d0 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jhon309 0:88e313c910d0 53 #endif
jhon309 0:88e313c910d0 54
jhon309 0:88e313c910d0 55 #define MODE_USR 0x10
jhon309 0:88e313c910d0 56 #define MODE_FIQ 0x11
jhon309 0:88e313c910d0 57 #define MODE_IRQ 0x12
jhon309 0:88e313c910d0 58 #define MODE_SVC 0x13
jhon309 0:88e313c910d0 59 #define MODE_MON 0x16
jhon309 0:88e313c910d0 60 #define MODE_ABT 0x17
jhon309 0:88e313c910d0 61 #define MODE_HYP 0x1A
jhon309 0:88e313c910d0 62 #define MODE_UND 0x1B
jhon309 0:88e313c910d0 63 #define MODE_SYS 0x1F
jhon309 0:88e313c910d0 64
jhon309 0:88e313c910d0 65 /** \brief Get APSR Register
jhon309 0:88e313c910d0 66
jhon309 0:88e313c910d0 67 This function returns the content of the APSR Register.
jhon309 0:88e313c910d0 68
jhon309 0:88e313c910d0 69 \return APSR Register value
jhon309 0:88e313c910d0 70 */
jhon309 0:88e313c910d0 71 __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:88e313c910d0 72 {
jhon309 0:88e313c910d0 73 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:88e313c910d0 74 return(__regAPSR);
jhon309 0:88e313c910d0 75 }
jhon309 0:88e313c910d0 76
jhon309 0:88e313c910d0 77
jhon309 0:88e313c910d0 78 /** \brief Get CPSR Register
jhon309 0:88e313c910d0 79
jhon309 0:88e313c910d0 80 This function returns the content of the CPSR Register.
jhon309 0:88e313c910d0 81
jhon309 0:88e313c910d0 82 \return CPSR Register value
jhon309 0:88e313c910d0 83 */
jhon309 0:88e313c910d0 84 __STATIC_INLINE uint32_t __get_CPSR(void)
jhon309 0:88e313c910d0 85 {
jhon309 0:88e313c910d0 86 register uint32_t __regCPSR __ASM("cpsr");
jhon309 0:88e313c910d0 87 return(__regCPSR);
jhon309 0:88e313c910d0 88 }
jhon309 0:88e313c910d0 89
jhon309 0:88e313c910d0 90 /** \brief Set Stack Pointer
jhon309 0:88e313c910d0 91
jhon309 0:88e313c910d0 92 This function assigns the given value to the current stack pointer.
jhon309 0:88e313c910d0 93
jhon309 0:88e313c910d0 94 \param [in] topOfStack Stack Pointer value to set
jhon309 0:88e313c910d0 95 */
jhon309 0:88e313c910d0 96 register uint32_t __regSP __ASM("sp");
jhon309 0:88e313c910d0 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jhon309 0:88e313c910d0 98 {
jhon309 0:88e313c910d0 99 __regSP = topOfStack;
jhon309 0:88e313c910d0 100 }
jhon309 0:88e313c910d0 101
jhon309 0:88e313c910d0 102
jhon309 0:88e313c910d0 103 /** \brief Get link register
jhon309 0:88e313c910d0 104
jhon309 0:88e313c910d0 105 This function returns the value of the link register
jhon309 0:88e313c910d0 106
jhon309 0:88e313c910d0 107 \return Value of link register
jhon309 0:88e313c910d0 108 */
jhon309 0:88e313c910d0 109 register uint32_t __reglr __ASM("lr");
jhon309 0:88e313c910d0 110 __STATIC_INLINE uint32_t __get_LR(void)
jhon309 0:88e313c910d0 111 {
jhon309 0:88e313c910d0 112 return(__reglr);
jhon309 0:88e313c910d0 113 }
jhon309 0:88e313c910d0 114
jhon309 0:88e313c910d0 115 /** \brief Set link register
jhon309 0:88e313c910d0 116
jhon309 0:88e313c910d0 117 This function sets the value of the link register
jhon309 0:88e313c910d0 118
jhon309 0:88e313c910d0 119 \param [in] lr LR value to set
jhon309 0:88e313c910d0 120 */
jhon309 0:88e313c910d0 121 __STATIC_INLINE void __set_LR(uint32_t lr)
jhon309 0:88e313c910d0 122 {
jhon309 0:88e313c910d0 123 __reglr = lr;
jhon309 0:88e313c910d0 124 }
jhon309 0:88e313c910d0 125
jhon309 0:88e313c910d0 126 /** \brief Set Process Stack Pointer
jhon309 0:88e313c910d0 127
jhon309 0:88e313c910d0 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jhon309 0:88e313c910d0 129
jhon309 0:88e313c910d0 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:88e313c910d0 131 */
jhon309 0:88e313c910d0 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
jhon309 0:88e313c910d0 133 {
jhon309 0:88e313c910d0 134 ARM
jhon309 0:88e313c910d0 135 PRESERVE8
jhon309 0:88e313c910d0 136
jhon309 0:88e313c910d0 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
jhon309 0:88e313c910d0 138 MRS R1, CPSR
jhon309 0:88e313c910d0 139 CPS #MODE_SYS ;no effect in USR mode
jhon309 0:88e313c910d0 140 MOV SP, R0
jhon309 0:88e313c910d0 141 MSR CPSR_c, R1 ;no effect in USR mode
jhon309 0:88e313c910d0 142 ISB
jhon309 0:88e313c910d0 143 BX LR
jhon309 0:88e313c910d0 144
jhon309 0:88e313c910d0 145 }
jhon309 0:88e313c910d0 146
jhon309 0:88e313c910d0 147 /** \brief Set User Mode
jhon309 0:88e313c910d0 148
jhon309 0:88e313c910d0 149 This function changes the processor state to User Mode
jhon309 0:88e313c910d0 150
jhon309 0:88e313c910d0 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:88e313c910d0 152 */
jhon309 0:88e313c910d0 153 __STATIC_ASM void __set_CPS_USR(void)
jhon309 0:88e313c910d0 154 {
jhon309 0:88e313c910d0 155 ARM
jhon309 0:88e313c910d0 156
jhon309 0:88e313c910d0 157 CPS #MODE_USR
jhon309 0:88e313c910d0 158 BX LR
jhon309 0:88e313c910d0 159 }
jhon309 0:88e313c910d0 160
jhon309 0:88e313c910d0 161
jhon309 0:88e313c910d0 162 /** \brief Enable FIQ
jhon309 0:88e313c910d0 163
jhon309 0:88e313c910d0 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:88e313c910d0 165 Can only be executed in Privileged modes.
jhon309 0:88e313c910d0 166 */
jhon309 0:88e313c910d0 167 #define __enable_fault_irq __enable_fiq
jhon309 0:88e313c910d0 168
jhon309 0:88e313c910d0 169
jhon309 0:88e313c910d0 170 /** \brief Disable FIQ
jhon309 0:88e313c910d0 171
jhon309 0:88e313c910d0 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:88e313c910d0 173 Can only be executed in Privileged modes.
jhon309 0:88e313c910d0 174 */
jhon309 0:88e313c910d0 175 #define __disable_fault_irq __disable_fiq
jhon309 0:88e313c910d0 176
jhon309 0:88e313c910d0 177
jhon309 0:88e313c910d0 178 /** \brief Get FPSCR
jhon309 0:88e313c910d0 179
jhon309 0:88e313c910d0 180 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:88e313c910d0 181
jhon309 0:88e313c910d0 182 \return Floating Point Status/Control register value
jhon309 0:88e313c910d0 183 */
jhon309 0:88e313c910d0 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:88e313c910d0 185 {
jhon309 0:88e313c910d0 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:88e313c910d0 187 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:88e313c910d0 188 return(__regfpscr);
jhon309 0:88e313c910d0 189 #else
jhon309 0:88e313c910d0 190 return(0);
jhon309 0:88e313c910d0 191 #endif
jhon309 0:88e313c910d0 192 }
jhon309 0:88e313c910d0 193
jhon309 0:88e313c910d0 194
jhon309 0:88e313c910d0 195 /** \brief Set FPSCR
jhon309 0:88e313c910d0 196
jhon309 0:88e313c910d0 197 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:88e313c910d0 198
jhon309 0:88e313c910d0 199 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:88e313c910d0 200 */
jhon309 0:88e313c910d0 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:88e313c910d0 202 {
jhon309 0:88e313c910d0 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:88e313c910d0 204 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:88e313c910d0 205 __regfpscr = (fpscr);
jhon309 0:88e313c910d0 206 #endif
jhon309 0:88e313c910d0 207 }
jhon309 0:88e313c910d0 208
jhon309 0:88e313c910d0 209 /** \brief Get FPEXC
jhon309 0:88e313c910d0 210
jhon309 0:88e313c910d0 211 This function returns the current value of the Floating Point Exception Control register.
jhon309 0:88e313c910d0 212
jhon309 0:88e313c910d0 213 \return Floating Point Exception Control register value
jhon309 0:88e313c910d0 214 */
jhon309 0:88e313c910d0 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
jhon309 0:88e313c910d0 216 {
jhon309 0:88e313c910d0 217 #if (__FPU_PRESENT == 1)
jhon309 0:88e313c910d0 218 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:88e313c910d0 219 return(__regfpexc);
jhon309 0:88e313c910d0 220 #else
jhon309 0:88e313c910d0 221 return(0);
jhon309 0:88e313c910d0 222 #endif
jhon309 0:88e313c910d0 223 }
jhon309 0:88e313c910d0 224
jhon309 0:88e313c910d0 225
jhon309 0:88e313c910d0 226 /** \brief Set FPEXC
jhon309 0:88e313c910d0 227
jhon309 0:88e313c910d0 228 This function assigns the given value to the Floating Point Exception Control register.
jhon309 0:88e313c910d0 229
jhon309 0:88e313c910d0 230 \param [in] fpscr Floating Point Exception Control value to set
jhon309 0:88e313c910d0 231 */
jhon309 0:88e313c910d0 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jhon309 0:88e313c910d0 233 {
jhon309 0:88e313c910d0 234 #if (__FPU_PRESENT == 1)
jhon309 0:88e313c910d0 235 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:88e313c910d0 236 __regfpexc = (fpexc);
jhon309 0:88e313c910d0 237 #endif
jhon309 0:88e313c910d0 238 }
jhon309 0:88e313c910d0 239
jhon309 0:88e313c910d0 240 /** \brief Get CPACR
jhon309 0:88e313c910d0 241
jhon309 0:88e313c910d0 242 This function returns the current value of the Coprocessor Access Control register.
jhon309 0:88e313c910d0 243
jhon309 0:88e313c910d0 244 \return Coprocessor Access Control register value
jhon309 0:88e313c910d0 245 */
jhon309 0:88e313c910d0 246 __STATIC_INLINE uint32_t __get_CPACR(void)
jhon309 0:88e313c910d0 247 {
jhon309 0:88e313c910d0 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:88e313c910d0 249 return __regCPACR;
jhon309 0:88e313c910d0 250 }
jhon309 0:88e313c910d0 251
jhon309 0:88e313c910d0 252 /** \brief Set CPACR
jhon309 0:88e313c910d0 253
jhon309 0:88e313c910d0 254 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:88e313c910d0 255
jhon309 0:88e313c910d0 256 \param [in] cpacr Coporcessor Acccess Control value to set
jhon309 0:88e313c910d0 257 */
jhon309 0:88e313c910d0 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jhon309 0:88e313c910d0 259 {
jhon309 0:88e313c910d0 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:88e313c910d0 261 __regCPACR = cpacr;
jhon309 0:88e313c910d0 262 __ISB();
jhon309 0:88e313c910d0 263 }
jhon309 0:88e313c910d0 264
jhon309 0:88e313c910d0 265 /** \brief Get CBAR
jhon309 0:88e313c910d0 266
jhon309 0:88e313c910d0 267 This function returns the value of the Configuration Base Address register.
jhon309 0:88e313c910d0 268
jhon309 0:88e313c910d0 269 \return Configuration Base Address register value
jhon309 0:88e313c910d0 270 */
jhon309 0:88e313c910d0 271 __STATIC_INLINE uint32_t __get_CBAR() {
jhon309 0:88e313c910d0 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jhon309 0:88e313c910d0 273 return(__regCBAR);
jhon309 0:88e313c910d0 274 }
jhon309 0:88e313c910d0 275
jhon309 0:88e313c910d0 276 /** \brief Get TTBR0
jhon309 0:88e313c910d0 277
jhon309 0:88e313c910d0 278 This function returns the value of the Configuration Base Address register.
jhon309 0:88e313c910d0 279
jhon309 0:88e313c910d0 280 \return Translation Table Base Register 0 value
jhon309 0:88e313c910d0 281 */
jhon309 0:88e313c910d0 282 __STATIC_INLINE uint32_t __get_TTBR0() {
jhon309 0:88e313c910d0 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:88e313c910d0 284 return(__regTTBR0);
jhon309 0:88e313c910d0 285 }
jhon309 0:88e313c910d0 286
jhon309 0:88e313c910d0 287 /** \brief Set TTBR0
jhon309 0:88e313c910d0 288
jhon309 0:88e313c910d0 289 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:88e313c910d0 290
jhon309 0:88e313c910d0 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
jhon309 0:88e313c910d0 292 */
jhon309 0:88e313c910d0 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jhon309 0:88e313c910d0 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:88e313c910d0 295 __regTTBR0 = ttbr0;
jhon309 0:88e313c910d0 296 __ISB();
jhon309 0:88e313c910d0 297 }
jhon309 0:88e313c910d0 298
jhon309 0:88e313c910d0 299 /** \brief Get DACR
jhon309 0:88e313c910d0 300
jhon309 0:88e313c910d0 301 This function returns the value of the Domain Access Control Register.
jhon309 0:88e313c910d0 302
jhon309 0:88e313c910d0 303 \return Domain Access Control Register value
jhon309 0:88e313c910d0 304 */
jhon309 0:88e313c910d0 305 __STATIC_INLINE uint32_t __get_DACR() {
jhon309 0:88e313c910d0 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:88e313c910d0 307 return(__regDACR);
jhon309 0:88e313c910d0 308 }
jhon309 0:88e313c910d0 309
jhon309 0:88e313c910d0 310 /** \brief Set DACR
jhon309 0:88e313c910d0 311
jhon309 0:88e313c910d0 312 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:88e313c910d0 313
jhon309 0:88e313c910d0 314 \param [in] dacr Domain Access Control Register value to set
jhon309 0:88e313c910d0 315 */
jhon309 0:88e313c910d0 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jhon309 0:88e313c910d0 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:88e313c910d0 318 __regDACR = dacr;
jhon309 0:88e313c910d0 319 __ISB();
jhon309 0:88e313c910d0 320 }
jhon309 0:88e313c910d0 321
jhon309 0:88e313c910d0 322 /******************************** Cache and BTAC enable ****************************************************/
jhon309 0:88e313c910d0 323
jhon309 0:88e313c910d0 324 /** \brief Set SCTLR
jhon309 0:88e313c910d0 325
jhon309 0:88e313c910d0 326 This function assigns the given value to the System Control Register.
jhon309 0:88e313c910d0 327
jhon309 0:88e313c910d0 328 \param [in] sctlr System Control Register, value to set
jhon309 0:88e313c910d0 329 */
jhon309 0:88e313c910d0 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jhon309 0:88e313c910d0 331 {
jhon309 0:88e313c910d0 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:88e313c910d0 333 __regSCTLR = sctlr;
jhon309 0:88e313c910d0 334 }
jhon309 0:88e313c910d0 335
jhon309 0:88e313c910d0 336 /** \brief Get SCTLR
jhon309 0:88e313c910d0 337
jhon309 0:88e313c910d0 338 This function returns the value of the System Control Register.
jhon309 0:88e313c910d0 339
jhon309 0:88e313c910d0 340 \return System Control Register value
jhon309 0:88e313c910d0 341 */
jhon309 0:88e313c910d0 342 __STATIC_INLINE uint32_t __get_SCTLR() {
jhon309 0:88e313c910d0 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:88e313c910d0 344 return(__regSCTLR);
jhon309 0:88e313c910d0 345 }
jhon309 0:88e313c910d0 346
jhon309 0:88e313c910d0 347 /** \brief Enable Caches
jhon309 0:88e313c910d0 348
jhon309 0:88e313c910d0 349 Enable Caches
jhon309 0:88e313c910d0 350 */
jhon309 0:88e313c910d0 351 __STATIC_INLINE void __enable_caches(void) {
jhon309 0:88e313c910d0 352 // Set I bit 12 to enable I Cache
jhon309 0:88e313c910d0 353 // Set C bit 2 to enable D Cache
jhon309 0:88e313c910d0 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jhon309 0:88e313c910d0 355 }
jhon309 0:88e313c910d0 356
jhon309 0:88e313c910d0 357 /** \brief Disable Caches
jhon309 0:88e313c910d0 358
jhon309 0:88e313c910d0 359 Disable Caches
jhon309 0:88e313c910d0 360 */
jhon309 0:88e313c910d0 361 __STATIC_INLINE void __disable_caches(void) {
jhon309 0:88e313c910d0 362 // Clear I bit 12 to disable I Cache
jhon309 0:88e313c910d0 363 // Clear C bit 2 to disable D Cache
jhon309 0:88e313c910d0 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jhon309 0:88e313c910d0 365 __ISB();
jhon309 0:88e313c910d0 366 }
jhon309 0:88e313c910d0 367
jhon309 0:88e313c910d0 368 /** \brief Enable BTAC
jhon309 0:88e313c910d0 369
jhon309 0:88e313c910d0 370 Enable BTAC
jhon309 0:88e313c910d0 371 */
jhon309 0:88e313c910d0 372 __STATIC_INLINE void __enable_btac(void) {
jhon309 0:88e313c910d0 373 // Set Z bit 11 to enable branch prediction
jhon309 0:88e313c910d0 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
jhon309 0:88e313c910d0 375 __ISB();
jhon309 0:88e313c910d0 376 }
jhon309 0:88e313c910d0 377
jhon309 0:88e313c910d0 378 /** \brief Disable BTAC
jhon309 0:88e313c910d0 379
jhon309 0:88e313c910d0 380 Disable BTAC
jhon309 0:88e313c910d0 381 */
jhon309 0:88e313c910d0 382 __STATIC_INLINE void __disable_btac(void) {
jhon309 0:88e313c910d0 383 // Clear Z bit 11 to disable branch prediction
jhon309 0:88e313c910d0 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jhon309 0:88e313c910d0 385 }
jhon309 0:88e313c910d0 386
jhon309 0:88e313c910d0 387
jhon309 0:88e313c910d0 388 /** \brief Enable MMU
jhon309 0:88e313c910d0 389
jhon309 0:88e313c910d0 390 Enable MMU
jhon309 0:88e313c910d0 391 */
jhon309 0:88e313c910d0 392 __STATIC_INLINE void __enable_mmu(void) {
jhon309 0:88e313c910d0 393 // Set M bit 0 to enable the MMU
jhon309 0:88e313c910d0 394 // Set AFE bit to enable simplified access permissions model
jhon309 0:88e313c910d0 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jhon309 0:88e313c910d0 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jhon309 0:88e313c910d0 397 __ISB();
jhon309 0:88e313c910d0 398 }
jhon309 0:88e313c910d0 399
jhon309 0:88e313c910d0 400 /** \brief Enable MMU
jhon309 0:88e313c910d0 401
jhon309 0:88e313c910d0 402 Enable MMU
jhon309 0:88e313c910d0 403 */
jhon309 0:88e313c910d0 404 __STATIC_INLINE void __disable_mmu(void) {
jhon309 0:88e313c910d0 405 // Clear M bit 0 to disable the MMU
jhon309 0:88e313c910d0 406 __set_SCTLR( __get_SCTLR() & ~1);
jhon309 0:88e313c910d0 407 __ISB();
jhon309 0:88e313c910d0 408 }
jhon309 0:88e313c910d0 409
jhon309 0:88e313c910d0 410 /******************************** TLB maintenance operations ************************************************/
jhon309 0:88e313c910d0 411 /** \brief Invalidate the whole tlb
jhon309 0:88e313c910d0 412
jhon309 0:88e313c910d0 413 TLBIALL. Invalidate the whole tlb
jhon309 0:88e313c910d0 414 */
jhon309 0:88e313c910d0 415
jhon309 0:88e313c910d0 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jhon309 0:88e313c910d0 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jhon309 0:88e313c910d0 418 __TLBIALL = 0;
jhon309 0:88e313c910d0 419 __DSB();
jhon309 0:88e313c910d0 420 __ISB();
jhon309 0:88e313c910d0 421 }
jhon309 0:88e313c910d0 422
jhon309 0:88e313c910d0 423 /******************************** BTB maintenance operations ************************************************/
jhon309 0:88e313c910d0 424 /** \brief Invalidate entire branch predictor array
jhon309 0:88e313c910d0 425
jhon309 0:88e313c910d0 426 BPIALL. Branch Predictor Invalidate All.
jhon309 0:88e313c910d0 427 */
jhon309 0:88e313c910d0 428
jhon309 0:88e313c910d0 429 __STATIC_INLINE void __v7_inv_btac(void) {
jhon309 0:88e313c910d0 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jhon309 0:88e313c910d0 431 __BPIALL = 0;
jhon309 0:88e313c910d0 432 __DSB(); //ensure completion of the invalidation
jhon309 0:88e313c910d0 433 __ISB(); //ensure instruction fetch path sees new state
jhon309 0:88e313c910d0 434 }
jhon309 0:88e313c910d0 435
jhon309 0:88e313c910d0 436
jhon309 0:88e313c910d0 437 /******************************** L1 cache operations ******************************************************/
jhon309 0:88e313c910d0 438
jhon309 0:88e313c910d0 439 /** \brief Invalidate the whole I$
jhon309 0:88e313c910d0 440
jhon309 0:88e313c910d0 441 ICIALLU. Instruction Cache Invalidate All to PoU
jhon309 0:88e313c910d0 442 */
jhon309 0:88e313c910d0 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
jhon309 0:88e313c910d0 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jhon309 0:88e313c910d0 445 __ICIALLU = 0;
jhon309 0:88e313c910d0 446 __DSB(); //ensure completion of the invalidation
jhon309 0:88e313c910d0 447 __ISB(); //ensure instruction fetch path sees new I cache state
jhon309 0:88e313c910d0 448 }
jhon309 0:88e313c910d0 449
jhon309 0:88e313c910d0 450 /** \brief Clean D$ by MVA
jhon309 0:88e313c910d0 451
jhon309 0:88e313c910d0 452 DCCMVAC. Data cache clean by MVA to PoC
jhon309 0:88e313c910d0 453 */
jhon309 0:88e313c910d0 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jhon309 0:88e313c910d0 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jhon309 0:88e313c910d0 456 __DCCMVAC = (uint32_t)va;
jhon309 0:88e313c910d0 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:88e313c910d0 458 }
jhon309 0:88e313c910d0 459
jhon309 0:88e313c910d0 460 /** \brief Invalidate D$ by MVA
jhon309 0:88e313c910d0 461
jhon309 0:88e313c910d0 462 DCIMVAC. Data cache invalidate by MVA to PoC
jhon309 0:88e313c910d0 463 */
jhon309 0:88e313c910d0 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jhon309 0:88e313c910d0 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jhon309 0:88e313c910d0 466 __DCIMVAC = (uint32_t)va;
jhon309 0:88e313c910d0 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:88e313c910d0 468 }
jhon309 0:88e313c910d0 469
jhon309 0:88e313c910d0 470 /** \brief Clean and Invalidate D$ by MVA
jhon309 0:88e313c910d0 471
jhon309 0:88e313c910d0 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jhon309 0:88e313c910d0 473 */
jhon309 0:88e313c910d0 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jhon309 0:88e313c910d0 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jhon309 0:88e313c910d0 476 __DCCIMVAC = (uint32_t)va;
jhon309 0:88e313c910d0 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:88e313c910d0 478 }
jhon309 0:88e313c910d0 479
jhon309 0:88e313c910d0 480 /** \brief
jhon309 0:88e313c910d0 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jhon309 0:88e313c910d0 482 */
jhon309 0:88e313c910d0 483 #pragma push
jhon309 0:88e313c910d0 484 #pragma arm
jhon309 0:88e313c910d0 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
jhon309 0:88e313c910d0 486 ARM
jhon309 0:88e313c910d0 487
jhon309 0:88e313c910d0 488 PUSH {R4-R11}
jhon309 0:88e313c910d0 489
jhon309 0:88e313c910d0 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
jhon309 0:88e313c910d0 491 ANDS R3, R6, #0x07000000 // Extract coherency level
jhon309 0:88e313c910d0 492 MOV R3, R3, LSR #23 // Total cache levels << 1
jhon309 0:88e313c910d0 493 BEQ Finished // If 0, no need to clean
jhon309 0:88e313c910d0 494
jhon309 0:88e313c910d0 495 MOV R10, #0 // R10 holds current cache level << 1
jhon309 0:88e313c910d0 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
jhon309 0:88e313c910d0 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
jhon309 0:88e313c910d0 498 AND R1, R1, #7 // Isolate those lower 3 bits
jhon309 0:88e313c910d0 499 CMP R1, #2
jhon309 0:88e313c910d0 500 BLT Skip // No cache or only instruction cache at this level
jhon309 0:88e313c910d0 501
jhon309 0:88e313c910d0 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
jhon309 0:88e313c910d0 503 ISB // ISB to sync the change to the CacheSizeID reg
jhon309 0:88e313c910d0 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
jhon309 0:88e313c910d0 505 AND R2, R1, #7 // Extract the line length field
jhon309 0:88e313c910d0 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
jhon309 0:88e313c910d0 507 LDR R4, =0x3FF
jhon309 0:88e313c910d0 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
jhon309 0:88e313c910d0 509 CLZ R5, R4 // R5 is the bit position of the way size increment
jhon309 0:88e313c910d0 510 LDR R7, =0x7FFF
jhon309 0:88e313c910d0 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
jhon309 0:88e313c910d0 512
jhon309 0:88e313c910d0 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
jhon309 0:88e313c910d0 514
jhon309 0:88e313c910d0 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
jhon309 0:88e313c910d0 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
jhon309 0:88e313c910d0 517 CMP R0, #0
jhon309 0:88e313c910d0 518 BNE Dccsw
jhon309 0:88e313c910d0 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
jhon309 0:88e313c910d0 520 B cont
jhon309 0:88e313c910d0 521 Dccsw CMP R0, #1
jhon309 0:88e313c910d0 522 BNE Dccisw
jhon309 0:88e313c910d0 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
jhon309 0:88e313c910d0 524 B cont
jhon309 0:88e313c910d0 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
jhon309 0:88e313c910d0 526 cont SUBS R9, R9, #1 // Decrement the Way number
jhon309 0:88e313c910d0 527 BGE Loop3
jhon309 0:88e313c910d0 528 SUBS R7, R7, #1 // Decrement the Set number
jhon309 0:88e313c910d0 529 BGE Loop2
jhon309 0:88e313c910d0 530 Skip ADD R10, R10, #2 // increment the cache number
jhon309 0:88e313c910d0 531 CMP R3, R10
jhon309 0:88e313c910d0 532 BGT Loop1
jhon309 0:88e313c910d0 533
jhon309 0:88e313c910d0 534 Finished
jhon309 0:88e313c910d0 535 DSB
jhon309 0:88e313c910d0 536 POP {R4-R11}
jhon309 0:88e313c910d0 537 BX lr
jhon309 0:88e313c910d0 538
jhon309 0:88e313c910d0 539 }
jhon309 0:88e313c910d0 540 #pragma pop
jhon309 0:88e313c910d0 541
jhon309 0:88e313c910d0 542 /** \brief __v7_all_cache - helper function
jhon309 0:88e313c910d0 543
jhon309 0:88e313c910d0 544 */
jhon309 0:88e313c910d0 545
jhon309 0:88e313c910d0 546 /** \brief Invalidate the whole D$
jhon309 0:88e313c910d0 547
jhon309 0:88e313c910d0 548 DCISW. Invalidate by Set/Way
jhon309 0:88e313c910d0 549 */
jhon309 0:88e313c910d0 550
jhon309 0:88e313c910d0 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
jhon309 0:88e313c910d0 552 __v7_all_cache(0);
jhon309 0:88e313c910d0 553 }
jhon309 0:88e313c910d0 554
jhon309 0:88e313c910d0 555 /** \brief Clean the whole D$
jhon309 0:88e313c910d0 556
jhon309 0:88e313c910d0 557 DCCSW. Clean by Set/Way
jhon309 0:88e313c910d0 558 */
jhon309 0:88e313c910d0 559
jhon309 0:88e313c910d0 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
jhon309 0:88e313c910d0 561 __v7_all_cache(1);
jhon309 0:88e313c910d0 562 }
jhon309 0:88e313c910d0 563
jhon309 0:88e313c910d0 564 /** \brief Clean and invalidate the whole D$
jhon309 0:88e313c910d0 565
jhon309 0:88e313c910d0 566 DCCISW. Clean and Invalidate by Set/Way
jhon309 0:88e313c910d0 567 */
jhon309 0:88e313c910d0 568
jhon309 0:88e313c910d0 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jhon309 0:88e313c910d0 570 __v7_all_cache(2);
jhon309 0:88e313c910d0 571 }
jhon309 0:88e313c910d0 572
jhon309 0:88e313c910d0 573 #include "core_ca_mmu.h"
jhon309 0:88e313c910d0 574
jhon309 0:88e313c910d0 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
jhon309 0:88e313c910d0 576
jhon309 0:88e313c910d0 577 #error IAR Compiler support not implemented for Cortex-A
jhon309 0:88e313c910d0 578
jhon309 0:88e313c910d0 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
jhon309 0:88e313c910d0 580
jhon309 0:88e313c910d0 581 /* GNU gcc specific functions */
jhon309 0:88e313c910d0 582
jhon309 0:88e313c910d0 583 #define MODE_USR 0x10
jhon309 0:88e313c910d0 584 #define MODE_FIQ 0x11
jhon309 0:88e313c910d0 585 #define MODE_IRQ 0x12
jhon309 0:88e313c910d0 586 #define MODE_SVC 0x13
jhon309 0:88e313c910d0 587 #define MODE_MON 0x16
jhon309 0:88e313c910d0 588 #define MODE_ABT 0x17
jhon309 0:88e313c910d0 589 #define MODE_HYP 0x1A
jhon309 0:88e313c910d0 590 #define MODE_UND 0x1B
jhon309 0:88e313c910d0 591 #define MODE_SYS 0x1F
jhon309 0:88e313c910d0 592
jhon309 0:88e313c910d0 593
jhon309 0:88e313c910d0 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
jhon309 0:88e313c910d0 595 {
jhon309 0:88e313c910d0 596 __ASM volatile ("cpsie i");
jhon309 0:88e313c910d0 597 }
jhon309 0:88e313c910d0 598
jhon309 0:88e313c910d0 599 /** \brief Disable IRQ Interrupts
jhon309 0:88e313c910d0 600
jhon309 0:88e313c910d0 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
jhon309 0:88e313c910d0 602 Can only be executed in Privileged modes.
jhon309 0:88e313c910d0 603 */
jhon309 0:88e313c910d0 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
jhon309 0:88e313c910d0 605 {
jhon309 0:88e313c910d0 606 uint32_t result;
jhon309 0:88e313c910d0 607
jhon309 0:88e313c910d0 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
jhon309 0:88e313c910d0 609 __ASM volatile ("cpsid i");
jhon309 0:88e313c910d0 610 return(result & 0x80);
jhon309 0:88e313c910d0 611 }
jhon309 0:88e313c910d0 612
jhon309 0:88e313c910d0 613
jhon309 0:88e313c910d0 614 /** \brief Get APSR Register
jhon309 0:88e313c910d0 615
jhon309 0:88e313c910d0 616 This function returns the content of the APSR Register.
jhon309 0:88e313c910d0 617
jhon309 0:88e313c910d0 618 \return APSR Register value
jhon309 0:88e313c910d0 619 */
jhon309 0:88e313c910d0 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:88e313c910d0 621 {
jhon309 0:88e313c910d0 622 #if 1
jhon309 0:88e313c910d0 623 uint32_t result;
jhon309 0:88e313c910d0 624
jhon309 0:88e313c910d0 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
jhon309 0:88e313c910d0 626 return (result);
jhon309 0:88e313c910d0 627 #else
jhon309 0:88e313c910d0 628 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:88e313c910d0 629 return(__regAPSR);
jhon309 0:88e313c910d0 630 #endif
jhon309 0:88e313c910d0 631 }
jhon309 0:88e313c910d0 632
jhon309 0:88e313c910d0 633
jhon309 0:88e313c910d0 634 /** \brief Get CPSR Register
jhon309 0:88e313c910d0 635
jhon309 0:88e313c910d0 636 This function returns the content of the CPSR Register.
jhon309 0:88e313c910d0 637
jhon309 0:88e313c910d0 638 \return CPSR Register value
jhon309 0:88e313c910d0 639 */
jhon309 0:88e313c910d0 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
jhon309 0:88e313c910d0 641 {
jhon309 0:88e313c910d0 642 #if 1
jhon309 0:88e313c910d0 643 register uint32_t __regCPSR;
jhon309 0:88e313c910d0 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
jhon309 0:88e313c910d0 645 #else
jhon309 0:88e313c910d0 646 register uint32_t __regCPSR __ASM("cpsr");
jhon309 0:88e313c910d0 647 #endif
jhon309 0:88e313c910d0 648 return(__regCPSR);
jhon309 0:88e313c910d0 649 }
jhon309 0:88e313c910d0 650
jhon309 0:88e313c910d0 651 #if 0
jhon309 0:88e313c910d0 652 /** \brief Set Stack Pointer
jhon309 0:88e313c910d0 653
jhon309 0:88e313c910d0 654 This function assigns the given value to the current stack pointer.
jhon309 0:88e313c910d0 655
jhon309 0:88e313c910d0 656 \param [in] topOfStack Stack Pointer value to set
jhon309 0:88e313c910d0 657 */
jhon309 0:88e313c910d0 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jhon309 0:88e313c910d0 659 {
jhon309 0:88e313c910d0 660 register uint32_t __regSP __ASM("sp");
jhon309 0:88e313c910d0 661 __regSP = topOfStack;
jhon309 0:88e313c910d0 662 }
jhon309 0:88e313c910d0 663 #endif
jhon309 0:88e313c910d0 664
jhon309 0:88e313c910d0 665 /** \brief Get link register
jhon309 0:88e313c910d0 666
jhon309 0:88e313c910d0 667 This function returns the value of the link register
jhon309 0:88e313c910d0 668
jhon309 0:88e313c910d0 669 \return Value of link register
jhon309 0:88e313c910d0 670 */
jhon309 0:88e313c910d0 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
jhon309 0:88e313c910d0 672 {
jhon309 0:88e313c910d0 673 register uint32_t __reglr __ASM("lr");
jhon309 0:88e313c910d0 674 return(__reglr);
jhon309 0:88e313c910d0 675 }
jhon309 0:88e313c910d0 676
jhon309 0:88e313c910d0 677 #if 0
jhon309 0:88e313c910d0 678 /** \brief Set link register
jhon309 0:88e313c910d0 679
jhon309 0:88e313c910d0 680 This function sets the value of the link register
jhon309 0:88e313c910d0 681
jhon309 0:88e313c910d0 682 \param [in] lr LR value to set
jhon309 0:88e313c910d0 683 */
jhon309 0:88e313c910d0 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
jhon309 0:88e313c910d0 685 {
jhon309 0:88e313c910d0 686 register uint32_t __reglr __ASM("lr");
jhon309 0:88e313c910d0 687 __reglr = lr;
jhon309 0:88e313c910d0 688 }
jhon309 0:88e313c910d0 689 #endif
jhon309 0:88e313c910d0 690
jhon309 0:88e313c910d0 691 /** \brief Set Process Stack Pointer
jhon309 0:88e313c910d0 692
jhon309 0:88e313c910d0 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jhon309 0:88e313c910d0 694
jhon309 0:88e313c910d0 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:88e313c910d0 696 */
jhon309 0:88e313c910d0 697 extern void __set_PSP(uint32_t topOfProcStack);
jhon309 0:88e313c910d0 698
jhon309 0:88e313c910d0 699 /** \brief Set User Mode
jhon309 0:88e313c910d0 700
jhon309 0:88e313c910d0 701 This function changes the processor state to User Mode
jhon309 0:88e313c910d0 702
jhon309 0:88e313c910d0 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:88e313c910d0 704 */
jhon309 0:88e313c910d0 705 extern void __set_CPS_USR(void);
jhon309 0:88e313c910d0 706
jhon309 0:88e313c910d0 707 /** \brief Enable FIQ
jhon309 0:88e313c910d0 708
jhon309 0:88e313c910d0 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:88e313c910d0 710 Can only be executed in Privileged modes.
jhon309 0:88e313c910d0 711 */
jhon309 0:88e313c910d0 712 #define __enable_fault_irq __enable_fiq
jhon309 0:88e313c910d0 713
jhon309 0:88e313c910d0 714
jhon309 0:88e313c910d0 715 /** \brief Disable FIQ
jhon309 0:88e313c910d0 716
jhon309 0:88e313c910d0 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:88e313c910d0 718 Can only be executed in Privileged modes.
jhon309 0:88e313c910d0 719 */
jhon309 0:88e313c910d0 720 #define __disable_fault_irq __disable_fiq
jhon309 0:88e313c910d0 721
jhon309 0:88e313c910d0 722
jhon309 0:88e313c910d0 723 /** \brief Get FPSCR
jhon309 0:88e313c910d0 724
jhon309 0:88e313c910d0 725 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:88e313c910d0 726
jhon309 0:88e313c910d0 727 \return Floating Point Status/Control register value
jhon309 0:88e313c910d0 728 */
jhon309 0:88e313c910d0 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:88e313c910d0 730 {
jhon309 0:88e313c910d0 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:88e313c910d0 732 #if 1
jhon309 0:88e313c910d0 733 uint32_t result;
jhon309 0:88e313c910d0 734
jhon309 0:88e313c910d0 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
jhon309 0:88e313c910d0 736 return (result);
jhon309 0:88e313c910d0 737 #else
jhon309 0:88e313c910d0 738 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:88e313c910d0 739 return(__regfpscr);
jhon309 0:88e313c910d0 740 #endif
jhon309 0:88e313c910d0 741 #else
jhon309 0:88e313c910d0 742 return(0);
jhon309 0:88e313c910d0 743 #endif
jhon309 0:88e313c910d0 744 }
jhon309 0:88e313c910d0 745
jhon309 0:88e313c910d0 746
jhon309 0:88e313c910d0 747 /** \brief Set FPSCR
jhon309 0:88e313c910d0 748
jhon309 0:88e313c910d0 749 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:88e313c910d0 750
jhon309 0:88e313c910d0 751 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:88e313c910d0 752 */
jhon309 0:88e313c910d0 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:88e313c910d0 754 {
jhon309 0:88e313c910d0 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:88e313c910d0 756 #if 1
jhon309 0:88e313c910d0 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
jhon309 0:88e313c910d0 758 #else
jhon309 0:88e313c910d0 759 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:88e313c910d0 760 __regfpscr = (fpscr);
jhon309 0:88e313c910d0 761 #endif
jhon309 0:88e313c910d0 762 #endif
jhon309 0:88e313c910d0 763 }
jhon309 0:88e313c910d0 764
jhon309 0:88e313c910d0 765 /** \brief Get FPEXC
jhon309 0:88e313c910d0 766
jhon309 0:88e313c910d0 767 This function returns the current value of the Floating Point Exception Control register.
jhon309 0:88e313c910d0 768
jhon309 0:88e313c910d0 769 \return Floating Point Exception Control register value
jhon309 0:88e313c910d0 770 */
jhon309 0:88e313c910d0 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
jhon309 0:88e313c910d0 772 {
jhon309 0:88e313c910d0 773 #if (__FPU_PRESENT == 1)
jhon309 0:88e313c910d0 774 #if 1
jhon309 0:88e313c910d0 775 uint32_t result;
jhon309 0:88e313c910d0 776
jhon309 0:88e313c910d0 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
jhon309 0:88e313c910d0 778 return (result);
jhon309 0:88e313c910d0 779 #else
jhon309 0:88e313c910d0 780 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:88e313c910d0 781 return(__regfpexc);
jhon309 0:88e313c910d0 782 #endif
jhon309 0:88e313c910d0 783 #else
jhon309 0:88e313c910d0 784 return(0);
jhon309 0:88e313c910d0 785 #endif
jhon309 0:88e313c910d0 786 }
jhon309 0:88e313c910d0 787
jhon309 0:88e313c910d0 788
jhon309 0:88e313c910d0 789 /** \brief Set FPEXC
jhon309 0:88e313c910d0 790
jhon309 0:88e313c910d0 791 This function assigns the given value to the Floating Point Exception Control register.
jhon309 0:88e313c910d0 792
jhon309 0:88e313c910d0 793 \param [in] fpscr Floating Point Exception Control value to set
jhon309 0:88e313c910d0 794 */
jhon309 0:88e313c910d0 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jhon309 0:88e313c910d0 796 {
jhon309 0:88e313c910d0 797 #if (__FPU_PRESENT == 1)
jhon309 0:88e313c910d0 798 #if 1
jhon309 0:88e313c910d0 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
jhon309 0:88e313c910d0 800 #else
jhon309 0:88e313c910d0 801 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:88e313c910d0 802 __regfpexc = (fpexc);
jhon309 0:88e313c910d0 803 #endif
jhon309 0:88e313c910d0 804 #endif
jhon309 0:88e313c910d0 805 }
jhon309 0:88e313c910d0 806
jhon309 0:88e313c910d0 807 /** \brief Get CPACR
jhon309 0:88e313c910d0 808
jhon309 0:88e313c910d0 809 This function returns the current value of the Coprocessor Access Control register.
jhon309 0:88e313c910d0 810
jhon309 0:88e313c910d0 811 \return Coprocessor Access Control register value
jhon309 0:88e313c910d0 812 */
jhon309 0:88e313c910d0 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
jhon309 0:88e313c910d0 814 {
jhon309 0:88e313c910d0 815 #if 1
jhon309 0:88e313c910d0 816 register uint32_t __regCPACR;
jhon309 0:88e313c910d0 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
jhon309 0:88e313c910d0 818 #else
jhon309 0:88e313c910d0 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:88e313c910d0 820 #endif
jhon309 0:88e313c910d0 821 return __regCPACR;
jhon309 0:88e313c910d0 822 }
jhon309 0:88e313c910d0 823
jhon309 0:88e313c910d0 824 /** \brief Set CPACR
jhon309 0:88e313c910d0 825
jhon309 0:88e313c910d0 826 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:88e313c910d0 827
jhon309 0:88e313c910d0 828 \param [in] cpacr Coporcessor Acccess Control value to set
jhon309 0:88e313c910d0 829 */
jhon309 0:88e313c910d0 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jhon309 0:88e313c910d0 831 {
jhon309 0:88e313c910d0 832 #if 1
jhon309 0:88e313c910d0 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
jhon309 0:88e313c910d0 834 #else
jhon309 0:88e313c910d0 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:88e313c910d0 836 __regCPACR = cpacr;
jhon309 0:88e313c910d0 837 #endif
jhon309 0:88e313c910d0 838 __ISB();
jhon309 0:88e313c910d0 839 }
jhon309 0:88e313c910d0 840
jhon309 0:88e313c910d0 841 /** \brief Get CBAR
jhon309 0:88e313c910d0 842
jhon309 0:88e313c910d0 843 This function returns the value of the Configuration Base Address register.
jhon309 0:88e313c910d0 844
jhon309 0:88e313c910d0 845 \return Configuration Base Address register value
jhon309 0:88e313c910d0 846 */
jhon309 0:88e313c910d0 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
jhon309 0:88e313c910d0 848 #if 1
jhon309 0:88e313c910d0 849 register uint32_t __regCBAR;
jhon309 0:88e313c910d0 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
jhon309 0:88e313c910d0 851 #else
jhon309 0:88e313c910d0 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jhon309 0:88e313c910d0 853 #endif
jhon309 0:88e313c910d0 854 return(__regCBAR);
jhon309 0:88e313c910d0 855 }
jhon309 0:88e313c910d0 856
jhon309 0:88e313c910d0 857 /** \brief Get TTBR0
jhon309 0:88e313c910d0 858
jhon309 0:88e313c910d0 859 This function returns the value of the Configuration Base Address register.
jhon309 0:88e313c910d0 860
jhon309 0:88e313c910d0 861 \return Translation Table Base Register 0 value
jhon309 0:88e313c910d0 862 */
jhon309 0:88e313c910d0 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
jhon309 0:88e313c910d0 864 #if 1
jhon309 0:88e313c910d0 865 register uint32_t __regTTBR0;
jhon309 0:88e313c910d0 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
jhon309 0:88e313c910d0 867 #else
jhon309 0:88e313c910d0 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:88e313c910d0 869 #endif
jhon309 0:88e313c910d0 870 return(__regTTBR0);
jhon309 0:88e313c910d0 871 }
jhon309 0:88e313c910d0 872
jhon309 0:88e313c910d0 873 /** \brief Set TTBR0
jhon309 0:88e313c910d0 874
jhon309 0:88e313c910d0 875 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:88e313c910d0 876
jhon309 0:88e313c910d0 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
jhon309 0:88e313c910d0 878 */
jhon309 0:88e313c910d0 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jhon309 0:88e313c910d0 880 #if 1
jhon309 0:88e313c910d0 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
jhon309 0:88e313c910d0 882 #else
jhon309 0:88e313c910d0 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:88e313c910d0 884 __regTTBR0 = ttbr0;
jhon309 0:88e313c910d0 885 #endif
jhon309 0:88e313c910d0 886 __ISB();
jhon309 0:88e313c910d0 887 }
jhon309 0:88e313c910d0 888
jhon309 0:88e313c910d0 889 /** \brief Get DACR
jhon309 0:88e313c910d0 890
jhon309 0:88e313c910d0 891 This function returns the value of the Domain Access Control Register.
jhon309 0:88e313c910d0 892
jhon309 0:88e313c910d0 893 \return Domain Access Control Register value
jhon309 0:88e313c910d0 894 */
jhon309 0:88e313c910d0 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
jhon309 0:88e313c910d0 896 #if 1
jhon309 0:88e313c910d0 897 register uint32_t __regDACR;
jhon309 0:88e313c910d0 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
jhon309 0:88e313c910d0 899 #else
jhon309 0:88e313c910d0 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:88e313c910d0 901 #endif
jhon309 0:88e313c910d0 902 return(__regDACR);
jhon309 0:88e313c910d0 903 }
jhon309 0:88e313c910d0 904
jhon309 0:88e313c910d0 905 /** \brief Set DACR
jhon309 0:88e313c910d0 906
jhon309 0:88e313c910d0 907 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:88e313c910d0 908
jhon309 0:88e313c910d0 909 \param [in] dacr Domain Access Control Register value to set
jhon309 0:88e313c910d0 910 */
jhon309 0:88e313c910d0 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jhon309 0:88e313c910d0 912 #if 1
jhon309 0:88e313c910d0 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
jhon309 0:88e313c910d0 914 #else
jhon309 0:88e313c910d0 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:88e313c910d0 916 __regDACR = dacr;
jhon309 0:88e313c910d0 917 #endif
jhon309 0:88e313c910d0 918 __ISB();
jhon309 0:88e313c910d0 919 }
jhon309 0:88e313c910d0 920
jhon309 0:88e313c910d0 921 /******************************** Cache and BTAC enable ****************************************************/
jhon309 0:88e313c910d0 922
jhon309 0:88e313c910d0 923 /** \brief Set SCTLR
jhon309 0:88e313c910d0 924
jhon309 0:88e313c910d0 925 This function assigns the given value to the System Control Register.
jhon309 0:88e313c910d0 926
jhon309 0:88e313c910d0 927 \param [in] sctlr System Control Register, value to set
jhon309 0:88e313c910d0 928 */
jhon309 0:88e313c910d0 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jhon309 0:88e313c910d0 930 {
jhon309 0:88e313c910d0 931 #if 1
jhon309 0:88e313c910d0 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
jhon309 0:88e313c910d0 933 #else
jhon309 0:88e313c910d0 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:88e313c910d0 935 __regSCTLR = sctlr;
jhon309 0:88e313c910d0 936 #endif
jhon309 0:88e313c910d0 937 }
jhon309 0:88e313c910d0 938
jhon309 0:88e313c910d0 939 /** \brief Get SCTLR
jhon309 0:88e313c910d0 940
jhon309 0:88e313c910d0 941 This function returns the value of the System Control Register.
jhon309 0:88e313c910d0 942
jhon309 0:88e313c910d0 943 \return System Control Register value
jhon309 0:88e313c910d0 944 */
jhon309 0:88e313c910d0 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
jhon309 0:88e313c910d0 946 #if 1
jhon309 0:88e313c910d0 947 register uint32_t __regSCTLR;
jhon309 0:88e313c910d0 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
jhon309 0:88e313c910d0 949 #else
jhon309 0:88e313c910d0 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:88e313c910d0 951 #endif
jhon309 0:88e313c910d0 952 return(__regSCTLR);
jhon309 0:88e313c910d0 953 }
jhon309 0:88e313c910d0 954
jhon309 0:88e313c910d0 955 /** \brief Enable Caches
jhon309 0:88e313c910d0 956
jhon309 0:88e313c910d0 957 Enable Caches
jhon309 0:88e313c910d0 958 */
jhon309 0:88e313c910d0 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
jhon309 0:88e313c910d0 960 // Set I bit 12 to enable I Cache
jhon309 0:88e313c910d0 961 // Set C bit 2 to enable D Cache
jhon309 0:88e313c910d0 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jhon309 0:88e313c910d0 963 }
jhon309 0:88e313c910d0 964
jhon309 0:88e313c910d0 965 /** \brief Disable Caches
jhon309 0:88e313c910d0 966
jhon309 0:88e313c910d0 967 Disable Caches
jhon309 0:88e313c910d0 968 */
jhon309 0:88e313c910d0 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
jhon309 0:88e313c910d0 970 // Clear I bit 12 to disable I Cache
jhon309 0:88e313c910d0 971 // Clear C bit 2 to disable D Cache
jhon309 0:88e313c910d0 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jhon309 0:88e313c910d0 973 __ISB();
jhon309 0:88e313c910d0 974 }
jhon309 0:88e313c910d0 975
jhon309 0:88e313c910d0 976 /** \brief Enable BTAC
jhon309 0:88e313c910d0 977
jhon309 0:88e313c910d0 978 Enable BTAC
jhon309 0:88e313c910d0 979 */
jhon309 0:88e313c910d0 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
jhon309 0:88e313c910d0 981 // Set Z bit 11 to enable branch prediction
jhon309 0:88e313c910d0 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
jhon309 0:88e313c910d0 983 __ISB();
jhon309 0:88e313c910d0 984 }
jhon309 0:88e313c910d0 985
jhon309 0:88e313c910d0 986 /** \brief Disable BTAC
jhon309 0:88e313c910d0 987
jhon309 0:88e313c910d0 988 Disable BTAC
jhon309 0:88e313c910d0 989 */
jhon309 0:88e313c910d0 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
jhon309 0:88e313c910d0 991 // Clear Z bit 11 to disable branch prediction
jhon309 0:88e313c910d0 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jhon309 0:88e313c910d0 993 }
jhon309 0:88e313c910d0 994
jhon309 0:88e313c910d0 995
jhon309 0:88e313c910d0 996 /** \brief Enable MMU
jhon309 0:88e313c910d0 997
jhon309 0:88e313c910d0 998 Enable MMU
jhon309 0:88e313c910d0 999 */
jhon309 0:88e313c910d0 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
jhon309 0:88e313c910d0 1001 // Set M bit 0 to enable the MMU
jhon309 0:88e313c910d0 1002 // Set AFE bit to enable simplified access permissions model
jhon309 0:88e313c910d0 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jhon309 0:88e313c910d0 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jhon309 0:88e313c910d0 1005 __ISB();
jhon309 0:88e313c910d0 1006 }
jhon309 0:88e313c910d0 1007
jhon309 0:88e313c910d0 1008 /** \brief Enable MMU
jhon309 0:88e313c910d0 1009
jhon309 0:88e313c910d0 1010 Enable MMU
jhon309 0:88e313c910d0 1011 */
jhon309 0:88e313c910d0 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
jhon309 0:88e313c910d0 1013 // Clear M bit 0 to disable the MMU
jhon309 0:88e313c910d0 1014 __set_SCTLR( __get_SCTLR() & ~1);
jhon309 0:88e313c910d0 1015 __ISB();
jhon309 0:88e313c910d0 1016 }
jhon309 0:88e313c910d0 1017
jhon309 0:88e313c910d0 1018 /******************************** TLB maintenance operations ************************************************/
jhon309 0:88e313c910d0 1019 /** \brief Invalidate the whole tlb
jhon309 0:88e313c910d0 1020
jhon309 0:88e313c910d0 1021 TLBIALL. Invalidate the whole tlb
jhon309 0:88e313c910d0 1022 */
jhon309 0:88e313c910d0 1023
jhon309 0:88e313c910d0 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jhon309 0:88e313c910d0 1025 #if 1
jhon309 0:88e313c910d0 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
jhon309 0:88e313c910d0 1027 #else
jhon309 0:88e313c910d0 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jhon309 0:88e313c910d0 1029 __TLBIALL = 0;
jhon309 0:88e313c910d0 1030 #endif
jhon309 0:88e313c910d0 1031 __DSB();
jhon309 0:88e313c910d0 1032 __ISB();
jhon309 0:88e313c910d0 1033 }
jhon309 0:88e313c910d0 1034
jhon309 0:88e313c910d0 1035 /******************************** BTB maintenance operations ************************************************/
jhon309 0:88e313c910d0 1036 /** \brief Invalidate entire branch predictor array
jhon309 0:88e313c910d0 1037
jhon309 0:88e313c910d0 1038 BPIALL. Branch Predictor Invalidate All.
jhon309 0:88e313c910d0 1039 */
jhon309 0:88e313c910d0 1040
jhon309 0:88e313c910d0 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
jhon309 0:88e313c910d0 1042 #if 1
jhon309 0:88e313c910d0 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
jhon309 0:88e313c910d0 1044 #else
jhon309 0:88e313c910d0 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jhon309 0:88e313c910d0 1046 __BPIALL = 0;
jhon309 0:88e313c910d0 1047 #endif
jhon309 0:88e313c910d0 1048 __DSB(); //ensure completion of the invalidation
jhon309 0:88e313c910d0 1049 __ISB(); //ensure instruction fetch path sees new state
jhon309 0:88e313c910d0 1050 }
jhon309 0:88e313c910d0 1051
jhon309 0:88e313c910d0 1052
jhon309 0:88e313c910d0 1053 /******************************** L1 cache operations ******************************************************/
jhon309 0:88e313c910d0 1054
jhon309 0:88e313c910d0 1055 /** \brief Invalidate the whole I$
jhon309 0:88e313c910d0 1056
jhon309 0:88e313c910d0 1057 ICIALLU. Instruction Cache Invalidate All to PoU
jhon309 0:88e313c910d0 1058 */
jhon309 0:88e313c910d0 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
jhon309 0:88e313c910d0 1060 #if 1
jhon309 0:88e313c910d0 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
jhon309 0:88e313c910d0 1062 #else
jhon309 0:88e313c910d0 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jhon309 0:88e313c910d0 1064 __ICIALLU = 0;
jhon309 0:88e313c910d0 1065 #endif
jhon309 0:88e313c910d0 1066 __DSB(); //ensure completion of the invalidation
jhon309 0:88e313c910d0 1067 __ISB(); //ensure instruction fetch path sees new I cache state
jhon309 0:88e313c910d0 1068 }
jhon309 0:88e313c910d0 1069
jhon309 0:88e313c910d0 1070 /** \brief Clean D$ by MVA
jhon309 0:88e313c910d0 1071
jhon309 0:88e313c910d0 1072 DCCMVAC. Data cache clean by MVA to PoC
jhon309 0:88e313c910d0 1073 */
jhon309 0:88e313c910d0 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jhon309 0:88e313c910d0 1075 #if 1
jhon309 0:88e313c910d0 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
jhon309 0:88e313c910d0 1077 #else
jhon309 0:88e313c910d0 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jhon309 0:88e313c910d0 1079 __DCCMVAC = (uint32_t)va;
jhon309 0:88e313c910d0 1080 #endif
jhon309 0:88e313c910d0 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:88e313c910d0 1082 }
jhon309 0:88e313c910d0 1083
jhon309 0:88e313c910d0 1084 /** \brief Invalidate D$ by MVA
jhon309 0:88e313c910d0 1085
jhon309 0:88e313c910d0 1086 DCIMVAC. Data cache invalidate by MVA to PoC
jhon309 0:88e313c910d0 1087 */
jhon309 0:88e313c910d0 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jhon309 0:88e313c910d0 1089 #if 1
jhon309 0:88e313c910d0 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
jhon309 0:88e313c910d0 1091 #else
jhon309 0:88e313c910d0 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jhon309 0:88e313c910d0 1093 __DCIMVAC = (uint32_t)va;
jhon309 0:88e313c910d0 1094 #endif
jhon309 0:88e313c910d0 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:88e313c910d0 1096 }
jhon309 0:88e313c910d0 1097
jhon309 0:88e313c910d0 1098 /** \brief Clean and Invalidate D$ by MVA
jhon309 0:88e313c910d0 1099
jhon309 0:88e313c910d0 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jhon309 0:88e313c910d0 1101 */
jhon309 0:88e313c910d0 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jhon309 0:88e313c910d0 1103 #if 1
jhon309 0:88e313c910d0 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
jhon309 0:88e313c910d0 1105 #else
jhon309 0:88e313c910d0 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jhon309 0:88e313c910d0 1107 __DCCIMVAC = (uint32_t)va;
jhon309 0:88e313c910d0 1108 #endif
jhon309 0:88e313c910d0 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:88e313c910d0 1110 }
jhon309 0:88e313c910d0 1111
jhon309 0:88e313c910d0 1112 /** \brief
jhon309 0:88e313c910d0 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jhon309 0:88e313c910d0 1114 */
jhon309 0:88e313c910d0 1115
jhon309 0:88e313c910d0 1116 /** \brief __v7_all_cache - helper function
jhon309 0:88e313c910d0 1117
jhon309 0:88e313c910d0 1118 */
jhon309 0:88e313c910d0 1119
jhon309 0:88e313c910d0 1120 extern void __v7_all_cache(uint32_t op);
jhon309 0:88e313c910d0 1121
jhon309 0:88e313c910d0 1122
jhon309 0:88e313c910d0 1123 /** \brief Invalidate the whole D$
jhon309 0:88e313c910d0 1124
jhon309 0:88e313c910d0 1125 DCISW. Invalidate by Set/Way
jhon309 0:88e313c910d0 1126 */
jhon309 0:88e313c910d0 1127
jhon309 0:88e313c910d0 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
jhon309 0:88e313c910d0 1129 __v7_all_cache(0);
jhon309 0:88e313c910d0 1130 }
jhon309 0:88e313c910d0 1131
jhon309 0:88e313c910d0 1132 /** \brief Clean the whole D$
jhon309 0:88e313c910d0 1133
jhon309 0:88e313c910d0 1134 DCCSW. Clean by Set/Way
jhon309 0:88e313c910d0 1135 */
jhon309 0:88e313c910d0 1136
jhon309 0:88e313c910d0 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
jhon309 0:88e313c910d0 1138 __v7_all_cache(1);
jhon309 0:88e313c910d0 1139 }
jhon309 0:88e313c910d0 1140
jhon309 0:88e313c910d0 1141 /** \brief Clean and invalidate the whole D$
jhon309 0:88e313c910d0 1142
jhon309 0:88e313c910d0 1143 DCCISW. Clean and Invalidate by Set/Way
jhon309 0:88e313c910d0 1144 */
jhon309 0:88e313c910d0 1145
jhon309 0:88e313c910d0 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jhon309 0:88e313c910d0 1147 __v7_all_cache(2);
jhon309 0:88e313c910d0 1148 }
jhon309 0:88e313c910d0 1149
jhon309 0:88e313c910d0 1150 #include "core_ca_mmu.h"
jhon309 0:88e313c910d0 1151
jhon309 0:88e313c910d0 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
jhon309 0:88e313c910d0 1153
jhon309 0:88e313c910d0 1154 #error TASKING Compiler support not implemented for Cortex-A
jhon309 0:88e313c910d0 1155
jhon309 0:88e313c910d0 1156 #endif
jhon309 0:88e313c910d0 1157
jhon309 0:88e313c910d0 1158 /*@} end of CMSIS_Core_RegAccFunctions */
jhon309 0:88e313c910d0 1159
jhon309 0:88e313c910d0 1160
jhon309 0:88e313c910d0 1161 #endif /* __CORE_CAFUNC_H__ */