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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@0:88e313c910d0, 2015-08-13 (annotated)

Committer:: jhon309
Date:: Thu Aug 13 00:20:09 2015 +0000
Revision:: 0:88e313c910d0

RTC Example

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User	Revision	Line number	New contents of line
jhon309	0:88e313c910d0	1	/**
jhon309	0:88e313c910d0	2	******************************************************************************
jhon309	0:88e313c910d0	3	* @file stm32f0xx_hal_rcc_ex.h
jhon309	0:88e313c910d0	4	* @author MCD Application Team
jhon309	0:88e313c910d0	5	* @version V1.2.0
jhon309	0:88e313c910d0	6	* @date 11-December-2014
jhon309	0:88e313c910d0	7	* @brief Header file of RCC HAL Extension module.
jhon309	0:88e313c910d0	8	******************************************************************************
jhon309	0:88e313c910d0	9	* @attention
jhon309	0:88e313c910d0	10	*
jhon309	0:88e313c910d0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309	0:88e313c910d0	12	*
jhon309	0:88e313c910d0	13	* Redistribution and use in source and binary forms, with or without modification,
jhon309	0:88e313c910d0	14	* are permitted provided that the following conditions are met:
jhon309	0:88e313c910d0	15	* 1. Redistributions of source code must retain the above copyright notice,
jhon309	0:88e313c910d0	16	* this list of conditions and the following disclaimer.
jhon309	0:88e313c910d0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309	0:88e313c910d0	18	* this list of conditions and the following disclaimer in the documentation
jhon309	0:88e313c910d0	19	* and/or other materials provided with the distribution.
jhon309	0:88e313c910d0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309	0:88e313c910d0	21	* may be used to endorse or promote products derived from this software
jhon309	0:88e313c910d0	22	* without specific prior written permission.
jhon309	0:88e313c910d0	23	*
jhon309	0:88e313c910d0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309	0:88e313c910d0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309	0:88e313c910d0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309	0:88e313c910d0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309	0:88e313c910d0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309	0:88e313c910d0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309	0:88e313c910d0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309	0:88e313c910d0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309	0:88e313c910d0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309	0:88e313c910d0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309	0:88e313c910d0	34	*
jhon309	0:88e313c910d0	35	******************************************************************************
jhon309	0:88e313c910d0	36	*/
jhon309	0:88e313c910d0	37
jhon309	0:88e313c910d0	38	/* Define to prevent recursive inclusion -------------------------------------*/
jhon309	0:88e313c910d0	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
jhon309	0:88e313c910d0	40	#define __STM32F0xx_HAL_RCC_EX_H
jhon309	0:88e313c910d0	41
jhon309	0:88e313c910d0	42	#ifdef __cplusplus
jhon309	0:88e313c910d0	43	extern "C" {
jhon309	0:88e313c910d0	44	#endif
jhon309	0:88e313c910d0	45
jhon309	0:88e313c910d0	46	/* Includes ------------------------------------------------------------------*/
jhon309	0:88e313c910d0	47	#include "stm32f0xx_hal_def.h"
jhon309	0:88e313c910d0	48
jhon309	0:88e313c910d0	49	/** @addtogroup STM32F0xx_HAL_Driver
jhon309	0:88e313c910d0	50	* @{
jhon309	0:88e313c910d0	51	*/
jhon309	0:88e313c910d0	52
jhon309	0:88e313c910d0	53	/** @addtogroup RCCEx
jhon309	0:88e313c910d0	54	* @{
jhon309	0:88e313c910d0	55	*/
jhon309	0:88e313c910d0	56
jhon309	0:88e313c910d0	57	/* Exported types ------------------------------------------------------------*/
jhon309	0:88e313c910d0	58
jhon309	0:88e313c910d0	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
jhon309	0:88e313c910d0	60	* @{
jhon309	0:88e313c910d0	61	*/
jhon309	0:88e313c910d0	62
jhon309	0:88e313c910d0	63	/**
jhon309	0:88e313c910d0	64	* @brief RCC extended clocks structure definition
jhon309	0:88e313c910d0	65	*/
jhon309	0:88e313c910d0	66	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:88e313c910d0	67	defined(STM32F030xC)
jhon309	0:88e313c910d0	68	typedef struct
jhon309	0:88e313c910d0	69	{
jhon309	0:88e313c910d0	70	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	71	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	72
jhon309	0:88e313c910d0	73	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	74	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	75
jhon309	0:88e313c910d0	76	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	77	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	78
jhon309	0:88e313c910d0	79	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	80	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	81
jhon309	0:88e313c910d0	82	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	83	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
jhon309	0:88e313c910d0	84	STM32F030xC */
jhon309	0:88e313c910d0	85
jhon309	0:88e313c910d0	86	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:88e313c910d0	87	typedef struct
jhon309	0:88e313c910d0	88	{
jhon309	0:88e313c910d0	89	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	90	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	91
jhon309	0:88e313c910d0	92	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	93	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	94
jhon309	0:88e313c910d0	95	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	96	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	97
jhon309	0:88e313c910d0	98	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	99	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	100
jhon309	0:88e313c910d0	101	uint32_t UsbClockSelection; /*!< USB clock source
jhon309	0:88e313c910d0	102	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
jhon309	0:88e313c910d0	103
jhon309	0:88e313c910d0	104	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	105	#endif /* STM32F070x6 \|\| STM32F070xB */
jhon309	0:88e313c910d0	106
jhon309	0:88e313c910d0	107	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
jhon309	0:88e313c910d0	108	typedef struct
jhon309	0:88e313c910d0	109	{
jhon309	0:88e313c910d0	110	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	111	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	112
jhon309	0:88e313c910d0	113	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	114	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	115
jhon309	0:88e313c910d0	116	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	117	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	118
jhon309	0:88e313c910d0	119	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	120	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	121
jhon309	0:88e313c910d0	122	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:88e313c910d0	123	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:88e313c910d0	124
jhon309	0:88e313c910d0	125	uint32_t UsbClockSelection; /*!< USB clock source
jhon309	0:88e313c910d0	126	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
jhon309	0:88e313c910d0	127
jhon309	0:88e313c910d0	128	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	129	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:88e313c910d0	130
jhon309	0:88e313c910d0	131	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:88e313c910d0	132	typedef struct
jhon309	0:88e313c910d0	133	{
jhon309	0:88e313c910d0	134	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	135	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	136
jhon309	0:88e313c910d0	137	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	138	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	139
jhon309	0:88e313c910d0	140	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	141	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	142
jhon309	0:88e313c910d0	143	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	144	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	145
jhon309	0:88e313c910d0	146	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:88e313c910d0	147	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:88e313c910d0	148
jhon309	0:88e313c910d0	149	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	150	#endif /* STM32F051x8 \|\| STM32F058xx */
jhon309	0:88e313c910d0	151
jhon309	0:88e313c910d0	152	#if defined(STM32F071xB)
jhon309	0:88e313c910d0	153	typedef struct
jhon309	0:88e313c910d0	154	{
jhon309	0:88e313c910d0	155	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	156	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	157
jhon309	0:88e313c910d0	158	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	159	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	160
jhon309	0:88e313c910d0	161	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	162	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	163
jhon309	0:88e313c910d0	164	uint32_t Usart2ClockSelection; /*!< USART2 clock source
jhon309	0:88e313c910d0	165	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
jhon309	0:88e313c910d0	166
jhon309	0:88e313c910d0	167	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	168	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	169
jhon309	0:88e313c910d0	170	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:88e313c910d0	171	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:88e313c910d0	172
jhon309	0:88e313c910d0	173	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	174	#endif /* STM32F071xB */
jhon309	0:88e313c910d0	175
jhon309	0:88e313c910d0	176	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:88e313c910d0	177	typedef struct
jhon309	0:88e313c910d0	178	{
jhon309	0:88e313c910d0	179	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	180	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	181
jhon309	0:88e313c910d0	182	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	183	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	184
jhon309	0:88e313c910d0	185	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	186	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	187
jhon309	0:88e313c910d0	188	uint32_t Usart2ClockSelection; /*!< USART2 clock source
jhon309	0:88e313c910d0	189	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
jhon309	0:88e313c910d0	190
jhon309	0:88e313c910d0	191	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	192	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	193
jhon309	0:88e313c910d0	194	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:88e313c910d0	195	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:88e313c910d0	196
jhon309	0:88e313c910d0	197	uint32_t UsbClockSelection; /*!< USB clock source
jhon309	0:88e313c910d0	198	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
jhon309	0:88e313c910d0	199
jhon309	0:88e313c910d0	200	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	201	#endif /* STM32F072xB \|\| STM32F078xx */
jhon309	0:88e313c910d0	202
jhon309	0:88e313c910d0	203
jhon309	0:88e313c910d0	204	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	205	typedef struct
jhon309	0:88e313c910d0	206	{
jhon309	0:88e313c910d0	207	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:88e313c910d0	208	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:88e313c910d0	209
jhon309	0:88e313c910d0	210	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:88e313c910d0	211	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:88e313c910d0	212
jhon309	0:88e313c910d0	213	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:88e313c910d0	214	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:88e313c910d0	215
jhon309	0:88e313c910d0	216	uint32_t Usart2ClockSelection; /*!< USART2 clock source
jhon309	0:88e313c910d0	217	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
jhon309	0:88e313c910d0	218
jhon309	0:88e313c910d0	219	uint32_t Usart3ClockSelection; /*!< USART3 clock source
jhon309	0:88e313c910d0	220	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
jhon309	0:88e313c910d0	221
jhon309	0:88e313c910d0	222	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:88e313c910d0	223	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:88e313c910d0	224
jhon309	0:88e313c910d0	225	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:88e313c910d0	226	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:88e313c910d0	227
jhon309	0:88e313c910d0	228	}RCC_PeriphCLKInitTypeDef;
jhon309	0:88e313c910d0	229	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	230
jhon309	0:88e313c910d0	231	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	232	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	233	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	234
jhon309	0:88e313c910d0	235	/**
jhon309	0:88e313c910d0	236	* @brief RCC_CRS Init structure definition
jhon309	0:88e313c910d0	237	*/
jhon309	0:88e313c910d0	238	typedef struct
jhon309	0:88e313c910d0	239	{
jhon309	0:88e313c910d0	240	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
jhon309	0:88e313c910d0	241	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
jhon309	0:88e313c910d0	242
jhon309	0:88e313c910d0	243	uint32_t Source; /*!< Specifies the SYNC signal source.
jhon309	0:88e313c910d0	244	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
jhon309	0:88e313c910d0	245
jhon309	0:88e313c910d0	246	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
jhon309	0:88e313c910d0	247	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
jhon309	0:88e313c910d0	248
jhon309	0:88e313c910d0	249	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
jhon309	0:88e313c910d0	250	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
jhon309	0:88e313c910d0	251	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
jhon309	0:88e313c910d0	252
jhon309	0:88e313c910d0	253	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
jhon309	0:88e313c910d0	254	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
jhon309	0:88e313c910d0	255
jhon309	0:88e313c910d0	256	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
jhon309	0:88e313c910d0	257	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
jhon309	0:88e313c910d0	258
jhon309	0:88e313c910d0	259	}RCC_CRSInitTypeDef;
jhon309	0:88e313c910d0	260
jhon309	0:88e313c910d0	261	/**
jhon309	0:88e313c910d0	262	* @brief RCC_CRS Synchronization structure definition
jhon309	0:88e313c910d0	263	*/
jhon309	0:88e313c910d0	264	typedef struct
jhon309	0:88e313c910d0	265	{
jhon309	0:88e313c910d0	266	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
jhon309	0:88e313c910d0	267	This parameter must be a number between 0 and 0xFFFF*/
jhon309	0:88e313c910d0	268
jhon309	0:88e313c910d0	269	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
jhon309	0:88e313c910d0	270	This parameter must be a number between 0 and 0x3F */
jhon309	0:88e313c910d0	271
jhon309	0:88e313c910d0	272	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
jhon309	0:88e313c910d0	273	value latched in the time of the last SYNC event.
jhon309	0:88e313c910d0	274	This parameter must be a number between 0 and 0xFFFF */
jhon309	0:88e313c910d0	275
jhon309	0:88e313c910d0	276	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
jhon309	0:88e313c910d0	277	frequency error counter latched in the time of the last SYNC event.
jhon309	0:88e313c910d0	278	It shows whether the actual frequency is below or above the target.
jhon309	0:88e313c910d0	279	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
jhon309	0:88e313c910d0	280
jhon309	0:88e313c910d0	281	}RCC_CRSSynchroInfoTypeDef;
jhon309	0:88e313c910d0	282
jhon309	0:88e313c910d0	283	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:88e313c910d0	284	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	285	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	286
jhon309	0:88e313c910d0	287	/**
jhon309	0:88e313c910d0	288	* @}
jhon309	0:88e313c910d0	289	*/
jhon309	0:88e313c910d0	290
jhon309	0:88e313c910d0	291	/* Exported constants --------------------------------------------------------*/
jhon309	0:88e313c910d0	292
jhon309	0:88e313c910d0	293	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
jhon309	0:88e313c910d0	294	* @{
jhon309	0:88e313c910d0	295	*/
jhon309	0:88e313c910d0	296
jhon309	0:88e313c910d0	297	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
jhon309	0:88e313c910d0	298	* @{
jhon309	0:88e313c910d0	299	*/
jhon309	0:88e313c910d0	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	301	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	302	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	303
jhon309	0:88e313c910d0	304	#define RCC_CRS_NONE ((uint32_t)0x00000000)
jhon309	0:88e313c910d0	305	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	306	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
jhon309	0:88e313c910d0	307	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
jhon309	0:88e313c910d0	308	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
jhon309	0:88e313c910d0	309	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
jhon309	0:88e313c910d0	310	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	311
jhon309	0:88e313c910d0	312	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:88e313c910d0	313	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	314	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	315	/**
jhon309	0:88e313c910d0	316	* @}
jhon309	0:88e313c910d0	317	*/
jhon309	0:88e313c910d0	318
jhon309	0:88e313c910d0	319	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
jhon309	0:88e313c910d0	320	* @{
jhon309	0:88e313c910d0	321	*/
jhon309	0:88e313c910d0	322	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:88e313c910d0	323	defined(STM32F030xC)
jhon309	0:88e313c910d0	324	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	325	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	326	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	327
jhon309	0:88e313c910d0	328	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:88e313c910d0	329	RCC_PERIPHCLK_RTC))
jhon309	0:88e313c910d0	330	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
jhon309	0:88e313c910d0	331	STM32F030xC */
jhon309	0:88e313c910d0	332
jhon309	0:88e313c910d0	333	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:88e313c910d0	334	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	335	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	336	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	337	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
jhon309	0:88e313c910d0	338
jhon309	0:88e313c910d0	339	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:88e313c910d0	340	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
jhon309	0:88e313c910d0	341	#endif /* STM32F070x6 \|\| STM32F070xB */
jhon309	0:88e313c910d0	342
jhon309	0:88e313c910d0	343	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
jhon309	0:88e313c910d0	344	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	345	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	346	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:88e313c910d0	347	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	348	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
jhon309	0:88e313c910d0	349
jhon309	0:88e313c910d0	350	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:88e313c910d0	351	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
jhon309	0:88e313c910d0	352	RCC_PERIPHCLK_USB))
jhon309	0:88e313c910d0	353	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:88e313c910d0	354
jhon309	0:88e313c910d0	355	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:88e313c910d0	356	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	357	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	358	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:88e313c910d0	359	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	360
jhon309	0:88e313c910d0	361	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:88e313c910d0	362	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
jhon309	0:88e313c910d0	363	#endif /* STM32F051x8 \|\| STM32F058xx */
jhon309	0:88e313c910d0	364
jhon309	0:88e313c910d0	365	#if defined(STM32F071xB)
jhon309	0:88e313c910d0	366	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	367	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
jhon309	0:88e313c910d0	368	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	369	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:88e313c910d0	370	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	371
jhon309	0:88e313c910d0	372	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
jhon309	0:88e313c910d0	373	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
jhon309	0:88e313c910d0	374	RCC_PERIPHCLK_RTC))
jhon309	0:88e313c910d0	375	#endif /* STM32F071xB */
jhon309	0:88e313c910d0	376
jhon309	0:88e313c910d0	377	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:88e313c910d0	378	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	379	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
jhon309	0:88e313c910d0	380	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	381	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:88e313c910d0	382	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	383	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
jhon309	0:88e313c910d0	384
jhon309	0:88e313c910d0	385	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
jhon309	0:88e313c910d0	386	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
jhon309	0:88e313c910d0	387	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
jhon309	0:88e313c910d0	388	#endif /* STM32F072xB \|\| STM32F078xx */
jhon309	0:88e313c910d0	389
jhon309	0:88e313c910d0	390	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	391	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:88e313c910d0	392	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
jhon309	0:88e313c910d0	393	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:88e313c910d0	394	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:88e313c910d0	395	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:88e313c910d0	396	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
jhon309	0:88e313c910d0	397
jhon309	0:88e313c910d0	398	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
jhon309	0:88e313c910d0	399	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
jhon309	0:88e313c910d0	400	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
jhon309	0:88e313c910d0	401	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	402
jhon309	0:88e313c910d0	403	/**
jhon309	0:88e313c910d0	404	* @}
jhon309	0:88e313c910d0	405	*/
jhon309	0:88e313c910d0	406
jhon309	0:88e313c910d0	407	/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
jhon309	0:88e313c910d0	408	* @{
jhon309	0:88e313c910d0	409	*/
jhon309	0:88e313c910d0	410
jhon309	0:88e313c910d0	411	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	412
jhon309	0:88e313c910d0	413	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
jhon309	0:88e313c910d0	414
jhon309	0:88e313c910d0	415	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
jhon309	0:88e313c910d0	416	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
jhon309	0:88e313c910d0	417	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
jhon309	0:88e313c910d0	418	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
jhon309	0:88e313c910d0	419	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	420	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
jhon309	0:88e313c910d0	421	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
jhon309	0:88e313c910d0	422	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
jhon309	0:88e313c910d0	423	((SOURCE) == RCC_MCOSOURCE_HSI14))
jhon309	0:88e313c910d0	424
jhon309	0:88e313c910d0	425	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
jhon309	0:88e313c910d0	426
jhon309	0:88e313c910d0	427	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:88e313c910d0	428
jhon309	0:88e313c910d0	429	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
jhon309	0:88e313c910d0	430	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
jhon309	0:88e313c910d0	431	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
jhon309	0:88e313c910d0	432	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
jhon309	0:88e313c910d0	433	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	434	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
jhon309	0:88e313c910d0	435	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
jhon309	0:88e313c910d0	436	((SOURCE) == RCC_MCOSOURCE_HSI14))
jhon309	0:88e313c910d0	437
jhon309	0:88e313c910d0	438	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
jhon309	0:88e313c910d0	439
jhon309	0:88e313c910d0	440	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	441	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	442	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	443
jhon309	0:88e313c910d0	444	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
jhon309	0:88e313c910d0	445	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
jhon309	0:88e313c910d0	446
jhon309	0:88e313c910d0	447	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
jhon309	0:88e313c910d0	448	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
jhon309	0:88e313c910d0	449	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
jhon309	0:88e313c910d0	450	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
jhon309	0:88e313c910d0	451	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	452	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
jhon309	0:88e313c910d0	453	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
jhon309	0:88e313c910d0	454	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
jhon309	0:88e313c910d0	455	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
jhon309	0:88e313c910d0	456	((SOURCE) == RCC_MCOSOURCE_HSI48))
jhon309	0:88e313c910d0	457
jhon309	0:88e313c910d0	458	#define RCC_IT_HSI48 ((uint8_t)0x40)
jhon309	0:88e313c910d0	459
jhon309	0:88e313c910d0	460	/* Flags in the CR2 register */
jhon309	0:88e313c910d0	461	#define RCC_CR2_HSI48RDY_BitNumber 16
jhon309	0:88e313c910d0	462
jhon309	0:88e313c910d0	463	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
jhon309	0:88e313c910d0	464
jhon309	0:88e313c910d0	465	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	467	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	468	/**
jhon309	0:88e313c910d0	469	* @}
jhon309	0:88e313c910d0	470	*/
jhon309	0:88e313c910d0	471
jhon309	0:88e313c910d0	472	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:88e313c910d0	473
jhon309	0:88e313c910d0	474	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
jhon309	0:88e313c910d0	475	* @{
jhon309	0:88e313c910d0	476	*/
jhon309	0:88e313c910d0	477	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
jhon309	0:88e313c910d0	478	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
jhon309	0:88e313c910d0	479
jhon309	0:88e313c910d0	480	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
jhon309	0:88e313c910d0	481	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
jhon309	0:88e313c910d0	482	/**
jhon309	0:88e313c910d0	483	* @}
jhon309	0:88e313c910d0	484	*/
jhon309	0:88e313c910d0	485
jhon309	0:88e313c910d0	486	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
jhon309	0:88e313c910d0	487
jhon309	0:88e313c910d0	488	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:88e313c910d0	489
jhon309	0:88e313c910d0	490	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
jhon309	0:88e313c910d0	491	* @{
jhon309	0:88e313c910d0	492	*/
jhon309	0:88e313c910d0	493	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
jhon309	0:88e313c910d0	494
jhon309	0:88e313c910d0	495	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
jhon309	0:88e313c910d0	496	/**
jhon309	0:88e313c910d0	497	* @}
jhon309	0:88e313c910d0	498	*/
jhon309	0:88e313c910d0	499
jhon309	0:88e313c910d0	500	#endif /* STM32F070x6 \|\| STM32F070xB */
jhon309	0:88e313c910d0	501
jhon309	0:88e313c910d0	502	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	503	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	504
jhon309	0:88e313c910d0	505	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
jhon309	0:88e313c910d0	506	* @{
jhon309	0:88e313c910d0	507	*/
jhon309	0:88e313c910d0	508	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
jhon309	0:88e313c910d0	509	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
jhon309	0:88e313c910d0	510	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
jhon309	0:88e313c910d0	511	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
jhon309	0:88e313c910d0	512
jhon309	0:88e313c910d0	513	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
jhon309	0:88e313c910d0	514	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
jhon309	0:88e313c910d0	515	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
jhon309	0:88e313c910d0	516	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
jhon309	0:88e313c910d0	517	/**
jhon309	0:88e313c910d0	518	* @}
jhon309	0:88e313c910d0	519	*/
jhon309	0:88e313c910d0	520
jhon309	0:88e313c910d0	521	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	522	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	523
jhon309	0:88e313c910d0	524	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	525
jhon309	0:88e313c910d0	526	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
jhon309	0:88e313c910d0	527	* @{
jhon309	0:88e313c910d0	528	*/
jhon309	0:88e313c910d0	529	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
jhon309	0:88e313c910d0	530	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
jhon309	0:88e313c910d0	531	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
jhon309	0:88e313c910d0	532	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
jhon309	0:88e313c910d0	533
jhon309	0:88e313c910d0	534	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
jhon309	0:88e313c910d0	535	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
jhon309	0:88e313c910d0	536	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
jhon309	0:88e313c910d0	537	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
jhon309	0:88e313c910d0	538	/**
jhon309	0:88e313c910d0	539	* @}
jhon309	0:88e313c910d0	540	*/
jhon309	0:88e313c910d0	541
jhon309	0:88e313c910d0	542	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	543
jhon309	0:88e313c910d0	544
jhon309	0:88e313c910d0	545	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	546	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	547	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	548	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	549
jhon309	0:88e313c910d0	550	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
jhon309	0:88e313c910d0	551	* @{
jhon309	0:88e313c910d0	552	*/
jhon309	0:88e313c910d0	553	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
jhon309	0:88e313c910d0	554	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
jhon309	0:88e313c910d0	555
jhon309	0:88e313c910d0	556	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	557	((SOURCE) == RCC_CECCLKSOURCE_LSE))
jhon309	0:88e313c910d0	558	/**
jhon309	0:88e313c910d0	559	* @}
jhon309	0:88e313c910d0	560	*/
jhon309	0:88e313c910d0	561
jhon309	0:88e313c910d0	562	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	563	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	564	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	565	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	566
jhon309	0:88e313c910d0	567	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	568	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	569	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	570
jhon309	0:88e313c910d0	571	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
jhon309	0:88e313c910d0	572	* @{
jhon309	0:88e313c910d0	573	*/
jhon309	0:88e313c910d0	574	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
jhon309	0:88e313c910d0	575	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
jhon309	0:88e313c910d0	576
jhon309	0:88e313c910d0	577	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	578	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
jhon309	0:88e313c910d0	579	((SOURCE) == RCC_PLLSOURCE_HSE))
jhon309	0:88e313c910d0	580	/**
jhon309	0:88e313c910d0	581	* @}
jhon309	0:88e313c910d0	582	*/
jhon309	0:88e313c910d0	583
jhon309	0:88e313c910d0	584	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
jhon309	0:88e313c910d0	585	* @{
jhon309	0:88e313c910d0	586	*/
jhon309	0:88e313c910d0	587	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
jhon309	0:88e313c910d0	588
jhon309	0:88e313c910d0	589	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	590	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
jhon309	0:88e313c910d0	591	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
jhon309	0:88e313c910d0	592	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
jhon309	0:88e313c910d0	593
jhon309	0:88e313c910d0	594	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
jhon309	0:88e313c910d0	595
jhon309	0:88e313c910d0	596	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
jhon309	0:88e313c910d0	597	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
jhon309	0:88e313c910d0	598	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
jhon309	0:88e313c910d0	599	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
jhon309	0:88e313c910d0	600	/**
jhon309	0:88e313c910d0	601	* @}
jhon309	0:88e313c910d0	602	*/
jhon309	0:88e313c910d0	603
jhon309	0:88e313c910d0	604	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
jhon309	0:88e313c910d0	605	* @{
jhon309	0:88e313c910d0	606	*/
jhon309	0:88e313c910d0	607	#define RCC_HSI48_OFF ((uint8_t)0x00)
jhon309	0:88e313c910d0	608	#define RCC_HSI48_ON ((uint8_t)0x01)
jhon309	0:88e313c910d0	609
jhon309	0:88e313c910d0	610	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
jhon309	0:88e313c910d0	611	/**
jhon309	0:88e313c910d0	612	* @}
jhon309	0:88e313c910d0	613	*/
jhon309	0:88e313c910d0	614	#else
jhon309	0:88e313c910d0	615	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
jhon309	0:88e313c910d0	616	* @{
jhon309	0:88e313c910d0	617	*/
jhon309	0:88e313c910d0	618
jhon309	0:88e313c910d0	619	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	620	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
jhon309	0:88e313c910d0	621	#else
jhon309	0:88e313c910d0	622	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
jhon309	0:88e313c910d0	623	#endif
jhon309	0:88e313c910d0	624
jhon309	0:88e313c910d0	625	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	626	((SOURCE) == RCC_PLLSOURCE_HSE))
jhon309	0:88e313c910d0	627	/**
jhon309	0:88e313c910d0	628	* @}
jhon309	0:88e313c910d0	629	*/
jhon309	0:88e313c910d0	630
jhon309	0:88e313c910d0	631	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
jhon309	0:88e313c910d0	632	* @{
jhon309	0:88e313c910d0	633	*/
jhon309	0:88e313c910d0	634	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
jhon309	0:88e313c910d0	635	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
jhon309	0:88e313c910d0	636	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
jhon309	0:88e313c910d0	637
jhon309	0:88e313c910d0	638	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
jhon309	0:88e313c910d0	639	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
jhon309	0:88e313c910d0	640	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
jhon309	0:88e313c910d0	641	/**
jhon309	0:88e313c910d0	642	* @}
jhon309	0:88e313c910d0	643	*/
jhon309	0:88e313c910d0	644
jhon309	0:88e313c910d0	645	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
jhon309	0:88e313c910d0	646	* @{
jhon309	0:88e313c910d0	647	*/
jhon309	0:88e313c910d0	648	#define RCC_HSI48_OFF ((uint8_t)0x00)
jhon309	0:88e313c910d0	649
jhon309	0:88e313c910d0	650	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
jhon309	0:88e313c910d0	651	/**
jhon309	0:88e313c910d0	652	* @}
jhon309	0:88e313c910d0	653	*/
jhon309	0:88e313c910d0	654
jhon309	0:88e313c910d0	655	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	656	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	657	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	658
jhon309	0:88e313c910d0	659
jhon309	0:88e313c910d0	660	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
jhon309	0:88e313c910d0	661	* @{
jhon309	0:88e313c910d0	662	*/
jhon309	0:88e313c910d0	663
jhon309	0:88e313c910d0	664	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:88e313c910d0	665
jhon309	0:88e313c910d0	666	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
jhon309	0:88e313c910d0	667
jhon309	0:88e313c910d0	668	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
jhon309	0:88e313c910d0	669
jhon309	0:88e313c910d0	670	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
jhon309	0:88e313c910d0	671
jhon309	0:88e313c910d0	672	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	673	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	674	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	675	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	676
jhon309	0:88e313c910d0	677	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
jhon309	0:88e313c910d0	678	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
jhon309	0:88e313c910d0	679	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
jhon309	0:88e313c910d0	680	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
jhon309	0:88e313c910d0	681	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
jhon309	0:88e313c910d0	682	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
jhon309	0:88e313c910d0	683	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
jhon309	0:88e313c910d0	684	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
jhon309	0:88e313c910d0	685
jhon309	0:88e313c910d0	686	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
jhon309	0:88e313c910d0	687	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
jhon309	0:88e313c910d0	688	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
jhon309	0:88e313c910d0	689	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
jhon309	0:88e313c910d0	690
jhon309	0:88e313c910d0	691	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	692	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
jhon309	0:88e313c910d0	693	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	694
jhon309	0:88e313c910d0	695	/**
jhon309	0:88e313c910d0	696	* @}
jhon309	0:88e313c910d0	697	*/
jhon309	0:88e313c910d0	698
jhon309	0:88e313c910d0	699	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	700	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	701	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	702
jhon309	0:88e313c910d0	703	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
jhon309	0:88e313c910d0	704	* @{
jhon309	0:88e313c910d0	705	*/
jhon309	0:88e313c910d0	706	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
jhon309	0:88e313c910d0	707	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
jhon309	0:88e313c910d0	708	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
jhon309	0:88e313c910d0	709
jhon309	0:88e313c910d0	710	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
jhon309	0:88e313c910d0	711	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
jhon309	0:88e313c910d0	712	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
jhon309	0:88e313c910d0	713	/**
jhon309	0:88e313c910d0	714	* @}
jhon309	0:88e313c910d0	715	*/
jhon309	0:88e313c910d0	716
jhon309	0:88e313c910d0	717	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
jhon309	0:88e313c910d0	718	* @{
jhon309	0:88e313c910d0	719	*/
jhon309	0:88e313c910d0	720	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
jhon309	0:88e313c910d0	721	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
jhon309	0:88e313c910d0	722	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
jhon309	0:88e313c910d0	723	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
jhon309	0:88e313c910d0	724	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
jhon309	0:88e313c910d0	725	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
jhon309	0:88e313c910d0	726	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
jhon309	0:88e313c910d0	727	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
jhon309	0:88e313c910d0	728
jhon309	0:88e313c910d0	729	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
jhon309	0:88e313c910d0	730	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
jhon309	0:88e313c910d0	731	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
jhon309	0:88e313c910d0	732	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
jhon309	0:88e313c910d0	733	/**
jhon309	0:88e313c910d0	734	* @}
jhon309	0:88e313c910d0	735	*/
jhon309	0:88e313c910d0	736
jhon309	0:88e313c910d0	737	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
jhon309	0:88e313c910d0	738	* @{
jhon309	0:88e313c910d0	739	*/
jhon309	0:88e313c910d0	740	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
jhon309	0:88e313c910d0	741	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
jhon309	0:88e313c910d0	742
jhon309	0:88e313c910d0	743	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
jhon309	0:88e313c910d0	744	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
jhon309	0:88e313c910d0	745	/**
jhon309	0:88e313c910d0	746	* @}
jhon309	0:88e313c910d0	747	*/
jhon309	0:88e313c910d0	748
jhon309	0:88e313c910d0	749	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
jhon309	0:88e313c910d0	750	* @{
jhon309	0:88e313c910d0	751	*/
jhon309	0:88e313c910d0	752	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
jhon309	0:88e313c910d0	753	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
jhon309	0:88e313c910d0	754
jhon309	0:88e313c910d0	755	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
jhon309	0:88e313c910d0	756	/**
jhon309	0:88e313c910d0	757	* @}
jhon309	0:88e313c910d0	758	*/
jhon309	0:88e313c910d0	759
jhon309	0:88e313c910d0	760	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
jhon309	0:88e313c910d0	761	* @{
jhon309	0:88e313c910d0	762	*/
jhon309	0:88e313c910d0	763	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
jhon309	0:88e313c910d0	764
jhon309	0:88e313c910d0	765	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
jhon309	0:88e313c910d0	766	/**
jhon309	0:88e313c910d0	767	* @}
jhon309	0:88e313c910d0	768	*/
jhon309	0:88e313c910d0	769
jhon309	0:88e313c910d0	770	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
jhon309	0:88e313c910d0	771	* @{
jhon309	0:88e313c910d0	772	*/
jhon309	0:88e313c910d0	773	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
jhon309	0:88e313c910d0	774	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
jhon309	0:88e313c910d0	775	corresponds to a higher output frequency */
jhon309	0:88e313c910d0	776
jhon309	0:88e313c910d0	777	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
jhon309	0:88e313c910d0	778	/**
jhon309	0:88e313c910d0	779	* @}
jhon309	0:88e313c910d0	780	*/
jhon309	0:88e313c910d0	781
jhon309	0:88e313c910d0	782	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
jhon309	0:88e313c910d0	783	* @{
jhon309	0:88e313c910d0	784	*/
jhon309	0:88e313c910d0	785	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
jhon309	0:88e313c910d0	786	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
jhon309	0:88e313c910d0	787
jhon309	0:88e313c910d0	788	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
jhon309	0:88e313c910d0	789	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
jhon309	0:88e313c910d0	790	/**
jhon309	0:88e313c910d0	791	* @}
jhon309	0:88e313c910d0	792	*/
jhon309	0:88e313c910d0	793
jhon309	0:88e313c910d0	794	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
jhon309	0:88e313c910d0	795	* @{
jhon309	0:88e313c910d0	796	*/
jhon309	0:88e313c910d0	797	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
jhon309	0:88e313c910d0	798	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
jhon309	0:88e313c910d0	799	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
jhon309	0:88e313c910d0	800	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
jhon309	0:88e313c910d0	801	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
jhon309	0:88e313c910d0	802	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
jhon309	0:88e313c910d0	803	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
jhon309	0:88e313c910d0	804
jhon309	0:88e313c910d0	805	/**
jhon309	0:88e313c910d0	806	* @}
jhon309	0:88e313c910d0	807	*/
jhon309	0:88e313c910d0	808
jhon309	0:88e313c910d0	809	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
jhon309	0:88e313c910d0	810	* @{
jhon309	0:88e313c910d0	811	*/
jhon309	0:88e313c910d0	812	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
jhon309	0:88e313c910d0	813	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
jhon309	0:88e313c910d0	814	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
jhon309	0:88e313c910d0	815	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
jhon309	0:88e313c910d0	816	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
jhon309	0:88e313c910d0	817	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
jhon309	0:88e313c910d0	818	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
jhon309	0:88e313c910d0	819
jhon309	0:88e313c910d0	820	/**
jhon309	0:88e313c910d0	821	* @}
jhon309	0:88e313c910d0	822	*/
jhon309	0:88e313c910d0	823
jhon309	0:88e313c910d0	824	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	825	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	826	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	827
jhon309	0:88e313c910d0	828	/**
jhon309	0:88e313c910d0	829	* @}
jhon309	0:88e313c910d0	830	*/
jhon309	0:88e313c910d0	831
jhon309	0:88e313c910d0	832	/* Exported macros ------------------------------------------------------------*/
jhon309	0:88e313c910d0	833	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
jhon309	0:88e313c910d0	834	* @{
jhon309	0:88e313c910d0	835	*/
jhon309	0:88e313c910d0	836
jhon309	0:88e313c910d0	837	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
jhon309	0:88e313c910d0	838	* @brief Enables or disables the AHB1 peripheral clock.
jhon309	0:88e313c910d0	839	* @note After reset, the peripheral clock (used for registers read/write access)
jhon309	0:88e313c910d0	840	* is disabled and the application software has to enable this clock before
jhon309	0:88e313c910d0	841	* using it.
jhon309	0:88e313c910d0	842	* @{
jhon309	0:88e313c910d0	843	*/
jhon309	0:88e313c910d0	844	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
jhon309	0:88e313c910d0	845	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	846	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	847	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	848
jhon309	0:88e313c910d0	849	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
jhon309	0:88e313c910d0	850
jhon309	0:88e313c910d0	851	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
jhon309	0:88e313c910d0	852
jhon309	0:88e313c910d0	853	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
jhon309	0:88e313c910d0	854	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	855	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	856	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	857
jhon309	0:88e313c910d0	858	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	859	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	860
jhon309	0:88e313c910d0	861	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
jhon309	0:88e313c910d0	862
jhon309	0:88e313c910d0	863	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
jhon309	0:88e313c910d0	864
jhon309	0:88e313c910d0	865	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	866	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	867
jhon309	0:88e313c910d0	868	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	869	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	870	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	871	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	872
jhon309	0:88e313c910d0	873	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
jhon309	0:88e313c910d0	874
jhon309	0:88e313c910d0	875	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
jhon309	0:88e313c910d0	876
jhon309	0:88e313c910d0	877	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	878	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	879	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	880	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	881
jhon309	0:88e313c910d0	882	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	883
jhon309	0:88e313c910d0	884	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
jhon309	0:88e313c910d0	885
jhon309	0:88e313c910d0	886	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
jhon309	0:88e313c910d0	887
jhon309	0:88e313c910d0	888	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	889
jhon309	0:88e313c910d0	890	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
jhon309	0:88e313c910d0	891	* @note After reset, the peripheral clock (used for registers read/write access)
jhon309	0:88e313c910d0	892	* is disabled and the application software has to enable this clock before
jhon309	0:88e313c910d0	893	* using it.
jhon309	0:88e313c910d0	894	*/
jhon309	0:88e313c910d0	895	#if defined(STM32F030x8) \|\| \
jhon309	0:88e313c910d0	896	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	897	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	898	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	899	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	900
jhon309	0:88e313c910d0	901	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
jhon309	0:88e313c910d0	902	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
jhon309	0:88e313c910d0	903
jhon309	0:88e313c910d0	904	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
jhon309	0:88e313c910d0	905	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
jhon309	0:88e313c910d0	906
jhon309	0:88e313c910d0	907	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	908	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	909	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	910	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	911
jhon309	0:88e313c910d0	912	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:88e313c910d0	913	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	914	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	915	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	916	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	917
jhon309	0:88e313c910d0	918	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
jhon309	0:88e313c910d0	919
jhon309	0:88e313c910d0	920	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
jhon309	0:88e313c910d0	921
jhon309	0:88e313c910d0	922	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
jhon309	0:88e313c910d0	923	/* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	924	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	925	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	926	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	927
jhon309	0:88e313c910d0	928	#if defined(STM32F030x8) \|\| \
jhon309	0:88e313c910d0	929	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	930	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	931	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	932
jhon309	0:88e313c910d0	933	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
jhon309	0:88e313c910d0	934	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
jhon309	0:88e313c910d0	935
jhon309	0:88e313c910d0	936	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
jhon309	0:88e313c910d0	937	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
jhon309	0:88e313c910d0	938
jhon309	0:88e313c910d0	939	#endif /* STM32F030x8 \|\| */
jhon309	0:88e313c910d0	940	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	941	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	942	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	943
jhon309	0:88e313c910d0	944	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	945	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	946	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	947
jhon309	0:88e313c910d0	948	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
jhon309	0:88e313c910d0	949
jhon309	0:88e313c910d0	950	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
jhon309	0:88e313c910d0	951
jhon309	0:88e313c910d0	952	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	953	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	954	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	955
jhon309	0:88e313c910d0	956	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	957	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	958	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	959	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	960
jhon309	0:88e313c910d0	961	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
jhon309	0:88e313c910d0	962
jhon309	0:88e313c910d0	963	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
jhon309	0:88e313c910d0	964
jhon309	0:88e313c910d0	965	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	966	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	967	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	968	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	969
jhon309	0:88e313c910d0	970	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	971	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	972
jhon309	0:88e313c910d0	973	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
jhon309	0:88e313c910d0	974	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
jhon309	0:88e313c910d0	975	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
jhon309	0:88e313c910d0	976
jhon309	0:88e313c910d0	977	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
jhon309	0:88e313c910d0	978	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
jhon309	0:88e313c910d0	979	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
jhon309	0:88e313c910d0	980
jhon309	0:88e313c910d0	981	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	982	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	983
jhon309	0:88e313c910d0	984	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	985	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
jhon309	0:88e313c910d0	986
jhon309	0:88e313c910d0	987	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
jhon309	0:88e313c910d0	988
jhon309	0:88e313c910d0	989	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
jhon309	0:88e313c910d0	990
jhon309	0:88e313c910d0	991	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:88e313c910d0	992	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
jhon309	0:88e313c910d0	993
jhon309	0:88e313c910d0	994	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
jhon309	0:88e313c910d0	995	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	996
jhon309	0:88e313c910d0	997	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
jhon309	0:88e313c910d0	998	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
jhon309	0:88e313c910d0	999
jhon309	0:88e313c910d0	1000	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
jhon309	0:88e313c910d0	1001	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1002
jhon309	0:88e313c910d0	1003	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1004	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1005	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1006
jhon309	0:88e313c910d0	1007	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
jhon309	0:88e313c910d0	1008
jhon309	0:88e313c910d0	1009	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
jhon309	0:88e313c910d0	1010
jhon309	0:88e313c910d0	1011	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1012	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1013	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1014
jhon309	0:88e313c910d0	1015	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1016
jhon309	0:88e313c910d0	1017	#define __USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
jhon309	0:88e313c910d0	1018
jhon309	0:88e313c910d0	1019	#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
jhon309	0:88e313c910d0	1020
jhon309	0:88e313c910d0	1021	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1022
jhon309	0:88e313c910d0	1023	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
jhon309	0:88e313c910d0	1024	* @note After reset, the peripheral clock (used for registers read/write access)
jhon309	0:88e313c910d0	1025	* is disabled and the application software has to enable this clock before
jhon309	0:88e313c910d0	1026	* using it.
jhon309	0:88e313c910d0	1027	*/
jhon309	0:88e313c910d0	1028	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	1029	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1030	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1031	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1032
jhon309	0:88e313c910d0	1033	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
jhon309	0:88e313c910d0	1034
jhon309	0:88e313c910d0	1035	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
jhon309	0:88e313c910d0	1036
jhon309	0:88e313c910d0	1037	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:88e313c910d0	1038	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1039	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1040	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1041
jhon309	0:88e313c910d0	1042	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1043
jhon309	0:88e313c910d0	1044	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
jhon309	0:88e313c910d0	1045
jhon309	0:88e313c910d0	1046	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
jhon309	0:88e313c910d0	1047
jhon309	0:88e313c910d0	1048	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1049
jhon309	0:88e313c910d0	1050	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1051
jhon309	0:88e313c910d0	1052	#define __USART7_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART7EN))
jhon309	0:88e313c910d0	1053	#define __USART8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART8EN))
jhon309	0:88e313c910d0	1054
jhon309	0:88e313c910d0	1055	#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
jhon309	0:88e313c910d0	1056	#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
jhon309	0:88e313c910d0	1057
jhon309	0:88e313c910d0	1058	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1059
jhon309	0:88e313c910d0	1060	/**
jhon309	0:88e313c910d0	1061	* @}
jhon309	0:88e313c910d0	1062	*/
jhon309	0:88e313c910d0	1063
jhon309	0:88e313c910d0	1064
jhon309	0:88e313c910d0	1065	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
jhon309	0:88e313c910d0	1066	* @brief Forces or releases peripheral reset.
jhon309	0:88e313c910d0	1067	* @{
jhon309	0:88e313c910d0	1068	*/
jhon309	0:88e313c910d0	1069
jhon309	0:88e313c910d0	1070	/** @brief Force or release AHB peripheral reset.
jhon309	0:88e313c910d0	1071	*/
jhon309	0:88e313c910d0	1072	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
jhon309	0:88e313c910d0	1073	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1074	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1075	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1076
jhon309	0:88e313c910d0	1077	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
jhon309	0:88e313c910d0	1078
jhon309	0:88e313c910d0	1079	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
jhon309	0:88e313c910d0	1080
jhon309	0:88e313c910d0	1081	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
jhon309	0:88e313c910d0	1082	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1083	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1084	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1085
jhon309	0:88e313c910d0	1086	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1087	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1088
jhon309	0:88e313c910d0	1089	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
jhon309	0:88e313c910d0	1090
jhon309	0:88e313c910d0	1091	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
jhon309	0:88e313c910d0	1092
jhon309	0:88e313c910d0	1093	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1094	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1095
jhon309	0:88e313c910d0	1096	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1097	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1098	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1099	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1100
jhon309	0:88e313c910d0	1101	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
jhon309	0:88e313c910d0	1102
jhon309	0:88e313c910d0	1103	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
jhon309	0:88e313c910d0	1104
jhon309	0:88e313c910d0	1105	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1106	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1107	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1108	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1109
jhon309	0:88e313c910d0	1110	/** @brief Force or release APB1 peripheral reset.
jhon309	0:88e313c910d0	1111	*/
jhon309	0:88e313c910d0	1112	#if defined(STM32F030x8) \|\| \
jhon309	0:88e313c910d0	1113	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	1114	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1115	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1116	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1117
jhon309	0:88e313c910d0	1118	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
jhon309	0:88e313c910d0	1119	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
jhon309	0:88e313c910d0	1120
jhon309	0:88e313c910d0	1121	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
jhon309	0:88e313c910d0	1122	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
jhon309	0:88e313c910d0	1123
jhon309	0:88e313c910d0	1124	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:88e313c910d0	1125	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1126	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1127	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1128
jhon309	0:88e313c910d0	1129	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:88e313c910d0	1130	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1131	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1132	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1133	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1134
jhon309	0:88e313c910d0	1135	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
jhon309	0:88e313c910d0	1136
jhon309	0:88e313c910d0	1137	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
jhon309	0:88e313c910d0	1138
jhon309	0:88e313c910d0	1139	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
jhon309	0:88e313c910d0	1140	/* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1141	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1142	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1143	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1144
jhon309	0:88e313c910d0	1145	#if defined(STM32F030x8) \|\| \
jhon309	0:88e313c910d0	1146	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1147	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\|\
jhon309	0:88e313c910d0	1148	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1149
jhon309	0:88e313c910d0	1150	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
jhon309	0:88e313c910d0	1151	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
jhon309	0:88e313c910d0	1152
jhon309	0:88e313c910d0	1153	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
jhon309	0:88e313c910d0	1154	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
jhon309	0:88e313c910d0	1155
jhon309	0:88e313c910d0	1156	#endif /* STM32F030x8 \|\| */
jhon309	0:88e313c910d0	1157	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1158	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1159	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1160
jhon309	0:88e313c910d0	1161	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1162	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1163	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1164
jhon309	0:88e313c910d0	1165	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
jhon309	0:88e313c910d0	1166
jhon309	0:88e313c910d0	1167	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
jhon309	0:88e313c910d0	1168
jhon309	0:88e313c910d0	1169	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1170	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1171	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1172
jhon309	0:88e313c910d0	1173	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1174	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1175	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1176	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1177
jhon309	0:88e313c910d0	1178	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
jhon309	0:88e313c910d0	1179
jhon309	0:88e313c910d0	1180	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
jhon309	0:88e313c910d0	1181
jhon309	0:88e313c910d0	1182	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1183	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1184	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1185	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1186
jhon309	0:88e313c910d0	1187	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1188	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1189
jhon309	0:88e313c910d0	1190	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
jhon309	0:88e313c910d0	1191	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
jhon309	0:88e313c910d0	1192	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
jhon309	0:88e313c910d0	1193
jhon309	0:88e313c910d0	1194	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
jhon309	0:88e313c910d0	1195	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
jhon309	0:88e313c910d0	1196	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
jhon309	0:88e313c910d0	1197
jhon309	0:88e313c910d0	1198	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1199	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1200
jhon309	0:88e313c910d0	1201	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	1202	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
jhon309	0:88e313c910d0	1203
jhon309	0:88e313c910d0	1204	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
jhon309	0:88e313c910d0	1205
jhon309	0:88e313c910d0	1206	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
jhon309	0:88e313c910d0	1207
jhon309	0:88e313c910d0	1208	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:88e313c910d0	1209	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
jhon309	0:88e313c910d0	1210
jhon309	0:88e313c910d0	1211	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
jhon309	0:88e313c910d0	1212	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1213
jhon309	0:88e313c910d0	1214	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
jhon309	0:88e313c910d0	1215
jhon309	0:88e313c910d0	1216	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
jhon309	0:88e313c910d0	1217
jhon309	0:88e313c910d0	1218	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
jhon309	0:88e313c910d0	1219	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1220
jhon309	0:88e313c910d0	1221	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1222	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1223	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1224
jhon309	0:88e313c910d0	1225	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
jhon309	0:88e313c910d0	1226
jhon309	0:88e313c910d0	1227	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
jhon309	0:88e313c910d0	1228
jhon309	0:88e313c910d0	1229	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1230	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1231	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1232
jhon309	0:88e313c910d0	1233	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1234
jhon309	0:88e313c910d0	1235	#define __USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
jhon309	0:88e313c910d0	1236
jhon309	0:88e313c910d0	1237	#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
jhon309	0:88e313c910d0	1238
jhon309	0:88e313c910d0	1239	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1240
jhon309	0:88e313c910d0	1241
jhon309	0:88e313c910d0	1242	/** @brief Force or release APB2 peripheral reset.
jhon309	0:88e313c910d0	1243	*/
jhon309	0:88e313c910d0	1244	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	1245	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1246	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1247	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1248
jhon309	0:88e313c910d0	1249	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
jhon309	0:88e313c910d0	1250
jhon309	0:88e313c910d0	1251	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
jhon309	0:88e313c910d0	1252
jhon309	0:88e313c910d0	1253	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:88e313c910d0	1254	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1255	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1256	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1257
jhon309	0:88e313c910d0	1258	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1259
jhon309	0:88e313c910d0	1260	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
jhon309	0:88e313c910d0	1261
jhon309	0:88e313c910d0	1262	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
jhon309	0:88e313c910d0	1263
jhon309	0:88e313c910d0	1264	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1265
jhon309	0:88e313c910d0	1266	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1267
jhon309	0:88e313c910d0	1268	#define __USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
jhon309	0:88e313c910d0	1269	#define __USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
jhon309	0:88e313c910d0	1270
jhon309	0:88e313c910d0	1271	#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
jhon309	0:88e313c910d0	1272	#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
jhon309	0:88e313c910d0	1273
jhon309	0:88e313c910d0	1274	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1275
jhon309	0:88e313c910d0	1276	/**
jhon309	0:88e313c910d0	1277	* @}
jhon309	0:88e313c910d0	1278	*/
jhon309	0:88e313c910d0	1279
jhon309	0:88e313c910d0	1280	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
jhon309	0:88e313c910d0	1281	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
jhon309	0:88e313c910d0	1282	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
jhon309	0:88e313c910d0	1283	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
jhon309	0:88e313c910d0	1284	* you have to select another source of the system clock then stop the HSI14.
jhon309	0:88e313c910d0	1285	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
jhon309	0:88e313c910d0	1286	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
jhon309	0:88e313c910d0	1287	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
jhon309	0:88e313c910d0	1288	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
jhon309	0:88e313c910d0	1289	* clock cycles.
jhon309	0:88e313c910d0	1290	* @{
jhon309	0:88e313c910d0	1291	*/
jhon309	0:88e313c910d0	1292	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1293	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1294	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1295
jhon309	0:88e313c910d0	1296	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
jhon309	0:88e313c910d0	1297	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
jhon309	0:88e313c910d0	1298
jhon309	0:88e313c910d0	1299	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
jhon309	0:88e313c910d0	1300	* @retval The clock source can be one of the following values:
jhon309	0:88e313c910d0	1301	* @arg RCC_HSI48_ON: HSI48 enabled
jhon309	0:88e313c910d0	1302	* @arg RCC_HSI48_OFF: HSI48 disabled
jhon309	0:88e313c910d0	1303	*/
jhon309	0:88e313c910d0	1304	#define __HAL_RCC_GET_HSI48_STATE() \
jhon309	0:88e313c910d0	1305	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
jhon309	0:88e313c910d0	1306
jhon309	0:88e313c910d0	1307	#else
jhon309	0:88e313c910d0	1308
jhon309	0:88e313c910d0	1309	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
jhon309	0:88e313c910d0	1310	* @retval The clock source can be one of the following values:
jhon309	0:88e313c910d0	1311	* @arg RCC_HSI_OFF: HSI48 disabled
jhon309	0:88e313c910d0	1312	*/
jhon309	0:88e313c910d0	1313	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
jhon309	0:88e313c910d0	1314
jhon309	0:88e313c910d0	1315	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1316	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1317	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1318
jhon309	0:88e313c910d0	1319	/**
jhon309	0:88e313c910d0	1320	* @}
jhon309	0:88e313c910d0	1321	*/
jhon309	0:88e313c910d0	1322
jhon309	0:88e313c910d0	1323	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
jhon309	0:88e313c910d0	1324	* @{
jhon309	0:88e313c910d0	1325	*/
jhon309	0:88e313c910d0	1326	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1327	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1328	defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:88e313c910d0	1329
jhon309	0:88e313c910d0	1330	/** @brief Macro to configure the USB clock (USBCLK).
jhon309	0:88e313c910d0	1331	* @param __USBCLKSource__: specifies the USB clock source.
jhon309	0:88e313c910d0	1332	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1333	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
jhon309	0:88e313c910d0	1334	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
jhon309	0:88e313c910d0	1335	*/
jhon309	0:88e313c910d0	1336	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
jhon309	0:88e313c910d0	1337	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
jhon309	0:88e313c910d0	1338
jhon309	0:88e313c910d0	1339	/** @brief Macro to get the USB clock source.
jhon309	0:88e313c910d0	1340	* @retval The clock source can be one of the following values:
jhon309	0:88e313c910d0	1341	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
jhon309	0:88e313c910d0	1342	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
jhon309	0:88e313c910d0	1343	*/
jhon309	0:88e313c910d0	1344	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
jhon309	0:88e313c910d0	1345
jhon309	0:88e313c910d0	1346	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1347	/* STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1348	/* STM32F070x6 \|\| STM32F070xB */
jhon309	0:88e313c910d0	1349
jhon309	0:88e313c910d0	1350	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1351	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:88e313c910d0	1352	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1353	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1354
jhon309	0:88e313c910d0	1355	/** @brief Macro to configure the CEC clock.
jhon309	0:88e313c910d0	1356	* @param __CECCLKSource__: specifies the CEC clock source.
jhon309	0:88e313c910d0	1357	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1358	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
jhon309	0:88e313c910d0	1359	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
jhon309	0:88e313c910d0	1360	*/
jhon309	0:88e313c910d0	1361	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
jhon309	0:88e313c910d0	1362	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
jhon309	0:88e313c910d0	1363
jhon309	0:88e313c910d0	1364	/** @brief Macro to get the HDMI CEC clock source.
jhon309	0:88e313c910d0	1365	* @retval The clock source can be one of the following values:
jhon309	0:88e313c910d0	1366	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
jhon309	0:88e313c910d0	1367	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
jhon309	0:88e313c910d0	1368	*/
jhon309	0:88e313c910d0	1369	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
jhon309	0:88e313c910d0	1370
jhon309	0:88e313c910d0	1371	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1372	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:88e313c910d0	1373	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1374	/* STM32F091xC \|\| defined(STM32F098xx) */
jhon309	0:88e313c910d0	1375
jhon309	0:88e313c910d0	1376	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:88e313c910d0	1377	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:88e313c910d0	1378	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:88e313c910d0	1379	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	1380
jhon309	0:88e313c910d0	1381	/** @brief Macro to configure the MCO clock.
jhon309	0:88e313c910d0	1382	* @param __MCOCLKSource__: specifies the MCO clock source.
jhon309	0:88e313c910d0	1383	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1384	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
jhon309	0:88e313c910d0	1385	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
jhon309	0:88e313c910d0	1386	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
jhon309	0:88e313c910d0	1387	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
jhon309	0:88e313c910d0	1388	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
jhon309	0:88e313c910d0	1389	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
jhon309	0:88e313c910d0	1390	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
jhon309	0:88e313c910d0	1391	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
jhon309	0:88e313c910d0	1392	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
jhon309	0:88e313c910d0	1393	* @param __MCODiv__: specifies the MCO clock prescaler.
jhon309	0:88e313c910d0	1394	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1395	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
jhon309	0:88e313c910d0	1396	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
jhon309	0:88e313c910d0	1397	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
jhon309	0:88e313c910d0	1398	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
jhon309	0:88e313c910d0	1399	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
jhon309	0:88e313c910d0	1400	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
jhon309	0:88e313c910d0	1401	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
jhon309	0:88e313c910d0	1402	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
jhon309	0:88e313c910d0	1403	*/
jhon309	0:88e313c910d0	1404	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
jhon309	0:88e313c910d0	1405	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
jhon309	0:88e313c910d0	1406	#else
jhon309	0:88e313c910d0	1407
jhon309	0:88e313c910d0	1408	/** @brief Macro to configure the MCO clock.
jhon309	0:88e313c910d0	1409	* @param __MCOCLKSource__: specifies the MCO clock source.
jhon309	0:88e313c910d0	1410	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1411	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
jhon309	0:88e313c910d0	1412	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
jhon309	0:88e313c910d0	1413	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
jhon309	0:88e313c910d0	1414	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
jhon309	0:88e313c910d0	1415	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
jhon309	0:88e313c910d0	1416	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
jhon309	0:88e313c910d0	1417	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
jhon309	0:88e313c910d0	1418	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
jhon309	0:88e313c910d0	1419	* @param __MCODiv__: specifies the MCO clock prescaler.
jhon309	0:88e313c910d0	1420	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1421	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
jhon309	0:88e313c910d0	1422	*/
jhon309	0:88e313c910d0	1423	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
jhon309	0:88e313c910d0	1424	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
jhon309	0:88e313c910d0	1425
jhon309	0:88e313c910d0	1426	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
jhon309	0:88e313c910d0	1427	/* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1428	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:88e313c910d0	1429	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	1430
jhon309	0:88e313c910d0	1431	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1432	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1433	/** @brief Macro to configure the USART2 clock (USART2CLK).
jhon309	0:88e313c910d0	1434	* @param __USART2CLKSource__: specifies the USART2 clock source.
jhon309	0:88e313c910d0	1435	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1436	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
jhon309	0:88e313c910d0	1437	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
jhon309	0:88e313c910d0	1438	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
jhon309	0:88e313c910d0	1439	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
jhon309	0:88e313c910d0	1440	*/
jhon309	0:88e313c910d0	1441	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
jhon309	0:88e313c910d0	1442	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
jhon309	0:88e313c910d0	1443
jhon309	0:88e313c910d0	1444	/** @brief Macro to get the USART2 clock source.
jhon309	0:88e313c910d0	1445	* @retval The clock source can be one of the following values:
jhon309	0:88e313c910d0	1446	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
jhon309	0:88e313c910d0	1447	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
jhon309	0:88e313c910d0	1448	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
jhon309	0:88e313c910d0	1449	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
jhon309	0:88e313c910d0	1450	*/
jhon309	0:88e313c910d0	1451	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
jhon309	0:88e313c910d0	1452	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
jhon309	0:88e313c910d0	1453
jhon309	0:88e313c910d0	1454	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1455	/** @brief Macro to configure the USART3 clock (USART3CLK).
jhon309	0:88e313c910d0	1456	* @param __USART3CLKSource__: specifies the USART3 clock source.
jhon309	0:88e313c910d0	1457	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1458	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
jhon309	0:88e313c910d0	1459	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
jhon309	0:88e313c910d0	1460	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
jhon309	0:88e313c910d0	1461	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
jhon309	0:88e313c910d0	1462	*/
jhon309	0:88e313c910d0	1463	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
jhon309	0:88e313c910d0	1464	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
jhon309	0:88e313c910d0	1465
jhon309	0:88e313c910d0	1466	/** @brief Macro to get the USART3 clock source.
jhon309	0:88e313c910d0	1467	* @retval The clock source can be one of the following values:
jhon309	0:88e313c910d0	1468	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
jhon309	0:88e313c910d0	1469	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
jhon309	0:88e313c910d0	1470	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
jhon309	0:88e313c910d0	1471	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
jhon309	0:88e313c910d0	1472	*/
jhon309	0:88e313c910d0	1473	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
jhon309	0:88e313c910d0	1474
jhon309	0:88e313c910d0	1475	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1476	/**
jhon309	0:88e313c910d0	1477	* @}
jhon309	0:88e313c910d0	1478	*/
jhon309	0:88e313c910d0	1479
jhon309	0:88e313c910d0	1480	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1481	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1482	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1483
jhon309	0:88e313c910d0	1484	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
jhon309	0:88e313c910d0	1485	* @{
jhon309	0:88e313c910d0	1486	*/
jhon309	0:88e313c910d0	1487	/* Interrupt & Flag management */
jhon309	0:88e313c910d0	1488
jhon309	0:88e313c910d0	1489	/**
jhon309	0:88e313c910d0	1490	* @brief Enables the specified CRS interrupts.
jhon309	0:88e313c910d0	1491	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
jhon309	0:88e313c910d0	1492	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	1493	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:88e313c910d0	1494	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:88e313c910d0	1495	* @arg RCC_CRS_IT_ERR
jhon309	0:88e313c910d0	1496	* @arg RCC_CRS_IT_ESYNC
jhon309	0:88e313c910d0	1497	* @retval None
jhon309	0:88e313c910d0	1498	*/
jhon309	0:88e313c910d0	1499	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
jhon309	0:88e313c910d0	1500
jhon309	0:88e313c910d0	1501	/**
jhon309	0:88e313c910d0	1502	* @brief Disables the specified CRS interrupts.
jhon309	0:88e313c910d0	1503	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
jhon309	0:88e313c910d0	1504	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	1505	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:88e313c910d0	1506	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:88e313c910d0	1507	* @arg RCC_CRS_IT_ERR
jhon309	0:88e313c910d0	1508	* @arg RCC_CRS_IT_ESYNC
jhon309	0:88e313c910d0	1509	* @retval None
jhon309	0:88e313c910d0	1510	*/
jhon309	0:88e313c910d0	1511	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
jhon309	0:88e313c910d0	1512
jhon309	0:88e313c910d0	1513	/** @brief Check the CRS's interrupt has occurred or not.
jhon309	0:88e313c910d0	1514	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
jhon309	0:88e313c910d0	1515	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1516	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:88e313c910d0	1517	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:88e313c910d0	1518	* @arg RCC_CRS_IT_ERR
jhon309	0:88e313c910d0	1519	* @arg RCC_CRS_IT_ESYNC
jhon309	0:88e313c910d0	1520	* @retval The new state of __INTERRUPT__ (SET or RESET).
jhon309	0:88e313c910d0	1521	*/
jhon309	0:88e313c910d0	1522	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
jhon309	0:88e313c910d0	1523
jhon309	0:88e313c910d0	1524	/** @brief Clear the CRS's interrupt pending bits
jhon309	0:88e313c910d0	1525	* bits to clear the selected interrupt pending bits.
jhon309	0:88e313c910d0	1526	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
jhon309	0:88e313c910d0	1527	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	1528	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:88e313c910d0	1529	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:88e313c910d0	1530	* @arg RCC_CRS_IT_ERR
jhon309	0:88e313c910d0	1531	* @arg RCC_CRS_IT_ESYNC
jhon309	0:88e313c910d0	1532	* @arg RCC_CRS_IT_TRIMOVF
jhon309	0:88e313c910d0	1533	* @arg RCC_CRS_IT_SYNCERR
jhon309	0:88e313c910d0	1534	* @arg RCC_CRS_IT_SYNCMISS
jhon309	0:88e313c910d0	1535	*/
jhon309	0:88e313c910d0	1536	/* CRS IT Error Mask */
jhon309	0:88e313c910d0	1537	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
jhon309	0:88e313c910d0	1538
jhon309	0:88e313c910d0	1539	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
jhon309	0:88e313c910d0	1540	(CRS->ICR \|= (__INTERRUPT__)))
jhon309	0:88e313c910d0	1541
jhon309	0:88e313c910d0	1542	/**
jhon309	0:88e313c910d0	1543	* @brief Checks whether the specified CRS flag is set or not.
jhon309	0:88e313c910d0	1544	* @param _FLAG_: specifies the flag to check.
jhon309	0:88e313c910d0	1545	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1546	* @arg RCC_CRS_FLAG_SYNCOK
jhon309	0:88e313c910d0	1547	* @arg RCC_CRS_FLAG_SYNCWARN
jhon309	0:88e313c910d0	1548	* @arg RCC_CRS_FLAG_ERR
jhon309	0:88e313c910d0	1549	* @arg RCC_CRS_FLAG_ESYNC
jhon309	0:88e313c910d0	1550	* @arg RCC_CRS_FLAG_TRIMOVF
jhon309	0:88e313c910d0	1551	* @arg RCC_CRS_FLAG_SYNCERR
jhon309	0:88e313c910d0	1552	* @arg RCC_CRS_FLAG_SYNCMISS
jhon309	0:88e313c910d0	1553	* @retval The new state of _FLAG_ (TRUE or FALSE).
jhon309	0:88e313c910d0	1554	*/
jhon309	0:88e313c910d0	1555	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
jhon309	0:88e313c910d0	1556
jhon309	0:88e313c910d0	1557	/**
jhon309	0:88e313c910d0	1558	* @brief Clears the CRS specified FLAG.
jhon309	0:88e313c910d0	1559	* @param _FLAG_: specifies the flag to clear.
jhon309	0:88e313c910d0	1560	* This parameter can be one of the following values:
jhon309	0:88e313c910d0	1561	* @arg RCC_CRS_FLAG_SYNCOK
jhon309	0:88e313c910d0	1562	* @arg RCC_CRS_FLAG_SYNCWARN
jhon309	0:88e313c910d0	1563	* @arg RCC_CRS_FLAG_ERR
jhon309	0:88e313c910d0	1564	* @arg RCC_CRS_FLAG_ESYNC
jhon309	0:88e313c910d0	1565	* @arg RCC_CRS_FLAG_TRIMOVF
jhon309	0:88e313c910d0	1566	* @arg RCC_CRS_FLAG_SYNCERR
jhon309	0:88e313c910d0	1567	* @arg RCC_CRS_FLAG_SYNCMISS
jhon309	0:88e313c910d0	1568	* @retval None
jhon309	0:88e313c910d0	1569	*/
jhon309	0:88e313c910d0	1570
jhon309	0:88e313c910d0	1571	/* CRS Flag Error Mask */
jhon309	0:88e313c910d0	1572	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
jhon309	0:88e313c910d0	1573
jhon309	0:88e313c910d0	1574	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
jhon309	0:88e313c910d0	1575	(CRS->ICR \|= (__FLAG__)))
jhon309	0:88e313c910d0	1576
jhon309	0:88e313c910d0	1577	/**
jhon309	0:88e313c910d0	1578	* @}
jhon309	0:88e313c910d0	1579	*/
jhon309	0:88e313c910d0	1580
jhon309	0:88e313c910d0	1581	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
jhon309	0:88e313c910d0	1582	* @{
jhon309	0:88e313c910d0	1583	*/
jhon309	0:88e313c910d0	1584	/**
jhon309	0:88e313c910d0	1585	* @brief Enables the oscillator clock for frequency error counter.
jhon309	0:88e313c910d0	1586	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
jhon309	0:88e313c910d0	1587	* @retval None
jhon309	0:88e313c910d0	1588	*/
jhon309	0:88e313c910d0	1589	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
jhon309	0:88e313c910d0	1590
jhon309	0:88e313c910d0	1591	/**
jhon309	0:88e313c910d0	1592	* @brief Disables the oscillator clock for frequency error counter.
jhon309	0:88e313c910d0	1593	* @retval None
jhon309	0:88e313c910d0	1594	*/
jhon309	0:88e313c910d0	1595	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
jhon309	0:88e313c910d0	1596
jhon309	0:88e313c910d0	1597	/**
jhon309	0:88e313c910d0	1598	* @brief Enables the automatic hardware adjustement of TRIM bits.
jhon309	0:88e313c910d0	1599	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
jhon309	0:88e313c910d0	1600	* @retval None
jhon309	0:88e313c910d0	1601	*/
jhon309	0:88e313c910d0	1602	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
jhon309	0:88e313c910d0	1603
jhon309	0:88e313c910d0	1604	/**
jhon309	0:88e313c910d0	1605	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
jhon309	0:88e313c910d0	1606	* @retval None
jhon309	0:88e313c910d0	1607	*/
jhon309	0:88e313c910d0	1608	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
jhon309	0:88e313c910d0	1609
jhon309	0:88e313c910d0	1610	/**
jhon309	0:88e313c910d0	1611	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
jhon309	0:88e313c910d0	1612	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
jhon309	0:88e313c910d0	1613	* of the synchronization source after prescaling. It is then decreased by one in order to
jhon309	0:88e313c910d0	1614	* reach the expected synchronization on the zero value. The formula is the following:
jhon309	0:88e313c910d0	1615	* RELOAD = (fTARGET / fSYNC) -1
jhon309	0:88e313c910d0	1616	* @param _FTARGET_ Target frequency (value in Hz)
jhon309	0:88e313c910d0	1617	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
jhon309	0:88e313c910d0	1618	* @retval None
jhon309	0:88e313c910d0	1619	*/
jhon309	0:88e313c910d0	1620	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
jhon309	0:88e313c910d0	1621
jhon309	0:88e313c910d0	1622	/**
jhon309	0:88e313c910d0	1623	* @}
jhon309	0:88e313c910d0	1624	*/
jhon309	0:88e313c910d0	1625
jhon309	0:88e313c910d0	1626	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1627	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1628	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1629
jhon309	0:88e313c910d0	1630	/**
jhon309	0:88e313c910d0	1631	* @}
jhon309	0:88e313c910d0	1632	*/
jhon309	0:88e313c910d0	1633
jhon309	0:88e313c910d0	1634	/* Exported functions --------------------------------------------------------*/
jhon309	0:88e313c910d0	1635	/** @addtogroup RCCEx_Exported_Functions
jhon309	0:88e313c910d0	1636	* @{
jhon309	0:88e313c910d0	1637	*/
jhon309	0:88e313c910d0	1638
jhon309	0:88e313c910d0	1639	/** @addtogroup RCCEx_Exported_Functions_Group1
jhon309	0:88e313c910d0	1640	* @{
jhon309	0:88e313c910d0	1641	*/
jhon309	0:88e313c910d0	1642
jhon309	0:88e313c910d0	1643	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
jhon309	0:88e313c910d0	1644	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
jhon309	0:88e313c910d0	1645
jhon309	0:88e313c910d0	1646	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:88e313c910d0	1647	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:88e313c910d0	1648	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	1649	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
jhon309	0:88e313c910d0	1650	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
jhon309	0:88e313c910d0	1651	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
jhon309	0:88e313c910d0	1652	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
jhon309	0:88e313c910d0	1653	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:88e313c910d0	1654	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:88e313c910d0	1655	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	1656
jhon309	0:88e313c910d0	1657
jhon309	0:88e313c910d0	1658	/**
jhon309	0:88e313c910d0	1659	* @}
jhon309	0:88e313c910d0	1660	*/
jhon309	0:88e313c910d0	1661
jhon309	0:88e313c910d0	1662	/**
jhon309	0:88e313c910d0	1663	* @}
jhon309	0:88e313c910d0	1664	*/
jhon309	0:88e313c910d0	1665
jhon309	0:88e313c910d0	1666	/**
jhon309	0:88e313c910d0	1667	* @}
jhon309	0:88e313c910d0	1668	*/
jhon309	0:88e313c910d0	1669
jhon309	0:88e313c910d0	1670	/**
jhon309	0:88e313c910d0	1671	* @}
jhon309	0:88e313c910d0	1672	*/
jhon309	0:88e313c910d0	1673
jhon309	0:88e313c910d0	1674	#ifdef __cplusplus
jhon309	0:88e313c910d0	1675	}
jhon309	0:88e313c910d0	1676	#endif
jhon309	0:88e313c910d0	1677
jhon309	0:88e313c910d0	1678	#endif /* __STM32F0xx_HAL_RCC_EX_H */
jhon309	0:88e313c910d0	1679
jhon309	0:88e313c910d0	1680	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	13 Aug 2015
Imports:	6
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@0:88e313c910d0, 2015-08-13 (annotated)

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