Jhon Plantikow / mbed

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Dependents:   RTC

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@0:88e313c910d0, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:20:09 2015 +0000
Revision:
0:88e313c910d0
RTC Example

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jhon309 0:88e313c910d0 1 /**
jhon309 0:88e313c910d0 2 ******************************************************************************
jhon309 0:88e313c910d0 3 * @file stm32f0xx_hal_rcc.h
jhon309 0:88e313c910d0 4 * @author MCD Application Team
jhon309 0:88e313c910d0 5 * @version V1.2.0
jhon309 0:88e313c910d0 6 * @date 11-December-2014
jhon309 0:88e313c910d0 7 * @brief Header file of RCC HAL module.
jhon309 0:88e313c910d0 8 ******************************************************************************
jhon309 0:88e313c910d0 9 * @attention
jhon309 0:88e313c910d0 10 *
jhon309 0:88e313c910d0 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309 0:88e313c910d0 12 *
jhon309 0:88e313c910d0 13 * Redistribution and use in source and binary forms, with or without modification,
jhon309 0:88e313c910d0 14 * are permitted provided that the following conditions are met:
jhon309 0:88e313c910d0 15 * 1. Redistributions of source code must retain the above copyright notice,
jhon309 0:88e313c910d0 16 * this list of conditions and the following disclaimer.
jhon309 0:88e313c910d0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309 0:88e313c910d0 18 * this list of conditions and the following disclaimer in the documentation
jhon309 0:88e313c910d0 19 * and/or other materials provided with the distribution.
jhon309 0:88e313c910d0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309 0:88e313c910d0 21 * may be used to endorse or promote products derived from this software
jhon309 0:88e313c910d0 22 * without specific prior written permission.
jhon309 0:88e313c910d0 23 *
jhon309 0:88e313c910d0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:88e313c910d0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:88e313c910d0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309 0:88e313c910d0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309 0:88e313c910d0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309 0:88e313c910d0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309 0:88e313c910d0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309 0:88e313c910d0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309 0:88e313c910d0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309 0:88e313c910d0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309 0:88e313c910d0 34 *
jhon309 0:88e313c910d0 35 ******************************************************************************
jhon309 0:88e313c910d0 36 */
jhon309 0:88e313c910d0 37
jhon309 0:88e313c910d0 38 /* Define to prevent recursive inclusion -------------------------------------*/
jhon309 0:88e313c910d0 39 #ifndef __STM32F0xx_HAL_RCC_H
jhon309 0:88e313c910d0 40 #define __STM32F0xx_HAL_RCC_H
jhon309 0:88e313c910d0 41
jhon309 0:88e313c910d0 42 #ifdef __cplusplus
jhon309 0:88e313c910d0 43 extern "C" {
jhon309 0:88e313c910d0 44 #endif
jhon309 0:88e313c910d0 45
jhon309 0:88e313c910d0 46 /* Includes ------------------------------------------------------------------*/
jhon309 0:88e313c910d0 47 #include "stm32f0xx_hal_def.h"
jhon309 0:88e313c910d0 48
jhon309 0:88e313c910d0 49 /** @addtogroup STM32F0xx_HAL_Driver
jhon309 0:88e313c910d0 50 * @{
jhon309 0:88e313c910d0 51 */
jhon309 0:88e313c910d0 52
jhon309 0:88e313c910d0 53 /** @addtogroup RCC
jhon309 0:88e313c910d0 54 * @{
jhon309 0:88e313c910d0 55 */
jhon309 0:88e313c910d0 56
jhon309 0:88e313c910d0 57 /* Exported types ------------------------------------------------------------*/
jhon309 0:88e313c910d0 58
jhon309 0:88e313c910d0 59 /** @defgroup RCC_Exported_Types RCC Exported Types
jhon309 0:88e313c910d0 60 * @{
jhon309 0:88e313c910d0 61 */
jhon309 0:88e313c910d0 62
jhon309 0:88e313c910d0 63 /**
jhon309 0:88e313c910d0 64 * @brief RCC PLL configuration structure definition
jhon309 0:88e313c910d0 65 */
jhon309 0:88e313c910d0 66 typedef struct
jhon309 0:88e313c910d0 67 {
jhon309 0:88e313c910d0 68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
jhon309 0:88e313c910d0 69 This parameter can be a value of @ref RCC_PLL_Config */
jhon309 0:88e313c910d0 70
jhon309 0:88e313c910d0 71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
jhon309 0:88e313c910d0 72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
jhon309 0:88e313c910d0 73
jhon309 0:88e313c910d0 74 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
jhon309 0:88e313c910d0 75 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
jhon309 0:88e313c910d0 76
jhon309 0:88e313c910d0 77 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
jhon309 0:88e313c910d0 78 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
jhon309 0:88e313c910d0 79
jhon309 0:88e313c910d0 80 }RCC_PLLInitTypeDef;
jhon309 0:88e313c910d0 81
jhon309 0:88e313c910d0 82 /**
jhon309 0:88e313c910d0 83 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
jhon309 0:88e313c910d0 84 */
jhon309 0:88e313c910d0 85 typedef struct
jhon309 0:88e313c910d0 86 {
jhon309 0:88e313c910d0 87 uint32_t OscillatorType; /*!< The Oscillators to be configured.
jhon309 0:88e313c910d0 88 This parameter can be a value of @ref RCC_Oscillator_Type */
jhon309 0:88e313c910d0 89
jhon309 0:88e313c910d0 90 uint32_t HSEState; /*!< The new state of the HSE.
jhon309 0:88e313c910d0 91 This parameter can be a value of @ref RCC_HSE_Config */
jhon309 0:88e313c910d0 92
jhon309 0:88e313c910d0 93 uint32_t LSEState; /*!< The new state of the LSE.
jhon309 0:88e313c910d0 94 This parameter can be a value of @ref RCC_LSE_Config */
jhon309 0:88e313c910d0 95
jhon309 0:88e313c910d0 96 uint32_t HSIState; /*!< The new state of the HSI.
jhon309 0:88e313c910d0 97 This parameter can be a value of @ref RCC_HSI_Config */
jhon309 0:88e313c910d0 98
jhon309 0:88e313c910d0 99 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
jhon309 0:88e313c910d0 100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
jhon309 0:88e313c910d0 101
jhon309 0:88e313c910d0 102 uint32_t HSI14State; /*!< The new state of the HSI14.
jhon309 0:88e313c910d0 103 This parameter can be a value of @ref RCC_HSI14_Config */
jhon309 0:88e313c910d0 104
jhon309 0:88e313c910d0 105 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
jhon309 0:88e313c910d0 106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
jhon309 0:88e313c910d0 107
jhon309 0:88e313c910d0 108 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
jhon309 0:88e313c910d0 109 This parameter can be a value of @ref RCCEx_HSI48_Config */
jhon309 0:88e313c910d0 110
jhon309 0:88e313c910d0 111 uint32_t LSIState; /*!< The new state of the LSI.
jhon309 0:88e313c910d0 112 This parameter can be a value of @ref RCC_LSI_Config */
jhon309 0:88e313c910d0 113
jhon309 0:88e313c910d0 114 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
jhon309 0:88e313c910d0 115
jhon309 0:88e313c910d0 116 }RCC_OscInitTypeDef;
jhon309 0:88e313c910d0 117
jhon309 0:88e313c910d0 118 /**
jhon309 0:88e313c910d0 119 * @brief RCC System, AHB and APB busses clock configuration structure definition
jhon309 0:88e313c910d0 120 */
jhon309 0:88e313c910d0 121 typedef struct
jhon309 0:88e313c910d0 122 {
jhon309 0:88e313c910d0 123 uint32_t ClockType; /*!< The clock to be configured.
jhon309 0:88e313c910d0 124 This parameter can be a value of @ref RCC_System_Clock_Type */
jhon309 0:88e313c910d0 125
jhon309 0:88e313c910d0 126 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
jhon309 0:88e313c910d0 127 This parameter can be a value of @ref RCC_System_Clock_Source */
jhon309 0:88e313c910d0 128
jhon309 0:88e313c910d0 129 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
jhon309 0:88e313c910d0 130 This parameter can be a value of @ref RCC_AHB_Clock_Source */
jhon309 0:88e313c910d0 131
jhon309 0:88e313c910d0 132 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
jhon309 0:88e313c910d0 133 This parameter can be a value of @ref RCC_APB1_Clock_Source */
jhon309 0:88e313c910d0 134
jhon309 0:88e313c910d0 135 }RCC_ClkInitTypeDef;
jhon309 0:88e313c910d0 136
jhon309 0:88e313c910d0 137 /**
jhon309 0:88e313c910d0 138 * @}
jhon309 0:88e313c910d0 139 */
jhon309 0:88e313c910d0 140
jhon309 0:88e313c910d0 141 /* Exported constants --------------------------------------------------------*/
jhon309 0:88e313c910d0 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
jhon309 0:88e313c910d0 143 * @{
jhon309 0:88e313c910d0 144 */
jhon309 0:88e313c910d0 145
jhon309 0:88e313c910d0 146 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
jhon309 0:88e313c910d0 147 * @brief RCC registers bit address in the alias region
jhon309 0:88e313c910d0 148 * @{
jhon309 0:88e313c910d0 149 */
jhon309 0:88e313c910d0 150 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
jhon309 0:88e313c910d0 151 /* --- CR Register ---*/
jhon309 0:88e313c910d0 152 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
jhon309 0:88e313c910d0 153 /* --- CFGR Register ---*/
jhon309 0:88e313c910d0 154 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
jhon309 0:88e313c910d0 155 /* --- CIR Register ---*/
jhon309 0:88e313c910d0 156 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
jhon309 0:88e313c910d0 157 /* --- BDCR Register ---*/
jhon309 0:88e313c910d0 158 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
jhon309 0:88e313c910d0 159 /* --- CSR Register ---*/
jhon309 0:88e313c910d0 160 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
jhon309 0:88e313c910d0 161 /* --- CR2 Register ---*/
jhon309 0:88e313c910d0 162 #define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
jhon309 0:88e313c910d0 163
jhon309 0:88e313c910d0 164 /* CR register byte 2 (Bits[23:16]) base address */
jhon309 0:88e313c910d0 165 #define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
jhon309 0:88e313c910d0 166
jhon309 0:88e313c910d0 167 /* CIR register byte 1 (Bits[15:8]) base address */
jhon309 0:88e313c910d0 168 #define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
jhon309 0:88e313c910d0 169
jhon309 0:88e313c910d0 170 /* CIR register byte 2 (Bits[23:16]) base address */
jhon309 0:88e313c910d0 171 #define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
jhon309 0:88e313c910d0 172
jhon309 0:88e313c910d0 173 /* CSR register byte 1 (Bits[15:8]) base address */
jhon309 0:88e313c910d0 174 #define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
jhon309 0:88e313c910d0 175
jhon309 0:88e313c910d0 176 /* BDCR register byte 0 (Bits[7:0] base address */
jhon309 0:88e313c910d0 177 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
jhon309 0:88e313c910d0 178
jhon309 0:88e313c910d0 179 #define RCC_CFGR_PLLMUL_BITNUMBER 18
jhon309 0:88e313c910d0 180 #define RCC_CFGR2_PREDIV_BITNUMBER 0
jhon309 0:88e313c910d0 181
jhon309 0:88e313c910d0 182 /**
jhon309 0:88e313c910d0 183 * @}
jhon309 0:88e313c910d0 184 */
jhon309 0:88e313c910d0 185
jhon309 0:88e313c910d0 186 /** @defgroup RCC_Timeout RCC Timeout
jhon309 0:88e313c910d0 187 * @{
jhon309 0:88e313c910d0 188 */
jhon309 0:88e313c910d0 189 /* LSE state change timeout */
jhon309 0:88e313c910d0 190 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
jhon309 0:88e313c910d0 191
jhon309 0:88e313c910d0 192 /* Disable Backup domain write protection state change timeout */
jhon309 0:88e313c910d0 193 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
jhon309 0:88e313c910d0 194 /**
jhon309 0:88e313c910d0 195 * @}
jhon309 0:88e313c910d0 196 */
jhon309 0:88e313c910d0 197
jhon309 0:88e313c910d0 198 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
jhon309 0:88e313c910d0 199 * @{
jhon309 0:88e313c910d0 200 */
jhon309 0:88e313c910d0 201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
jhon309 0:88e313c910d0 202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
jhon309 0:88e313c910d0 203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
jhon309 0:88e313c910d0 204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
jhon309 0:88e313c910d0 205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
jhon309 0:88e313c910d0 206 #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
jhon309 0:88e313c910d0 207 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
jhon309 0:88e313c910d0 208
jhon309 0:88e313c910d0 209 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
jhon309 0:88e313c910d0 210 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
jhon309 0:88e313c910d0 211 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
jhon309 0:88e313c910d0 212 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
jhon309 0:88e313c910d0 213 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
jhon309 0:88e313c910d0 214 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
jhon309 0:88e313c910d0 215 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
jhon309 0:88e313c910d0 216 /**
jhon309 0:88e313c910d0 217 * @}
jhon309 0:88e313c910d0 218 */
jhon309 0:88e313c910d0 219
jhon309 0:88e313c910d0 220 /** @defgroup RCC_HSE_Config RCC HSE Config
jhon309 0:88e313c910d0 221 * @{
jhon309 0:88e313c910d0 222 */
jhon309 0:88e313c910d0 223 #define RCC_HSE_OFF ((uint8_t)0x00)
jhon309 0:88e313c910d0 224 #define RCC_HSE_ON ((uint8_t)0x01)
jhon309 0:88e313c910d0 225 #define RCC_HSE_BYPASS ((uint8_t)0x05)
jhon309 0:88e313c910d0 226
jhon309 0:88e313c910d0 227 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
jhon309 0:88e313c910d0 228 ((HSE) == RCC_HSE_BYPASS))
jhon309 0:88e313c910d0 229 /**
jhon309 0:88e313c910d0 230 * @}
jhon309 0:88e313c910d0 231 */
jhon309 0:88e313c910d0 232
jhon309 0:88e313c910d0 233 /** @defgroup RCC_LSE_Config RCC_LSE_Config
jhon309 0:88e313c910d0 234 * @{
jhon309 0:88e313c910d0 235 */
jhon309 0:88e313c910d0 236 #define RCC_LSE_OFF ((uint8_t)0x00)
jhon309 0:88e313c910d0 237 #define RCC_LSE_ON ((uint8_t)0x01)
jhon309 0:88e313c910d0 238 #define RCC_LSE_BYPASS ((uint8_t)0x05)
jhon309 0:88e313c910d0 239
jhon309 0:88e313c910d0 240 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
jhon309 0:88e313c910d0 241 ((LSE) == RCC_LSE_BYPASS))
jhon309 0:88e313c910d0 242 /**
jhon309 0:88e313c910d0 243 * @}
jhon309 0:88e313c910d0 244 */
jhon309 0:88e313c910d0 245
jhon309 0:88e313c910d0 246 /** @defgroup RCC_HSI_Config RCC HSI Config
jhon309 0:88e313c910d0 247 * @{
jhon309 0:88e313c910d0 248 */
jhon309 0:88e313c910d0 249 #define RCC_HSI_OFF ((uint8_t)0x00)
jhon309 0:88e313c910d0 250 #define RCC_HSI_ON ((uint8_t)0x01)
jhon309 0:88e313c910d0 251
jhon309 0:88e313c910d0 252 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
jhon309 0:88e313c910d0 253
jhon309 0:88e313c910d0 254 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
jhon309 0:88e313c910d0 255 /**
jhon309 0:88e313c910d0 256 * @}
jhon309 0:88e313c910d0 257 */
jhon309 0:88e313c910d0 258
jhon309 0:88e313c910d0 259 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
jhon309 0:88e313c910d0 260 * @{
jhon309 0:88e313c910d0 261 */
jhon309 0:88e313c910d0 262 #define RCC_HSI14_OFF ((uint32_t)0x00)
jhon309 0:88e313c910d0 263 #define RCC_HSI14_ON RCC_CR2_HSI14ON
jhon309 0:88e313c910d0 264 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
jhon309 0:88e313c910d0 265
jhon309 0:88e313c910d0 266 #define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
jhon309 0:88e313c910d0 267
jhon309 0:88e313c910d0 268 #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
jhon309 0:88e313c910d0 269 /**
jhon309 0:88e313c910d0 270 * @}
jhon309 0:88e313c910d0 271 */
jhon309 0:88e313c910d0 272
jhon309 0:88e313c910d0 273 /** @defgroup RCC_LSI_Config RCC LSI Config
jhon309 0:88e313c910d0 274 * @{
jhon309 0:88e313c910d0 275 */
jhon309 0:88e313c910d0 276 #define RCC_LSI_OFF ((uint8_t)0x00)
jhon309 0:88e313c910d0 277 #define RCC_LSI_ON ((uint8_t)0x01)
jhon309 0:88e313c910d0 278
jhon309 0:88e313c910d0 279 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
jhon309 0:88e313c910d0 280 /**
jhon309 0:88e313c910d0 281 * @}
jhon309 0:88e313c910d0 282 */
jhon309 0:88e313c910d0 283
jhon309 0:88e313c910d0 284 /** @defgroup RCC_PLL_Config RCC PLL Config
jhon309 0:88e313c910d0 285 * @{
jhon309 0:88e313c910d0 286 */
jhon309 0:88e313c910d0 287 #define RCC_PLL_NONE ((uint8_t)0x00)
jhon309 0:88e313c910d0 288 #define RCC_PLL_OFF ((uint8_t)0x01)
jhon309 0:88e313c910d0 289 #define RCC_PLL_ON ((uint8_t)0x02)
jhon309 0:88e313c910d0 290
jhon309 0:88e313c910d0 291 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
jhon309 0:88e313c910d0 292 /**
jhon309 0:88e313c910d0 293 * @}
jhon309 0:88e313c910d0 294 */
jhon309 0:88e313c910d0 295
jhon309 0:88e313c910d0 296 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
jhon309 0:88e313c910d0 297 * @{
jhon309 0:88e313c910d0 298 */
jhon309 0:88e313c910d0 299 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
jhon309 0:88e313c910d0 300 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
jhon309 0:88e313c910d0 301 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
jhon309 0:88e313c910d0 302 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
jhon309 0:88e313c910d0 303 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
jhon309 0:88e313c910d0 304 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
jhon309 0:88e313c910d0 305 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
jhon309 0:88e313c910d0 306 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
jhon309 0:88e313c910d0 307 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
jhon309 0:88e313c910d0 308 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
jhon309 0:88e313c910d0 309 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
jhon309 0:88e313c910d0 310 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
jhon309 0:88e313c910d0 311 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
jhon309 0:88e313c910d0 312 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
jhon309 0:88e313c910d0 313 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
jhon309 0:88e313c910d0 314 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
jhon309 0:88e313c910d0 315
jhon309 0:88e313c910d0 316 #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
jhon309 0:88e313c910d0 317 ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
jhon309 0:88e313c910d0 318 ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
jhon309 0:88e313c910d0 319 ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
jhon309 0:88e313c910d0 320 ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
jhon309 0:88e313c910d0 321 ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
jhon309 0:88e313c910d0 322 ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
jhon309 0:88e313c910d0 323 ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
jhon309 0:88e313c910d0 324 /**
jhon309 0:88e313c910d0 325 * @}
jhon309 0:88e313c910d0 326 */
jhon309 0:88e313c910d0 327
jhon309 0:88e313c910d0 328 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
jhon309 0:88e313c910d0 329 * @{
jhon309 0:88e313c910d0 330 */
jhon309 0:88e313c910d0 331 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
jhon309 0:88e313c910d0 332 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
jhon309 0:88e313c910d0 333 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
jhon309 0:88e313c910d0 334 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
jhon309 0:88e313c910d0 335 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
jhon309 0:88e313c910d0 336 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
jhon309 0:88e313c910d0 337 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
jhon309 0:88e313c910d0 338 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
jhon309 0:88e313c910d0 339 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
jhon309 0:88e313c910d0 340 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
jhon309 0:88e313c910d0 341 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
jhon309 0:88e313c910d0 342 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
jhon309 0:88e313c910d0 343 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
jhon309 0:88e313c910d0 344 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
jhon309 0:88e313c910d0 345 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
jhon309 0:88e313c910d0 346
jhon309 0:88e313c910d0 347 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
jhon309 0:88e313c910d0 348 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
jhon309 0:88e313c910d0 349 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
jhon309 0:88e313c910d0 350 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
jhon309 0:88e313c910d0 351 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
jhon309 0:88e313c910d0 352 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
jhon309 0:88e313c910d0 353 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
jhon309 0:88e313c910d0 354 ((MUL) == RCC_PLL_MUL16))
jhon309 0:88e313c910d0 355 /**
jhon309 0:88e313c910d0 356 * @}
jhon309 0:88e313c910d0 357 */
jhon309 0:88e313c910d0 358
jhon309 0:88e313c910d0 359 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
jhon309 0:88e313c910d0 360 * @{
jhon309 0:88e313c910d0 361 */
jhon309 0:88e313c910d0 362 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
jhon309 0:88e313c910d0 363 /**
jhon309 0:88e313c910d0 364 * @}
jhon309 0:88e313c910d0 365 */
jhon309 0:88e313c910d0 366
jhon309 0:88e313c910d0 367 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
jhon309 0:88e313c910d0 368 * @{
jhon309 0:88e313c910d0 369 */
jhon309 0:88e313c910d0 370 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
jhon309 0:88e313c910d0 371 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
jhon309 0:88e313c910d0 372 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
jhon309 0:88e313c910d0 373
jhon309 0:88e313c910d0 374 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
jhon309 0:88e313c910d0 375 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
jhon309 0:88e313c910d0 376 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
jhon309 0:88e313c910d0 377 /**
jhon309 0:88e313c910d0 378 * @}
jhon309 0:88e313c910d0 379 */
jhon309 0:88e313c910d0 380
jhon309 0:88e313c910d0 381 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
jhon309 0:88e313c910d0 382 * @{
jhon309 0:88e313c910d0 383 */
jhon309 0:88e313c910d0 384 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
jhon309 0:88e313c910d0 385 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
jhon309 0:88e313c910d0 386 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
jhon309 0:88e313c910d0 387 /**
jhon309 0:88e313c910d0 388 * @}
jhon309 0:88e313c910d0 389 */
jhon309 0:88e313c910d0 390
jhon309 0:88e313c910d0 391 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
jhon309 0:88e313c910d0 392 * @{
jhon309 0:88e313c910d0 393 */
jhon309 0:88e313c910d0 394 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
jhon309 0:88e313c910d0 395 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
jhon309 0:88e313c910d0 396 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
jhon309 0:88e313c910d0 397 /**
jhon309 0:88e313c910d0 398 * @}
jhon309 0:88e313c910d0 399 */
jhon309 0:88e313c910d0 400
jhon309 0:88e313c910d0 401 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
jhon309 0:88e313c910d0 402 * @{
jhon309 0:88e313c910d0 403 */
jhon309 0:88e313c910d0 404 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
jhon309 0:88e313c910d0 405 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
jhon309 0:88e313c910d0 406 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
jhon309 0:88e313c910d0 407 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
jhon309 0:88e313c910d0 408 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
jhon309 0:88e313c910d0 409 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
jhon309 0:88e313c910d0 410 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
jhon309 0:88e313c910d0 411 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
jhon309 0:88e313c910d0 412 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
jhon309 0:88e313c910d0 413
jhon309 0:88e313c910d0 414 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
jhon309 0:88e313c910d0 415 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
jhon309 0:88e313c910d0 416 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
jhon309 0:88e313c910d0 417 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
jhon309 0:88e313c910d0 418 ((DIV) == RCC_SYSCLK_DIV512))
jhon309 0:88e313c910d0 419 /**
jhon309 0:88e313c910d0 420 * @}
jhon309 0:88e313c910d0 421 */
jhon309 0:88e313c910d0 422
jhon309 0:88e313c910d0 423 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
jhon309 0:88e313c910d0 424 * @{
jhon309 0:88e313c910d0 425 */
jhon309 0:88e313c910d0 426 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
jhon309 0:88e313c910d0 427 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
jhon309 0:88e313c910d0 428 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
jhon309 0:88e313c910d0 429 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
jhon309 0:88e313c910d0 430 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
jhon309 0:88e313c910d0 431
jhon309 0:88e313c910d0 432 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
jhon309 0:88e313c910d0 433 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
jhon309 0:88e313c910d0 434 ((DIV) == RCC_HCLK_DIV16))
jhon309 0:88e313c910d0 435 /**
jhon309 0:88e313c910d0 436 * @}
jhon309 0:88e313c910d0 437 */
jhon309 0:88e313c910d0 438
jhon309 0:88e313c910d0 439 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
jhon309 0:88e313c910d0 440 * @{
jhon309 0:88e313c910d0 441 */
jhon309 0:88e313c910d0 442 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
jhon309 0:88e313c910d0 443 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
jhon309 0:88e313c910d0 444 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
jhon309 0:88e313c910d0 445 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
jhon309 0:88e313c910d0 446
jhon309 0:88e313c910d0 447 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
jhon309 0:88e313c910d0 448 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
jhon309 0:88e313c910d0 449 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
jhon309 0:88e313c910d0 450 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
jhon309 0:88e313c910d0 451 /**
jhon309 0:88e313c910d0 452 * @}
jhon309 0:88e313c910d0 453 */
jhon309 0:88e313c910d0 454
jhon309 0:88e313c910d0 455 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
jhon309 0:88e313c910d0 456 * @{
jhon309 0:88e313c910d0 457 */
jhon309 0:88e313c910d0 458 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
jhon309 0:88e313c910d0 459 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
jhon309 0:88e313c910d0 460 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
jhon309 0:88e313c910d0 461 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
jhon309 0:88e313c910d0 462
jhon309 0:88e313c910d0 463 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
jhon309 0:88e313c910d0 464 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
jhon309 0:88e313c910d0 465 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
jhon309 0:88e313c910d0 466 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
jhon309 0:88e313c910d0 467 /**
jhon309 0:88e313c910d0 468 * @}
jhon309 0:88e313c910d0 469 */
jhon309 0:88e313c910d0 470
jhon309 0:88e313c910d0 471 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
jhon309 0:88e313c910d0 472 * @{
jhon309 0:88e313c910d0 473 */
jhon309 0:88e313c910d0 474 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
jhon309 0:88e313c910d0 475 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
jhon309 0:88e313c910d0 476
jhon309 0:88e313c910d0 477 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
jhon309 0:88e313c910d0 478 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
jhon309 0:88e313c910d0 479 /**
jhon309 0:88e313c910d0 480 * @}
jhon309 0:88e313c910d0 481 */
jhon309 0:88e313c910d0 482
jhon309 0:88e313c910d0 483 /** @defgroup RCC_MCOx_Index RCC MCOx Index
jhon309 0:88e313c910d0 484 * @{
jhon309 0:88e313c910d0 485 */
jhon309 0:88e313c910d0 486 #define RCC_MCO ((uint32_t)0x00000000)
jhon309 0:88e313c910d0 487
jhon309 0:88e313c910d0 488 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
jhon309 0:88e313c910d0 489 /**
jhon309 0:88e313c910d0 490 * @}
jhon309 0:88e313c910d0 491 */
jhon309 0:88e313c910d0 492
jhon309 0:88e313c910d0 493 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
jhon309 0:88e313c910d0 494 * @{
jhon309 0:88e313c910d0 495 */
jhon309 0:88e313c910d0 496 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
jhon309 0:88e313c910d0 497 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
jhon309 0:88e313c910d0 498 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
jhon309 0:88e313c910d0 499 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
jhon309 0:88e313c910d0 500 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
jhon309 0:88e313c910d0 501 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
jhon309 0:88e313c910d0 502 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
jhon309 0:88e313c910d0 503 #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
jhon309 0:88e313c910d0 504 /**
jhon309 0:88e313c910d0 505 * @}
jhon309 0:88e313c910d0 506 */
jhon309 0:88e313c910d0 507
jhon309 0:88e313c910d0 508 /** @defgroup RCC_Interrupt RCC Interrupt
jhon309 0:88e313c910d0 509 * @{
jhon309 0:88e313c910d0 510 */
jhon309 0:88e313c910d0 511 #define RCC_IT_LSIRDY ((uint8_t)0x01)
jhon309 0:88e313c910d0 512 #define RCC_IT_LSERDY ((uint8_t)0x02)
jhon309 0:88e313c910d0 513 #define RCC_IT_HSIRDY ((uint8_t)0x04)
jhon309 0:88e313c910d0 514 #define RCC_IT_HSERDY ((uint8_t)0x08)
jhon309 0:88e313c910d0 515 #define RCC_IT_PLLRDY ((uint8_t)0x10)
jhon309 0:88e313c910d0 516 #define RCC_IT_HSI14 ((uint8_t)0x20)
jhon309 0:88e313c910d0 517 #define RCC_IT_CSS ((uint8_t)0x80)
jhon309 0:88e313c910d0 518 /**
jhon309 0:88e313c910d0 519 * @}
jhon309 0:88e313c910d0 520 */
jhon309 0:88e313c910d0 521
jhon309 0:88e313c910d0 522 /** @defgroup RCC_Flag RCC Flag
jhon309 0:88e313c910d0 523 * Elements values convention: 0XXYYYYYb
jhon309 0:88e313c910d0 524 * - YYYYY : Flag position in the register
jhon309 0:88e313c910d0 525 * - XX : Register index
jhon309 0:88e313c910d0 526 * - 00: CR register
jhon309 0:88e313c910d0 527 * - 01: CR2 register
jhon309 0:88e313c910d0 528 * - 10: BDCR register
jhon309 0:88e313c910d0 529 * - 11: CSR register
jhon309 0:88e313c910d0 530 * @{
jhon309 0:88e313c910d0 531 */
jhon309 0:88e313c910d0 532 #define CR_REG_INDEX 0
jhon309 0:88e313c910d0 533 #define CR2_REG_INDEX 1
jhon309 0:88e313c910d0 534 #define BDCR_REG_INDEX 2
jhon309 0:88e313c910d0 535 #define CSR_REG_INDEX 3
jhon309 0:88e313c910d0 536
jhon309 0:88e313c910d0 537 /* Flags in the CR register */
jhon309 0:88e313c910d0 538 #define RCC_CR_HSIRDY_BitNumber 1
jhon309 0:88e313c910d0 539 #define RCC_CR_HSERDY_BitNumber 17
jhon309 0:88e313c910d0 540 #define RCC_CR_PLLRDY_BitNumber 25
jhon309 0:88e313c910d0 541
jhon309 0:88e313c910d0 542 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
jhon309 0:88e313c910d0 543 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
jhon309 0:88e313c910d0 544 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
jhon309 0:88e313c910d0 545
jhon309 0:88e313c910d0 546 /* Flags in the CR2 register */
jhon309 0:88e313c910d0 547 #define RCC_CR2_HSI14RDY_BitNumber 1
jhon309 0:88e313c910d0 548
jhon309 0:88e313c910d0 549 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
jhon309 0:88e313c910d0 550
jhon309 0:88e313c910d0 551 /* Flags in the BDCR register */
jhon309 0:88e313c910d0 552 #define RCC_BDCR_LSERDY_BitNumber 1
jhon309 0:88e313c910d0 553
jhon309 0:88e313c910d0 554 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
jhon309 0:88e313c910d0 555
jhon309 0:88e313c910d0 556 /* Flags in the CSR register */
jhon309 0:88e313c910d0 557 #define RCC_CSR_LSIRDY_BitNumber 1
jhon309 0:88e313c910d0 558 #define RCC_CSR_V18PWRRSTF_BitNumber 23
jhon309 0:88e313c910d0 559 #define RCC_CSR_RMVF_BitNumber 24
jhon309 0:88e313c910d0 560 #define RCC_CSR_OBLRSTF_BitNumber 25
jhon309 0:88e313c910d0 561 #define RCC_CSR_PINRSTF_BitNumber 26
jhon309 0:88e313c910d0 562 #define RCC_CSR_PORRSTF_BitNumber 27
jhon309 0:88e313c910d0 563 #define RCC_CSR_SFTRSTF_BitNumber 28
jhon309 0:88e313c910d0 564 #define RCC_CSR_IWDGRSTF_BitNumber 29
jhon309 0:88e313c910d0 565 #define RCC_CSR_WWDGRSTF_BitNumber 30
jhon309 0:88e313c910d0 566 #define RCC_CSR_LPWRRSTF_BitNumber 31
jhon309 0:88e313c910d0 567
jhon309 0:88e313c910d0 568 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
jhon309 0:88e313c910d0 569 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
jhon309 0:88e313c910d0 570 #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
jhon309 0:88e313c910d0 571 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
jhon309 0:88e313c910d0 572 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber))
jhon309 0:88e313c910d0 573 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber))
jhon309 0:88e313c910d0 574 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber))
jhon309 0:88e313c910d0 575 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
jhon309 0:88e313c910d0 576 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
jhon309 0:88e313c910d0 577 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
jhon309 0:88e313c910d0 578 /**
jhon309 0:88e313c910d0 579 * @}
jhon309 0:88e313c910d0 580 */
jhon309 0:88e313c910d0 581
jhon309 0:88e313c910d0 582 /** @defgroup RCC_Calibration_values RCC Calibration values
jhon309 0:88e313c910d0 583 * @{
jhon309 0:88e313c910d0 584 */
jhon309 0:88e313c910d0 585 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
jhon309 0:88e313c910d0 586
jhon309 0:88e313c910d0 587 /**
jhon309 0:88e313c910d0 588 * @}
jhon309 0:88e313c910d0 589 */
jhon309 0:88e313c910d0 590
jhon309 0:88e313c910d0 591 /** @addtogroup RCC_Timeout
jhon309 0:88e313c910d0 592 * @{
jhon309 0:88e313c910d0 593 */
jhon309 0:88e313c910d0 594
jhon309 0:88e313c910d0 595 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
jhon309 0:88e313c910d0 596 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
jhon309 0:88e313c910d0 597 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
jhon309 0:88e313c910d0 598 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
jhon309 0:88e313c910d0 599 #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
jhon309 0:88e313c910d0 600 #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
jhon309 0:88e313c910d0 601 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
jhon309 0:88e313c910d0 602 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
jhon309 0:88e313c910d0 603
jhon309 0:88e313c910d0 604 /**
jhon309 0:88e313c910d0 605 * @}
jhon309 0:88e313c910d0 606 */
jhon309 0:88e313c910d0 607
jhon309 0:88e313c910d0 608 /**
jhon309 0:88e313c910d0 609 * @}
jhon309 0:88e313c910d0 610 */
jhon309 0:88e313c910d0 611
jhon309 0:88e313c910d0 612 /* Exported macro ------------------------------------------------------------*/
jhon309 0:88e313c910d0 613
jhon309 0:88e313c910d0 614 /** @defgroup RCC_Exported_Macros RCC Exported Macros
jhon309 0:88e313c910d0 615 * @{
jhon309 0:88e313c910d0 616 */
jhon309 0:88e313c910d0 617
jhon309 0:88e313c910d0 618 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
jhon309 0:88e313c910d0 619 * @brief Enable or disable the AHB peripheral clock.
jhon309 0:88e313c910d0 620 * @note After reset, the peripheral clock (used for registers read/write access)
jhon309 0:88e313c910d0 621 * is disabled and the application software has to enable this clock before
jhon309 0:88e313c910d0 622 * using it.
jhon309 0:88e313c910d0 623 * @{
jhon309 0:88e313c910d0 624 */
jhon309 0:88e313c910d0 625 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
jhon309 0:88e313c910d0 626 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
jhon309 0:88e313c910d0 627 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
jhon309 0:88e313c910d0 628 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
jhon309 0:88e313c910d0 629 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
jhon309 0:88e313c910d0 630 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
jhon309 0:88e313c910d0 631 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
jhon309 0:88e313c910d0 632 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
jhon309 0:88e313c910d0 633
jhon309 0:88e313c910d0 634 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
jhon309 0:88e313c910d0 635 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
jhon309 0:88e313c910d0 636 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
jhon309 0:88e313c910d0 637 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
jhon309 0:88e313c910d0 638 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
jhon309 0:88e313c910d0 639 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
jhon309 0:88e313c910d0 640 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
jhon309 0:88e313c910d0 641 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
jhon309 0:88e313c910d0 642 /**
jhon309 0:88e313c910d0 643 * @}
jhon309 0:88e313c910d0 644 */
jhon309 0:88e313c910d0 645
jhon309 0:88e313c910d0 646 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
jhon309 0:88e313c910d0 647 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
jhon309 0:88e313c910d0 648 * @note After reset, the peripheral clock (used for registers read/write access)
jhon309 0:88e313c910d0 649 * is disabled and the application software has to enable this clock before
jhon309 0:88e313c910d0 650 * using it.
jhon309 0:88e313c910d0 651 * @{
jhon309 0:88e313c910d0 652 */
jhon309 0:88e313c910d0 653 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
jhon309 0:88e313c910d0 654 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
jhon309 0:88e313c910d0 655 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
jhon309 0:88e313c910d0 656 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
jhon309 0:88e313c910d0 657 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
jhon309 0:88e313c910d0 658
jhon309 0:88e313c910d0 659 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
jhon309 0:88e313c910d0 660 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
jhon309 0:88e313c910d0 661 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
jhon309 0:88e313c910d0 662 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
jhon309 0:88e313c910d0 663 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
jhon309 0:88e313c910d0 664 /**
jhon309 0:88e313c910d0 665 * @}
jhon309 0:88e313c910d0 666 */
jhon309 0:88e313c910d0 667
jhon309 0:88e313c910d0 668 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
jhon309 0:88e313c910d0 669 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
jhon309 0:88e313c910d0 670 * @note After reset, the peripheral clock (used for registers read/write access)
jhon309 0:88e313c910d0 671 * is disabled and the application software has to enable this clock before
jhon309 0:88e313c910d0 672 * using it.
jhon309 0:88e313c910d0 673 * @{
jhon309 0:88e313c910d0 674 */
jhon309 0:88e313c910d0 675 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
jhon309 0:88e313c910d0 676 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
jhon309 0:88e313c910d0 677 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
jhon309 0:88e313c910d0 678 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
jhon309 0:88e313c910d0 679 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
jhon309 0:88e313c910d0 680 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
jhon309 0:88e313c910d0 681 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
jhon309 0:88e313c910d0 682 #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
jhon309 0:88e313c910d0 683
jhon309 0:88e313c910d0 684 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
jhon309 0:88e313c910d0 685 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
jhon309 0:88e313c910d0 686 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
jhon309 0:88e313c910d0 687 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
jhon309 0:88e313c910d0 688 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
jhon309 0:88e313c910d0 689 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
jhon309 0:88e313c910d0 690 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
jhon309 0:88e313c910d0 691 #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
jhon309 0:88e313c910d0 692 /**
jhon309 0:88e313c910d0 693 * @}
jhon309 0:88e313c910d0 694 */
jhon309 0:88e313c910d0 695
jhon309 0:88e313c910d0 696 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
jhon309 0:88e313c910d0 697 * @brief Force or release AHB peripheral reset.
jhon309 0:88e313c910d0 698 * @{
jhon309 0:88e313c910d0 699 */
jhon309 0:88e313c910d0 700 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
jhon309 0:88e313c910d0 701 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
jhon309 0:88e313c910d0 702 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
jhon309 0:88e313c910d0 703 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
jhon309 0:88e313c910d0 704 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
jhon309 0:88e313c910d0 705
jhon309 0:88e313c910d0 706 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
jhon309 0:88e313c910d0 707 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
jhon309 0:88e313c910d0 708 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
jhon309 0:88e313c910d0 709 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
jhon309 0:88e313c910d0 710 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
jhon309 0:88e313c910d0 711 /**
jhon309 0:88e313c910d0 712 * @}
jhon309 0:88e313c910d0 713 */
jhon309 0:88e313c910d0 714
jhon309 0:88e313c910d0 715 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
jhon309 0:88e313c910d0 716 * @brief Force or release APB1 peripheral reset.
jhon309 0:88e313c910d0 717 * @{
jhon309 0:88e313c910d0 718 */
jhon309 0:88e313c910d0 719 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
jhon309 0:88e313c910d0 720 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
jhon309 0:88e313c910d0 721 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
jhon309 0:88e313c910d0 722 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
jhon309 0:88e313c910d0 723 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
jhon309 0:88e313c910d0 724 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
jhon309 0:88e313c910d0 725
jhon309 0:88e313c910d0 726 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
jhon309 0:88e313c910d0 727 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
jhon309 0:88e313c910d0 728 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
jhon309 0:88e313c910d0 729 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
jhon309 0:88e313c910d0 730 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
jhon309 0:88e313c910d0 731 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
jhon309 0:88e313c910d0 732 /**
jhon309 0:88e313c910d0 733 * @}
jhon309 0:88e313c910d0 734 */
jhon309 0:88e313c910d0 735
jhon309 0:88e313c910d0 736 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
jhon309 0:88e313c910d0 737 * @brief Force or release APB2 peripheral reset.
jhon309 0:88e313c910d0 738 * @{
jhon309 0:88e313c910d0 739 */
jhon309 0:88e313c910d0 740 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
jhon309 0:88e313c910d0 741 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
jhon309 0:88e313c910d0 742 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
jhon309 0:88e313c910d0 743 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
jhon309 0:88e313c910d0 744 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
jhon309 0:88e313c910d0 745 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
jhon309 0:88e313c910d0 746 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
jhon309 0:88e313c910d0 747 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
jhon309 0:88e313c910d0 748 #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
jhon309 0:88e313c910d0 749
jhon309 0:88e313c910d0 750 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
jhon309 0:88e313c910d0 751 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
jhon309 0:88e313c910d0 752 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
jhon309 0:88e313c910d0 753 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
jhon309 0:88e313c910d0 754 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
jhon309 0:88e313c910d0 755 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
jhon309 0:88e313c910d0 756 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
jhon309 0:88e313c910d0 757 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
jhon309 0:88e313c910d0 758 #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
jhon309 0:88e313c910d0 759 /**
jhon309 0:88e313c910d0 760 * @}
jhon309 0:88e313c910d0 761 */
jhon309 0:88e313c910d0 762
jhon309 0:88e313c910d0 763 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
jhon309 0:88e313c910d0 764 * @{
jhon309 0:88e313c910d0 765 */
jhon309 0:88e313c910d0 766
jhon309 0:88e313c910d0 767 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
jhon309 0:88e313c910d0 768 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
jhon309 0:88e313c910d0 769 * It is used (enabled by hardware) as system clock source after startup
jhon309 0:88e313c910d0 770 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
jhon309 0:88e313c910d0 771 * of the HSE used directly or indirectly as system clock (if the Clock
jhon309 0:88e313c910d0 772 * Security System CSS is enabled).
jhon309 0:88e313c910d0 773 * @note HSI can not be stopped if it is used as system clock source. In this case,
jhon309 0:88e313c910d0 774 * you have to select another source of the system clock then stop the HSI.
jhon309 0:88e313c910d0 775 * @note After enabling the HSI, the application software should wait on HSIRDY
jhon309 0:88e313c910d0 776 * flag to be set indicating that HSI clock is stable and can be used as
jhon309 0:88e313c910d0 777 * system clock source.
jhon309 0:88e313c910d0 778 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
jhon309 0:88e313c910d0 779 * clock cycles.
jhon309 0:88e313c910d0 780 */
jhon309 0:88e313c910d0 781 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
jhon309 0:88e313c910d0 782 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
jhon309 0:88e313c910d0 783
jhon309 0:88e313c910d0 784 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
jhon309 0:88e313c910d0 785 * @note The calibration is used to compensate for the variations in voltage
jhon309 0:88e313c910d0 786 * and temperature that influence the frequency of the internal HSI RC.
jhon309 0:88e313c910d0 787 * @param __HSICalibrationValue__: specifies the calibration trimming value
jhon309 0:88e313c910d0 788 * (default is RCC_HSICALIBRATION_DEFAULT).
jhon309 0:88e313c910d0 789 * This parameter must be a number between 0 and 0x1F.
jhon309 0:88e313c910d0 790 */
jhon309 0:88e313c910d0 791 #define RCC_CR_HSITRIM_BitNumber 3
jhon309 0:88e313c910d0 792 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
jhon309 0:88e313c910d0 793 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
jhon309 0:88e313c910d0 794 /**
jhon309 0:88e313c910d0 795 * @}
jhon309 0:88e313c910d0 796 */
jhon309 0:88e313c910d0 797
jhon309 0:88e313c910d0 798 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
jhon309 0:88e313c910d0 799 * @{
jhon309 0:88e313c910d0 800 */
jhon309 0:88e313c910d0 801
jhon309 0:88e313c910d0 802 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
jhon309 0:88e313c910d0 803 * @note After enabling the LSI, the application software should wait on
jhon309 0:88e313c910d0 804 * LSIRDY flag to be set indicating that LSI clock is stable and can
jhon309 0:88e313c910d0 805 * be used to clock the IWDG and/or the RTC.
jhon309 0:88e313c910d0 806 * @note LSI can not be disabled if the IWDG is running.
jhon309 0:88e313c910d0 807 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
jhon309 0:88e313c910d0 808 * clock cycles.
jhon309 0:88e313c910d0 809 */
jhon309 0:88e313c910d0 810 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
jhon309 0:88e313c910d0 811 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
jhon309 0:88e313c910d0 812 /**
jhon309 0:88e313c910d0 813 * @}
jhon309 0:88e313c910d0 814 */
jhon309 0:88e313c910d0 815
jhon309 0:88e313c910d0 816 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
jhon309 0:88e313c910d0 817 * @{
jhon309 0:88e313c910d0 818 */
jhon309 0:88e313c910d0 819
jhon309 0:88e313c910d0 820 /**
jhon309 0:88e313c910d0 821 * @brief Macro to configure the External High Speed oscillator (HSE).
jhon309 0:88e313c910d0 822 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
jhon309 0:88e313c910d0 823 * software should wait on HSERDY flag to be set indicating that HSE clock
jhon309 0:88e313c910d0 824 * is stable and can be used to clock the PLL and/or system clock.
jhon309 0:88e313c910d0 825 * @note HSE state can not be changed if it is used directly or through the
jhon309 0:88e313c910d0 826 * PLL as system clock. In this case, you have to select another source
jhon309 0:88e313c910d0 827 * of the system clock then change the HSE state (ex. disable it).
jhon309 0:88e313c910d0 828 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
jhon309 0:88e313c910d0 829 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
jhon309 0:88e313c910d0 830 * was previously enabled you have to enable it again after calling this
jhon309 0:88e313c910d0 831 * function.
jhon309 0:88e313c910d0 832 * @param __STATE__: specifies the new state of the HSE.
jhon309 0:88e313c910d0 833 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 834 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
jhon309 0:88e313c910d0 835 * 6 HSE oscillator clock cycles.
jhon309 0:88e313c910d0 836 * @arg RCC_HSE_ON: turn ON the HSE oscillator
jhon309 0:88e313c910d0 837 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
jhon309 0:88e313c910d0 838 */
jhon309 0:88e313c910d0 839 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
jhon309 0:88e313c910d0 840
jhon309 0:88e313c910d0 841 /**
jhon309 0:88e313c910d0 842 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
jhon309 0:88e313c910d0 843 * @note Predivision factor can not be changed if PLL is used as system clock
jhon309 0:88e313c910d0 844 * In this case, you have to select another source of the system clock, disable the PLL and
jhon309 0:88e313c910d0 845 * then change the HSE predivision factor.
jhon309 0:88e313c910d0 846 * @param __HSEPredivValue__: specifies the division value applied to HSE.
jhon309 0:88e313c910d0 847 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
jhon309 0:88e313c910d0 848 */
jhon309 0:88e313c910d0 849 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
jhon309 0:88e313c910d0 850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
jhon309 0:88e313c910d0 851 /**
jhon309 0:88e313c910d0 852 * @}
jhon309 0:88e313c910d0 853 */
jhon309 0:88e313c910d0 854
jhon309 0:88e313c910d0 855 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
jhon309 0:88e313c910d0 856 * @{
jhon309 0:88e313c910d0 857 */
jhon309 0:88e313c910d0 858 /**
jhon309 0:88e313c910d0 859 * @brief Macro to configure the External Low Speed oscillator (LSE).
jhon309 0:88e313c910d0 860 * @note As the LSE is in the Backup domain and write access is denied to
jhon309 0:88e313c910d0 861 * this domain after reset, you have to enable write access using
jhon309 0:88e313c910d0 862 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
jhon309 0:88e313c910d0 863 * (to be done once after reset).
jhon309 0:88e313c910d0 864 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
jhon309 0:88e313c910d0 865 * software should wait on LSERDY flag to be set indicating that LSE clock
jhon309 0:88e313c910d0 866 * is stable and can be used to clock the RTC.
jhon309 0:88e313c910d0 867 * @param __STATE__: specifies the new state of the LSE.
jhon309 0:88e313c910d0 868 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 869 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
jhon309 0:88e313c910d0 870 * 6 LSE oscillator clock cycles.
jhon309 0:88e313c910d0 871 * @arg RCC_LSE_ON: turn ON the LSE oscillator
jhon309 0:88e313c910d0 872 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
jhon309 0:88e313c910d0 873 */
jhon309 0:88e313c910d0 874 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
jhon309 0:88e313c910d0 875 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
jhon309 0:88e313c910d0 876 /**
jhon309 0:88e313c910d0 877 * @}
jhon309 0:88e313c910d0 878 */
jhon309 0:88e313c910d0 879
jhon309 0:88e313c910d0 880 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
jhon309 0:88e313c910d0 881 * @{
jhon309 0:88e313c910d0 882 */
jhon309 0:88e313c910d0 883
jhon309 0:88e313c910d0 884 /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
jhon309 0:88e313c910d0 885 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
jhon309 0:88e313c910d0 886 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
jhon309 0:88e313c910d0 887 * you have to select another source of the system clock then stop the HSI14.
jhon309 0:88e313c910d0 888 * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
jhon309 0:88e313c910d0 889 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
jhon309 0:88e313c910d0 890 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
jhon309 0:88e313c910d0 891 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
jhon309 0:88e313c910d0 892 * clock cycles.
jhon309 0:88e313c910d0 893 */
jhon309 0:88e313c910d0 894 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
jhon309 0:88e313c910d0 895 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
jhon309 0:88e313c910d0 896
jhon309 0:88e313c910d0 897 /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
jhon309 0:88e313c910d0 898 */
jhon309 0:88e313c910d0 899 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
jhon309 0:88e313c910d0 900 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
jhon309 0:88e313c910d0 901
jhon309 0:88e313c910d0 902 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
jhon309 0:88e313c910d0 903 * @note The calibration is used to compensate for the variations in voltage
jhon309 0:88e313c910d0 904 * and temperature that influence the frequency of the internal HSI14 RC.
jhon309 0:88e313c910d0 905 * @param __HSI14CalibrationValue__: specifies the calibration trimming value
jhon309 0:88e313c910d0 906 * (default is RCC_HSI14CALIBRATION_DEFAULT).
jhon309 0:88e313c910d0 907 * This parameter must be a number between 0 and 0x1F.
jhon309 0:88e313c910d0 908 */
jhon309 0:88e313c910d0 909 #define RCC_CR2_HSI14TRIM_BitNumber 3
jhon309 0:88e313c910d0 910 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
jhon309 0:88e313c910d0 911 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
jhon309 0:88e313c910d0 912 /**
jhon309 0:88e313c910d0 913 * @}
jhon309 0:88e313c910d0 914 */
jhon309 0:88e313c910d0 915
jhon309 0:88e313c910d0 916 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
jhon309 0:88e313c910d0 917 * @{
jhon309 0:88e313c910d0 918 */
jhon309 0:88e313c910d0 919
jhon309 0:88e313c910d0 920 /** @brief Macro to configure the USART1 clock (USART1CLK).
jhon309 0:88e313c910d0 921 * @param __USART1CLKSource__: specifies the USART1 clock source.
jhon309 0:88e313c910d0 922 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 923 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
jhon309 0:88e313c910d0 924 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
jhon309 0:88e313c910d0 925 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
jhon309 0:88e313c910d0 926 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
jhon309 0:88e313c910d0 927 */
jhon309 0:88e313c910d0 928 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
jhon309 0:88e313c910d0 929 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
jhon309 0:88e313c910d0 930
jhon309 0:88e313c910d0 931 /** @brief Macro to get the USART1 clock source.
jhon309 0:88e313c910d0 932 * @retval The clock source can be one of the following values:
jhon309 0:88e313c910d0 933 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
jhon309 0:88e313c910d0 934 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
jhon309 0:88e313c910d0 935 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
jhon309 0:88e313c910d0 936 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
jhon309 0:88e313c910d0 937 */
jhon309 0:88e313c910d0 938 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
jhon309 0:88e313c910d0 939 /**
jhon309 0:88e313c910d0 940 * @}
jhon309 0:88e313c910d0 941 */
jhon309 0:88e313c910d0 942
jhon309 0:88e313c910d0 943 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
jhon309 0:88e313c910d0 944 * @{
jhon309 0:88e313c910d0 945 */
jhon309 0:88e313c910d0 946
jhon309 0:88e313c910d0 947 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
jhon309 0:88e313c910d0 948 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
jhon309 0:88e313c910d0 949 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 950 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
jhon309 0:88e313c910d0 951 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
jhon309 0:88e313c910d0 952 */
jhon309 0:88e313c910d0 953 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
jhon309 0:88e313c910d0 954 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
jhon309 0:88e313c910d0 955
jhon309 0:88e313c910d0 956 /** @brief Macro to get the I2C1 clock source.
jhon309 0:88e313c910d0 957 * @retval The clock source can be one of the following values:
jhon309 0:88e313c910d0 958 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
jhon309 0:88e313c910d0 959 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
jhon309 0:88e313c910d0 960 */
jhon309 0:88e313c910d0 961 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
jhon309 0:88e313c910d0 962 /**
jhon309 0:88e313c910d0 963 * @}
jhon309 0:88e313c910d0 964 */
jhon309 0:88e313c910d0 965
jhon309 0:88e313c910d0 966 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
jhon309 0:88e313c910d0 967 * @{
jhon309 0:88e313c910d0 968 */
jhon309 0:88e313c910d0 969 /** @brief Macros to enable or disable the the RTC clock.
jhon309 0:88e313c910d0 970 * @note These macros must be used only after the RTC clock source was selected.
jhon309 0:88e313c910d0 971 */
jhon309 0:88e313c910d0 972 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
jhon309 0:88e313c910d0 973 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
jhon309 0:88e313c910d0 974
jhon309 0:88e313c910d0 975 /** @brief Macro to configure the RTC clock (RTCCLK).
jhon309 0:88e313c910d0 976 * @note As the RTC clock configuration bits are in the Backup domain and write
jhon309 0:88e313c910d0 977 * access is denied to this domain after reset, you have to enable write
jhon309 0:88e313c910d0 978 * access using the Power Backup Access macro before to configure
jhon309 0:88e313c910d0 979 * the RTC clock source (to be done once after reset).
jhon309 0:88e313c910d0 980 * @note Once the RTC clock is configured it can't be changed unless the
jhon309 0:88e313c910d0 981 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
jhon309 0:88e313c910d0 982 * a Power On Reset (POR).
jhon309 0:88e313c910d0 983 * @param __RTCCLKSource__: specifies the RTC clock source.
jhon309 0:88e313c910d0 984 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 985 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
jhon309 0:88e313c910d0 986 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
jhon309 0:88e313c910d0 987 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
jhon309 0:88e313c910d0 988 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
jhon309 0:88e313c910d0 989 *
jhon309 0:88e313c910d0 990 * @note If the LSE is used as RTC clock source, the RTC continues to
jhon309 0:88e313c910d0 991 * work in STOP and STANDBY modes, and can be used as wakeup source.
jhon309 0:88e313c910d0 992 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
jhon309 0:88e313c910d0 993 * the RTC cannot be used in STOP and STANDBY modes.
jhon309 0:88e313c910d0 994 * @note The system must always be configured so as to get a PCLK frequency greater than or
jhon309 0:88e313c910d0 995 * equal to the RTCCLK frequency for a proper operation of the RTC.
jhon309 0:88e313c910d0 996 */
jhon309 0:88e313c910d0 997 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
jhon309 0:88e313c910d0 998 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
jhon309 0:88e313c910d0 999
jhon309 0:88e313c910d0 1000 /** @brief Macro to get the RTC clock source.
jhon309 0:88e313c910d0 1001 * @retval The clock source can be one of the following values:
jhon309 0:88e313c910d0 1002 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
jhon309 0:88e313c910d0 1003 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
jhon309 0:88e313c910d0 1004 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
jhon309 0:88e313c910d0 1005 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
jhon309 0:88e313c910d0 1006 */
jhon309 0:88e313c910d0 1007 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
jhon309 0:88e313c910d0 1008 /**
jhon309 0:88e313c910d0 1009 * @}
jhon309 0:88e313c910d0 1010 */
jhon309 0:88e313c910d0 1011
jhon309 0:88e313c910d0 1012 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
jhon309 0:88e313c910d0 1013 * @{
jhon309 0:88e313c910d0 1014 */
jhon309 0:88e313c910d0 1015
jhon309 0:88e313c910d0 1016 /** @brief Macro to force or release the Backup domain reset.
jhon309 0:88e313c910d0 1017 * @note These macros reset the RTC peripheral (including the backup registers)
jhon309 0:88e313c910d0 1018 * and the RTC clock source selection in RCC_CSR register.
jhon309 0:88e313c910d0 1019 * @note The BKPSRAM is not affected by this reset.
jhon309 0:88e313c910d0 1020 */
jhon309 0:88e313c910d0 1021 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
jhon309 0:88e313c910d0 1022 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
jhon309 0:88e313c910d0 1023 /**
jhon309 0:88e313c910d0 1024 * @}
jhon309 0:88e313c910d0 1025 */
jhon309 0:88e313c910d0 1026
jhon309 0:88e313c910d0 1027 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
jhon309 0:88e313c910d0 1028 * @{
jhon309 0:88e313c910d0 1029 */
jhon309 0:88e313c910d0 1030
jhon309 0:88e313c910d0 1031 /** @brief Macro to enable or disable the PLL.
jhon309 0:88e313c910d0 1032 * @note After enabling the PLL, the application software should wait on
jhon309 0:88e313c910d0 1033 * PLLRDY flag to be set indicating that PLL clock is stable and can
jhon309 0:88e313c910d0 1034 * be used as system clock source.
jhon309 0:88e313c910d0 1035 * @note The PLL can not be disabled if it is used as system clock source
jhon309 0:88e313c910d0 1036 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
jhon309 0:88e313c910d0 1037 */
jhon309 0:88e313c910d0 1038 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
jhon309 0:88e313c910d0 1039 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
jhon309 0:88e313c910d0 1040
jhon309 0:88e313c910d0 1041 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
jhon309 0:88e313c910d0 1042 * @note This macro must be used only when the PLL is disabled.
jhon309 0:88e313c910d0 1043 *
jhon309 0:88e313c910d0 1044 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
jhon309 0:88e313c910d0 1045 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 1046 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
jhon309 0:88e313c910d0 1047 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
jhon309 0:88e313c910d0 1048 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
jhon309 0:88e313c910d0 1049 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
jhon309 0:88e313c910d0 1050 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
jhon309 0:88e313c910d0 1051 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
jhon309 0:88e313c910d0 1052 *
jhon309 0:88e313c910d0 1053 */
jhon309 0:88e313c910d0 1054 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
jhon309 0:88e313c910d0 1055 do { \
jhon309 0:88e313c910d0 1056 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
jhon309 0:88e313c910d0 1057 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
jhon309 0:88e313c910d0 1058 } while(0)
jhon309 0:88e313c910d0 1059 /**
jhon309 0:88e313c910d0 1060 * @}
jhon309 0:88e313c910d0 1061 */
jhon309 0:88e313c910d0 1062
jhon309 0:88e313c910d0 1063 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
jhon309 0:88e313c910d0 1064 * @{
jhon309 0:88e313c910d0 1065 */
jhon309 0:88e313c910d0 1066
jhon309 0:88e313c910d0 1067 /** @brief Macro to get the clock source used as system clock.
jhon309 0:88e313c910d0 1068 * @retval The clock source used as system clock.
jhon309 0:88e313c910d0 1069 * The returned value can be one of the following value:
jhon309 0:88e313c910d0 1070 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
jhon309 0:88e313c910d0 1071 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
jhon309 0:88e313c910d0 1072 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
jhon309 0:88e313c910d0 1073 */
jhon309 0:88e313c910d0 1074 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
jhon309 0:88e313c910d0 1075
jhon309 0:88e313c910d0 1076 /** @brief Macro to get the oscillator used as PLL clock source.
jhon309 0:88e313c910d0 1077 * @retval The oscillator used as PLL clock source. The returned value can be one
jhon309 0:88e313c910d0 1078 * of the following:
jhon309 0:88e313c910d0 1079 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
jhon309 0:88e313c910d0 1080 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
jhon309 0:88e313c910d0 1081 */
jhon309 0:88e313c910d0 1082 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
jhon309 0:88e313c910d0 1083 /**
jhon309 0:88e313c910d0 1084 * @}
jhon309 0:88e313c910d0 1085 */
jhon309 0:88e313c910d0 1086
jhon309 0:88e313c910d0 1087 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
jhon309 0:88e313c910d0 1088 * @brief macros to manage the specified RCC Flags and interrupts.
jhon309 0:88e313c910d0 1089 * @{
jhon309 0:88e313c910d0 1090 */
jhon309 0:88e313c910d0 1091
jhon309 0:88e313c910d0 1092 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
jhon309 0:88e313c910d0 1093 * the selected interrupts.).
jhon309 0:88e313c910d0 1094 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
jhon309 0:88e313c910d0 1095 * This parameter can be any combination of the following values:
jhon309 0:88e313c910d0 1096 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
jhon309 0:88e313c910d0 1097 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
jhon309 0:88e313c910d0 1098 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
jhon309 0:88e313c910d0 1099 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
jhon309 0:88e313c910d0 1100 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
jhon309 0:88e313c910d0 1101 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
jhon309 0:88e313c910d0 1102 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
jhon309 0:88e313c910d0 1103 */
jhon309 0:88e313c910d0 1104 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
jhon309 0:88e313c910d0 1105
jhon309 0:88e313c910d0 1106 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
jhon309 0:88e313c910d0 1107 * the selected interrupts.).
jhon309 0:88e313c910d0 1108 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
jhon309 0:88e313c910d0 1109 * This parameter can be any combination of the following values:
jhon309 0:88e313c910d0 1110 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
jhon309 0:88e313c910d0 1111 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
jhon309 0:88e313c910d0 1112 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
jhon309 0:88e313c910d0 1113 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
jhon309 0:88e313c910d0 1114 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
jhon309 0:88e313c910d0 1115 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
jhon309 0:88e313c910d0 1116 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
jhon309 0:88e313c910d0 1117 */
jhon309 0:88e313c910d0 1118 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
jhon309 0:88e313c910d0 1119
jhon309 0:88e313c910d0 1120 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
jhon309 0:88e313c910d0 1121 * bits to clear the selected interrupt pending bits.
jhon309 0:88e313c910d0 1122 * @param __IT__: specifies the interrupt pending bit to clear.
jhon309 0:88e313c910d0 1123 * This parameter can be any combination of the following values:
jhon309 0:88e313c910d0 1124 * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
jhon309 0:88e313c910d0 1125 * @arg RCC_IT_LSERDY: LSE ready interrupt clear
jhon309 0:88e313c910d0 1126 * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
jhon309 0:88e313c910d0 1127 * @arg RCC_IT_HSERDY: HSE ready interrupt clear
jhon309 0:88e313c910d0 1128 * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
jhon309 0:88e313c910d0 1129 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
jhon309 0:88e313c910d0 1130 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
jhon309 0:88e313c910d0 1131 * @arg RCC_IT_CSS: Clock Security System interrupt clear
jhon309 0:88e313c910d0 1132 */
jhon309 0:88e313c910d0 1133 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
jhon309 0:88e313c910d0 1134
jhon309 0:88e313c910d0 1135 /** @brief Check the RCC's interrupt has occurred or not.
jhon309 0:88e313c910d0 1136 * @param __IT__: specifies the RCC interrupt source to check.
jhon309 0:88e313c910d0 1137 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 1138 * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
jhon309 0:88e313c910d0 1139 * @arg RCC_IT_LSERDY: LSE ready interrupt flag
jhon309 0:88e313c910d0 1140 * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
jhon309 0:88e313c910d0 1141 * @arg RCC_IT_HSERDY: HSE ready interrupt flag
jhon309 0:88e313c910d0 1142 * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
jhon309 0:88e313c910d0 1143 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
jhon309 0:88e313c910d0 1144 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
jhon309 0:88e313c910d0 1145 * @arg RCC_IT_CSS: Clock Security System interrupt flag
jhon309 0:88e313c910d0 1146 * @retval The new state of __IT__ (TRUE or FALSE).
jhon309 0:88e313c910d0 1147 */
jhon309 0:88e313c910d0 1148 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
jhon309 0:88e313c910d0 1149
jhon309 0:88e313c910d0 1150 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
jhon309 0:88e313c910d0 1151 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
jhon309 0:88e313c910d0 1152 */
jhon309 0:88e313c910d0 1153 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
jhon309 0:88e313c910d0 1154
jhon309 0:88e313c910d0 1155 /** @brief Check RCC flag is set or not.
jhon309 0:88e313c910d0 1156 * @param __FLAG__: specifies the flag to check.
jhon309 0:88e313c910d0 1157 * This parameter can be one of the following values:
jhon309 0:88e313c910d0 1158 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
jhon309 0:88e313c910d0 1159 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
jhon309 0:88e313c910d0 1160 * @arg RCC_FLAG_PLLRDY: PLL clock ready
jhon309 0:88e313c910d0 1161 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
jhon309 0:88e313c910d0 1162 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
jhon309 0:88e313c910d0 1163 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
jhon309 0:88e313c910d0 1164 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
jhon309 0:88e313c910d0 1165 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
jhon309 0:88e313c910d0 1166 * @arg RCC_FLAG_PINRST: Pin reset
jhon309 0:88e313c910d0 1167 * @arg RCC_FLAG_PORRST: POR/PDR reset
jhon309 0:88e313c910d0 1168 * @arg RCC_FLAG_SFTRST: Software reset
jhon309 0:88e313c910d0 1169 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
jhon309 0:88e313c910d0 1170 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
jhon309 0:88e313c910d0 1171 * @arg RCC_FLAG_LPWRRST: Low Power reset
jhon309 0:88e313c910d0 1172 * @retval The new state of __FLAG__ (TRUE or FALSE).
jhon309 0:88e313c910d0 1173 */
jhon309 0:88e313c910d0 1174 #define RCC_FLAG_MASK ((uint8_t)0x1F)
jhon309 0:88e313c910d0 1175 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
jhon309 0:88e313c910d0 1176 (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
jhon309 0:88e313c910d0 1177 (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
jhon309 0:88e313c910d0 1178 RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
jhon309 0:88e313c910d0 1179
jhon309 0:88e313c910d0 1180
jhon309 0:88e313c910d0 1181
jhon309 0:88e313c910d0 1182 /**
jhon309 0:88e313c910d0 1183 * @}
jhon309 0:88e313c910d0 1184 */
jhon309 0:88e313c910d0 1185
jhon309 0:88e313c910d0 1186 /**
jhon309 0:88e313c910d0 1187 * @}
jhon309 0:88e313c910d0 1188 */
jhon309 0:88e313c910d0 1189
jhon309 0:88e313c910d0 1190 /* Include RCC HAL Extension module */
jhon309 0:88e313c910d0 1191 #include "stm32f0xx_hal_rcc_ex.h"
jhon309 0:88e313c910d0 1192
jhon309 0:88e313c910d0 1193 /* Exported functions --------------------------------------------------------*/
jhon309 0:88e313c910d0 1194
jhon309 0:88e313c910d0 1195 /** @addtogroup RCC_Exported_Functions
jhon309 0:88e313c910d0 1196 * @{
jhon309 0:88e313c910d0 1197 */
jhon309 0:88e313c910d0 1198
jhon309 0:88e313c910d0 1199 /** @addtogroup RCC_Exported_Functions_Group1
jhon309 0:88e313c910d0 1200 * @{
jhon309 0:88e313c910d0 1201 */
jhon309 0:88e313c910d0 1202
jhon309 0:88e313c910d0 1203 /* Initialization and de-initialization functions ***************************/
jhon309 0:88e313c910d0 1204 void HAL_RCC_DeInit(void);
jhon309 0:88e313c910d0 1205 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
jhon309 0:88e313c910d0 1206 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
jhon309 0:88e313c910d0 1207
jhon309 0:88e313c910d0 1208 /**
jhon309 0:88e313c910d0 1209 * @}
jhon309 0:88e313c910d0 1210 */
jhon309 0:88e313c910d0 1211
jhon309 0:88e313c910d0 1212 /** @addtogroup RCC_Exported_Functions_Group2
jhon309 0:88e313c910d0 1213 * @{
jhon309 0:88e313c910d0 1214 */
jhon309 0:88e313c910d0 1215
jhon309 0:88e313c910d0 1216 /* Peripheral Control functions *********************************************/
jhon309 0:88e313c910d0 1217 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
jhon309 0:88e313c910d0 1218 void HAL_RCC_EnableCSS(void);
jhon309 0:88e313c910d0 1219 void HAL_RCC_DisableCSS(void);
jhon309 0:88e313c910d0 1220 uint32_t HAL_RCC_GetSysClockFreq(void);
jhon309 0:88e313c910d0 1221 uint32_t HAL_RCC_GetHCLKFreq(void);
jhon309 0:88e313c910d0 1222 uint32_t HAL_RCC_GetPCLK1Freq(void);
jhon309 0:88e313c910d0 1223 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
jhon309 0:88e313c910d0 1224 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
jhon309 0:88e313c910d0 1225
jhon309 0:88e313c910d0 1226 /* CSS NMI IRQ handler */
jhon309 0:88e313c910d0 1227 void HAL_RCC_NMI_IRQHandler(void);
jhon309 0:88e313c910d0 1228
jhon309 0:88e313c910d0 1229 /* User Callbacks in non blocking mode (IT mode) */
jhon309 0:88e313c910d0 1230 void HAL_RCC_CCSCallback(void);
jhon309 0:88e313c910d0 1231
jhon309 0:88e313c910d0 1232 /**
jhon309 0:88e313c910d0 1233 * @}
jhon309 0:88e313c910d0 1234 */
jhon309 0:88e313c910d0 1235
jhon309 0:88e313c910d0 1236 /**
jhon309 0:88e313c910d0 1237 * @}
jhon309 0:88e313c910d0 1238 */
jhon309 0:88e313c910d0 1239
jhon309 0:88e313c910d0 1240 /**
jhon309 0:88e313c910d0 1241 * @}
jhon309 0:88e313c910d0 1242 */
jhon309 0:88e313c910d0 1243
jhon309 0:88e313c910d0 1244 /**
jhon309 0:88e313c910d0 1245 * @}
jhon309 0:88e313c910d0 1246 */
jhon309 0:88e313c910d0 1247
jhon309 0:88e313c910d0 1248 #ifdef __cplusplus
jhon309 0:88e313c910d0 1249 }
jhon309 0:88e313c910d0 1250 #endif
jhon309 0:88e313c910d0 1251
jhon309 0:88e313c910d0 1252 #endif /* __STM32F0xx_HAL_RCC_H */
jhon309 0:88e313c910d0 1253
jhon309 0:88e313c910d0 1254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
jhon309 0:88e313c910d0 1255