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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma_ex.h@0:88e313c910d0, 2015-08-13 (annotated)

Committer:: jhon309
Date:: Thu Aug 13 00:20:09 2015 +0000
Revision:: 0:88e313c910d0

RTC Example

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User	Revision	Line number	New contents of line
jhon309	0:88e313c910d0	1	/**
jhon309	0:88e313c910d0	2	******************************************************************************
jhon309	0:88e313c910d0	3	* @file stm32f0xx_hal_dma_ex.h
jhon309	0:88e313c910d0	4	* @author MCD Application Team
jhon309	0:88e313c910d0	5	* @version V1.2.0
jhon309	0:88e313c910d0	6	* @date 11-December-2014
jhon309	0:88e313c910d0	7	* @brief Header file of DMA HAL Extension module.
jhon309	0:88e313c910d0	8	******************************************************************************
jhon309	0:88e313c910d0	9	* @attention
jhon309	0:88e313c910d0	10	*
jhon309	0:88e313c910d0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309	0:88e313c910d0	12	*
jhon309	0:88e313c910d0	13	* Redistribution and use in source and binary forms, with or without modification,
jhon309	0:88e313c910d0	14	* are permitted provided that the following conditions are met:
jhon309	0:88e313c910d0	15	* 1. Redistributions of source code must retain the above copyright notice,
jhon309	0:88e313c910d0	16	* this list of conditions and the following disclaimer.
jhon309	0:88e313c910d0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309	0:88e313c910d0	18	* this list of conditions and the following disclaimer in the documentation
jhon309	0:88e313c910d0	19	* and/or other materials provided with the distribution.
jhon309	0:88e313c910d0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309	0:88e313c910d0	21	* may be used to endorse or promote products derived from this software
jhon309	0:88e313c910d0	22	* without specific prior written permission.
jhon309	0:88e313c910d0	23	*
jhon309	0:88e313c910d0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309	0:88e313c910d0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309	0:88e313c910d0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309	0:88e313c910d0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309	0:88e313c910d0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309	0:88e313c910d0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309	0:88e313c910d0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309	0:88e313c910d0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309	0:88e313c910d0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309	0:88e313c910d0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309	0:88e313c910d0	34	*
jhon309	0:88e313c910d0	35	******************************************************************************
jhon309	0:88e313c910d0	36	*/
jhon309	0:88e313c910d0	37
jhon309	0:88e313c910d0	38	/* Define to prevent recursive inclusion -------------------------------------*/
jhon309	0:88e313c910d0	39	#ifndef __STM32F0xx_HAL_DMA_EX_H
jhon309	0:88e313c910d0	40	#define __STM32F0xx_HAL_DMA_EX_H
jhon309	0:88e313c910d0	41
jhon309	0:88e313c910d0	42	#ifdef __cplusplus
jhon309	0:88e313c910d0	43	extern "C" {
jhon309	0:88e313c910d0	44	#endif
jhon309	0:88e313c910d0	45
jhon309	0:88e313c910d0	46	/* Includes ------------------------------------------------------------------*/
jhon309	0:88e313c910d0	47	#include "stm32f0xx_hal_def.h"
jhon309	0:88e313c910d0	48
jhon309	0:88e313c910d0	49	/** @addtogroup STM32F0xx_HAL_Driver
jhon309	0:88e313c910d0	50	* @{
jhon309	0:88e313c910d0	51	*/
jhon309	0:88e313c910d0	52
jhon309	0:88e313c910d0	53	/** @addtogroup DMAEx
jhon309	0:88e313c910d0	54	* @{
jhon309	0:88e313c910d0	55	*/
jhon309	0:88e313c910d0	56
jhon309	0:88e313c910d0	57	/* Exported types ------------------------------------------------------------*/
jhon309	0:88e313c910d0	58	/* Exported constants --------------------------------------------------------*/
jhon309	0:88e313c910d0	59	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	60	/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
jhon309	0:88e313c910d0	61	* @{
jhon309	0:88e313c910d0	62	*/
jhon309	0:88e313c910d0	63	#define DMA1_CHANNEL1_RMP 0x00000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	64	#define DMA1_CHANNEL2_RMP 0x10000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	65	#define DMA1_CHANNEL3_RMP 0x20000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	66	#define DMA1_CHANNEL4_RMP 0x30000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	67	#define DMA1_CHANNEL5_RMP 0x40000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	68	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	69	#define DMA1_CHANNEL6_RMP 0x50000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	70	#define DMA1_CHANNEL7_RMP 0x60000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	71	#define DMA2_CHANNEL1_RMP 0x00000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	72	#define DMA2_CHANNEL2_RMP 0x10000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	73	#define DMA2_CHANNEL3_RMP 0x20000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	74	#define DMA2_CHANNEL4_RMP 0x30000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	75	#define DMA2_CHANNEL5_RMP 0x40000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:88e313c910d0	76	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	77
jhon309	0:88e313c910d0	78	/**************** DMA1 remap bit field definition******************/
jhon309	0:88e313c910d0	79	/* DMA1 - Channel 1 */
jhon309	0:88e313c910d0	80	#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	81	#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_ADC) /!< Remap ADC on DMA1 Channel 1/
jhon309	0:88e313c910d0	82	#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 1 /
jhon309	0:88e313c910d0	83	#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 1 /
jhon309	0:88e313c910d0	84	#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	85	#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	86	#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	87	#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	88	#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	89	#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	90	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	91	#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	92	#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 1 /
jhon309	0:88e313c910d0	93	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	94
jhon309	0:88e313c910d0	95	/* DMA1 - Channel 2 */
jhon309	0:88e313c910d0	96	#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	97	#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_ADC) /!< Remap ADC on DMA1 channel 2 /
jhon309	0:88e313c910d0	98	#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_I2C1_TX) /!< Remap I2C1 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	99	#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_SPI1_RX) /!< Remap SPI1 Rx on DMA1 channel 2 /
jhon309	0:88e313c910d0	100	#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM1_CH1) /!< Remap TIM1 channel 1 on DMA1 channel 2 /
jhon309	0:88e313c910d0	101	#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 2 /
jhon309	0:88e313c910d0	102	#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 2 /
jhon309	0:88e313c910d0	103	#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	104	#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	105	#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	106	#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	107	#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	108	#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	109	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	110	#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	111	#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 2 /
jhon309	0:88e313c910d0	112	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	113
jhon309	0:88e313c910d0	114	/* DMA1 - Channel 3 */
jhon309	0:88e313c910d0	115	#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	116	#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM6_UP) /!< Remap TIM6 up on DMA1 channel 3 /
jhon309	0:88e313c910d0	117	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	118	#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_DAC_CH1) /!< Remap DAC Channel 1on DMA1 channel 3 /
jhon309	0:88e313c910d0	119	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	120	#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_I2C1_RX) /!< Remap I2C1 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	121	#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_SPI1_TX) /!< Remap SPI1 Tx on DMA1 channel 3 /
jhon309	0:88e313c910d0	122	#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM1_CH2) /!< Remap TIM1 channel 2 on DMA1 channel 3 /
jhon309	0:88e313c910d0	123	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	124	#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM2_CH2) /!< Remap TIM2 channel 2 on DMA1 channel 3 /
jhon309	0:88e313c910d0	125	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	126	#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 3 /
jhon309	0:88e313c910d0	127	#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 3 /
jhon309	0:88e313c910d0	128	#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	129	#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	130	#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	131	#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	132	#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	133	#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	134	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	135	#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	136	#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 3 /
jhon309	0:88e313c910d0	137	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	138
jhon309	0:88e313c910d0	139	/* DMA1 - Channel 4 */
jhon309	0:88e313c910d0	140	#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	141	#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM7_UP) /!< Remap TIM7 up on DMA1 channel 4 /
jhon309	0:88e313c910d0	142	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	143	#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_DAC_CH2) /!< Remap DAC Channel 2 on DMA1 channel 4 /
jhon309	0:88e313c910d0	144	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	145	#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_I2C2_TX) /!< Remap I2C2 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	146	#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_SPI2_RX) /!< Remap SPI2 Rx on DMA1 channel 4 /
jhon309	0:88e313c910d0	147	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	148	#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM2_CH4) /!< Remap TIM2 channel 4 on DMA1 channel 4 /
jhon309	0:88e313c910d0	149	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	150	#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM3_CH1) /!< Remap TIM3 channel 1 on DMA1 channel 4 /
jhon309	0:88e313c910d0	151	#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM3_TRIG) /!< Remap TIM3 Trig on DMA1 channel 4 /
jhon309	0:88e313c910d0	152	#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 4 /
jhon309	0:88e313c910d0	153	#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 4 /
jhon309	0:88e313c910d0	154	#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	155	#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	156	#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	157	#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	158	#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	159	#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	160	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	161	#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	162	#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 4 /
jhon309	0:88e313c910d0	163	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	164
jhon309	0:88e313c910d0	165	/* DMA1 - Channel 5 */
jhon309	0:88e313c910d0	166	#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	167	#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_I2C2_RX) /!< Remap I2C2 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	168	#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_SPI2_TX) /!< Remap SPI1 Tx on DMA1 channel 5 /
jhon309	0:88e313c910d0	169	#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_TIM1_CH3) /!< Remap TIM1 channel 3 on DMA1 channel 5 /
jhon309	0:88e313c910d0	170	#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	171	#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	172	#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	173	#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	174	#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	175	#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	176	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	177	#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	178	#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 5 /
jhon309	0:88e313c910d0	179	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	180
jhon309	0:88e313c910d0	181	#if !defined(STM32F030xC)
jhon309	0:88e313c910d0	182	/* DMA1 - Channel 6 */
jhon309	0:88e313c910d0	183	#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	184	#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_I2C1_TX) /!< Remap I2C1 Tx on DMA1 channel 6 /
jhon309	0:88e313c910d0	185	#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_SPI2_RX) /!< Remap SPI2 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	186	#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH1) /!< Remap TIM1 channel 1 on DMA1 channel 6 /
jhon309	0:88e313c910d0	187	#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH2) /!< Remap TIM1 channel 2 on DMA1 channel 6 /
jhon309	0:88e313c910d0	188	#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH3) /!< Remap TIM1 channel 3 on DMA1 channel 6 /
jhon309	0:88e313c910d0	189	#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM3_CH1) /!< Remap TIM3 channel 1 on DMA1 channel 6 /
jhon309	0:88e313c910d0	190	#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM3_TRIG) /!< Remap TIM3 Trig on DMA1 channel 6 /
jhon309	0:88e313c910d0	191	#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 6 /
jhon309	0:88e313c910d0	192	#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 6 /
jhon309	0:88e313c910d0	193	#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	194	#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	195	#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	196	#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	197	#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	198	#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	199	#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	200	#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 6 /
jhon309	0:88e313c910d0	201	/* DMA1 - Channel 7 */
jhon309	0:88e313c910d0	202	#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:88e313c910d0	203	#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_I2C1_RX) /!< Remap I2C1 Rx on DMA1 channel 7 /
jhon309	0:88e313c910d0	204	#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_SPI2_TX) /!< Remap SPI2 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	205	#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM2_CH2) /!< Remap TIM2 channel 2 on DMA1 channel 7 /
jhon309	0:88e313c910d0	206	#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM2_CH4) /!< Remap TIM2 channel 4 on DMA1 channel 7 /
jhon309	0:88e313c910d0	207	#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 7 /
jhon309	0:88e313c910d0	208	#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 7 /
jhon309	0:88e313c910d0	209	#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	210	#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	211	#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	212	#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	213	#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	214	#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	215	#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	216	#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 7 /
jhon309	0:88e313c910d0	217
jhon309	0:88e313c910d0	218	/**************** DMA2 remap bit field definition******************/
jhon309	0:88e313c910d0	219	/* DMA2 - Channel 1 */
jhon309	0:88e313c910d0	220	#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:88e313c910d0	221	#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_I2C2_TX) /!< Remap I2C2 TX on DMA2 channel 1 /
jhon309	0:88e313c910d0	222	#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	223	#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	224	#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	225	#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	226	#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	227	#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	228	#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	229	#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 1 /
jhon309	0:88e313c910d0	230	/* DMA2 - Channel 2 */
jhon309	0:88e313c910d0	231	#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:88e313c910d0	232	#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_I2C2_RX) /!< Remap I2C2 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	233	#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART1_RX) /!< Remap USART1 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	234	#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART2_RX) /!< Remap USART2 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	235	#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART3_RX) /!< Remap USART3 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	236	#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART4_RX) /!< Remap USART4 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	237	#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART5_RX) /!< Remap USART5 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	238	#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART6_RX) /!< Remap USART6 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	239	#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART7_RX) /!< Remap USART7 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	240	#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART8_RX) /!< Remap USART8 Rx on DMA2 channel 2 /
jhon309	0:88e313c910d0	241	/* DMA2 - Channel 3 */
jhon309	0:88e313c910d0	242	#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:88e313c910d0	243	#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_TIM6_UP) /!< Remap TIM6 up on DMA2 channel 3 /
jhon309	0:88e313c910d0	244	#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_DAC_CH1) /!< Remap DAC channel 1 on DMA2 channel 3 /
jhon309	0:88e313c910d0	245	#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_SPI1_RX) /!< Remap SPI1 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	246	#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART1_RX) /!< Remap USART1 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	247	#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART2_RX) /!< Remap USART2 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	248	#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART3_RX) /!< Remap USART3 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	249	#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART4_RX) /!< Remap USART4 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	250	#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART5_RX) /!< Remap USART5 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	251	#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART6_RX) /!< Remap USART6 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	252	#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART7_RX) /!< Remap USART7 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	253	#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART8_RX) /!< Remap USART8 Rx on DMA2 channel 3 /
jhon309	0:88e313c910d0	254	/* DMA2 - Channel 4 */
jhon309	0:88e313c910d0	255	#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:88e313c910d0	256	#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_TIM7_UP) /!< Remap TIM7 up on DMA2 channel 4 /
jhon309	0:88e313c910d0	257	#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_DAC_CH2) /!< Remap DAC channel 2 on DMA2 channel 4 /
jhon309	0:88e313c910d0	258	#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_SPI1_TX) /!< Remap SPI1 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	259	#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	260	#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	261	#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	262	#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	263	#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	264	#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	265	#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	266	#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 4 /
jhon309	0:88e313c910d0	267	/* DMA2 - Channel 5 */
jhon309	0:88e313c910d0	268	#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:88e313c910d0	269	#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_ADC) /!< Remap ADC on DMA2 channel 5 /
jhon309	0:88e313c910d0	270	#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	271	#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	272	#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	273	#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	274	#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	275	#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	276	#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	277	#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 5 /
jhon309	0:88e313c910d0	278	#endif /* !defined(STM32F030xC) */
jhon309	0:88e313c910d0	279
jhon309	0:88e313c910d0	280	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	281	#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) \|\|\
jhon309	0:88e313c910d0	282	((REQUEST) == HAL_DMA1_CH1_ADC) \|\|\
jhon309	0:88e313c910d0	283	((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) \|\|\
jhon309	0:88e313c910d0	284	((REQUEST) == HAL_DMA1_CH1_TIM17_UP) \|\|\
jhon309	0:88e313c910d0	285	((REQUEST) == HAL_DMA1_CH1_USART1_RX) \|\|\
jhon309	0:88e313c910d0	286	((REQUEST) == HAL_DMA1_CH1_USART2_RX) \|\|\
jhon309	0:88e313c910d0	287	((REQUEST) == HAL_DMA1_CH1_USART3_RX) \|\|\
jhon309	0:88e313c910d0	288	((REQUEST) == HAL_DMA1_CH1_USART4_RX) \|\|\
jhon309	0:88e313c910d0	289	((REQUEST) == HAL_DMA1_CH1_USART5_RX) \|\|\
jhon309	0:88e313c910d0	290	((REQUEST) == HAL_DMA1_CH1_USART6_RX) \|\|\
jhon309	0:88e313c910d0	291	((REQUEST) == HAL_DMA1_CH1_USART7_RX) \|\|\
jhon309	0:88e313c910d0	292	((REQUEST) == HAL_DMA1_CH1_USART8_RX) \|\|\
jhon309	0:88e313c910d0	293	((REQUEST) == HAL_DMA1_CH2_DEFAULT) \|\|\
jhon309	0:88e313c910d0	294	((REQUEST) == HAL_DMA1_CH2_ADC) \|\|\
jhon309	0:88e313c910d0	295	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:88e313c910d0	296	((REQUEST) == HAL_DMA1_CH2_SPI1_RX) \|\|\
jhon309	0:88e313c910d0	297	((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) \|\|\
jhon309	0:88e313c910d0	298	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:88e313c910d0	299	((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) \|\|\
jhon309	0:88e313c910d0	300	((REQUEST) == HAL_DMA1_CH2_TIM17_UP) \|\|\
jhon309	0:88e313c910d0	301	((REQUEST) == HAL_DMA1_CH2_USART1_TX) \|\|\
jhon309	0:88e313c910d0	302	((REQUEST) == HAL_DMA1_CH2_USART2_TX) \|\|\
jhon309	0:88e313c910d0	303	((REQUEST) == HAL_DMA1_CH2_USART3_TX) \|\|\
jhon309	0:88e313c910d0	304	((REQUEST) == HAL_DMA1_CH2_USART4_TX) \|\|\
jhon309	0:88e313c910d0	305	((REQUEST) == HAL_DMA1_CH2_USART5_TX) \|\|\
jhon309	0:88e313c910d0	306	((REQUEST) == HAL_DMA1_CH2_USART6_TX) \|\|\
jhon309	0:88e313c910d0	307	((REQUEST) == HAL_DMA1_CH2_USART7_TX) \|\|\
jhon309	0:88e313c910d0	308	((REQUEST) == HAL_DMA1_CH2_USART8_TX) \|\|\
jhon309	0:88e313c910d0	309	((REQUEST) == HAL_DMA1_CH3_DEFAULT) \|\|\
jhon309	0:88e313c910d0	310	((REQUEST) == HAL_DMA1_CH3_TIM6_UP) \|\|\
jhon309	0:88e313c910d0	311	((REQUEST) == HAL_DMA1_CH3_DAC_CH1) \|\|\
jhon309	0:88e313c910d0	312	((REQUEST) == HAL_DMA1_CH3_I2C1_RX) \|\|\
jhon309	0:88e313c910d0	313	((REQUEST) == HAL_DMA1_CH3_SPI1_TX) \|\|\
jhon309	0:88e313c910d0	314	((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) \|\|\
jhon309	0:88e313c910d0	315	((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) \|\|\
jhon309	0:88e313c910d0	316	((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) \|\|\
jhon309	0:88e313c910d0	317	((REQUEST) == HAL_DMA1_CH3_TIM16_UP) \|\|\
jhon309	0:88e313c910d0	318	((REQUEST) == HAL_DMA1_CH3_USART1_RX) \|\|\
jhon309	0:88e313c910d0	319	((REQUEST) == HAL_DMA1_CH3_USART2_RX) \|\|\
jhon309	0:88e313c910d0	320	((REQUEST) == HAL_DMA1_CH3_USART3_RX) \|\|\
jhon309	0:88e313c910d0	321	((REQUEST) == HAL_DMA1_CH3_USART4_RX) \|\|\
jhon309	0:88e313c910d0	322	((REQUEST) == HAL_DMA1_CH3_USART5_RX) \|\|\
jhon309	0:88e313c910d0	323	((REQUEST) == HAL_DMA1_CH3_USART6_RX) \|\|\
jhon309	0:88e313c910d0	324	((REQUEST) == HAL_DMA1_CH3_USART7_RX) \|\|\
jhon309	0:88e313c910d0	325	((REQUEST) == HAL_DMA1_CH3_USART8_RX) \|\|\
jhon309	0:88e313c910d0	326	((REQUEST) == HAL_DMA1_CH4_DEFAULT) \|\|\
jhon309	0:88e313c910d0	327	((REQUEST) == HAL_DMA1_CH4_TIM7_UP) \|\|\
jhon309	0:88e313c910d0	328	((REQUEST) == HAL_DMA1_CH4_DAC_CH2) \|\|\
jhon309	0:88e313c910d0	329	((REQUEST) == HAL_DMA1_CH4_I2C2_TX) \|\|\
jhon309	0:88e313c910d0	330	((REQUEST) == HAL_DMA1_CH4_SPI2_RX) \|\|\
jhon309	0:88e313c910d0	331	((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) \|\|\
jhon309	0:88e313c910d0	332	((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) \|\|\
jhon309	0:88e313c910d0	333	((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) \|\|\
jhon309	0:88e313c910d0	334	((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) \|\|\
jhon309	0:88e313c910d0	335	((REQUEST) == HAL_DMA1_CH4_TIM16_UP) \|\|\
jhon309	0:88e313c910d0	336	((REQUEST) == HAL_DMA1_CH4_USART1_TX) \|\|\
jhon309	0:88e313c910d0	337	((REQUEST) == HAL_DMA1_CH4_USART2_TX) \|\|\
jhon309	0:88e313c910d0	338	((REQUEST) == HAL_DMA1_CH4_USART3_TX) \|\|\
jhon309	0:88e313c910d0	339	((REQUEST) == HAL_DMA1_CH4_USART4_TX) \|\|\
jhon309	0:88e313c910d0	340	((REQUEST) == HAL_DMA1_CH4_USART5_TX) \|\|\
jhon309	0:88e313c910d0	341	((REQUEST) == HAL_DMA1_CH4_USART6_TX) \|\|\
jhon309	0:88e313c910d0	342	((REQUEST) == HAL_DMA1_CH4_USART7_TX) \|\|\
jhon309	0:88e313c910d0	343	((REQUEST) == HAL_DMA1_CH4_USART8_TX) \|\|\
jhon309	0:88e313c910d0	344	((REQUEST) == HAL_DMA1_CH5_DEFAULT) \|\|\
jhon309	0:88e313c910d0	345	((REQUEST) == HAL_DMA1_CH5_I2C2_RX) \|\|\
jhon309	0:88e313c910d0	346	((REQUEST) == HAL_DMA1_CH5_SPI2_TX) \|\|\
jhon309	0:88e313c910d0	347	((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) \|\|\
jhon309	0:88e313c910d0	348	((REQUEST) == HAL_DMA1_CH5_USART1_RX) \|\|\
jhon309	0:88e313c910d0	349	((REQUEST) == HAL_DMA1_CH5_USART2_RX) \|\|\
jhon309	0:88e313c910d0	350	((REQUEST) == HAL_DMA1_CH5_USART3_RX) \|\|\
jhon309	0:88e313c910d0	351	((REQUEST) == HAL_DMA1_CH5_USART4_RX) \|\|\
jhon309	0:88e313c910d0	352	((REQUEST) == HAL_DMA1_CH5_USART5_RX) \|\|\
jhon309	0:88e313c910d0	353	((REQUEST) == HAL_DMA1_CH5_USART6_RX) \|\|\
jhon309	0:88e313c910d0	354	((REQUEST) == HAL_DMA1_CH5_USART7_RX) \|\|\
jhon309	0:88e313c910d0	355	((REQUEST) == HAL_DMA1_CH5_USART8_RX) \|\|\
jhon309	0:88e313c910d0	356	((REQUEST) == HAL_DMA1_CH6_DEFAULT) \|\|\
jhon309	0:88e313c910d0	357	((REQUEST) == HAL_DMA1_CH6_I2C1_TX) \|\|\
jhon309	0:88e313c910d0	358	((REQUEST) == HAL_DMA1_CH6_SPI2_RX) \|\|\
jhon309	0:88e313c910d0	359	((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) \|\|\
jhon309	0:88e313c910d0	360	((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) \|\|\
jhon309	0:88e313c910d0	361	((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) \|\|\
jhon309	0:88e313c910d0	362	((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) \|\|\
jhon309	0:88e313c910d0	363	((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) \|\|\
jhon309	0:88e313c910d0	364	((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) \|\|\
jhon309	0:88e313c910d0	365	((REQUEST) == HAL_DMA1_CH6_TIM16_UP) \|\|\
jhon309	0:88e313c910d0	366	((REQUEST) == HAL_DMA1_CH6_USART1_RX) \|\|\
jhon309	0:88e313c910d0	367	((REQUEST) == HAL_DMA1_CH6_USART2_RX) \|\|\
jhon309	0:88e313c910d0	368	((REQUEST) == HAL_DMA1_CH6_USART3_RX) \|\|\
jhon309	0:88e313c910d0	369	((REQUEST) == HAL_DMA1_CH6_USART4_RX) \|\|\
jhon309	0:88e313c910d0	370	((REQUEST) == HAL_DMA1_CH6_USART5_RX) \|\|\
jhon309	0:88e313c910d0	371	((REQUEST) == HAL_DMA1_CH6_USART6_RX) \|\|\
jhon309	0:88e313c910d0	372	((REQUEST) == HAL_DMA1_CH6_USART7_RX) \|\|\
jhon309	0:88e313c910d0	373	((REQUEST) == HAL_DMA1_CH6_USART8_RX) \|\|\
jhon309	0:88e313c910d0	374	((REQUEST) == HAL_DMA1_CH7_DEFAULT) \|\|\
jhon309	0:88e313c910d0	375	((REQUEST) == HAL_DMA1_CH7_I2C1_RX) \|\|\
jhon309	0:88e313c910d0	376	((REQUEST) == HAL_DMA1_CH7_SPI2_TX) \|\|\
jhon309	0:88e313c910d0	377	((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) \|\|\
jhon309	0:88e313c910d0	378	((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) \|\|\
jhon309	0:88e313c910d0	379	((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) \|\|\
jhon309	0:88e313c910d0	380	((REQUEST) == HAL_DMA1_CH7_TIM17_UP) \|\|\
jhon309	0:88e313c910d0	381	((REQUEST) == HAL_DMA1_CH7_USART1_TX) \|\|\
jhon309	0:88e313c910d0	382	((REQUEST) == HAL_DMA1_CH7_USART2_TX) \|\|\
jhon309	0:88e313c910d0	383	((REQUEST) == HAL_DMA1_CH7_USART3_TX) \|\|\
jhon309	0:88e313c910d0	384	((REQUEST) == HAL_DMA1_CH7_USART4_TX) \|\|\
jhon309	0:88e313c910d0	385	((REQUEST) == HAL_DMA1_CH7_USART5_TX) \|\|\
jhon309	0:88e313c910d0	386	((REQUEST) == HAL_DMA1_CH7_USART6_TX) \|\|\
jhon309	0:88e313c910d0	387	((REQUEST) == HAL_DMA1_CH7_USART7_TX) \|\|\
jhon309	0:88e313c910d0	388	((REQUEST) == HAL_DMA1_CH7_USART8_TX))
jhon309	0:88e313c910d0	389
jhon309	0:88e313c910d0	390	#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) \|\|\
jhon309	0:88e313c910d0	391	((REQUEST) == HAL_DMA2_CH1_I2C2_TX) \|\|\
jhon309	0:88e313c910d0	392	((REQUEST) == HAL_DMA2_CH1_USART1_TX) \|\|\
jhon309	0:88e313c910d0	393	((REQUEST) == HAL_DMA2_CH1_USART2_TX) \|\|\
jhon309	0:88e313c910d0	394	((REQUEST) == HAL_DMA2_CH1_USART3_TX) \|\|\
jhon309	0:88e313c910d0	395	((REQUEST) == HAL_DMA2_CH1_USART4_TX) \|\|\
jhon309	0:88e313c910d0	396	((REQUEST) == HAL_DMA2_CH1_USART5_TX) \|\|\
jhon309	0:88e313c910d0	397	((REQUEST) == HAL_DMA2_CH1_USART6_TX) \|\|\
jhon309	0:88e313c910d0	398	((REQUEST) == HAL_DMA2_CH1_USART7_TX) \|\|\
jhon309	0:88e313c910d0	399	((REQUEST) == HAL_DMA2_CH1_USART8_TX) \|\|\
jhon309	0:88e313c910d0	400	((REQUEST) == HAL_DMA2_CH2_DEFAULT) \|\|\
jhon309	0:88e313c910d0	401	((REQUEST) == HAL_DMA2_CH2_I2C2_RX) \|\|\
jhon309	0:88e313c910d0	402	((REQUEST) == HAL_DMA2_CH2_USART1_RX) \|\|\
jhon309	0:88e313c910d0	403	((REQUEST) == HAL_DMA2_CH2_USART2_RX) \|\|\
jhon309	0:88e313c910d0	404	((REQUEST) == HAL_DMA2_CH2_USART3_RX) \|\|\
jhon309	0:88e313c910d0	405	((REQUEST) == HAL_DMA2_CH2_USART4_RX) \|\|\
jhon309	0:88e313c910d0	406	((REQUEST) == HAL_DMA2_CH2_USART5_RX) \|\|\
jhon309	0:88e313c910d0	407	((REQUEST) == HAL_DMA2_CH2_USART6_RX) \|\|\
jhon309	0:88e313c910d0	408	((REQUEST) == HAL_DMA2_CH2_USART7_RX) \|\|\
jhon309	0:88e313c910d0	409	((REQUEST) == HAL_DMA2_CH2_USART8_RX) \|\|\
jhon309	0:88e313c910d0	410	((REQUEST) == HAL_DMA2_CH3_DEFAULT) \|\|\
jhon309	0:88e313c910d0	411	((REQUEST) == HAL_DMA2_CH3_TIM6_UP) \|\|\
jhon309	0:88e313c910d0	412	((REQUEST) == HAL_DMA2_CH3_DAC_CH1) \|\|\
jhon309	0:88e313c910d0	413	((REQUEST) == HAL_DMA2_CH3_SPI1_RX) \|\|\
jhon309	0:88e313c910d0	414	((REQUEST) == HAL_DMA2_CH3_USART1_RX) \|\|\
jhon309	0:88e313c910d0	415	((REQUEST) == HAL_DMA2_CH3_USART2_RX) \|\|\
jhon309	0:88e313c910d0	416	((REQUEST) == HAL_DMA2_CH3_USART3_RX) \|\|\
jhon309	0:88e313c910d0	417	((REQUEST) == HAL_DMA2_CH3_USART4_RX) \|\|\
jhon309	0:88e313c910d0	418	((REQUEST) == HAL_DMA2_CH3_USART5_RX) \|\|\
jhon309	0:88e313c910d0	419	((REQUEST) == HAL_DMA2_CH3_USART6_RX) \|\|\
jhon309	0:88e313c910d0	420	((REQUEST) == HAL_DMA2_CH3_USART7_RX) \|\|\
jhon309	0:88e313c910d0	421	((REQUEST) == HAL_DMA2_CH3_USART8_RX) \|\|\
jhon309	0:88e313c910d0	422	((REQUEST) == HAL_DMA2_CH4_DEFAULT) \|\|\
jhon309	0:88e313c910d0	423	((REQUEST) == HAL_DMA2_CH4_TIM7_UP) \|\|\
jhon309	0:88e313c910d0	424	((REQUEST) == HAL_DMA2_CH4_DAC_CH2) \|\|\
jhon309	0:88e313c910d0	425	((REQUEST) == HAL_DMA2_CH4_SPI1_TX) \|\|\
jhon309	0:88e313c910d0	426	((REQUEST) == HAL_DMA2_CH4_USART1_TX) \|\|\
jhon309	0:88e313c910d0	427	((REQUEST) == HAL_DMA2_CH4_USART2_TX) \|\|\
jhon309	0:88e313c910d0	428	((REQUEST) == HAL_DMA2_CH4_USART3_TX) \|\|\
jhon309	0:88e313c910d0	429	((REQUEST) == HAL_DMA2_CH4_USART4_TX) \|\|\
jhon309	0:88e313c910d0	430	((REQUEST) == HAL_DMA2_CH4_USART5_TX) \|\|\
jhon309	0:88e313c910d0	431	((REQUEST) == HAL_DMA2_CH4_USART6_TX) \|\|\
jhon309	0:88e313c910d0	432	((REQUEST) == HAL_DMA2_CH4_USART7_TX) \|\|\
jhon309	0:88e313c910d0	433	((REQUEST) == HAL_DMA2_CH4_USART8_TX) \|\|\
jhon309	0:88e313c910d0	434	((REQUEST) == HAL_DMA2_CH5_DEFAULT) \|\|\
jhon309	0:88e313c910d0	435	((REQUEST) == HAL_DMA2_CH5_ADC) \|\|\
jhon309	0:88e313c910d0	436	((REQUEST) == HAL_DMA2_CH5_USART1_TX) \|\|\
jhon309	0:88e313c910d0	437	((REQUEST) == HAL_DMA2_CH5_USART2_TX) \|\|\
jhon309	0:88e313c910d0	438	((REQUEST) == HAL_DMA2_CH5_USART3_TX) \|\|\
jhon309	0:88e313c910d0	439	((REQUEST) == HAL_DMA2_CH5_USART4_TX) \|\|\
jhon309	0:88e313c910d0	440	((REQUEST) == HAL_DMA2_CH5_USART5_TX) \|\|\
jhon309	0:88e313c910d0	441	((REQUEST) == HAL_DMA2_CH5_USART6_TX) \|\|\
jhon309	0:88e313c910d0	442	((REQUEST) == HAL_DMA2_CH5_USART7_TX) \|\|\
jhon309	0:88e313c910d0	443	((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
jhon309	0:88e313c910d0	444	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	445
jhon309	0:88e313c910d0	446	#if defined(STM32F030xC)
jhon309	0:88e313c910d0	447	#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) \|\|\
jhon309	0:88e313c910d0	448	((REQUEST) == HAL_DMA1_CH1_ADC) \|\|\
jhon309	0:88e313c910d0	449	((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) \|\|\
jhon309	0:88e313c910d0	450	((REQUEST) == HAL_DMA1_CH1_TIM17_UP) \|\|\
jhon309	0:88e313c910d0	451	((REQUEST) == HAL_DMA1_CH1_USART1_RX) \|\|\
jhon309	0:88e313c910d0	452	((REQUEST) == HAL_DMA1_CH1_USART2_RX) \|\|\
jhon309	0:88e313c910d0	453	((REQUEST) == HAL_DMA1_CH1_USART3_RX) \|\|\
jhon309	0:88e313c910d0	454	((REQUEST) == HAL_DMA1_CH1_USART4_RX) \|\|\
jhon309	0:88e313c910d0	455	((REQUEST) == HAL_DMA1_CH1_USART5_RX) \|\|\
jhon309	0:88e313c910d0	456	((REQUEST) == HAL_DMA1_CH1_USART6_RX) \|\|\
jhon309	0:88e313c910d0	457	((REQUEST) == HAL_DMA1_CH2_DEFAULT) \|\|\
jhon309	0:88e313c910d0	458	((REQUEST) == HAL_DMA1_CH2_ADC) \|\|\
jhon309	0:88e313c910d0	459	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:88e313c910d0	460	((REQUEST) == HAL_DMA1_CH2_SPI1_RX) \|\|\
jhon309	0:88e313c910d0	461	((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) \|\|\
jhon309	0:88e313c910d0	462	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:88e313c910d0	463	((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) \|\|\
jhon309	0:88e313c910d0	464	((REQUEST) == HAL_DMA1_CH2_TIM17_UP) \|\|\
jhon309	0:88e313c910d0	465	((REQUEST) == HAL_DMA1_CH2_USART1_TX) \|\|\
jhon309	0:88e313c910d0	466	((REQUEST) == HAL_DMA1_CH2_USART2_TX) \|\|\
jhon309	0:88e313c910d0	467	((REQUEST) == HAL_DMA1_CH2_USART3_TX) \|\|\
jhon309	0:88e313c910d0	468	((REQUEST) == HAL_DMA1_CH2_USART4_TX) \|\|\
jhon309	0:88e313c910d0	469	((REQUEST) == HAL_DMA1_CH2_USART5_TX) \|\|\
jhon309	0:88e313c910d0	470	((REQUEST) == HAL_DMA1_CH2_USART6_TX) \|\|\
jhon309	0:88e313c910d0	471	((REQUEST) == HAL_DMA1_CH3_DEFAULT) \|\|\
jhon309	0:88e313c910d0	472	((REQUEST) == HAL_DMA1_CH3_TIM6_UP) \|\|\
jhon309	0:88e313c910d0	473	((REQUEST) == HAL_DMA1_CH3_I2C1_RX) \|\|\
jhon309	0:88e313c910d0	474	((REQUEST) == HAL_DMA1_CH3_SPI1_TX) \|\|\
jhon309	0:88e313c910d0	475	((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) \|\|\
jhon309	0:88e313c910d0	476	((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) \|\|\
jhon309	0:88e313c910d0	477	((REQUEST) == HAL_DMA1_CH3_TIM16_UP) \|\|\
jhon309	0:88e313c910d0	478	((REQUEST) == HAL_DMA1_CH3_USART1_RX) \|\|\
jhon309	0:88e313c910d0	479	((REQUEST) == HAL_DMA1_CH3_USART2_RX) \|\|\
jhon309	0:88e313c910d0	480	((REQUEST) == HAL_DMA1_CH3_USART3_RX) \|\|\
jhon309	0:88e313c910d0	481	((REQUEST) == HAL_DMA1_CH3_USART4_RX) \|\|\
jhon309	0:88e313c910d0	482	((REQUEST) == HAL_DMA1_CH3_USART5_RX) \|\|\
jhon309	0:88e313c910d0	483	((REQUEST) == HAL_DMA1_CH3_USART6_RX) \|\|\
jhon309	0:88e313c910d0	484	((REQUEST) == HAL_DMA1_CH4_DEFAULT) \|\|\
jhon309	0:88e313c910d0	485	((REQUEST) == HAL_DMA1_CH4_TIM7_UP) \|\|\
jhon309	0:88e313c910d0	486	((REQUEST) == HAL_DMA1_CH4_I2C2_TX) \|\|\
jhon309	0:88e313c910d0	487	((REQUEST) == HAL_DMA1_CH4_SPI2_RX) \|\|\
jhon309	0:88e313c910d0	488	((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) \|\|\
jhon309	0:88e313c910d0	489	((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) \|\|\
jhon309	0:88e313c910d0	490	((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) \|\|\
jhon309	0:88e313c910d0	491	((REQUEST) == HAL_DMA1_CH4_TIM16_UP) \|\|\
jhon309	0:88e313c910d0	492	((REQUEST) == HAL_DMA1_CH4_USART1_TX) \|\|\
jhon309	0:88e313c910d0	493	((REQUEST) == HAL_DMA1_CH4_USART2_TX) \|\|\
jhon309	0:88e313c910d0	494	((REQUEST) == HAL_DMA1_CH4_USART3_TX) \|\|\
jhon309	0:88e313c910d0	495	((REQUEST) == HAL_DMA1_CH4_USART4_TX) \|\|\
jhon309	0:88e313c910d0	496	((REQUEST) == HAL_DMA1_CH4_USART5_TX) \|\|\
jhon309	0:88e313c910d0	497	((REQUEST) == HAL_DMA1_CH4_USART6_TX) \|\|\
jhon309	0:88e313c910d0	498	((REQUEST) == HAL_DMA1_CH5_DEFAULT) \|\|\
jhon309	0:88e313c910d0	499	((REQUEST) == HAL_DMA1_CH5_I2C2_RX) \|\|\
jhon309	0:88e313c910d0	500	((REQUEST) == HAL_DMA1_CH5_SPI2_TX) \|\|\
jhon309	0:88e313c910d0	501	((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) \|\|\
jhon309	0:88e313c910d0	502	((REQUEST) == HAL_DMA1_CH5_USART1_RX) \|\|\
jhon309	0:88e313c910d0	503	((REQUEST) == HAL_DMA1_CH5_USART2_RX) \|\|\
jhon309	0:88e313c910d0	504	((REQUEST) == HAL_DMA1_CH5_USART3_RX) \|\|\
jhon309	0:88e313c910d0	505	((REQUEST) == HAL_DMA1_CH5_USART4_RX) \|\|\
jhon309	0:88e313c910d0	506	((REQUEST) == HAL_DMA1_CH5_USART5_RX) \|\|\
jhon309	0:88e313c910d0	507	((REQUEST) == HAL_DMA1_CH5_USART6_RX))
jhon309	0:88e313c910d0	508	#endif /* STM32F030xC */
jhon309	0:88e313c910d0	509
jhon309	0:88e313c910d0	510	/**
jhon309	0:88e313c910d0	511	* @}
jhon309	0:88e313c910d0	512	*/
jhon309	0:88e313c910d0	513	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	514
jhon309	0:88e313c910d0	515	/* Exported macros -----------------------------------------------------------*/
jhon309	0:88e313c910d0	516
jhon309	0:88e313c910d0	517	/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
jhon309	0:88e313c910d0	518	* @{
jhon309	0:88e313c910d0	519	*/
jhon309	0:88e313c910d0	520	/* Interrupt & Flag management */
jhon309	0:88e313c910d0	521
jhon309	0:88e313c910d0	522	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:88e313c910d0	523	/**
jhon309	0:88e313c910d0	524	* @brief Returns the current DMA Channel transfer complete flag.
jhon309	0:88e313c910d0	525	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	526	* @retval The specified transfer complete flag index.
jhon309	0:88e313c910d0	527	*/
jhon309	0:88e313c910d0	528	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
jhon309	0:88e313c910d0	529	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:88e313c910d0	530	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:88e313c910d0	531	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:88e313c910d0	532	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:88e313c910d0	533	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
jhon309	0:88e313c910d0	534	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
jhon309	0:88e313c910d0	535	DMA_FLAG_TC7)
jhon309	0:88e313c910d0	536
jhon309	0:88e313c910d0	537	/**
jhon309	0:88e313c910d0	538	* @brief Returns the current DMA Channel half transfer complete flag.
jhon309	0:88e313c910d0	539	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	540	* @retval The specified half transfer complete flag index.
jhon309	0:88e313c910d0	541	*/
jhon309	0:88e313c910d0	542	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
jhon309	0:88e313c910d0	543	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:88e313c910d0	544	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:88e313c910d0	545	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:88e313c910d0	546	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:88e313c910d0	547	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
jhon309	0:88e313c910d0	548	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
jhon309	0:88e313c910d0	549	DMA_FLAG_HT7)
jhon309	0:88e313c910d0	550
jhon309	0:88e313c910d0	551	/**
jhon309	0:88e313c910d0	552	* @brief Returns the current DMA Channel transfer error flag.
jhon309	0:88e313c910d0	553	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	554	* @retval The specified transfer error flag index.
jhon309	0:88e313c910d0	555	*/
jhon309	0:88e313c910d0	556	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
jhon309	0:88e313c910d0	557	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:88e313c910d0	558	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:88e313c910d0	559	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:88e313c910d0	560	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:88e313c910d0	561	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
jhon309	0:88e313c910d0	562	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
jhon309	0:88e313c910d0	563	DMA_FLAG_TE7)
jhon309	0:88e313c910d0	564
jhon309	0:88e313c910d0	565	/**
jhon309	0:88e313c910d0	566	* @brief Get the DMA Channel pending flags.
jhon309	0:88e313c910d0	567	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	568	* @param __FLAG__: Get the specified flag.
jhon309	0:88e313c910d0	569	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	570	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:88e313c910d0	571	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:88e313c910d0	572	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:88e313c910d0	573	* Where x can be 1_7 to select the DMA Channel flag.
jhon309	0:88e313c910d0	574	* @retval The state of FLAG (SET or RESET).
jhon309	0:88e313c910d0	575	*/
jhon309	0:88e313c910d0	576
jhon309	0:88e313c910d0	577	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
jhon309	0:88e313c910d0	578
jhon309	0:88e313c910d0	579	/**
jhon309	0:88e313c910d0	580	* @brief Clears the DMA Channel pending flags.
jhon309	0:88e313c910d0	581	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	582	* @param __FLAG__: specifies the flag to clear.
jhon309	0:88e313c910d0	583	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	584	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:88e313c910d0	585	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:88e313c910d0	586	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:88e313c910d0	587	* Where x can be 1_7 to select the DMA Channel flag.
jhon309	0:88e313c910d0	588	* @retval None
jhon309	0:88e313c910d0	589	*/
jhon309	0:88e313c910d0	590	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
jhon309	0:88e313c910d0	591
jhon309	0:88e313c910d0	592	#elif defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	593	/**
jhon309	0:88e313c910d0	594	* @brief Returns the current DMA Channel transfer complete flag.
jhon309	0:88e313c910d0	595	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	596	* @retval The specified transfer complete flag index.
jhon309	0:88e313c910d0	597	*/
jhon309	0:88e313c910d0	598	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
jhon309	0:88e313c910d0	599	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:88e313c910d0	600	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:88e313c910d0	601	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:88e313c910d0	602	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:88e313c910d0	603	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
jhon309	0:88e313c910d0	604	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
jhon309	0:88e313c910d0	605	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
jhon309	0:88e313c910d0	606	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:88e313c910d0	607	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:88e313c910d0	608	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:88e313c910d0	609	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:88e313c910d0	610	DMA_FLAG_TC5)
jhon309	0:88e313c910d0	611
jhon309	0:88e313c910d0	612	/**
jhon309	0:88e313c910d0	613	* @brief Returns the current DMA Channel half transfer complete flag.
jhon309	0:88e313c910d0	614	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	615	* @retval The specified half transfer complete flag index.
jhon309	0:88e313c910d0	616	*/
jhon309	0:88e313c910d0	617	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
jhon309	0:88e313c910d0	618	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:88e313c910d0	619	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:88e313c910d0	620	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:88e313c910d0	621	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:88e313c910d0	622	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
jhon309	0:88e313c910d0	623	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
jhon309	0:88e313c910d0	624	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
jhon309	0:88e313c910d0	625	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:88e313c910d0	626	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:88e313c910d0	627	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:88e313c910d0	628	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:88e313c910d0	629	DMA_FLAG_HT5)
jhon309	0:88e313c910d0	630
jhon309	0:88e313c910d0	631	/**
jhon309	0:88e313c910d0	632	* @brief Returns the current DMA Channel transfer error flag.
jhon309	0:88e313c910d0	633	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	634	* @retval The specified transfer error flag index.
jhon309	0:88e313c910d0	635	*/
jhon309	0:88e313c910d0	636	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
jhon309	0:88e313c910d0	637	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:88e313c910d0	638	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:88e313c910d0	639	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:88e313c910d0	640	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:88e313c910d0	641	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
jhon309	0:88e313c910d0	642	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
jhon309	0:88e313c910d0	643	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
jhon309	0:88e313c910d0	644	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:88e313c910d0	645	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:88e313c910d0	646	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:88e313c910d0	647	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:88e313c910d0	648	DMA_FLAG_TE5)
jhon309	0:88e313c910d0	649
jhon309	0:88e313c910d0	650	/**
jhon309	0:88e313c910d0	651	* @brief Get the DMA Channel pending flags.
jhon309	0:88e313c910d0	652	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	653	* @param __FLAG__: Get the specified flag.
jhon309	0:88e313c910d0	654	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	655	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:88e313c910d0	656	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:88e313c910d0	657	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:88e313c910d0	658	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
jhon309	0:88e313c910d0	659	* @retval The state of FLAG (SET or RESET).
jhon309	0:88e313c910d0	660	*/
jhon309	0:88e313c910d0	661
jhon309	0:88e313c910d0	662	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
jhon309	0:88e313c910d0	663	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
jhon309	0:88e313c910d0	664	(DMA1->ISR & (__FLAG__)))
jhon309	0:88e313c910d0	665
jhon309	0:88e313c910d0	666	/**
jhon309	0:88e313c910d0	667	* @brief Clears the DMA Channel pending flags.
jhon309	0:88e313c910d0	668	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	669	* @param __FLAG__: specifies the flag to clear.
jhon309	0:88e313c910d0	670	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	671	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:88e313c910d0	672	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:88e313c910d0	673	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:88e313c910d0	674	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
jhon309	0:88e313c910d0	675	* @retval None
jhon309	0:88e313c910d0	676	*/
jhon309	0:88e313c910d0	677	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
jhon309	0:88e313c910d0	678	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
jhon309	0:88e313c910d0	679	(DMA1->IFCR = (__FLAG__)))
jhon309	0:88e313c910d0	680
jhon309	0:88e313c910d0	681	#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
jhon309	0:88e313c910d0	682	/**
jhon309	0:88e313c910d0	683	* @brief Returns the current DMA Channel transfer complete flag.
jhon309	0:88e313c910d0	684	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	685	* @retval The specified transfer complete flag index.
jhon309	0:88e313c910d0	686	*/
jhon309	0:88e313c910d0	687	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
jhon309	0:88e313c910d0	688	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:88e313c910d0	689	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:88e313c910d0	690	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:88e313c910d0	691	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:88e313c910d0	692	DMA_FLAG_TC5)
jhon309	0:88e313c910d0	693
jhon309	0:88e313c910d0	694	/**
jhon309	0:88e313c910d0	695	* @brief Returns the current DMA Channel half transfer complete flag.
jhon309	0:88e313c910d0	696	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	697	* @retval The specified half transfer complete flag index.
jhon309	0:88e313c910d0	698	*/
jhon309	0:88e313c910d0	699	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
jhon309	0:88e313c910d0	700	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:88e313c910d0	701	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:88e313c910d0	702	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:88e313c910d0	703	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:88e313c910d0	704	DMA_FLAG_HT5)
jhon309	0:88e313c910d0	705
jhon309	0:88e313c910d0	706	/**
jhon309	0:88e313c910d0	707	* @brief Returns the current DMA Channel transfer error flag.
jhon309	0:88e313c910d0	708	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	709	* @retval The specified transfer error flag index.
jhon309	0:88e313c910d0	710	*/
jhon309	0:88e313c910d0	711	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
jhon309	0:88e313c910d0	712	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:88e313c910d0	713	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:88e313c910d0	714	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:88e313c910d0	715	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:88e313c910d0	716	DMA_FLAG_TE5)
jhon309	0:88e313c910d0	717
jhon309	0:88e313c910d0	718	/**
jhon309	0:88e313c910d0	719	* @brief Get the DMA Channel pending flags.
jhon309	0:88e313c910d0	720	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	721	* @param __FLAG__: Get the specified flag.
jhon309	0:88e313c910d0	722	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	723	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:88e313c910d0	724	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:88e313c910d0	725	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:88e313c910d0	726	* Where x can be 1_5 to select the DMA Channel flag.
jhon309	0:88e313c910d0	727	* @retval The state of FLAG (SET or RESET).
jhon309	0:88e313c910d0	728	*/
jhon309	0:88e313c910d0	729
jhon309	0:88e313c910d0	730	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
jhon309	0:88e313c910d0	731
jhon309	0:88e313c910d0	732	/**
jhon309	0:88e313c910d0	733	* @brief Clears the DMA Channel pending flags.
jhon309	0:88e313c910d0	734	* @param __HANDLE__: DMA handle
jhon309	0:88e313c910d0	735	* @param __FLAG__: specifies the flag to clear.
jhon309	0:88e313c910d0	736	* This parameter can be any combination of the following values:
jhon309	0:88e313c910d0	737	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:88e313c910d0	738	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:88e313c910d0	739	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:88e313c910d0	740	* Where x can be 1_5 to select the DMA Channel flag.
jhon309	0:88e313c910d0	741	* @retval None
jhon309	0:88e313c910d0	742	*/
jhon309	0:88e313c910d0	743	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
jhon309	0:88e313c910d0	744
jhon309	0:88e313c910d0	745	#endif
jhon309	0:88e313c910d0	746
jhon309	0:88e313c910d0	747
jhon309	0:88e313c910d0	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:88e313c910d0	749	#define __HAL_DMA1_REMAP(__REQUEST__) \
jhon309	0:88e313c910d0	750	do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
jhon309	0:88e313c910d0	751	DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
jhon309	0:88e313c910d0	752	DMA1->CSELR \|= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
jhon309	0:88e313c910d0	753	}while(0)
jhon309	0:88e313c910d0	754
jhon309	0:88e313c910d0	755	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:88e313c910d0	756	#define __HAL_DMA2_REMAP(__REQUEST__) \
jhon309	0:88e313c910d0	757	do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
jhon309	0:88e313c910d0	758	DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
jhon309	0:88e313c910d0	759	DMA2->CSELR \|= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
jhon309	0:88e313c910d0	760	}while(0)
jhon309	0:88e313c910d0	761	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:88e313c910d0	762
jhon309	0:88e313c910d0	763	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:88e313c910d0	764
jhon309	0:88e313c910d0	765	/**
jhon309	0:88e313c910d0	766	* @}
jhon309	0:88e313c910d0	767	*/
jhon309	0:88e313c910d0	768
jhon309	0:88e313c910d0	769	/**
jhon309	0:88e313c910d0	770	* @}
jhon309	0:88e313c910d0	771	*/
jhon309	0:88e313c910d0	772
jhon309	0:88e313c910d0	773	/**
jhon309	0:88e313c910d0	774	* @}
jhon309	0:88e313c910d0	775	*/
jhon309	0:88e313c910d0	776
jhon309	0:88e313c910d0	777	#ifdef __cplusplus
jhon309	0:88e313c910d0	778	}
jhon309	0:88e313c910d0	779	#endif
jhon309	0:88e313c910d0	780
jhon309	0:88e313c910d0	781	#endif /* __STM32F0xx_HAL_DMA_EX_H */
jhon309	0:88e313c910d0	782
jhon309	0:88e313c910d0	783	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	13 Aug 2015
Imports:	6
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma_ex.h@0:88e313c910d0, 2015-08-13 (annotated)

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