Jhon Plantikow / mbed

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Dependents:   RTC

TARGET_NUCLEO_F072RB/core_cm0plus.h@0:88e313c910d0, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:20:09 2015 +0000
Revision:
0:88e313c910d0
RTC Example

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jhon309 0:88e313c910d0 1 /**************************************************************************//**
jhon309 0:88e313c910d0 2 * @file core_cm0plus.h
jhon309 0:88e313c910d0 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
jhon309 0:88e313c910d0 4 * @version V3.20
jhon309 0:88e313c910d0 5 * @date 25. February 2013
jhon309 0:88e313c910d0 6 *
jhon309 0:88e313c910d0 7 * @note
jhon309 0:88e313c910d0 8 *
jhon309 0:88e313c910d0 9 ******************************************************************************/
jhon309 0:88e313c910d0 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:88e313c910d0 11
jhon309 0:88e313c910d0 12 All rights reserved.
jhon309 0:88e313c910d0 13 Redistribution and use in source and binary forms, with or without
jhon309 0:88e313c910d0 14 modification, are permitted provided that the following conditions are met:
jhon309 0:88e313c910d0 15 - Redistributions of source code must retain the above copyright
jhon309 0:88e313c910d0 16 notice, this list of conditions and the following disclaimer.
jhon309 0:88e313c910d0 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:88e313c910d0 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:88e313c910d0 19 documentation and/or other materials provided with the distribution.
jhon309 0:88e313c910d0 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:88e313c910d0 21 to endorse or promote products derived from this software without
jhon309 0:88e313c910d0 22 specific prior written permission.
jhon309 0:88e313c910d0 23 *
jhon309 0:88e313c910d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:88e313c910d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:88e313c910d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:88e313c910d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:88e313c910d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:88e313c910d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:88e313c910d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:88e313c910d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:88e313c910d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:88e313c910d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:88e313c910d0 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:88e313c910d0 35 ---------------------------------------------------------------------------*/
jhon309 0:88e313c910d0 36
jhon309 0:88e313c910d0 37
jhon309 0:88e313c910d0 38 #if defined ( __ICCARM__ )
jhon309 0:88e313c910d0 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:88e313c910d0 40 #endif
jhon309 0:88e313c910d0 41
jhon309 0:88e313c910d0 42 #ifdef __cplusplus
jhon309 0:88e313c910d0 43 extern "C" {
jhon309 0:88e313c910d0 44 #endif
jhon309 0:88e313c910d0 45
jhon309 0:88e313c910d0 46 #ifndef __CORE_CM0PLUS_H_GENERIC
jhon309 0:88e313c910d0 47 #define __CORE_CM0PLUS_H_GENERIC
jhon309 0:88e313c910d0 48
jhon309 0:88e313c910d0 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:88e313c910d0 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:88e313c910d0 51
jhon309 0:88e313c910d0 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:88e313c910d0 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:88e313c910d0 54
jhon309 0:88e313c910d0 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:88e313c910d0 56 Unions are used for effective representation of core registers.
jhon309 0:88e313c910d0 57
jhon309 0:88e313c910d0 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:88e313c910d0 59 Function-like macros are used to allow more efficient code.
jhon309 0:88e313c910d0 60 */
jhon309 0:88e313c910d0 61
jhon309 0:88e313c910d0 62
jhon309 0:88e313c910d0 63 /*******************************************************************************
jhon309 0:88e313c910d0 64 * CMSIS definitions
jhon309 0:88e313c910d0 65 ******************************************************************************/
jhon309 0:88e313c910d0 66 /** \ingroup Cortex-M0+
jhon309 0:88e313c910d0 67 @{
jhon309 0:88e313c910d0 68 */
jhon309 0:88e313c910d0 69
jhon309 0:88e313c910d0 70 /* CMSIS CM0P definitions */
jhon309 0:88e313c910d0 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jhon309 0:88e313c910d0 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:88e313c910d0 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:88e313c910d0 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
jhon309 0:88e313c910d0 75
jhon309 0:88e313c910d0 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
jhon309 0:88e313c910d0 77
jhon309 0:88e313c910d0 78
jhon309 0:88e313c910d0 79 #if defined ( __CC_ARM )
jhon309 0:88e313c910d0 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:88e313c910d0 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:88e313c910d0 82 #define __STATIC_INLINE static __inline
jhon309 0:88e313c910d0 83
jhon309 0:88e313c910d0 84 #elif defined ( __ICCARM__ )
jhon309 0:88e313c910d0 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:88e313c910d0 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:88e313c910d0 87 #define __STATIC_INLINE static inline
jhon309 0:88e313c910d0 88
jhon309 0:88e313c910d0 89 #elif defined ( __GNUC__ )
jhon309 0:88e313c910d0 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:88e313c910d0 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:88e313c910d0 92 #define __STATIC_INLINE static inline
jhon309 0:88e313c910d0 93
jhon309 0:88e313c910d0 94 #elif defined ( __TASKING__ )
jhon309 0:88e313c910d0 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:88e313c910d0 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:88e313c910d0 97 #define __STATIC_INLINE static inline
jhon309 0:88e313c910d0 98
jhon309 0:88e313c910d0 99 #endif
jhon309 0:88e313c910d0 100
jhon309 0:88e313c910d0 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jhon309 0:88e313c910d0 102 */
jhon309 0:88e313c910d0 103 #define __FPU_USED 0
jhon309 0:88e313c910d0 104
jhon309 0:88e313c910d0 105 #if defined ( __CC_ARM )
jhon309 0:88e313c910d0 106 #if defined __TARGET_FPU_VFP
jhon309 0:88e313c910d0 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:88e313c910d0 108 #endif
jhon309 0:88e313c910d0 109
jhon309 0:88e313c910d0 110 #elif defined ( __ICCARM__ )
jhon309 0:88e313c910d0 111 #if defined __ARMVFP__
jhon309 0:88e313c910d0 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:88e313c910d0 113 #endif
jhon309 0:88e313c910d0 114
jhon309 0:88e313c910d0 115 #elif defined ( __GNUC__ )
jhon309 0:88e313c910d0 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:88e313c910d0 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:88e313c910d0 118 #endif
jhon309 0:88e313c910d0 119
jhon309 0:88e313c910d0 120 #elif defined ( __TASKING__ )
jhon309 0:88e313c910d0 121 #if defined __FPU_VFP__
jhon309 0:88e313c910d0 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:88e313c910d0 123 #endif
jhon309 0:88e313c910d0 124 #endif
jhon309 0:88e313c910d0 125
jhon309 0:88e313c910d0 126 #include <stdint.h> /* standard types definitions */
jhon309 0:88e313c910d0 127 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:88e313c910d0 128 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:88e313c910d0 129
jhon309 0:88e313c910d0 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
jhon309 0:88e313c910d0 131
jhon309 0:88e313c910d0 132 #ifndef __CMSIS_GENERIC
jhon309 0:88e313c910d0 133
jhon309 0:88e313c910d0 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
jhon309 0:88e313c910d0 135 #define __CORE_CM0PLUS_H_DEPENDANT
jhon309 0:88e313c910d0 136
jhon309 0:88e313c910d0 137 /* check device defines and use defaults */
jhon309 0:88e313c910d0 138 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:88e313c910d0 139 #ifndef __CM0PLUS_REV
jhon309 0:88e313c910d0 140 #define __CM0PLUS_REV 0x0000
jhon309 0:88e313c910d0 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
jhon309 0:88e313c910d0 142 #endif
jhon309 0:88e313c910d0 143
jhon309 0:88e313c910d0 144 #ifndef __MPU_PRESENT
jhon309 0:88e313c910d0 145 #define __MPU_PRESENT 0
jhon309 0:88e313c910d0 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
jhon309 0:88e313c910d0 147 #endif
jhon309 0:88e313c910d0 148
jhon309 0:88e313c910d0 149 #ifndef __VTOR_PRESENT
jhon309 0:88e313c910d0 150 #define __VTOR_PRESENT 0
jhon309 0:88e313c910d0 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
jhon309 0:88e313c910d0 152 #endif
jhon309 0:88e313c910d0 153
jhon309 0:88e313c910d0 154 #ifndef __NVIC_PRIO_BITS
jhon309 0:88e313c910d0 155 #define __NVIC_PRIO_BITS 2
jhon309 0:88e313c910d0 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:88e313c910d0 157 #endif
jhon309 0:88e313c910d0 158
jhon309 0:88e313c910d0 159 #ifndef __Vendor_SysTickConfig
jhon309 0:88e313c910d0 160 #define __Vendor_SysTickConfig 0
jhon309 0:88e313c910d0 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:88e313c910d0 162 #endif
jhon309 0:88e313c910d0 163 #endif
jhon309 0:88e313c910d0 164
jhon309 0:88e313c910d0 165 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:88e313c910d0 166 /**
jhon309 0:88e313c910d0 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:88e313c910d0 168
jhon309 0:88e313c910d0 169 <strong>IO Type Qualifiers</strong> are used
jhon309 0:88e313c910d0 170 \li to specify the access to peripheral variables.
jhon309 0:88e313c910d0 171 \li for automatic generation of peripheral register debug information.
jhon309 0:88e313c910d0 172 */
jhon309 0:88e313c910d0 173 #ifdef __cplusplus
jhon309 0:88e313c910d0 174 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:88e313c910d0 175 #else
jhon309 0:88e313c910d0 176 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:88e313c910d0 177 #endif
jhon309 0:88e313c910d0 178 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:88e313c910d0 179 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:88e313c910d0 180
jhon309 0:88e313c910d0 181 /*@} end of group Cortex-M0+ */
jhon309 0:88e313c910d0 182
jhon309 0:88e313c910d0 183
jhon309 0:88e313c910d0 184
jhon309 0:88e313c910d0 185 /*******************************************************************************
jhon309 0:88e313c910d0 186 * Register Abstraction
jhon309 0:88e313c910d0 187 Core Register contain:
jhon309 0:88e313c910d0 188 - Core Register
jhon309 0:88e313c910d0 189 - Core NVIC Register
jhon309 0:88e313c910d0 190 - Core SCB Register
jhon309 0:88e313c910d0 191 - Core SysTick Register
jhon309 0:88e313c910d0 192 - Core MPU Register
jhon309 0:88e313c910d0 193 ******************************************************************************/
jhon309 0:88e313c910d0 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:88e313c910d0 195 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:88e313c910d0 196 */
jhon309 0:88e313c910d0 197
jhon309 0:88e313c910d0 198 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 199 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:88e313c910d0 200 \brief Core Register type definitions.
jhon309 0:88e313c910d0 201 @{
jhon309 0:88e313c910d0 202 */
jhon309 0:88e313c910d0 203
jhon309 0:88e313c910d0 204 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:88e313c910d0 205 */
jhon309 0:88e313c910d0 206 typedef union
jhon309 0:88e313c910d0 207 {
jhon309 0:88e313c910d0 208 struct
jhon309 0:88e313c910d0 209 {
jhon309 0:88e313c910d0 210 #if (__CORTEX_M != 0x04)
jhon309 0:88e313c910d0 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jhon309 0:88e313c910d0 212 #else
jhon309 0:88e313c910d0 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:88e313c910d0 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:88e313c910d0 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:88e313c910d0 216 #endif
jhon309 0:88e313c910d0 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:88e313c910d0 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:88e313c910d0 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:88e313c910d0 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:88e313c910d0 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:88e313c910d0 222 } b; /*!< Structure used for bit access */
jhon309 0:88e313c910d0 223 uint32_t w; /*!< Type used for word access */
jhon309 0:88e313c910d0 224 } APSR_Type;
jhon309 0:88e313c910d0 225
jhon309 0:88e313c910d0 226
jhon309 0:88e313c910d0 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:88e313c910d0 228 */
jhon309 0:88e313c910d0 229 typedef union
jhon309 0:88e313c910d0 230 {
jhon309 0:88e313c910d0 231 struct
jhon309 0:88e313c910d0 232 {
jhon309 0:88e313c910d0 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:88e313c910d0 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:88e313c910d0 235 } b; /*!< Structure used for bit access */
jhon309 0:88e313c910d0 236 uint32_t w; /*!< Type used for word access */
jhon309 0:88e313c910d0 237 } IPSR_Type;
jhon309 0:88e313c910d0 238
jhon309 0:88e313c910d0 239
jhon309 0:88e313c910d0 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:88e313c910d0 241 */
jhon309 0:88e313c910d0 242 typedef union
jhon309 0:88e313c910d0 243 {
jhon309 0:88e313c910d0 244 struct
jhon309 0:88e313c910d0 245 {
jhon309 0:88e313c910d0 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:88e313c910d0 247 #if (__CORTEX_M != 0x04)
jhon309 0:88e313c910d0 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jhon309 0:88e313c910d0 249 #else
jhon309 0:88e313c910d0 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:88e313c910d0 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:88e313c910d0 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:88e313c910d0 253 #endif
jhon309 0:88e313c910d0 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:88e313c910d0 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:88e313c910d0 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:88e313c910d0 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:88e313c910d0 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:88e313c910d0 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:88e313c910d0 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:88e313c910d0 261 } b; /*!< Structure used for bit access */
jhon309 0:88e313c910d0 262 uint32_t w; /*!< Type used for word access */
jhon309 0:88e313c910d0 263 } xPSR_Type;
jhon309 0:88e313c910d0 264
jhon309 0:88e313c910d0 265
jhon309 0:88e313c910d0 266 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:88e313c910d0 267 */
jhon309 0:88e313c910d0 268 typedef union
jhon309 0:88e313c910d0 269 {
jhon309 0:88e313c910d0 270 struct
jhon309 0:88e313c910d0 271 {
jhon309 0:88e313c910d0 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:88e313c910d0 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:88e313c910d0 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:88e313c910d0 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:88e313c910d0 276 } b; /*!< Structure used for bit access */
jhon309 0:88e313c910d0 277 uint32_t w; /*!< Type used for word access */
jhon309 0:88e313c910d0 278 } CONTROL_Type;
jhon309 0:88e313c910d0 279
jhon309 0:88e313c910d0 280 /*@} end of group CMSIS_CORE */
jhon309 0:88e313c910d0 281
jhon309 0:88e313c910d0 282
jhon309 0:88e313c910d0 283 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:88e313c910d0 285 \brief Type definitions for the NVIC Registers
jhon309 0:88e313c910d0 286 @{
jhon309 0:88e313c910d0 287 */
jhon309 0:88e313c910d0 288
jhon309 0:88e313c910d0 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:88e313c910d0 290 */
jhon309 0:88e313c910d0 291 typedef struct
jhon309 0:88e313c910d0 292 {
jhon309 0:88e313c910d0 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:88e313c910d0 294 uint32_t RESERVED0[31];
jhon309 0:88e313c910d0 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:88e313c910d0 296 uint32_t RSERVED1[31];
jhon309 0:88e313c910d0 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:88e313c910d0 298 uint32_t RESERVED2[31];
jhon309 0:88e313c910d0 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:88e313c910d0 300 uint32_t RESERVED3[31];
jhon309 0:88e313c910d0 301 uint32_t RESERVED4[64];
jhon309 0:88e313c910d0 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
jhon309 0:88e313c910d0 303 } NVIC_Type;
jhon309 0:88e313c910d0 304
jhon309 0:88e313c910d0 305 /*@} end of group CMSIS_NVIC */
jhon309 0:88e313c910d0 306
jhon309 0:88e313c910d0 307
jhon309 0:88e313c910d0 308 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 309 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:88e313c910d0 310 \brief Type definitions for the System Control Block Registers
jhon309 0:88e313c910d0 311 @{
jhon309 0:88e313c910d0 312 */
jhon309 0:88e313c910d0 313
jhon309 0:88e313c910d0 314 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:88e313c910d0 315 */
jhon309 0:88e313c910d0 316 typedef struct
jhon309 0:88e313c910d0 317 {
jhon309 0:88e313c910d0 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:88e313c910d0 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:88e313c910d0 320 #if (__VTOR_PRESENT == 1)
jhon309 0:88e313c910d0 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jhon309 0:88e313c910d0 322 #else
jhon309 0:88e313c910d0 323 uint32_t RESERVED0;
jhon309 0:88e313c910d0 324 #endif
jhon309 0:88e313c910d0 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:88e313c910d0 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:88e313c910d0 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:88e313c910d0 328 uint32_t RESERVED1;
jhon309 0:88e313c910d0 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
jhon309 0:88e313c910d0 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:88e313c910d0 331 } SCB_Type;
jhon309 0:88e313c910d0 332
jhon309 0:88e313c910d0 333 /* SCB CPUID Register Definitions */
jhon309 0:88e313c910d0 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:88e313c910d0 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:88e313c910d0 336
jhon309 0:88e313c910d0 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:88e313c910d0 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:88e313c910d0 339
jhon309 0:88e313c910d0 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:88e313c910d0 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:88e313c910d0 342
jhon309 0:88e313c910d0 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:88e313c910d0 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:88e313c910d0 345
jhon309 0:88e313c910d0 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:88e313c910d0 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jhon309 0:88e313c910d0 348
jhon309 0:88e313c910d0 349 /* SCB Interrupt Control State Register Definitions */
jhon309 0:88e313c910d0 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:88e313c910d0 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:88e313c910d0 352
jhon309 0:88e313c910d0 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:88e313c910d0 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:88e313c910d0 355
jhon309 0:88e313c910d0 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:88e313c910d0 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:88e313c910d0 358
jhon309 0:88e313c910d0 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:88e313c910d0 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:88e313c910d0 361
jhon309 0:88e313c910d0 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:88e313c910d0 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:88e313c910d0 364
jhon309 0:88e313c910d0 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:88e313c910d0 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:88e313c910d0 367
jhon309 0:88e313c910d0 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:88e313c910d0 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:88e313c910d0 370
jhon309 0:88e313c910d0 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:88e313c910d0 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:88e313c910d0 373
jhon309 0:88e313c910d0 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:88e313c910d0 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:88e313c910d0 376
jhon309 0:88e313c910d0 377 #if (__VTOR_PRESENT == 1)
jhon309 0:88e313c910d0 378 /* SCB Interrupt Control State Register Definitions */
jhon309 0:88e313c910d0 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
jhon309 0:88e313c910d0 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jhon309 0:88e313c910d0 381 #endif
jhon309 0:88e313c910d0 382
jhon309 0:88e313c910d0 383 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:88e313c910d0 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:88e313c910d0 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:88e313c910d0 386
jhon309 0:88e313c910d0 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:88e313c910d0 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:88e313c910d0 389
jhon309 0:88e313c910d0 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:88e313c910d0 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:88e313c910d0 392
jhon309 0:88e313c910d0 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:88e313c910d0 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:88e313c910d0 395
jhon309 0:88e313c910d0 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:88e313c910d0 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:88e313c910d0 398
jhon309 0:88e313c910d0 399 /* SCB System Control Register Definitions */
jhon309 0:88e313c910d0 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:88e313c910d0 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:88e313c910d0 402
jhon309 0:88e313c910d0 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:88e313c910d0 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:88e313c910d0 405
jhon309 0:88e313c910d0 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:88e313c910d0 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:88e313c910d0 408
jhon309 0:88e313c910d0 409 /* SCB Configuration Control Register Definitions */
jhon309 0:88e313c910d0 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:88e313c910d0 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:88e313c910d0 412
jhon309 0:88e313c910d0 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:88e313c910d0 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:88e313c910d0 415
jhon309 0:88e313c910d0 416 /* SCB System Handler Control and State Register Definitions */
jhon309 0:88e313c910d0 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:88e313c910d0 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:88e313c910d0 419
jhon309 0:88e313c910d0 420 /*@} end of group CMSIS_SCB */
jhon309 0:88e313c910d0 421
jhon309 0:88e313c910d0 422
jhon309 0:88e313c910d0 423 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:88e313c910d0 425 \brief Type definitions for the System Timer Registers.
jhon309 0:88e313c910d0 426 @{
jhon309 0:88e313c910d0 427 */
jhon309 0:88e313c910d0 428
jhon309 0:88e313c910d0 429 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:88e313c910d0 430 */
jhon309 0:88e313c910d0 431 typedef struct
jhon309 0:88e313c910d0 432 {
jhon309 0:88e313c910d0 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:88e313c910d0 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:88e313c910d0 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:88e313c910d0 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:88e313c910d0 437 } SysTick_Type;
jhon309 0:88e313c910d0 438
jhon309 0:88e313c910d0 439 /* SysTick Control / Status Register Definitions */
jhon309 0:88e313c910d0 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:88e313c910d0 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:88e313c910d0 442
jhon309 0:88e313c910d0 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:88e313c910d0 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:88e313c910d0 445
jhon309 0:88e313c910d0 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:88e313c910d0 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:88e313c910d0 448
jhon309 0:88e313c910d0 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:88e313c910d0 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:88e313c910d0 451
jhon309 0:88e313c910d0 452 /* SysTick Reload Register Definitions */
jhon309 0:88e313c910d0 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:88e313c910d0 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:88e313c910d0 455
jhon309 0:88e313c910d0 456 /* SysTick Current Register Definitions */
jhon309 0:88e313c910d0 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:88e313c910d0 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:88e313c910d0 459
jhon309 0:88e313c910d0 460 /* SysTick Calibration Register Definitions */
jhon309 0:88e313c910d0 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:88e313c910d0 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:88e313c910d0 463
jhon309 0:88e313c910d0 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:88e313c910d0 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:88e313c910d0 466
jhon309 0:88e313c910d0 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:88e313c910d0 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:88e313c910d0 469
jhon309 0:88e313c910d0 470 /*@} end of group CMSIS_SysTick */
jhon309 0:88e313c910d0 471
jhon309 0:88e313c910d0 472 #if (__MPU_PRESENT == 1)
jhon309 0:88e313c910d0 473 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jhon309 0:88e313c910d0 475 \brief Type definitions for the Memory Protection Unit (MPU)
jhon309 0:88e313c910d0 476 @{
jhon309 0:88e313c910d0 477 */
jhon309 0:88e313c910d0 478
jhon309 0:88e313c910d0 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
jhon309 0:88e313c910d0 480 */
jhon309 0:88e313c910d0 481 typedef struct
jhon309 0:88e313c910d0 482 {
jhon309 0:88e313c910d0 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jhon309 0:88e313c910d0 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jhon309 0:88e313c910d0 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jhon309 0:88e313c910d0 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jhon309 0:88e313c910d0 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jhon309 0:88e313c910d0 488 } MPU_Type;
jhon309 0:88e313c910d0 489
jhon309 0:88e313c910d0 490 /* MPU Type Register */
jhon309 0:88e313c910d0 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jhon309 0:88e313c910d0 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jhon309 0:88e313c910d0 493
jhon309 0:88e313c910d0 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jhon309 0:88e313c910d0 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jhon309 0:88e313c910d0 496
jhon309 0:88e313c910d0 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jhon309 0:88e313c910d0 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
jhon309 0:88e313c910d0 499
jhon309 0:88e313c910d0 500 /* MPU Control Register */
jhon309 0:88e313c910d0 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jhon309 0:88e313c910d0 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jhon309 0:88e313c910d0 503
jhon309 0:88e313c910d0 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jhon309 0:88e313c910d0 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jhon309 0:88e313c910d0 506
jhon309 0:88e313c910d0 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jhon309 0:88e313c910d0 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
jhon309 0:88e313c910d0 509
jhon309 0:88e313c910d0 510 /* MPU Region Number Register */
jhon309 0:88e313c910d0 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jhon309 0:88e313c910d0 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
jhon309 0:88e313c910d0 513
jhon309 0:88e313c910d0 514 /* MPU Region Base Address Register */
jhon309 0:88e313c910d0 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
jhon309 0:88e313c910d0 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jhon309 0:88e313c910d0 517
jhon309 0:88e313c910d0 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jhon309 0:88e313c910d0 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jhon309 0:88e313c910d0 520
jhon309 0:88e313c910d0 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jhon309 0:88e313c910d0 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
jhon309 0:88e313c910d0 523
jhon309 0:88e313c910d0 524 /* MPU Region Attribute and Size Register */
jhon309 0:88e313c910d0 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jhon309 0:88e313c910d0 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jhon309 0:88e313c910d0 527
jhon309 0:88e313c910d0 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jhon309 0:88e313c910d0 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jhon309 0:88e313c910d0 530
jhon309 0:88e313c910d0 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jhon309 0:88e313c910d0 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jhon309 0:88e313c910d0 533
jhon309 0:88e313c910d0 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jhon309 0:88e313c910d0 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jhon309 0:88e313c910d0 536
jhon309 0:88e313c910d0 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jhon309 0:88e313c910d0 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jhon309 0:88e313c910d0 539
jhon309 0:88e313c910d0 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jhon309 0:88e313c910d0 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jhon309 0:88e313c910d0 542
jhon309 0:88e313c910d0 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jhon309 0:88e313c910d0 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jhon309 0:88e313c910d0 545
jhon309 0:88e313c910d0 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jhon309 0:88e313c910d0 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jhon309 0:88e313c910d0 548
jhon309 0:88e313c910d0 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jhon309 0:88e313c910d0 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jhon309 0:88e313c910d0 551
jhon309 0:88e313c910d0 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jhon309 0:88e313c910d0 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
jhon309 0:88e313c910d0 554
jhon309 0:88e313c910d0 555 /*@} end of group CMSIS_MPU */
jhon309 0:88e313c910d0 556 #endif
jhon309 0:88e313c910d0 557
jhon309 0:88e313c910d0 558
jhon309 0:88e313c910d0 559 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:88e313c910d0 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
jhon309 0:88e313c910d0 562 are only accessible over DAP and not via processor. Therefore
jhon309 0:88e313c910d0 563 they are not covered by the Cortex-M0 header file.
jhon309 0:88e313c910d0 564 @{
jhon309 0:88e313c910d0 565 */
jhon309 0:88e313c910d0 566 /*@} end of group CMSIS_CoreDebug */
jhon309 0:88e313c910d0 567
jhon309 0:88e313c910d0 568
jhon309 0:88e313c910d0 569 /** \ingroup CMSIS_core_register
jhon309 0:88e313c910d0 570 \defgroup CMSIS_core_base Core Definitions
jhon309 0:88e313c910d0 571 \brief Definitions for base addresses, unions, and structures.
jhon309 0:88e313c910d0 572 @{
jhon309 0:88e313c910d0 573 */
jhon309 0:88e313c910d0 574
jhon309 0:88e313c910d0 575 /* Memory mapping of Cortex-M0+ Hardware */
jhon309 0:88e313c910d0 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:88e313c910d0 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:88e313c910d0 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:88e313c910d0 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:88e313c910d0 580
jhon309 0:88e313c910d0 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:88e313c910d0 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:88e313c910d0 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:88e313c910d0 584
jhon309 0:88e313c910d0 585 #if (__MPU_PRESENT == 1)
jhon309 0:88e313c910d0 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jhon309 0:88e313c910d0 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jhon309 0:88e313c910d0 588 #endif
jhon309 0:88e313c910d0 589
jhon309 0:88e313c910d0 590 /*@} */
jhon309 0:88e313c910d0 591
jhon309 0:88e313c910d0 592
jhon309 0:88e313c910d0 593
jhon309 0:88e313c910d0 594 /*******************************************************************************
jhon309 0:88e313c910d0 595 * Hardware Abstraction Layer
jhon309 0:88e313c910d0 596 Core Function Interface contains:
jhon309 0:88e313c910d0 597 - Core NVIC Functions
jhon309 0:88e313c910d0 598 - Core SysTick Functions
jhon309 0:88e313c910d0 599 - Core Register Access Functions
jhon309 0:88e313c910d0 600 ******************************************************************************/
jhon309 0:88e313c910d0 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:88e313c910d0 602 */
jhon309 0:88e313c910d0 603
jhon309 0:88e313c910d0 604
jhon309 0:88e313c910d0 605
jhon309 0:88e313c910d0 606 /* ########################## NVIC functions #################################### */
jhon309 0:88e313c910d0 607 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:88e313c910d0 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:88e313c910d0 609 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:88e313c910d0 610 @{
jhon309 0:88e313c910d0 611 */
jhon309 0:88e313c910d0 612
jhon309 0:88e313c910d0 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
jhon309 0:88e313c910d0 614 /* The following MACROS handle generation of the register offset and byte masks */
jhon309 0:88e313c910d0 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
jhon309 0:88e313c910d0 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
jhon309 0:88e313c910d0 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
jhon309 0:88e313c910d0 618
jhon309 0:88e313c910d0 619
jhon309 0:88e313c910d0 620 /** \brief Enable External Interrupt
jhon309 0:88e313c910d0 621
jhon309 0:88e313c910d0 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:88e313c910d0 623
jhon309 0:88e313c910d0 624 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:88e313c910d0 625 */
jhon309 0:88e313c910d0 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:88e313c910d0 627 {
jhon309 0:88e313c910d0 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:88e313c910d0 629 }
jhon309 0:88e313c910d0 630
jhon309 0:88e313c910d0 631
jhon309 0:88e313c910d0 632 /** \brief Disable External Interrupt
jhon309 0:88e313c910d0 633
jhon309 0:88e313c910d0 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:88e313c910d0 635
jhon309 0:88e313c910d0 636 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:88e313c910d0 637 */
jhon309 0:88e313c910d0 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:88e313c910d0 639 {
jhon309 0:88e313c910d0 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:88e313c910d0 641 }
jhon309 0:88e313c910d0 642
jhon309 0:88e313c910d0 643
jhon309 0:88e313c910d0 644 /** \brief Get Pending Interrupt
jhon309 0:88e313c910d0 645
jhon309 0:88e313c910d0 646 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:88e313c910d0 647 for the specified interrupt.
jhon309 0:88e313c910d0 648
jhon309 0:88e313c910d0 649 \param [in] IRQn Interrupt number.
jhon309 0:88e313c910d0 650
jhon309 0:88e313c910d0 651 \return 0 Interrupt status is not pending.
jhon309 0:88e313c910d0 652 \return 1 Interrupt status is pending.
jhon309 0:88e313c910d0 653 */
jhon309 0:88e313c910d0 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:88e313c910d0 655 {
jhon309 0:88e313c910d0 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
jhon309 0:88e313c910d0 657 }
jhon309 0:88e313c910d0 658
jhon309 0:88e313c910d0 659
jhon309 0:88e313c910d0 660 /** \brief Set Pending Interrupt
jhon309 0:88e313c910d0 661
jhon309 0:88e313c910d0 662 The function sets the pending bit of an external interrupt.
jhon309 0:88e313c910d0 663
jhon309 0:88e313c910d0 664 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:88e313c910d0 665 */
jhon309 0:88e313c910d0 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:88e313c910d0 667 {
jhon309 0:88e313c910d0 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:88e313c910d0 669 }
jhon309 0:88e313c910d0 670
jhon309 0:88e313c910d0 671
jhon309 0:88e313c910d0 672 /** \brief Clear Pending Interrupt
jhon309 0:88e313c910d0 673
jhon309 0:88e313c910d0 674 The function clears the pending bit of an external interrupt.
jhon309 0:88e313c910d0 675
jhon309 0:88e313c910d0 676 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:88e313c910d0 677 */
jhon309 0:88e313c910d0 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:88e313c910d0 679 {
jhon309 0:88e313c910d0 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jhon309 0:88e313c910d0 681 }
jhon309 0:88e313c910d0 682
jhon309 0:88e313c910d0 683
jhon309 0:88e313c910d0 684 /** \brief Set Interrupt Priority
jhon309 0:88e313c910d0 685
jhon309 0:88e313c910d0 686 The function sets the priority of an interrupt.
jhon309 0:88e313c910d0 687
jhon309 0:88e313c910d0 688 \note The priority cannot be set for every core interrupt.
jhon309 0:88e313c910d0 689
jhon309 0:88e313c910d0 690 \param [in] IRQn Interrupt number.
jhon309 0:88e313c910d0 691 \param [in] priority Priority to set.
jhon309 0:88e313c910d0 692 */
jhon309 0:88e313c910d0 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:88e313c910d0 694 {
jhon309 0:88e313c910d0 695 if(IRQn < 0) {
jhon309 0:88e313c910d0 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:88e313c910d0 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:88e313c910d0 698 else {
jhon309 0:88e313c910d0 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:88e313c910d0 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:88e313c910d0 701 }
jhon309 0:88e313c910d0 702
jhon309 0:88e313c910d0 703
jhon309 0:88e313c910d0 704 /** \brief Get Interrupt Priority
jhon309 0:88e313c910d0 705
jhon309 0:88e313c910d0 706 The function reads the priority of an interrupt. The interrupt
jhon309 0:88e313c910d0 707 number can be positive to specify an external (device specific)
jhon309 0:88e313c910d0 708 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:88e313c910d0 709
jhon309 0:88e313c910d0 710
jhon309 0:88e313c910d0 711 \param [in] IRQn Interrupt number.
jhon309 0:88e313c910d0 712 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:88e313c910d0 713 priority bits of the microcontroller.
jhon309 0:88e313c910d0 714 */
jhon309 0:88e313c910d0 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:88e313c910d0 716 {
jhon309 0:88e313c910d0 717
jhon309 0:88e313c910d0 718 if(IRQn < 0) {
jhon309 0:88e313c910d0 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
jhon309 0:88e313c910d0 720 else {
jhon309 0:88e313c910d0 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jhon309 0:88e313c910d0 722 }
jhon309 0:88e313c910d0 723
jhon309 0:88e313c910d0 724
jhon309 0:88e313c910d0 725 /** \brief System Reset
jhon309 0:88e313c910d0 726
jhon309 0:88e313c910d0 727 The function initiates a system reset request to reset the MCU.
jhon309 0:88e313c910d0 728 */
jhon309 0:88e313c910d0 729 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:88e313c910d0 730 {
jhon309 0:88e313c910d0 731 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:88e313c910d0 732 buffered write are completed before reset */
jhon309 0:88e313c910d0 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:88e313c910d0 734 SCB_AIRCR_SYSRESETREQ_Msk);
jhon309 0:88e313c910d0 735 __DSB(); /* Ensure completion of memory access */
jhon309 0:88e313c910d0 736 while(1); /* wait until reset */
jhon309 0:88e313c910d0 737 }
jhon309 0:88e313c910d0 738
jhon309 0:88e313c910d0 739 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:88e313c910d0 740
jhon309 0:88e313c910d0 741
jhon309 0:88e313c910d0 742
jhon309 0:88e313c910d0 743 /* ################################## SysTick function ############################################ */
jhon309 0:88e313c910d0 744 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:88e313c910d0 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:88e313c910d0 746 \brief Functions that configure the System.
jhon309 0:88e313c910d0 747 @{
jhon309 0:88e313c910d0 748 */
jhon309 0:88e313c910d0 749
jhon309 0:88e313c910d0 750 #if (__Vendor_SysTickConfig == 0)
jhon309 0:88e313c910d0 751
jhon309 0:88e313c910d0 752 /** \brief System Tick Configuration
jhon309 0:88e313c910d0 753
jhon309 0:88e313c910d0 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:88e313c910d0 755 Counter is in free running mode to generate periodic interrupts.
jhon309 0:88e313c910d0 756
jhon309 0:88e313c910d0 757 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:88e313c910d0 758
jhon309 0:88e313c910d0 759 \return 0 Function succeeded.
jhon309 0:88e313c910d0 760 \return 1 Function failed.
jhon309 0:88e313c910d0 761
jhon309 0:88e313c910d0 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:88e313c910d0 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:88e313c910d0 764 must contain a vendor-specific implementation of this function.
jhon309 0:88e313c910d0 765
jhon309 0:88e313c910d0 766 */
jhon309 0:88e313c910d0 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:88e313c910d0 768 {
jhon309 0:88e313c910d0 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jhon309 0:88e313c910d0 770
jhon309 0:88e313c910d0 771 SysTick->LOAD = ticks - 1; /* set reload register */
jhon309 0:88e313c910d0 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jhon309 0:88e313c910d0 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jhon309 0:88e313c910d0 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:88e313c910d0 775 SysTick_CTRL_TICKINT_Msk |
jhon309 0:88e313c910d0 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:88e313c910d0 777 return (0); /* Function successful */
jhon309 0:88e313c910d0 778 }
jhon309 0:88e313c910d0 779
jhon309 0:88e313c910d0 780 #endif
jhon309 0:88e313c910d0 781
jhon309 0:88e313c910d0 782 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:88e313c910d0 783
jhon309 0:88e313c910d0 784
jhon309 0:88e313c910d0 785
jhon309 0:88e313c910d0 786
jhon309 0:88e313c910d0 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
jhon309 0:88e313c910d0 788
jhon309 0:88e313c910d0 789 #endif /* __CMSIS_GENERIC */
jhon309 0:88e313c910d0 790
jhon309 0:88e313c910d0 791 #ifdef __cplusplus
jhon309 0:88e313c910d0 792 }
jhon309 0:88e313c910d0 793 #endif