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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.h@0:666850d06c9f, 2015-08-20 (annotated)
- Committer:
- jhon309
- Date:
- Thu Aug 20 00:37:14 2015 +0000
- Revision:
- 0:666850d06c9f
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jhon309 | 0:666850d06c9f | 1 | /** |
jhon309 | 0:666850d06c9f | 2 | ****************************************************************************** |
jhon309 | 0:666850d06c9f | 3 | * @file stm32f0xx_hal_rcc.h |
jhon309 | 0:666850d06c9f | 4 | * @author MCD Application Team |
jhon309 | 0:666850d06c9f | 5 | * @version V1.2.0 |
jhon309 | 0:666850d06c9f | 6 | * @date 11-December-2014 |
jhon309 | 0:666850d06c9f | 7 | * @brief Header file of RCC HAL module. |
jhon309 | 0:666850d06c9f | 8 | ****************************************************************************** |
jhon309 | 0:666850d06c9f | 9 | * @attention |
jhon309 | 0:666850d06c9f | 10 | * |
jhon309 | 0:666850d06c9f | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
jhon309 | 0:666850d06c9f | 12 | * |
jhon309 | 0:666850d06c9f | 13 | * Redistribution and use in source and binary forms, with or without modification, |
jhon309 | 0:666850d06c9f | 14 | * are permitted provided that the following conditions are met: |
jhon309 | 0:666850d06c9f | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
jhon309 | 0:666850d06c9f | 16 | * this list of conditions and the following disclaimer. |
jhon309 | 0:666850d06c9f | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
jhon309 | 0:666850d06c9f | 18 | * this list of conditions and the following disclaimer in the documentation |
jhon309 | 0:666850d06c9f | 19 | * and/or other materials provided with the distribution. |
jhon309 | 0:666850d06c9f | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
jhon309 | 0:666850d06c9f | 21 | * may be used to endorse or promote products derived from this software |
jhon309 | 0:666850d06c9f | 22 | * without specific prior written permission. |
jhon309 | 0:666850d06c9f | 23 | * |
jhon309 | 0:666850d06c9f | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
jhon309 | 0:666850d06c9f | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
jhon309 | 0:666850d06c9f | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
jhon309 | 0:666850d06c9f | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
jhon309 | 0:666850d06c9f | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
jhon309 | 0:666850d06c9f | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
jhon309 | 0:666850d06c9f | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
jhon309 | 0:666850d06c9f | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
jhon309 | 0:666850d06c9f | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
jhon309 | 0:666850d06c9f | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
jhon309 | 0:666850d06c9f | 34 | * |
jhon309 | 0:666850d06c9f | 35 | ****************************************************************************** |
jhon309 | 0:666850d06c9f | 36 | */ |
jhon309 | 0:666850d06c9f | 37 | |
jhon309 | 0:666850d06c9f | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
jhon309 | 0:666850d06c9f | 39 | #ifndef __STM32F0xx_HAL_RCC_H |
jhon309 | 0:666850d06c9f | 40 | #define __STM32F0xx_HAL_RCC_H |
jhon309 | 0:666850d06c9f | 41 | |
jhon309 | 0:666850d06c9f | 42 | #ifdef __cplusplus |
jhon309 | 0:666850d06c9f | 43 | extern "C" { |
jhon309 | 0:666850d06c9f | 44 | #endif |
jhon309 | 0:666850d06c9f | 45 | |
jhon309 | 0:666850d06c9f | 46 | /* Includes ------------------------------------------------------------------*/ |
jhon309 | 0:666850d06c9f | 47 | #include "stm32f0xx_hal_def.h" |
jhon309 | 0:666850d06c9f | 48 | |
jhon309 | 0:666850d06c9f | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
jhon309 | 0:666850d06c9f | 50 | * @{ |
jhon309 | 0:666850d06c9f | 51 | */ |
jhon309 | 0:666850d06c9f | 52 | |
jhon309 | 0:666850d06c9f | 53 | /** @addtogroup RCC |
jhon309 | 0:666850d06c9f | 54 | * @{ |
jhon309 | 0:666850d06c9f | 55 | */ |
jhon309 | 0:666850d06c9f | 56 | |
jhon309 | 0:666850d06c9f | 57 | /* Exported types ------------------------------------------------------------*/ |
jhon309 | 0:666850d06c9f | 58 | |
jhon309 | 0:666850d06c9f | 59 | /** @defgroup RCC_Exported_Types RCC Exported Types |
jhon309 | 0:666850d06c9f | 60 | * @{ |
jhon309 | 0:666850d06c9f | 61 | */ |
jhon309 | 0:666850d06c9f | 62 | |
jhon309 | 0:666850d06c9f | 63 | /** |
jhon309 | 0:666850d06c9f | 64 | * @brief RCC PLL configuration structure definition |
jhon309 | 0:666850d06c9f | 65 | */ |
jhon309 | 0:666850d06c9f | 66 | typedef struct |
jhon309 | 0:666850d06c9f | 67 | { |
jhon309 | 0:666850d06c9f | 68 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
jhon309 | 0:666850d06c9f | 69 | This parameter can be a value of @ref RCC_PLL_Config */ |
jhon309 | 0:666850d06c9f | 70 | |
jhon309 | 0:666850d06c9f | 71 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
jhon309 | 0:666850d06c9f | 72 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
jhon309 | 0:666850d06c9f | 73 | |
jhon309 | 0:666850d06c9f | 74 | uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock |
jhon309 | 0:666850d06c9f | 75 | This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ |
jhon309 | 0:666850d06c9f | 76 | |
jhon309 | 0:666850d06c9f | 77 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
jhon309 | 0:666850d06c9f | 78 | This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */ |
jhon309 | 0:666850d06c9f | 79 | |
jhon309 | 0:666850d06c9f | 80 | }RCC_PLLInitTypeDef; |
jhon309 | 0:666850d06c9f | 81 | |
jhon309 | 0:666850d06c9f | 82 | /** |
jhon309 | 0:666850d06c9f | 83 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
jhon309 | 0:666850d06c9f | 84 | */ |
jhon309 | 0:666850d06c9f | 85 | typedef struct |
jhon309 | 0:666850d06c9f | 86 | { |
jhon309 | 0:666850d06c9f | 87 | uint32_t OscillatorType; /*!< The Oscillators to be configured. |
jhon309 | 0:666850d06c9f | 88 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
jhon309 | 0:666850d06c9f | 89 | |
jhon309 | 0:666850d06c9f | 90 | uint32_t HSEState; /*!< The new state of the HSE. |
jhon309 | 0:666850d06c9f | 91 | This parameter can be a value of @ref RCC_HSE_Config */ |
jhon309 | 0:666850d06c9f | 92 | |
jhon309 | 0:666850d06c9f | 93 | uint32_t LSEState; /*!< The new state of the LSE. |
jhon309 | 0:666850d06c9f | 94 | This parameter can be a value of @ref RCC_LSE_Config */ |
jhon309 | 0:666850d06c9f | 95 | |
jhon309 | 0:666850d06c9f | 96 | uint32_t HSIState; /*!< The new state of the HSI. |
jhon309 | 0:666850d06c9f | 97 | This parameter can be a value of @ref RCC_HSI_Config */ |
jhon309 | 0:666850d06c9f | 98 | |
jhon309 | 0:666850d06c9f | 99 | uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
jhon309 | 0:666850d06c9f | 100 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
jhon309 | 0:666850d06c9f | 101 | |
jhon309 | 0:666850d06c9f | 102 | uint32_t HSI14State; /*!< The new state of the HSI14. |
jhon309 | 0:666850d06c9f | 103 | This parameter can be a value of @ref RCC_HSI14_Config */ |
jhon309 | 0:666850d06c9f | 104 | |
jhon309 | 0:666850d06c9f | 105 | uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). |
jhon309 | 0:666850d06c9f | 106 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
jhon309 | 0:666850d06c9f | 107 | |
jhon309 | 0:666850d06c9f | 108 | uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices). |
jhon309 | 0:666850d06c9f | 109 | This parameter can be a value of @ref RCCEx_HSI48_Config */ |
jhon309 | 0:666850d06c9f | 110 | |
jhon309 | 0:666850d06c9f | 111 | uint32_t LSIState; /*!< The new state of the LSI. |
jhon309 | 0:666850d06c9f | 112 | This parameter can be a value of @ref RCC_LSI_Config */ |
jhon309 | 0:666850d06c9f | 113 | |
jhon309 | 0:666850d06c9f | 114 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
jhon309 | 0:666850d06c9f | 115 | |
jhon309 | 0:666850d06c9f | 116 | }RCC_OscInitTypeDef; |
jhon309 | 0:666850d06c9f | 117 | |
jhon309 | 0:666850d06c9f | 118 | /** |
jhon309 | 0:666850d06c9f | 119 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
jhon309 | 0:666850d06c9f | 120 | */ |
jhon309 | 0:666850d06c9f | 121 | typedef struct |
jhon309 | 0:666850d06c9f | 122 | { |
jhon309 | 0:666850d06c9f | 123 | uint32_t ClockType; /*!< The clock to be configured. |
jhon309 | 0:666850d06c9f | 124 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
jhon309 | 0:666850d06c9f | 125 | |
jhon309 | 0:666850d06c9f | 126 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
jhon309 | 0:666850d06c9f | 127 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
jhon309 | 0:666850d06c9f | 128 | |
jhon309 | 0:666850d06c9f | 129 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
jhon309 | 0:666850d06c9f | 130 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
jhon309 | 0:666850d06c9f | 131 | |
jhon309 | 0:666850d06c9f | 132 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
jhon309 | 0:666850d06c9f | 133 | This parameter can be a value of @ref RCC_APB1_Clock_Source */ |
jhon309 | 0:666850d06c9f | 134 | |
jhon309 | 0:666850d06c9f | 135 | }RCC_ClkInitTypeDef; |
jhon309 | 0:666850d06c9f | 136 | |
jhon309 | 0:666850d06c9f | 137 | /** |
jhon309 | 0:666850d06c9f | 138 | * @} |
jhon309 | 0:666850d06c9f | 139 | */ |
jhon309 | 0:666850d06c9f | 140 | |
jhon309 | 0:666850d06c9f | 141 | /* Exported constants --------------------------------------------------------*/ |
jhon309 | 0:666850d06c9f | 142 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
jhon309 | 0:666850d06c9f | 143 | * @{ |
jhon309 | 0:666850d06c9f | 144 | */ |
jhon309 | 0:666850d06c9f | 145 | |
jhon309 | 0:666850d06c9f | 146 | /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion |
jhon309 | 0:666850d06c9f | 147 | * @brief RCC registers bit address in the alias region |
jhon309 | 0:666850d06c9f | 148 | * @{ |
jhon309 | 0:666850d06c9f | 149 | */ |
jhon309 | 0:666850d06c9f | 150 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
jhon309 | 0:666850d06c9f | 151 | /* --- CR Register ---*/ |
jhon309 | 0:666850d06c9f | 152 | #define RCC_CR_OFFSET (RCC_OFFSET + 0x00) |
jhon309 | 0:666850d06c9f | 153 | /* --- CFGR Register ---*/ |
jhon309 | 0:666850d06c9f | 154 | #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04) |
jhon309 | 0:666850d06c9f | 155 | /* --- CIR Register ---*/ |
jhon309 | 0:666850d06c9f | 156 | #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08) |
jhon309 | 0:666850d06c9f | 157 | /* --- BDCR Register ---*/ |
jhon309 | 0:666850d06c9f | 158 | #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20) |
jhon309 | 0:666850d06c9f | 159 | /* --- CSR Register ---*/ |
jhon309 | 0:666850d06c9f | 160 | #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24) |
jhon309 | 0:666850d06c9f | 161 | /* --- CR2 Register ---*/ |
jhon309 | 0:666850d06c9f | 162 | #define RCC_CR2_OFFSET (RCC_OFFSET + 0x34) |
jhon309 | 0:666850d06c9f | 163 | |
jhon309 | 0:666850d06c9f | 164 | /* CR register byte 2 (Bits[23:16]) base address */ |
jhon309 | 0:666850d06c9f | 165 | #define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02) |
jhon309 | 0:666850d06c9f | 166 | |
jhon309 | 0:666850d06c9f | 167 | /* CIR register byte 1 (Bits[15:8]) base address */ |
jhon309 | 0:666850d06c9f | 168 | #define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01) |
jhon309 | 0:666850d06c9f | 169 | |
jhon309 | 0:666850d06c9f | 170 | /* CIR register byte 2 (Bits[23:16]) base address */ |
jhon309 | 0:666850d06c9f | 171 | #define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02) |
jhon309 | 0:666850d06c9f | 172 | |
jhon309 | 0:666850d06c9f | 173 | /* CSR register byte 1 (Bits[15:8]) base address */ |
jhon309 | 0:666850d06c9f | 174 | #define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01) |
jhon309 | 0:666850d06c9f | 175 | |
jhon309 | 0:666850d06c9f | 176 | /* BDCR register byte 0 (Bits[7:0] base address */ |
jhon309 | 0:666850d06c9f | 177 | #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) |
jhon309 | 0:666850d06c9f | 178 | |
jhon309 | 0:666850d06c9f | 179 | #define RCC_CFGR_PLLMUL_BITNUMBER 18 |
jhon309 | 0:666850d06c9f | 180 | #define RCC_CFGR2_PREDIV_BITNUMBER 0 |
jhon309 | 0:666850d06c9f | 181 | |
jhon309 | 0:666850d06c9f | 182 | /** |
jhon309 | 0:666850d06c9f | 183 | * @} |
jhon309 | 0:666850d06c9f | 184 | */ |
jhon309 | 0:666850d06c9f | 185 | |
jhon309 | 0:666850d06c9f | 186 | /** @defgroup RCC_Timeout RCC Timeout |
jhon309 | 0:666850d06c9f | 187 | * @{ |
jhon309 | 0:666850d06c9f | 188 | */ |
jhon309 | 0:666850d06c9f | 189 | /* LSE state change timeout */ |
jhon309 | 0:666850d06c9f | 190 | #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
jhon309 | 0:666850d06c9f | 191 | |
jhon309 | 0:666850d06c9f | 192 | /* Disable Backup domain write protection state change timeout */ |
jhon309 | 0:666850d06c9f | 193 | #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
jhon309 | 0:666850d06c9f | 194 | /** |
jhon309 | 0:666850d06c9f | 195 | * @} |
jhon309 | 0:666850d06c9f | 196 | */ |
jhon309 | 0:666850d06c9f | 197 | |
jhon309 | 0:666850d06c9f | 198 | /** @defgroup RCC_Oscillator_Type RCC Oscillator Type |
jhon309 | 0:666850d06c9f | 199 | * @{ |
jhon309 | 0:666850d06c9f | 200 | */ |
jhon309 | 0:666850d06c9f | 201 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) |
jhon309 | 0:666850d06c9f | 202 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) |
jhon309 | 0:666850d06c9f | 203 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) |
jhon309 | 0:666850d06c9f | 204 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) |
jhon309 | 0:666850d06c9f | 205 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) |
jhon309 | 0:666850d06c9f | 206 | #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010) |
jhon309 | 0:666850d06c9f | 207 | #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) |
jhon309 | 0:666850d06c9f | 208 | |
jhon309 | 0:666850d06c9f | 209 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
jhon309 | 0:666850d06c9f | 210 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
jhon309 | 0:666850d06c9f | 211 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
jhon309 | 0:666850d06c9f | 212 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
jhon309 | 0:666850d06c9f | 213 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
jhon309 | 0:666850d06c9f | 214 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ |
jhon309 | 0:666850d06c9f | 215 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) |
jhon309 | 0:666850d06c9f | 216 | /** |
jhon309 | 0:666850d06c9f | 217 | * @} |
jhon309 | 0:666850d06c9f | 218 | */ |
jhon309 | 0:666850d06c9f | 219 | |
jhon309 | 0:666850d06c9f | 220 | /** @defgroup RCC_HSE_Config RCC HSE Config |
jhon309 | 0:666850d06c9f | 221 | * @{ |
jhon309 | 0:666850d06c9f | 222 | */ |
jhon309 | 0:666850d06c9f | 223 | #define RCC_HSE_OFF ((uint8_t)0x00) |
jhon309 | 0:666850d06c9f | 224 | #define RCC_HSE_ON ((uint8_t)0x01) |
jhon309 | 0:666850d06c9f | 225 | #define RCC_HSE_BYPASS ((uint8_t)0x05) |
jhon309 | 0:666850d06c9f | 226 | |
jhon309 | 0:666850d06c9f | 227 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
jhon309 | 0:666850d06c9f | 228 | ((HSE) == RCC_HSE_BYPASS)) |
jhon309 | 0:666850d06c9f | 229 | /** |
jhon309 | 0:666850d06c9f | 230 | * @} |
jhon309 | 0:666850d06c9f | 231 | */ |
jhon309 | 0:666850d06c9f | 232 | |
jhon309 | 0:666850d06c9f | 233 | /** @defgroup RCC_LSE_Config RCC_LSE_Config |
jhon309 | 0:666850d06c9f | 234 | * @{ |
jhon309 | 0:666850d06c9f | 235 | */ |
jhon309 | 0:666850d06c9f | 236 | #define RCC_LSE_OFF ((uint8_t)0x00) |
jhon309 | 0:666850d06c9f | 237 | #define RCC_LSE_ON ((uint8_t)0x01) |
jhon309 | 0:666850d06c9f | 238 | #define RCC_LSE_BYPASS ((uint8_t)0x05) |
jhon309 | 0:666850d06c9f | 239 | |
jhon309 | 0:666850d06c9f | 240 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
jhon309 | 0:666850d06c9f | 241 | ((LSE) == RCC_LSE_BYPASS)) |
jhon309 | 0:666850d06c9f | 242 | /** |
jhon309 | 0:666850d06c9f | 243 | * @} |
jhon309 | 0:666850d06c9f | 244 | */ |
jhon309 | 0:666850d06c9f | 245 | |
jhon309 | 0:666850d06c9f | 246 | /** @defgroup RCC_HSI_Config RCC HSI Config |
jhon309 | 0:666850d06c9f | 247 | * @{ |
jhon309 | 0:666850d06c9f | 248 | */ |
jhon309 | 0:666850d06c9f | 249 | #define RCC_HSI_OFF ((uint8_t)0x00) |
jhon309 | 0:666850d06c9f | 250 | #define RCC_HSI_ON ((uint8_t)0x01) |
jhon309 | 0:666850d06c9f | 251 | |
jhon309 | 0:666850d06c9f | 252 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
jhon309 | 0:666850d06c9f | 253 | |
jhon309 | 0:666850d06c9f | 254 | #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ |
jhon309 | 0:666850d06c9f | 255 | /** |
jhon309 | 0:666850d06c9f | 256 | * @} |
jhon309 | 0:666850d06c9f | 257 | */ |
jhon309 | 0:666850d06c9f | 258 | |
jhon309 | 0:666850d06c9f | 259 | /** @defgroup RCC_HSI14_Config RCC HSI14 Config |
jhon309 | 0:666850d06c9f | 260 | * @{ |
jhon309 | 0:666850d06c9f | 261 | */ |
jhon309 | 0:666850d06c9f | 262 | #define RCC_HSI14_OFF ((uint32_t)0x00) |
jhon309 | 0:666850d06c9f | 263 | #define RCC_HSI14_ON RCC_CR2_HSI14ON |
jhon309 | 0:666850d06c9f | 264 | #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) |
jhon309 | 0:666850d06c9f | 265 | |
jhon309 | 0:666850d06c9f | 266 | #define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL)) |
jhon309 | 0:666850d06c9f | 267 | |
jhon309 | 0:666850d06c9f | 268 | #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */ |
jhon309 | 0:666850d06c9f | 269 | /** |
jhon309 | 0:666850d06c9f | 270 | * @} |
jhon309 | 0:666850d06c9f | 271 | */ |
jhon309 | 0:666850d06c9f | 272 | |
jhon309 | 0:666850d06c9f | 273 | /** @defgroup RCC_LSI_Config RCC LSI Config |
jhon309 | 0:666850d06c9f | 274 | * @{ |
jhon309 | 0:666850d06c9f | 275 | */ |
jhon309 | 0:666850d06c9f | 276 | #define RCC_LSI_OFF ((uint8_t)0x00) |
jhon309 | 0:666850d06c9f | 277 | #define RCC_LSI_ON ((uint8_t)0x01) |
jhon309 | 0:666850d06c9f | 278 | |
jhon309 | 0:666850d06c9f | 279 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
jhon309 | 0:666850d06c9f | 280 | /** |
jhon309 | 0:666850d06c9f | 281 | * @} |
jhon309 | 0:666850d06c9f | 282 | */ |
jhon309 | 0:666850d06c9f | 283 | |
jhon309 | 0:666850d06c9f | 284 | /** @defgroup RCC_PLL_Config RCC PLL Config |
jhon309 | 0:666850d06c9f | 285 | * @{ |
jhon309 | 0:666850d06c9f | 286 | */ |
jhon309 | 0:666850d06c9f | 287 | #define RCC_PLL_NONE ((uint8_t)0x00) |
jhon309 | 0:666850d06c9f | 288 | #define RCC_PLL_OFF ((uint8_t)0x01) |
jhon309 | 0:666850d06c9f | 289 | #define RCC_PLL_ON ((uint8_t)0x02) |
jhon309 | 0:666850d06c9f | 290 | |
jhon309 | 0:666850d06c9f | 291 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
jhon309 | 0:666850d06c9f | 292 | /** |
jhon309 | 0:666850d06c9f | 293 | * @} |
jhon309 | 0:666850d06c9f | 294 | */ |
jhon309 | 0:666850d06c9f | 295 | |
jhon309 | 0:666850d06c9f | 296 | /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor |
jhon309 | 0:666850d06c9f | 297 | * @{ |
jhon309 | 0:666850d06c9f | 298 | */ |
jhon309 | 0:666850d06c9f | 299 | #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
jhon309 | 0:666850d06c9f | 300 | #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
jhon309 | 0:666850d06c9f | 301 | #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
jhon309 | 0:666850d06c9f | 302 | #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
jhon309 | 0:666850d06c9f | 303 | #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
jhon309 | 0:666850d06c9f | 304 | #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
jhon309 | 0:666850d06c9f | 305 | #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
jhon309 | 0:666850d06c9f | 306 | #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
jhon309 | 0:666850d06c9f | 307 | #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
jhon309 | 0:666850d06c9f | 308 | #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
jhon309 | 0:666850d06c9f | 309 | #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
jhon309 | 0:666850d06c9f | 310 | #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
jhon309 | 0:666850d06c9f | 311 | #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
jhon309 | 0:666850d06c9f | 312 | #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
jhon309 | 0:666850d06c9f | 313 | #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
jhon309 | 0:666850d06c9f | 314 | #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
jhon309 | 0:666850d06c9f | 315 | |
jhon309 | 0:666850d06c9f | 316 | #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \ |
jhon309 | 0:666850d06c9f | 317 | ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \ |
jhon309 | 0:666850d06c9f | 318 | ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \ |
jhon309 | 0:666850d06c9f | 319 | ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \ |
jhon309 | 0:666850d06c9f | 320 | ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \ |
jhon309 | 0:666850d06c9f | 321 | ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \ |
jhon309 | 0:666850d06c9f | 322 | ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \ |
jhon309 | 0:666850d06c9f | 323 | ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16)) |
jhon309 | 0:666850d06c9f | 324 | /** |
jhon309 | 0:666850d06c9f | 325 | * @} |
jhon309 | 0:666850d06c9f | 326 | */ |
jhon309 | 0:666850d06c9f | 327 | |
jhon309 | 0:666850d06c9f | 328 | /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor |
jhon309 | 0:666850d06c9f | 329 | * @{ |
jhon309 | 0:666850d06c9f | 330 | */ |
jhon309 | 0:666850d06c9f | 331 | #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 |
jhon309 | 0:666850d06c9f | 332 | #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 |
jhon309 | 0:666850d06c9f | 333 | #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 |
jhon309 | 0:666850d06c9f | 334 | #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 |
jhon309 | 0:666850d06c9f | 335 | #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 |
jhon309 | 0:666850d06c9f | 336 | #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 |
jhon309 | 0:666850d06c9f | 337 | #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 |
jhon309 | 0:666850d06c9f | 338 | #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 |
jhon309 | 0:666850d06c9f | 339 | #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 |
jhon309 | 0:666850d06c9f | 340 | #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 |
jhon309 | 0:666850d06c9f | 341 | #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 |
jhon309 | 0:666850d06c9f | 342 | #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 |
jhon309 | 0:666850d06c9f | 343 | #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 |
jhon309 | 0:666850d06c9f | 344 | #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 |
jhon309 | 0:666850d06c9f | 345 | #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 |
jhon309 | 0:666850d06c9f | 346 | |
jhon309 | 0:666850d06c9f | 347 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \ |
jhon309 | 0:666850d06c9f | 348 | ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \ |
jhon309 | 0:666850d06c9f | 349 | ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \ |
jhon309 | 0:666850d06c9f | 350 | ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \ |
jhon309 | 0:666850d06c9f | 351 | ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \ |
jhon309 | 0:666850d06c9f | 352 | ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \ |
jhon309 | 0:666850d06c9f | 353 | ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \ |
jhon309 | 0:666850d06c9f | 354 | ((MUL) == RCC_PLL_MUL16)) |
jhon309 | 0:666850d06c9f | 355 | /** |
jhon309 | 0:666850d06c9f | 356 | * @} |
jhon309 | 0:666850d06c9f | 357 | */ |
jhon309 | 0:666850d06c9f | 358 | |
jhon309 | 0:666850d06c9f | 359 | /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source |
jhon309 | 0:666850d06c9f | 360 | * @{ |
jhon309 | 0:666850d06c9f | 361 | */ |
jhon309 | 0:666850d06c9f | 362 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV |
jhon309 | 0:666850d06c9f | 363 | /** |
jhon309 | 0:666850d06c9f | 364 | * @} |
jhon309 | 0:666850d06c9f | 365 | */ |
jhon309 | 0:666850d06c9f | 366 | |
jhon309 | 0:666850d06c9f | 367 | /** @defgroup RCC_System_Clock_Type RCC System Clock Type |
jhon309 | 0:666850d06c9f | 368 | * @{ |
jhon309 | 0:666850d06c9f | 369 | */ |
jhon309 | 0:666850d06c9f | 370 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) |
jhon309 | 0:666850d06c9f | 371 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) |
jhon309 | 0:666850d06c9f | 372 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) |
jhon309 | 0:666850d06c9f | 373 | |
jhon309 | 0:666850d06c9f | 374 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
jhon309 | 0:666850d06c9f | 375 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
jhon309 | 0:666850d06c9f | 376 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) |
jhon309 | 0:666850d06c9f | 377 | /** |
jhon309 | 0:666850d06c9f | 378 | * @} |
jhon309 | 0:666850d06c9f | 379 | */ |
jhon309 | 0:666850d06c9f | 380 | |
jhon309 | 0:666850d06c9f | 381 | /** @defgroup RCC_System_Clock_Source RCC System Clock Source |
jhon309 | 0:666850d06c9f | 382 | * @{ |
jhon309 | 0:666850d06c9f | 383 | */ |
jhon309 | 0:666850d06c9f | 384 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
jhon309 | 0:666850d06c9f | 385 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
jhon309 | 0:666850d06c9f | 386 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
jhon309 | 0:666850d06c9f | 387 | /** |
jhon309 | 0:666850d06c9f | 388 | * @} |
jhon309 | 0:666850d06c9f | 389 | */ |
jhon309 | 0:666850d06c9f | 390 | |
jhon309 | 0:666850d06c9f | 391 | /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status |
jhon309 | 0:666850d06c9f | 392 | * @{ |
jhon309 | 0:666850d06c9f | 393 | */ |
jhon309 | 0:666850d06c9f | 394 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
jhon309 | 0:666850d06c9f | 395 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
jhon309 | 0:666850d06c9f | 396 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL |
jhon309 | 0:666850d06c9f | 397 | /** |
jhon309 | 0:666850d06c9f | 398 | * @} |
jhon309 | 0:666850d06c9f | 399 | */ |
jhon309 | 0:666850d06c9f | 400 | |
jhon309 | 0:666850d06c9f | 401 | /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source |
jhon309 | 0:666850d06c9f | 402 | * @{ |
jhon309 | 0:666850d06c9f | 403 | */ |
jhon309 | 0:666850d06c9f | 404 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
jhon309 | 0:666850d06c9f | 405 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
jhon309 | 0:666850d06c9f | 406 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
jhon309 | 0:666850d06c9f | 407 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
jhon309 | 0:666850d06c9f | 408 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
jhon309 | 0:666850d06c9f | 409 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
jhon309 | 0:666850d06c9f | 410 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
jhon309 | 0:666850d06c9f | 411 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
jhon309 | 0:666850d06c9f | 412 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
jhon309 | 0:666850d06c9f | 413 | |
jhon309 | 0:666850d06c9f | 414 | #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \ |
jhon309 | 0:666850d06c9f | 415 | ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \ |
jhon309 | 0:666850d06c9f | 416 | ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \ |
jhon309 | 0:666850d06c9f | 417 | ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \ |
jhon309 | 0:666850d06c9f | 418 | ((DIV) == RCC_SYSCLK_DIV512)) |
jhon309 | 0:666850d06c9f | 419 | /** |
jhon309 | 0:666850d06c9f | 420 | * @} |
jhon309 | 0:666850d06c9f | 421 | */ |
jhon309 | 0:666850d06c9f | 422 | |
jhon309 | 0:666850d06c9f | 423 | /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source |
jhon309 | 0:666850d06c9f | 424 | * @{ |
jhon309 | 0:666850d06c9f | 425 | */ |
jhon309 | 0:666850d06c9f | 426 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 |
jhon309 | 0:666850d06c9f | 427 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 |
jhon309 | 0:666850d06c9f | 428 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 |
jhon309 | 0:666850d06c9f | 429 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 |
jhon309 | 0:666850d06c9f | 430 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 |
jhon309 | 0:666850d06c9f | 431 | |
jhon309 | 0:666850d06c9f | 432 | #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \ |
jhon309 | 0:666850d06c9f | 433 | ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \ |
jhon309 | 0:666850d06c9f | 434 | ((DIV) == RCC_HCLK_DIV16)) |
jhon309 | 0:666850d06c9f | 435 | /** |
jhon309 | 0:666850d06c9f | 436 | * @} |
jhon309 | 0:666850d06c9f | 437 | */ |
jhon309 | 0:666850d06c9f | 438 | |
jhon309 | 0:666850d06c9f | 439 | /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source |
jhon309 | 0:666850d06c9f | 440 | * @{ |
jhon309 | 0:666850d06c9f | 441 | */ |
jhon309 | 0:666850d06c9f | 442 | #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK |
jhon309 | 0:666850d06c9f | 443 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE |
jhon309 | 0:666850d06c9f | 444 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI |
jhon309 | 0:666850d06c9f | 445 | #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE |
jhon309 | 0:666850d06c9f | 446 | |
jhon309 | 0:666850d06c9f | 447 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \ |
jhon309 | 0:666850d06c9f | 448 | ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ |
jhon309 | 0:666850d06c9f | 449 | ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
jhon309 | 0:666850d06c9f | 450 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32)) |
jhon309 | 0:666850d06c9f | 451 | /** |
jhon309 | 0:666850d06c9f | 452 | * @} |
jhon309 | 0:666850d06c9f | 453 | */ |
jhon309 | 0:666850d06c9f | 454 | |
jhon309 | 0:666850d06c9f | 455 | /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source |
jhon309 | 0:666850d06c9f | 456 | * @{ |
jhon309 | 0:666850d06c9f | 457 | */ |
jhon309 | 0:666850d06c9f | 458 | #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK |
jhon309 | 0:666850d06c9f | 459 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
jhon309 | 0:666850d06c9f | 460 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
jhon309 | 0:666850d06c9f | 461 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
jhon309 | 0:666850d06c9f | 462 | |
jhon309 | 0:666850d06c9f | 463 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ |
jhon309 | 0:666850d06c9f | 464 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
jhon309 | 0:666850d06c9f | 465 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
jhon309 | 0:666850d06c9f | 466 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
jhon309 | 0:666850d06c9f | 467 | /** |
jhon309 | 0:666850d06c9f | 468 | * @} |
jhon309 | 0:666850d06c9f | 469 | */ |
jhon309 | 0:666850d06c9f | 470 | |
jhon309 | 0:666850d06c9f | 471 | /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source |
jhon309 | 0:666850d06c9f | 472 | * @{ |
jhon309 | 0:666850d06c9f | 473 | */ |
jhon309 | 0:666850d06c9f | 474 | #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI |
jhon309 | 0:666850d06c9f | 475 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK |
jhon309 | 0:666850d06c9f | 476 | |
jhon309 | 0:666850d06c9f | 477 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ |
jhon309 | 0:666850d06c9f | 478 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)) |
jhon309 | 0:666850d06c9f | 479 | /** |
jhon309 | 0:666850d06c9f | 480 | * @} |
jhon309 | 0:666850d06c9f | 481 | */ |
jhon309 | 0:666850d06c9f | 482 | |
jhon309 | 0:666850d06c9f | 483 | /** @defgroup RCC_MCOx_Index RCC MCOx Index |
jhon309 | 0:666850d06c9f | 484 | * @{ |
jhon309 | 0:666850d06c9f | 485 | */ |
jhon309 | 0:666850d06c9f | 486 | #define RCC_MCO ((uint32_t)0x00000000) |
jhon309 | 0:666850d06c9f | 487 | |
jhon309 | 0:666850d06c9f | 488 | #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO) |
jhon309 | 0:666850d06c9f | 489 | /** |
jhon309 | 0:666850d06c9f | 490 | * @} |
jhon309 | 0:666850d06c9f | 491 | */ |
jhon309 | 0:666850d06c9f | 492 | |
jhon309 | 0:666850d06c9f | 493 | /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source |
jhon309 | 0:666850d06c9f | 494 | * @{ |
jhon309 | 0:666850d06c9f | 495 | */ |
jhon309 | 0:666850d06c9f | 496 | #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK |
jhon309 | 0:666850d06c9f | 497 | #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI |
jhon309 | 0:666850d06c9f | 498 | #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE |
jhon309 | 0:666850d06c9f | 499 | #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK |
jhon309 | 0:666850d06c9f | 500 | #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI |
jhon309 | 0:666850d06c9f | 501 | #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE |
jhon309 | 0:666850d06c9f | 502 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL |
jhon309 | 0:666850d06c9f | 503 | #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14 |
jhon309 | 0:666850d06c9f | 504 | /** |
jhon309 | 0:666850d06c9f | 505 | * @} |
jhon309 | 0:666850d06c9f | 506 | */ |
jhon309 | 0:666850d06c9f | 507 | |
jhon309 | 0:666850d06c9f | 508 | /** @defgroup RCC_Interrupt RCC Interrupt |
jhon309 | 0:666850d06c9f | 509 | * @{ |
jhon309 | 0:666850d06c9f | 510 | */ |
jhon309 | 0:666850d06c9f | 511 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
jhon309 | 0:666850d06c9f | 512 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
jhon309 | 0:666850d06c9f | 513 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
jhon309 | 0:666850d06c9f | 514 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
jhon309 | 0:666850d06c9f | 515 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
jhon309 | 0:666850d06c9f | 516 | #define RCC_IT_HSI14 ((uint8_t)0x20) |
jhon309 | 0:666850d06c9f | 517 | #define RCC_IT_CSS ((uint8_t)0x80) |
jhon309 | 0:666850d06c9f | 518 | /** |
jhon309 | 0:666850d06c9f | 519 | * @} |
jhon309 | 0:666850d06c9f | 520 | */ |
jhon309 | 0:666850d06c9f | 521 | |
jhon309 | 0:666850d06c9f | 522 | /** @defgroup RCC_Flag RCC Flag |
jhon309 | 0:666850d06c9f | 523 | * Elements values convention: 0XXYYYYYb |
jhon309 | 0:666850d06c9f | 524 | * - YYYYY : Flag position in the register |
jhon309 | 0:666850d06c9f | 525 | * - XX : Register index |
jhon309 | 0:666850d06c9f | 526 | * - 00: CR register |
jhon309 | 0:666850d06c9f | 527 | * - 01: CR2 register |
jhon309 | 0:666850d06c9f | 528 | * - 10: BDCR register |
jhon309 | 0:666850d06c9f | 529 | * - 11: CSR register |
jhon309 | 0:666850d06c9f | 530 | * @{ |
jhon309 | 0:666850d06c9f | 531 | */ |
jhon309 | 0:666850d06c9f | 532 | #define CR_REG_INDEX 0 |
jhon309 | 0:666850d06c9f | 533 | #define CR2_REG_INDEX 1 |
jhon309 | 0:666850d06c9f | 534 | #define BDCR_REG_INDEX 2 |
jhon309 | 0:666850d06c9f | 535 | #define CSR_REG_INDEX 3 |
jhon309 | 0:666850d06c9f | 536 | |
jhon309 | 0:666850d06c9f | 537 | /* Flags in the CR register */ |
jhon309 | 0:666850d06c9f | 538 | #define RCC_CR_HSIRDY_BitNumber 1 |
jhon309 | 0:666850d06c9f | 539 | #define RCC_CR_HSERDY_BitNumber 17 |
jhon309 | 0:666850d06c9f | 540 | #define RCC_CR_PLLRDY_BitNumber 25 |
jhon309 | 0:666850d06c9f | 541 | |
jhon309 | 0:666850d06c9f | 542 | #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 543 | #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 544 | #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 545 | |
jhon309 | 0:666850d06c9f | 546 | /* Flags in the CR2 register */ |
jhon309 | 0:666850d06c9f | 547 | #define RCC_CR2_HSI14RDY_BitNumber 1 |
jhon309 | 0:666850d06c9f | 548 | |
jhon309 | 0:666850d06c9f | 549 | #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 550 | |
jhon309 | 0:666850d06c9f | 551 | /* Flags in the BDCR register */ |
jhon309 | 0:666850d06c9f | 552 | #define RCC_BDCR_LSERDY_BitNumber 1 |
jhon309 | 0:666850d06c9f | 553 | |
jhon309 | 0:666850d06c9f | 554 | #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 555 | |
jhon309 | 0:666850d06c9f | 556 | /* Flags in the CSR register */ |
jhon309 | 0:666850d06c9f | 557 | #define RCC_CSR_LSIRDY_BitNumber 1 |
jhon309 | 0:666850d06c9f | 558 | #define RCC_CSR_V18PWRRSTF_BitNumber 23 |
jhon309 | 0:666850d06c9f | 559 | #define RCC_CSR_RMVF_BitNumber 24 |
jhon309 | 0:666850d06c9f | 560 | #define RCC_CSR_OBLRSTF_BitNumber 25 |
jhon309 | 0:666850d06c9f | 561 | #define RCC_CSR_PINRSTF_BitNumber 26 |
jhon309 | 0:666850d06c9f | 562 | #define RCC_CSR_PORRSTF_BitNumber 27 |
jhon309 | 0:666850d06c9f | 563 | #define RCC_CSR_SFTRSTF_BitNumber 28 |
jhon309 | 0:666850d06c9f | 564 | #define RCC_CSR_IWDGRSTF_BitNumber 29 |
jhon309 | 0:666850d06c9f | 565 | #define RCC_CSR_WWDGRSTF_BitNumber 30 |
jhon309 | 0:666850d06c9f | 566 | #define RCC_CSR_LPWRRSTF_BitNumber 31 |
jhon309 | 0:666850d06c9f | 567 | |
jhon309 | 0:666850d06c9f | 568 | #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 569 | #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) |
jhon309 | 0:666850d06c9f | 570 | #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber)) |
jhon309 | 0:666850d06c9f | 571 | #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 572 | #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 573 | #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 574 | #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 575 | #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 576 | #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 577 | #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber)) |
jhon309 | 0:666850d06c9f | 578 | /** |
jhon309 | 0:666850d06c9f | 579 | * @} |
jhon309 | 0:666850d06c9f | 580 | */ |
jhon309 | 0:666850d06c9f | 581 | |
jhon309 | 0:666850d06c9f | 582 | /** @defgroup RCC_Calibration_values RCC Calibration values |
jhon309 | 0:666850d06c9f | 583 | * @{ |
jhon309 | 0:666850d06c9f | 584 | */ |
jhon309 | 0:666850d06c9f | 585 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
jhon309 | 0:666850d06c9f | 586 | |
jhon309 | 0:666850d06c9f | 587 | /** |
jhon309 | 0:666850d06c9f | 588 | * @} |
jhon309 | 0:666850d06c9f | 589 | */ |
jhon309 | 0:666850d06c9f | 590 | |
jhon309 | 0:666850d06c9f | 591 | /** @addtogroup RCC_Timeout |
jhon309 | 0:666850d06c9f | 592 | * @{ |
jhon309 | 0:666850d06c9f | 593 | */ |
jhon309 | 0:666850d06c9f | 594 | |
jhon309 | 0:666850d06c9f | 595 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
jhon309 | 0:666850d06c9f | 596 | #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
jhon309 | 0:666850d06c9f | 597 | #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
jhon309 | 0:666850d06c9f | 598 | #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
jhon309 | 0:666850d06c9f | 599 | #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
jhon309 | 0:666850d06c9f | 600 | #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
jhon309 | 0:666850d06c9f | 601 | #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
jhon309 | 0:666850d06c9f | 602 | #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
jhon309 | 0:666850d06c9f | 603 | |
jhon309 | 0:666850d06c9f | 604 | /** |
jhon309 | 0:666850d06c9f | 605 | * @} |
jhon309 | 0:666850d06c9f | 606 | */ |
jhon309 | 0:666850d06c9f | 607 | |
jhon309 | 0:666850d06c9f | 608 | /** |
jhon309 | 0:666850d06c9f | 609 | * @} |
jhon309 | 0:666850d06c9f | 610 | */ |
jhon309 | 0:666850d06c9f | 611 | |
jhon309 | 0:666850d06c9f | 612 | /* Exported macro ------------------------------------------------------------*/ |
jhon309 | 0:666850d06c9f | 613 | |
jhon309 | 0:666850d06c9f | 614 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
jhon309 | 0:666850d06c9f | 615 | * @{ |
jhon309 | 0:666850d06c9f | 616 | */ |
jhon309 | 0:666850d06c9f | 617 | |
jhon309 | 0:666850d06c9f | 618 | /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable |
jhon309 | 0:666850d06c9f | 619 | * @brief Enable or disable the AHB peripheral clock. |
jhon309 | 0:666850d06c9f | 620 | * @note After reset, the peripheral clock (used for registers read/write access) |
jhon309 | 0:666850d06c9f | 621 | * is disabled and the application software has to enable this clock before |
jhon309 | 0:666850d06c9f | 622 | * using it. |
jhon309 | 0:666850d06c9f | 623 | * @{ |
jhon309 | 0:666850d06c9f | 624 | */ |
jhon309 | 0:666850d06c9f | 625 | #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) |
jhon309 | 0:666850d06c9f | 626 | #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) |
jhon309 | 0:666850d06c9f | 627 | #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) |
jhon309 | 0:666850d06c9f | 628 | #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) |
jhon309 | 0:666850d06c9f | 629 | #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) |
jhon309 | 0:666850d06c9f | 630 | #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) |
jhon309 | 0:666850d06c9f | 631 | #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN)) |
jhon309 | 0:666850d06c9f | 632 | #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) |
jhon309 | 0:666850d06c9f | 633 | |
jhon309 | 0:666850d06c9f | 634 | #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) |
jhon309 | 0:666850d06c9f | 635 | #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) |
jhon309 | 0:666850d06c9f | 636 | #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) |
jhon309 | 0:666850d06c9f | 637 | #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
jhon309 | 0:666850d06c9f | 638 | #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
jhon309 | 0:666850d06c9f | 639 | #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
jhon309 | 0:666850d06c9f | 640 | #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
jhon309 | 0:666850d06c9f | 641 | #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
jhon309 | 0:666850d06c9f | 642 | /** |
jhon309 | 0:666850d06c9f | 643 | * @} |
jhon309 | 0:666850d06c9f | 644 | */ |
jhon309 | 0:666850d06c9f | 645 | |
jhon309 | 0:666850d06c9f | 646 | /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable |
jhon309 | 0:666850d06c9f | 647 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
jhon309 | 0:666850d06c9f | 648 | * @note After reset, the peripheral clock (used for registers read/write access) |
jhon309 | 0:666850d06c9f | 649 | * is disabled and the application software has to enable this clock before |
jhon309 | 0:666850d06c9f | 650 | * using it. |
jhon309 | 0:666850d06c9f | 651 | * @{ |
jhon309 | 0:666850d06c9f | 652 | */ |
jhon309 | 0:666850d06c9f | 653 | #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) |
jhon309 | 0:666850d06c9f | 654 | #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) |
jhon309 | 0:666850d06c9f | 655 | #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) |
jhon309 | 0:666850d06c9f | 656 | #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) |
jhon309 | 0:666850d06c9f | 657 | #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) |
jhon309 | 0:666850d06c9f | 658 | |
jhon309 | 0:666850d06c9f | 659 | #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
jhon309 | 0:666850d06c9f | 660 | #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
jhon309 | 0:666850d06c9f | 661 | #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
jhon309 | 0:666850d06c9f | 662 | #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
jhon309 | 0:666850d06c9f | 663 | #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
jhon309 | 0:666850d06c9f | 664 | /** |
jhon309 | 0:666850d06c9f | 665 | * @} |
jhon309 | 0:666850d06c9f | 666 | */ |
jhon309 | 0:666850d06c9f | 667 | |
jhon309 | 0:666850d06c9f | 668 | /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable |
jhon309 | 0:666850d06c9f | 669 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
jhon309 | 0:666850d06c9f | 670 | * @note After reset, the peripheral clock (used for registers read/write access) |
jhon309 | 0:666850d06c9f | 671 | * is disabled and the application software has to enable this clock before |
jhon309 | 0:666850d06c9f | 672 | * using it. |
jhon309 | 0:666850d06c9f | 673 | * @{ |
jhon309 | 0:666850d06c9f | 674 | */ |
jhon309 | 0:666850d06c9f | 675 | #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) |
jhon309 | 0:666850d06c9f | 676 | #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) |
jhon309 | 0:666850d06c9f | 677 | #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN)) |
jhon309 | 0:666850d06c9f | 678 | #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) |
jhon309 | 0:666850d06c9f | 679 | #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN)) |
jhon309 | 0:666850d06c9f | 680 | #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN)) |
jhon309 | 0:666850d06c9f | 681 | #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) |
jhon309 | 0:666850d06c9f | 682 | #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN)) |
jhon309 | 0:666850d06c9f | 683 | |
jhon309 | 0:666850d06c9f | 684 | #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
jhon309 | 0:666850d06c9f | 685 | #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
jhon309 | 0:666850d06c9f | 686 | #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
jhon309 | 0:666850d06c9f | 687 | #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
jhon309 | 0:666850d06c9f | 688 | #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
jhon309 | 0:666850d06c9f | 689 | #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
jhon309 | 0:666850d06c9f | 690 | #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
jhon309 | 0:666850d06c9f | 691 | #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) |
jhon309 | 0:666850d06c9f | 692 | /** |
jhon309 | 0:666850d06c9f | 693 | * @} |
jhon309 | 0:666850d06c9f | 694 | */ |
jhon309 | 0:666850d06c9f | 695 | |
jhon309 | 0:666850d06c9f | 696 | /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset |
jhon309 | 0:666850d06c9f | 697 | * @brief Force or release AHB peripheral reset. |
jhon309 | 0:666850d06c9f | 698 | * @{ |
jhon309 | 0:666850d06c9f | 699 | */ |
jhon309 | 0:666850d06c9f | 700 | #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) |
jhon309 | 0:666850d06c9f | 701 | #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) |
jhon309 | 0:666850d06c9f | 702 | #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) |
jhon309 | 0:666850d06c9f | 703 | #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) |
jhon309 | 0:666850d06c9f | 704 | #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
jhon309 | 0:666850d06c9f | 705 | |
jhon309 | 0:666850d06c9f | 706 | #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) |
jhon309 | 0:666850d06c9f | 707 | #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) |
jhon309 | 0:666850d06c9f | 708 | #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) |
jhon309 | 0:666850d06c9f | 709 | #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) |
jhon309 | 0:666850d06c9f | 710 | #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
jhon309 | 0:666850d06c9f | 711 | /** |
jhon309 | 0:666850d06c9f | 712 | * @} |
jhon309 | 0:666850d06c9f | 713 | */ |
jhon309 | 0:666850d06c9f | 714 | |
jhon309 | 0:666850d06c9f | 715 | /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset |
jhon309 | 0:666850d06c9f | 716 | * @brief Force or release APB1 peripheral reset. |
jhon309 | 0:666850d06c9f | 717 | * @{ |
jhon309 | 0:666850d06c9f | 718 | */ |
jhon309 | 0:666850d06c9f | 719 | #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) |
jhon309 | 0:666850d06c9f | 720 | #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
jhon309 | 0:666850d06c9f | 721 | #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
jhon309 | 0:666850d06c9f | 722 | #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
jhon309 | 0:666850d06c9f | 723 | #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
jhon309 | 0:666850d06c9f | 724 | #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
jhon309 | 0:666850d06c9f | 725 | |
jhon309 | 0:666850d06c9f | 726 | #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
jhon309 | 0:666850d06c9f | 727 | #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
jhon309 | 0:666850d06c9f | 728 | #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
jhon309 | 0:666850d06c9f | 729 | #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
jhon309 | 0:666850d06c9f | 730 | #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
jhon309 | 0:666850d06c9f | 731 | #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
jhon309 | 0:666850d06c9f | 732 | /** |
jhon309 | 0:666850d06c9f | 733 | * @} |
jhon309 | 0:666850d06c9f | 734 | */ |
jhon309 | 0:666850d06c9f | 735 | |
jhon309 | 0:666850d06c9f | 736 | /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset |
jhon309 | 0:666850d06c9f | 737 | * @brief Force or release APB2 peripheral reset. |
jhon309 | 0:666850d06c9f | 738 | * @{ |
jhon309 | 0:666850d06c9f | 739 | */ |
jhon309 | 0:666850d06c9f | 740 | #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) |
jhon309 | 0:666850d06c9f | 741 | #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
jhon309 | 0:666850d06c9f | 742 | #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) |
jhon309 | 0:666850d06c9f | 743 | #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
jhon309 | 0:666850d06c9f | 744 | #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
jhon309 | 0:666850d06c9f | 745 | #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
jhon309 | 0:666850d06c9f | 746 | #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
jhon309 | 0:666850d06c9f | 747 | #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
jhon309 | 0:666850d06c9f | 748 | #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) |
jhon309 | 0:666850d06c9f | 749 | |
jhon309 | 0:666850d06c9f | 750 | #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
jhon309 | 0:666850d06c9f | 751 | #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
jhon309 | 0:666850d06c9f | 752 | #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) |
jhon309 | 0:666850d06c9f | 753 | #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
jhon309 | 0:666850d06c9f | 754 | #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
jhon309 | 0:666850d06c9f | 755 | #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
jhon309 | 0:666850d06c9f | 756 | #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
jhon309 | 0:666850d06c9f | 757 | #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
jhon309 | 0:666850d06c9f | 758 | #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) |
jhon309 | 0:666850d06c9f | 759 | /** |
jhon309 | 0:666850d06c9f | 760 | * @} |
jhon309 | 0:666850d06c9f | 761 | */ |
jhon309 | 0:666850d06c9f | 762 | |
jhon309 | 0:666850d06c9f | 763 | /** @defgroup RCC_HSI_Configuration RCC HSI Configuration |
jhon309 | 0:666850d06c9f | 764 | * @{ |
jhon309 | 0:666850d06c9f | 765 | */ |
jhon309 | 0:666850d06c9f | 766 | |
jhon309 | 0:666850d06c9f | 767 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
jhon309 | 0:666850d06c9f | 768 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
jhon309 | 0:666850d06c9f | 769 | * It is used (enabled by hardware) as system clock source after startup |
jhon309 | 0:666850d06c9f | 770 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
jhon309 | 0:666850d06c9f | 771 | * of the HSE used directly or indirectly as system clock (if the Clock |
jhon309 | 0:666850d06c9f | 772 | * Security System CSS is enabled). |
jhon309 | 0:666850d06c9f | 773 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
jhon309 | 0:666850d06c9f | 774 | * you have to select another source of the system clock then stop the HSI. |
jhon309 | 0:666850d06c9f | 775 | * @note After enabling the HSI, the application software should wait on HSIRDY |
jhon309 | 0:666850d06c9f | 776 | * flag to be set indicating that HSI clock is stable and can be used as |
jhon309 | 0:666850d06c9f | 777 | * system clock source. |
jhon309 | 0:666850d06c9f | 778 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
jhon309 | 0:666850d06c9f | 779 | * clock cycles. |
jhon309 | 0:666850d06c9f | 780 | */ |
jhon309 | 0:666850d06c9f | 781 | #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) |
jhon309 | 0:666850d06c9f | 782 | #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) |
jhon309 | 0:666850d06c9f | 783 | |
jhon309 | 0:666850d06c9f | 784 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
jhon309 | 0:666850d06c9f | 785 | * @note The calibration is used to compensate for the variations in voltage |
jhon309 | 0:666850d06c9f | 786 | * and temperature that influence the frequency of the internal HSI RC. |
jhon309 | 0:666850d06c9f | 787 | * @param __HSICalibrationValue__: specifies the calibration trimming value |
jhon309 | 0:666850d06c9f | 788 | * (default is RCC_HSICALIBRATION_DEFAULT). |
jhon309 | 0:666850d06c9f | 789 | * This parameter must be a number between 0 and 0x1F. |
jhon309 | 0:666850d06c9f | 790 | */ |
jhon309 | 0:666850d06c9f | 791 | #define RCC_CR_HSITRIM_BitNumber 3 |
jhon309 | 0:666850d06c9f | 792 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ |
jhon309 | 0:666850d06c9f | 793 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber) |
jhon309 | 0:666850d06c9f | 794 | /** |
jhon309 | 0:666850d06c9f | 795 | * @} |
jhon309 | 0:666850d06c9f | 796 | */ |
jhon309 | 0:666850d06c9f | 797 | |
jhon309 | 0:666850d06c9f | 798 | /** @defgroup RCC_LSI_Configuration RCC LSI Configuration |
jhon309 | 0:666850d06c9f | 799 | * @{ |
jhon309 | 0:666850d06c9f | 800 | */ |
jhon309 | 0:666850d06c9f | 801 | |
jhon309 | 0:666850d06c9f | 802 | /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI). |
jhon309 | 0:666850d06c9f | 803 | * @note After enabling the LSI, the application software should wait on |
jhon309 | 0:666850d06c9f | 804 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
jhon309 | 0:666850d06c9f | 805 | * be used to clock the IWDG and/or the RTC. |
jhon309 | 0:666850d06c9f | 806 | * @note LSI can not be disabled if the IWDG is running. |
jhon309 | 0:666850d06c9f | 807 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
jhon309 | 0:666850d06c9f | 808 | * clock cycles. |
jhon309 | 0:666850d06c9f | 809 | */ |
jhon309 | 0:666850d06c9f | 810 | #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) |
jhon309 | 0:666850d06c9f | 811 | #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) |
jhon309 | 0:666850d06c9f | 812 | /** |
jhon309 | 0:666850d06c9f | 813 | * @} |
jhon309 | 0:666850d06c9f | 814 | */ |
jhon309 | 0:666850d06c9f | 815 | |
jhon309 | 0:666850d06c9f | 816 | /** @defgroup RCC_HSE_Configuration RCC HSE Configuration |
jhon309 | 0:666850d06c9f | 817 | * @{ |
jhon309 | 0:666850d06c9f | 818 | */ |
jhon309 | 0:666850d06c9f | 819 | |
jhon309 | 0:666850d06c9f | 820 | /** |
jhon309 | 0:666850d06c9f | 821 | * @brief Macro to configure the External High Speed oscillator (HSE). |
jhon309 | 0:666850d06c9f | 822 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
jhon309 | 0:666850d06c9f | 823 | * software should wait on HSERDY flag to be set indicating that HSE clock |
jhon309 | 0:666850d06c9f | 824 | * is stable and can be used to clock the PLL and/or system clock. |
jhon309 | 0:666850d06c9f | 825 | * @note HSE state can not be changed if it is used directly or through the |
jhon309 | 0:666850d06c9f | 826 | * PLL as system clock. In this case, you have to select another source |
jhon309 | 0:666850d06c9f | 827 | * of the system clock then change the HSE state (ex. disable it). |
jhon309 | 0:666850d06c9f | 828 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
jhon309 | 0:666850d06c9f | 829 | * @note This function reset the CSSON bit, so if the Clock security system(CSS) |
jhon309 | 0:666850d06c9f | 830 | * was previously enabled you have to enable it again after calling this |
jhon309 | 0:666850d06c9f | 831 | * function. |
jhon309 | 0:666850d06c9f | 832 | * @param __STATE__: specifies the new state of the HSE. |
jhon309 | 0:666850d06c9f | 833 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 834 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
jhon309 | 0:666850d06c9f | 835 | * 6 HSE oscillator clock cycles. |
jhon309 | 0:666850d06c9f | 836 | * @arg RCC_HSE_ON: turn ON the HSE oscillator |
jhon309 | 0:666850d06c9f | 837 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock |
jhon309 | 0:666850d06c9f | 838 | */ |
jhon309 | 0:666850d06c9f | 839 | #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__)) |
jhon309 | 0:666850d06c9f | 840 | |
jhon309 | 0:666850d06c9f | 841 | /** |
jhon309 | 0:666850d06c9f | 842 | * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. |
jhon309 | 0:666850d06c9f | 843 | * @note Predivision factor can not be changed if PLL is used as system clock |
jhon309 | 0:666850d06c9f | 844 | * In this case, you have to select another source of the system clock, disable the PLL and |
jhon309 | 0:666850d06c9f | 845 | * then change the HSE predivision factor. |
jhon309 | 0:666850d06c9f | 846 | * @param __HSEPredivValue__: specifies the division value applied to HSE. |
jhon309 | 0:666850d06c9f | 847 | * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. |
jhon309 | 0:666850d06c9f | 848 | */ |
jhon309 | 0:666850d06c9f | 849 | #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \ |
jhon309 | 0:666850d06c9f | 850 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__)) |
jhon309 | 0:666850d06c9f | 851 | /** |
jhon309 | 0:666850d06c9f | 852 | * @} |
jhon309 | 0:666850d06c9f | 853 | */ |
jhon309 | 0:666850d06c9f | 854 | |
jhon309 | 0:666850d06c9f | 855 | /** @defgroup RCC_LSE_Configuration RCC LSE Configuration |
jhon309 | 0:666850d06c9f | 856 | * @{ |
jhon309 | 0:666850d06c9f | 857 | */ |
jhon309 | 0:666850d06c9f | 858 | /** |
jhon309 | 0:666850d06c9f | 859 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
jhon309 | 0:666850d06c9f | 860 | * @note As the LSE is in the Backup domain and write access is denied to |
jhon309 | 0:666850d06c9f | 861 | * this domain after reset, you have to enable write access using |
jhon309 | 0:666850d06c9f | 862 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
jhon309 | 0:666850d06c9f | 863 | * (to be done once after reset). |
jhon309 | 0:666850d06c9f | 864 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
jhon309 | 0:666850d06c9f | 865 | * software should wait on LSERDY flag to be set indicating that LSE clock |
jhon309 | 0:666850d06c9f | 866 | * is stable and can be used to clock the RTC. |
jhon309 | 0:666850d06c9f | 867 | * @param __STATE__: specifies the new state of the LSE. |
jhon309 | 0:666850d06c9f | 868 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 869 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
jhon309 | 0:666850d06c9f | 870 | * 6 LSE oscillator clock cycles. |
jhon309 | 0:666850d06c9f | 871 | * @arg RCC_LSE_ON: turn ON the LSE oscillator |
jhon309 | 0:666850d06c9f | 872 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock |
jhon309 | 0:666850d06c9f | 873 | */ |
jhon309 | 0:666850d06c9f | 874 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
jhon309 | 0:666850d06c9f | 875 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__)) |
jhon309 | 0:666850d06c9f | 876 | /** |
jhon309 | 0:666850d06c9f | 877 | * @} |
jhon309 | 0:666850d06c9f | 878 | */ |
jhon309 | 0:666850d06c9f | 879 | |
jhon309 | 0:666850d06c9f | 880 | /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration |
jhon309 | 0:666850d06c9f | 881 | * @{ |
jhon309 | 0:666850d06c9f | 882 | */ |
jhon309 | 0:666850d06c9f | 883 | |
jhon309 | 0:666850d06c9f | 884 | /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14). |
jhon309 | 0:666850d06c9f | 885 | * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. |
jhon309 | 0:666850d06c9f | 886 | * @note HSI14 can not be stopped if it is used as system clock source. In this case, |
jhon309 | 0:666850d06c9f | 887 | * you have to select another source of the system clock then stop the HSI14. |
jhon309 | 0:666850d06c9f | 888 | * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software |
jhon309 | 0:666850d06c9f | 889 | * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be |
jhon309 | 0:666850d06c9f | 890 | * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. |
jhon309 | 0:666850d06c9f | 891 | * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator |
jhon309 | 0:666850d06c9f | 892 | * clock cycles. |
jhon309 | 0:666850d06c9f | 893 | */ |
jhon309 | 0:666850d06c9f | 894 | #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) |
jhon309 | 0:666850d06c9f | 895 | #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) |
jhon309 | 0:666850d06c9f | 896 | |
jhon309 | 0:666850d06c9f | 897 | /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC. |
jhon309 | 0:666850d06c9f | 898 | */ |
jhon309 | 0:666850d06c9f | 899 | #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) |
jhon309 | 0:666850d06c9f | 900 | #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) |
jhon309 | 0:666850d06c9f | 901 | |
jhon309 | 0:666850d06c9f | 902 | /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. |
jhon309 | 0:666850d06c9f | 903 | * @note The calibration is used to compensate for the variations in voltage |
jhon309 | 0:666850d06c9f | 904 | * and temperature that influence the frequency of the internal HSI14 RC. |
jhon309 | 0:666850d06c9f | 905 | * @param __HSI14CalibrationValue__: specifies the calibration trimming value |
jhon309 | 0:666850d06c9f | 906 | * (default is RCC_HSI14CALIBRATION_DEFAULT). |
jhon309 | 0:666850d06c9f | 907 | * This parameter must be a number between 0 and 0x1F. |
jhon309 | 0:666850d06c9f | 908 | */ |
jhon309 | 0:666850d06c9f | 909 | #define RCC_CR2_HSI14TRIM_BitNumber 3 |
jhon309 | 0:666850d06c9f | 910 | #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \ |
jhon309 | 0:666850d06c9f | 911 | MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber) |
jhon309 | 0:666850d06c9f | 912 | /** |
jhon309 | 0:666850d06c9f | 913 | * @} |
jhon309 | 0:666850d06c9f | 914 | */ |
jhon309 | 0:666850d06c9f | 915 | |
jhon309 | 0:666850d06c9f | 916 | /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config |
jhon309 | 0:666850d06c9f | 917 | * @{ |
jhon309 | 0:666850d06c9f | 918 | */ |
jhon309 | 0:666850d06c9f | 919 | |
jhon309 | 0:666850d06c9f | 920 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
jhon309 | 0:666850d06c9f | 921 | * @param __USART1CLKSource__: specifies the USART1 clock source. |
jhon309 | 0:666850d06c9f | 922 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 923 | * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock |
jhon309 | 0:666850d06c9f | 924 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
jhon309 | 0:666850d06c9f | 925 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
jhon309 | 0:666850d06c9f | 926 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
jhon309 | 0:666850d06c9f | 927 | */ |
jhon309 | 0:666850d06c9f | 928 | #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ |
jhon309 | 0:666850d06c9f | 929 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__)) |
jhon309 | 0:666850d06c9f | 930 | |
jhon309 | 0:666850d06c9f | 931 | /** @brief Macro to get the USART1 clock source. |
jhon309 | 0:666850d06c9f | 932 | * @retval The clock source can be one of the following values: |
jhon309 | 0:666850d06c9f | 933 | * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock |
jhon309 | 0:666850d06c9f | 934 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
jhon309 | 0:666850d06c9f | 935 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
jhon309 | 0:666850d06c9f | 936 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
jhon309 | 0:666850d06c9f | 937 | */ |
jhon309 | 0:666850d06c9f | 938 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) |
jhon309 | 0:666850d06c9f | 939 | /** |
jhon309 | 0:666850d06c9f | 940 | * @} |
jhon309 | 0:666850d06c9f | 941 | */ |
jhon309 | 0:666850d06c9f | 942 | |
jhon309 | 0:666850d06c9f | 943 | /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config |
jhon309 | 0:666850d06c9f | 944 | * @{ |
jhon309 | 0:666850d06c9f | 945 | */ |
jhon309 | 0:666850d06c9f | 946 | |
jhon309 | 0:666850d06c9f | 947 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
jhon309 | 0:666850d06c9f | 948 | * @param __I2C1CLKSource__: specifies the I2C1 clock source. |
jhon309 | 0:666850d06c9f | 949 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 950 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
jhon309 | 0:666850d06c9f | 951 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
jhon309 | 0:666850d06c9f | 952 | */ |
jhon309 | 0:666850d06c9f | 953 | #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ |
jhon309 | 0:666850d06c9f | 954 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__)) |
jhon309 | 0:666850d06c9f | 955 | |
jhon309 | 0:666850d06c9f | 956 | /** @brief Macro to get the I2C1 clock source. |
jhon309 | 0:666850d06c9f | 957 | * @retval The clock source can be one of the following values: |
jhon309 | 0:666850d06c9f | 958 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
jhon309 | 0:666850d06c9f | 959 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
jhon309 | 0:666850d06c9f | 960 | */ |
jhon309 | 0:666850d06c9f | 961 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) |
jhon309 | 0:666850d06c9f | 962 | /** |
jhon309 | 0:666850d06c9f | 963 | * @} |
jhon309 | 0:666850d06c9f | 964 | */ |
jhon309 | 0:666850d06c9f | 965 | |
jhon309 | 0:666850d06c9f | 966 | /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration |
jhon309 | 0:666850d06c9f | 967 | * @{ |
jhon309 | 0:666850d06c9f | 968 | */ |
jhon309 | 0:666850d06c9f | 969 | /** @brief Macros to enable or disable the the RTC clock. |
jhon309 | 0:666850d06c9f | 970 | * @note These macros must be used only after the RTC clock source was selected. |
jhon309 | 0:666850d06c9f | 971 | */ |
jhon309 | 0:666850d06c9f | 972 | #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
jhon309 | 0:666850d06c9f | 973 | #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
jhon309 | 0:666850d06c9f | 974 | |
jhon309 | 0:666850d06c9f | 975 | /** @brief Macro to configure the RTC clock (RTCCLK). |
jhon309 | 0:666850d06c9f | 976 | * @note As the RTC clock configuration bits are in the Backup domain and write |
jhon309 | 0:666850d06c9f | 977 | * access is denied to this domain after reset, you have to enable write |
jhon309 | 0:666850d06c9f | 978 | * access using the Power Backup Access macro before to configure |
jhon309 | 0:666850d06c9f | 979 | * the RTC clock source (to be done once after reset). |
jhon309 | 0:666850d06c9f | 980 | * @note Once the RTC clock is configured it can't be changed unless the |
jhon309 | 0:666850d06c9f | 981 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
jhon309 | 0:666850d06c9f | 982 | * a Power On Reset (POR). |
jhon309 | 0:666850d06c9f | 983 | * @param __RTCCLKSource__: specifies the RTC clock source. |
jhon309 | 0:666850d06c9f | 984 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 985 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
jhon309 | 0:666850d06c9f | 986 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
jhon309 | 0:666850d06c9f | 987 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
jhon309 | 0:666850d06c9f | 988 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 |
jhon309 | 0:666850d06c9f | 989 | * |
jhon309 | 0:666850d06c9f | 990 | * @note If the LSE is used as RTC clock source, the RTC continues to |
jhon309 | 0:666850d06c9f | 991 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
jhon309 | 0:666850d06c9f | 992 | * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, |
jhon309 | 0:666850d06c9f | 993 | * the RTC cannot be used in STOP and STANDBY modes. |
jhon309 | 0:666850d06c9f | 994 | * @note The system must always be configured so as to get a PCLK frequency greater than or |
jhon309 | 0:666850d06c9f | 995 | * equal to the RTCCLK frequency for a proper operation of the RTC. |
jhon309 | 0:666850d06c9f | 996 | */ |
jhon309 | 0:666850d06c9f | 997 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ |
jhon309 | 0:666850d06c9f | 998 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__)) |
jhon309 | 0:666850d06c9f | 999 | |
jhon309 | 0:666850d06c9f | 1000 | /** @brief Macro to get the RTC clock source. |
jhon309 | 0:666850d06c9f | 1001 | * @retval The clock source can be one of the following values: |
jhon309 | 0:666850d06c9f | 1002 | * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock |
jhon309 | 0:666850d06c9f | 1003 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock |
jhon309 | 0:666850d06c9f | 1004 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock |
jhon309 | 0:666850d06c9f | 1005 | * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock |
jhon309 | 0:666850d06c9f | 1006 | */ |
jhon309 | 0:666850d06c9f | 1007 | #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) |
jhon309 | 0:666850d06c9f | 1008 | /** |
jhon309 | 0:666850d06c9f | 1009 | * @} |
jhon309 | 0:666850d06c9f | 1010 | */ |
jhon309 | 0:666850d06c9f | 1011 | |
jhon309 | 0:666850d06c9f | 1012 | /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup |
jhon309 | 0:666850d06c9f | 1013 | * @{ |
jhon309 | 0:666850d06c9f | 1014 | */ |
jhon309 | 0:666850d06c9f | 1015 | |
jhon309 | 0:666850d06c9f | 1016 | /** @brief Macro to force or release the Backup domain reset. |
jhon309 | 0:666850d06c9f | 1017 | * @note These macros reset the RTC peripheral (including the backup registers) |
jhon309 | 0:666850d06c9f | 1018 | * and the RTC clock source selection in RCC_CSR register. |
jhon309 | 0:666850d06c9f | 1019 | * @note The BKPSRAM is not affected by this reset. |
jhon309 | 0:666850d06c9f | 1020 | */ |
jhon309 | 0:666850d06c9f | 1021 | #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
jhon309 | 0:666850d06c9f | 1022 | #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
jhon309 | 0:666850d06c9f | 1023 | /** |
jhon309 | 0:666850d06c9f | 1024 | * @} |
jhon309 | 0:666850d06c9f | 1025 | */ |
jhon309 | 0:666850d06c9f | 1026 | |
jhon309 | 0:666850d06c9f | 1027 | /** @defgroup RCC_PLL_Configuration RCC PLL Configuration |
jhon309 | 0:666850d06c9f | 1028 | * @{ |
jhon309 | 0:666850d06c9f | 1029 | */ |
jhon309 | 0:666850d06c9f | 1030 | |
jhon309 | 0:666850d06c9f | 1031 | /** @brief Macro to enable or disable the PLL. |
jhon309 | 0:666850d06c9f | 1032 | * @note After enabling the PLL, the application software should wait on |
jhon309 | 0:666850d06c9f | 1033 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
jhon309 | 0:666850d06c9f | 1034 | * be used as system clock source. |
jhon309 | 0:666850d06c9f | 1035 | * @note The PLL can not be disabled if it is used as system clock source |
jhon309 | 0:666850d06c9f | 1036 | * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. |
jhon309 | 0:666850d06c9f | 1037 | */ |
jhon309 | 0:666850d06c9f | 1038 | #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
jhon309 | 0:666850d06c9f | 1039 | #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
jhon309 | 0:666850d06c9f | 1040 | |
jhon309 | 0:666850d06c9f | 1041 | /** @brief Macro to configure the PLL clock source, multiplication and division factors. |
jhon309 | 0:666850d06c9f | 1042 | * @note This macro must be used only when the PLL is disabled. |
jhon309 | 0:666850d06c9f | 1043 | * |
jhon309 | 0:666850d06c9f | 1044 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
jhon309 | 0:666850d06c9f | 1045 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 1046 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
jhon309 | 0:666850d06c9f | 1047 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
jhon309 | 0:666850d06c9f | 1048 | * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock |
jhon309 | 0:666850d06c9f | 1049 | * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. |
jhon309 | 0:666850d06c9f | 1050 | * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock |
jhon309 | 0:666850d06c9f | 1051 | * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. |
jhon309 | 0:666850d06c9f | 1052 | * |
jhon309 | 0:666850d06c9f | 1053 | */ |
jhon309 | 0:666850d06c9f | 1054 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ |
jhon309 | 0:666850d06c9f | 1055 | do { \ |
jhon309 | 0:666850d06c9f | 1056 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ |
jhon309 | 0:666850d06c9f | 1057 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ |
jhon309 | 0:666850d06c9f | 1058 | } while(0) |
jhon309 | 0:666850d06c9f | 1059 | /** |
jhon309 | 0:666850d06c9f | 1060 | * @} |
jhon309 | 0:666850d06c9f | 1061 | */ |
jhon309 | 0:666850d06c9f | 1062 | |
jhon309 | 0:666850d06c9f | 1063 | /** @defgroup RCC_Get_Clock_source RCC Get Clock source |
jhon309 | 0:666850d06c9f | 1064 | * @{ |
jhon309 | 0:666850d06c9f | 1065 | */ |
jhon309 | 0:666850d06c9f | 1066 | |
jhon309 | 0:666850d06c9f | 1067 | /** @brief Macro to get the clock source used as system clock. |
jhon309 | 0:666850d06c9f | 1068 | * @retval The clock source used as system clock. |
jhon309 | 0:666850d06c9f | 1069 | * The returned value can be one of the following value: |
jhon309 | 0:666850d06c9f | 1070 | * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock |
jhon309 | 0:666850d06c9f | 1071 | * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock |
jhon309 | 0:666850d06c9f | 1072 | * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock |
jhon309 | 0:666850d06c9f | 1073 | */ |
jhon309 | 0:666850d06c9f | 1074 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) |
jhon309 | 0:666850d06c9f | 1075 | |
jhon309 | 0:666850d06c9f | 1076 | /** @brief Macro to get the oscillator used as PLL clock source. |
jhon309 | 0:666850d06c9f | 1077 | * @retval The oscillator used as PLL clock source. The returned value can be one |
jhon309 | 0:666850d06c9f | 1078 | * of the following: |
jhon309 | 0:666850d06c9f | 1079 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
jhon309 | 0:666850d06c9f | 1080 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
jhon309 | 0:666850d06c9f | 1081 | */ |
jhon309 | 0:666850d06c9f | 1082 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
jhon309 | 0:666850d06c9f | 1083 | /** |
jhon309 | 0:666850d06c9f | 1084 | * @} |
jhon309 | 0:666850d06c9f | 1085 | */ |
jhon309 | 0:666850d06c9f | 1086 | |
jhon309 | 0:666850d06c9f | 1087 | /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management |
jhon309 | 0:666850d06c9f | 1088 | * @brief macros to manage the specified RCC Flags and interrupts. |
jhon309 | 0:666850d06c9f | 1089 | * @{ |
jhon309 | 0:666850d06c9f | 1090 | */ |
jhon309 | 0:666850d06c9f | 1091 | |
jhon309 | 0:666850d06c9f | 1092 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable |
jhon309 | 0:666850d06c9f | 1093 | * the selected interrupts.). |
jhon309 | 0:666850d06c9f | 1094 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
jhon309 | 0:666850d06c9f | 1095 | * This parameter can be any combination of the following values: |
jhon309 | 0:666850d06c9f | 1096 | * @arg RCC_IT_LSIRDY: LSI ready interrupt enable |
jhon309 | 0:666850d06c9f | 1097 | * @arg RCC_IT_LSERDY: LSE ready interrupt enable |
jhon309 | 0:666850d06c9f | 1098 | * @arg RCC_IT_HSIRDY: HSI ready interrupt enable |
jhon309 | 0:666850d06c9f | 1099 | * @arg RCC_IT_HSERDY: HSE ready interrupt enable |
jhon309 | 0:666850d06c9f | 1100 | * @arg RCC_IT_PLLRDY: PLL ready interrupt enable |
jhon309 | 0:666850d06c9f | 1101 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable |
jhon309 | 0:666850d06c9f | 1102 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) |
jhon309 | 0:666850d06c9f | 1103 | */ |
jhon309 | 0:666850d06c9f | 1104 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
jhon309 | 0:666850d06c9f | 1105 | |
jhon309 | 0:666850d06c9f | 1106 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable |
jhon309 | 0:666850d06c9f | 1107 | * the selected interrupts.). |
jhon309 | 0:666850d06c9f | 1108 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
jhon309 | 0:666850d06c9f | 1109 | * This parameter can be any combination of the following values: |
jhon309 | 0:666850d06c9f | 1110 | * @arg RCC_IT_LSIRDY: LSI ready interrupt enable |
jhon309 | 0:666850d06c9f | 1111 | * @arg RCC_IT_LSERDY: LSE ready interrupt enable |
jhon309 | 0:666850d06c9f | 1112 | * @arg RCC_IT_HSIRDY: HSI ready interrupt enable |
jhon309 | 0:666850d06c9f | 1113 | * @arg RCC_IT_HSERDY: HSE ready interrupt enable |
jhon309 | 0:666850d06c9f | 1114 | * @arg RCC_IT_PLLRDY: PLL ready interrupt enable |
jhon309 | 0:666850d06c9f | 1115 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable |
jhon309 | 0:666850d06c9f | 1116 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) |
jhon309 | 0:666850d06c9f | 1117 | */ |
jhon309 | 0:666850d06c9f | 1118 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) |
jhon309 | 0:666850d06c9f | 1119 | |
jhon309 | 0:666850d06c9f | 1120 | /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] |
jhon309 | 0:666850d06c9f | 1121 | * bits to clear the selected interrupt pending bits. |
jhon309 | 0:666850d06c9f | 1122 | * @param __IT__: specifies the interrupt pending bit to clear. |
jhon309 | 0:666850d06c9f | 1123 | * This parameter can be any combination of the following values: |
jhon309 | 0:666850d06c9f | 1124 | * @arg RCC_IT_LSIRDY: LSI ready interrupt clear |
jhon309 | 0:666850d06c9f | 1125 | * @arg RCC_IT_LSERDY: LSE ready interrupt clear |
jhon309 | 0:666850d06c9f | 1126 | * @arg RCC_IT_HSIRDY: HSI ready interrupt clear |
jhon309 | 0:666850d06c9f | 1127 | * @arg RCC_IT_HSERDY: HSE ready interrupt clear |
jhon309 | 0:666850d06c9f | 1128 | * @arg RCC_IT_PLLRDY: PLL ready interrupt clear |
jhon309 | 0:666850d06c9f | 1129 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear |
jhon309 | 0:666850d06c9f | 1130 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices) |
jhon309 | 0:666850d06c9f | 1131 | * @arg RCC_IT_CSS: Clock Security System interrupt clear |
jhon309 | 0:666850d06c9f | 1132 | */ |
jhon309 | 0:666850d06c9f | 1133 | #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__)) |
jhon309 | 0:666850d06c9f | 1134 | |
jhon309 | 0:666850d06c9f | 1135 | /** @brief Check the RCC's interrupt has occurred or not. |
jhon309 | 0:666850d06c9f | 1136 | * @param __IT__: specifies the RCC interrupt source to check. |
jhon309 | 0:666850d06c9f | 1137 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 1138 | * @arg RCC_IT_LSIRDY: LSI ready interrupt flag |
jhon309 | 0:666850d06c9f | 1139 | * @arg RCC_IT_LSERDY: LSE ready interrupt flag |
jhon309 | 0:666850d06c9f | 1140 | * @arg RCC_IT_HSIRDY: HSI ready interrupt flag |
jhon309 | 0:666850d06c9f | 1141 | * @arg RCC_IT_HSERDY: HSE ready interrupt flag |
jhon309 | 0:666850d06c9f | 1142 | * @arg RCC_IT_PLLRDY: PLL ready interrupt flag |
jhon309 | 0:666850d06c9f | 1143 | * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag |
jhon309 | 0:666850d06c9f | 1144 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices) |
jhon309 | 0:666850d06c9f | 1145 | * @arg RCC_IT_CSS: Clock Security System interrupt flag |
jhon309 | 0:666850d06c9f | 1146 | * @retval The new state of __IT__ (TRUE or FALSE). |
jhon309 | 0:666850d06c9f | 1147 | */ |
jhon309 | 0:666850d06c9f | 1148 | #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__)) |
jhon309 | 0:666850d06c9f | 1149 | |
jhon309 | 0:666850d06c9f | 1150 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
jhon309 | 0:666850d06c9f | 1151 | * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
jhon309 | 0:666850d06c9f | 1152 | */ |
jhon309 | 0:666850d06c9f | 1153 | #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) |
jhon309 | 0:666850d06c9f | 1154 | |
jhon309 | 0:666850d06c9f | 1155 | /** @brief Check RCC flag is set or not. |
jhon309 | 0:666850d06c9f | 1156 | * @param __FLAG__: specifies the flag to check. |
jhon309 | 0:666850d06c9f | 1157 | * This parameter can be one of the following values: |
jhon309 | 0:666850d06c9f | 1158 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
jhon309 | 0:666850d06c9f | 1159 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
jhon309 | 0:666850d06c9f | 1160 | * @arg RCC_FLAG_PLLRDY: PLL clock ready |
jhon309 | 0:666850d06c9f | 1161 | * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready |
jhon309 | 0:666850d06c9f | 1162 | * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices) |
jhon309 | 0:666850d06c9f | 1163 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
jhon309 | 0:666850d06c9f | 1164 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
jhon309 | 0:666850d06c9f | 1165 | * @arg RCC_FLAG_OBLRST: Option Byte Load reset |
jhon309 | 0:666850d06c9f | 1166 | * @arg RCC_FLAG_PINRST: Pin reset |
jhon309 | 0:666850d06c9f | 1167 | * @arg RCC_FLAG_PORRST: POR/PDR reset |
jhon309 | 0:666850d06c9f | 1168 | * @arg RCC_FLAG_SFTRST: Software reset |
jhon309 | 0:666850d06c9f | 1169 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset |
jhon309 | 0:666850d06c9f | 1170 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset |
jhon309 | 0:666850d06c9f | 1171 | * @arg RCC_FLAG_LPWRRST: Low Power reset |
jhon309 | 0:666850d06c9f | 1172 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
jhon309 | 0:666850d06c9f | 1173 | */ |
jhon309 | 0:666850d06c9f | 1174 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
jhon309 | 0:666850d06c9f | 1175 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \ |
jhon309 | 0:666850d06c9f | 1176 | (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \ |
jhon309 | 0:666850d06c9f | 1177 | (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \ |
jhon309 | 0:666850d06c9f | 1178 | RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) |
jhon309 | 0:666850d06c9f | 1179 | |
jhon309 | 0:666850d06c9f | 1180 | |
jhon309 | 0:666850d06c9f | 1181 | |
jhon309 | 0:666850d06c9f | 1182 | /** |
jhon309 | 0:666850d06c9f | 1183 | * @} |
jhon309 | 0:666850d06c9f | 1184 | */ |
jhon309 | 0:666850d06c9f | 1185 | |
jhon309 | 0:666850d06c9f | 1186 | /** |
jhon309 | 0:666850d06c9f | 1187 | * @} |
jhon309 | 0:666850d06c9f | 1188 | */ |
jhon309 | 0:666850d06c9f | 1189 | |
jhon309 | 0:666850d06c9f | 1190 | /* Include RCC HAL Extension module */ |
jhon309 | 0:666850d06c9f | 1191 | #include "stm32f0xx_hal_rcc_ex.h" |
jhon309 | 0:666850d06c9f | 1192 | |
jhon309 | 0:666850d06c9f | 1193 | /* Exported functions --------------------------------------------------------*/ |
jhon309 | 0:666850d06c9f | 1194 | |
jhon309 | 0:666850d06c9f | 1195 | /** @addtogroup RCC_Exported_Functions |
jhon309 | 0:666850d06c9f | 1196 | * @{ |
jhon309 | 0:666850d06c9f | 1197 | */ |
jhon309 | 0:666850d06c9f | 1198 | |
jhon309 | 0:666850d06c9f | 1199 | /** @addtogroup RCC_Exported_Functions_Group1 |
jhon309 | 0:666850d06c9f | 1200 | * @{ |
jhon309 | 0:666850d06c9f | 1201 | */ |
jhon309 | 0:666850d06c9f | 1202 | |
jhon309 | 0:666850d06c9f | 1203 | /* Initialization and de-initialization functions ***************************/ |
jhon309 | 0:666850d06c9f | 1204 | void HAL_RCC_DeInit(void); |
jhon309 | 0:666850d06c9f | 1205 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
jhon309 | 0:666850d06c9f | 1206 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
jhon309 | 0:666850d06c9f | 1207 | |
jhon309 | 0:666850d06c9f | 1208 | /** |
jhon309 | 0:666850d06c9f | 1209 | * @} |
jhon309 | 0:666850d06c9f | 1210 | */ |
jhon309 | 0:666850d06c9f | 1211 | |
jhon309 | 0:666850d06c9f | 1212 | /** @addtogroup RCC_Exported_Functions_Group2 |
jhon309 | 0:666850d06c9f | 1213 | * @{ |
jhon309 | 0:666850d06c9f | 1214 | */ |
jhon309 | 0:666850d06c9f | 1215 | |
jhon309 | 0:666850d06c9f | 1216 | /* Peripheral Control functions *********************************************/ |
jhon309 | 0:666850d06c9f | 1217 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
jhon309 | 0:666850d06c9f | 1218 | void HAL_RCC_EnableCSS(void); |
jhon309 | 0:666850d06c9f | 1219 | void HAL_RCC_DisableCSS(void); |
jhon309 | 0:666850d06c9f | 1220 | uint32_t HAL_RCC_GetSysClockFreq(void); |
jhon309 | 0:666850d06c9f | 1221 | uint32_t HAL_RCC_GetHCLKFreq(void); |
jhon309 | 0:666850d06c9f | 1222 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
jhon309 | 0:666850d06c9f | 1223 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
jhon309 | 0:666850d06c9f | 1224 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
jhon309 | 0:666850d06c9f | 1225 | |
jhon309 | 0:666850d06c9f | 1226 | /* CSS NMI IRQ handler */ |
jhon309 | 0:666850d06c9f | 1227 | void HAL_RCC_NMI_IRQHandler(void); |
jhon309 | 0:666850d06c9f | 1228 | |
jhon309 | 0:666850d06c9f | 1229 | /* User Callbacks in non blocking mode (IT mode) */ |
jhon309 | 0:666850d06c9f | 1230 | void HAL_RCC_CCSCallback(void); |
jhon309 | 0:666850d06c9f | 1231 | |
jhon309 | 0:666850d06c9f | 1232 | /** |
jhon309 | 0:666850d06c9f | 1233 | * @} |
jhon309 | 0:666850d06c9f | 1234 | */ |
jhon309 | 0:666850d06c9f | 1235 | |
jhon309 | 0:666850d06c9f | 1236 | /** |
jhon309 | 0:666850d06c9f | 1237 | * @} |
jhon309 | 0:666850d06c9f | 1238 | */ |
jhon309 | 0:666850d06c9f | 1239 | |
jhon309 | 0:666850d06c9f | 1240 | /** |
jhon309 | 0:666850d06c9f | 1241 | * @} |
jhon309 | 0:666850d06c9f | 1242 | */ |
jhon309 | 0:666850d06c9f | 1243 | |
jhon309 | 0:666850d06c9f | 1244 | /** |
jhon309 | 0:666850d06c9f | 1245 | * @} |
jhon309 | 0:666850d06c9f | 1246 | */ |
jhon309 | 0:666850d06c9f | 1247 | |
jhon309 | 0:666850d06c9f | 1248 | #ifdef __cplusplus |
jhon309 | 0:666850d06c9f | 1249 | } |
jhon309 | 0:666850d06c9f | 1250 | #endif |
jhon309 | 0:666850d06c9f | 1251 | |
jhon309 | 0:666850d06c9f | 1252 | #endif /* __STM32F0xx_HAL_RCC_H */ |
jhon309 | 0:666850d06c9f | 1253 | |
jhon309 | 0:666850d06c9f | 1254 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
jhon309 | 0:666850d06c9f | 1255 |