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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h@0:666850d06c9f, 2015-08-20 (annotated)

Committer:
jhon309
Date:
Thu Aug 20 00:37:14 2015 +0000
Revision:
0:666850d06c9f
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jhon309 0:666850d06c9f 1 /**
jhon309 0:666850d06c9f 2 ******************************************************************************
jhon309 0:666850d06c9f 3 * @file stm32f0xx_hal_dma.h
jhon309 0:666850d06c9f 4 * @author MCD Application Team
jhon309 0:666850d06c9f 5 * @version V1.2.0
jhon309 0:666850d06c9f 6 * @date 11-December-2014
jhon309 0:666850d06c9f 7 * @brief Header file of DMA HAL module.
jhon309 0:666850d06c9f 8 ******************************************************************************
jhon309 0:666850d06c9f 9 * @attention
jhon309 0:666850d06c9f 10 *
jhon309 0:666850d06c9f 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309 0:666850d06c9f 12 *
jhon309 0:666850d06c9f 13 * Redistribution and use in source and binary forms, with or without modification,
jhon309 0:666850d06c9f 14 * are permitted provided that the following conditions are met:
jhon309 0:666850d06c9f 15 * 1. Redistributions of source code must retain the above copyright notice,
jhon309 0:666850d06c9f 16 * this list of conditions and the following disclaimer.
jhon309 0:666850d06c9f 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309 0:666850d06c9f 18 * this list of conditions and the following disclaimer in the documentation
jhon309 0:666850d06c9f 19 * and/or other materials provided with the distribution.
jhon309 0:666850d06c9f 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309 0:666850d06c9f 21 * may be used to endorse or promote products derived from this software
jhon309 0:666850d06c9f 22 * without specific prior written permission.
jhon309 0:666850d06c9f 23 *
jhon309 0:666850d06c9f 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:666850d06c9f 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:666850d06c9f 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309 0:666850d06c9f 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309 0:666850d06c9f 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309 0:666850d06c9f 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309 0:666850d06c9f 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309 0:666850d06c9f 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309 0:666850d06c9f 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309 0:666850d06c9f 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309 0:666850d06c9f 34 *
jhon309 0:666850d06c9f 35 ******************************************************************************
jhon309 0:666850d06c9f 36 */
jhon309 0:666850d06c9f 37
jhon309 0:666850d06c9f 38 /* Define to prevent recursive inclusion -------------------------------------*/
jhon309 0:666850d06c9f 39 #ifndef __STM32F0xx_HAL_DMA_H
jhon309 0:666850d06c9f 40 #define __STM32F0xx_HAL_DMA_H
jhon309 0:666850d06c9f 41
jhon309 0:666850d06c9f 42 #ifdef __cplusplus
jhon309 0:666850d06c9f 43 extern "C" {
jhon309 0:666850d06c9f 44 #endif
jhon309 0:666850d06c9f 45
jhon309 0:666850d06c9f 46 /* Includes ------------------------------------------------------------------*/
jhon309 0:666850d06c9f 47 #include "stm32f0xx_hal_def.h"
jhon309 0:666850d06c9f 48
jhon309 0:666850d06c9f 49 /** @addtogroup STM32F0xx_HAL_Driver
jhon309 0:666850d06c9f 50 * @{
jhon309 0:666850d06c9f 51 */
jhon309 0:666850d06c9f 52
jhon309 0:666850d06c9f 53 /** @addtogroup DMA
jhon309 0:666850d06c9f 54 * @{
jhon309 0:666850d06c9f 55 */
jhon309 0:666850d06c9f 56
jhon309 0:666850d06c9f 57 /* Exported types ------------------------------------------------------------*/
jhon309 0:666850d06c9f 58 /** @defgroup DMA_Exported_Types DMA Exported Types
jhon309 0:666850d06c9f 59 * @{
jhon309 0:666850d06c9f 60 */
jhon309 0:666850d06c9f 61
jhon309 0:666850d06c9f 62 /**
jhon309 0:666850d06c9f 63 * @brief DMA Configuration Structure definition
jhon309 0:666850d06c9f 64 */
jhon309 0:666850d06c9f 65 typedef struct
jhon309 0:666850d06c9f 66 {
jhon309 0:666850d06c9f 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
jhon309 0:666850d06c9f 68 from memory to memory or from peripheral to memory.
jhon309 0:666850d06c9f 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
jhon309 0:666850d06c9f 70
jhon309 0:666850d06c9f 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
jhon309 0:666850d06c9f 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
jhon309 0:666850d06c9f 73
jhon309 0:666850d06c9f 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
jhon309 0:666850d06c9f 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
jhon309 0:666850d06c9f 76
jhon309 0:666850d06c9f 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
jhon309 0:666850d06c9f 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
jhon309 0:666850d06c9f 79
jhon309 0:666850d06c9f 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
jhon309 0:666850d06c9f 81 This parameter can be a value of @ref DMA_Memory_data_size */
jhon309 0:666850d06c9f 82
jhon309 0:666850d06c9f 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
jhon309 0:666850d06c9f 84 This parameter can be a value of @ref DMA_mode
jhon309 0:666850d06c9f 85 @note The circular buffer mode cannot be used if the memory-to-memory
jhon309 0:666850d06c9f 86 data transfer is configured on the selected Channel */
jhon309 0:666850d06c9f 87
jhon309 0:666850d06c9f 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
jhon309 0:666850d06c9f 89 This parameter can be a value of @ref DMA_Priority_level */
jhon309 0:666850d06c9f 90
jhon309 0:666850d06c9f 91 } DMA_InitTypeDef;
jhon309 0:666850d06c9f 92
jhon309 0:666850d06c9f 93 /**
jhon309 0:666850d06c9f 94 * @brief DMA Configuration enumeration values definition
jhon309 0:666850d06c9f 95 */
jhon309 0:666850d06c9f 96 typedef enum
jhon309 0:666850d06c9f 97 {
jhon309 0:666850d06c9f 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
jhon309 0:666850d06c9f 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
jhon309 0:666850d06c9f 100
jhon309 0:666850d06c9f 101 } DMA_ControlTypeDef;
jhon309 0:666850d06c9f 102
jhon309 0:666850d06c9f 103 /**
jhon309 0:666850d06c9f 104 * @brief HAL DMA State structures definition
jhon309 0:666850d06c9f 105 */
jhon309 0:666850d06c9f 106 typedef enum
jhon309 0:666850d06c9f 107 {
jhon309 0:666850d06c9f 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
jhon309 0:666850d06c9f 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
jhon309 0:666850d06c9f 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
jhon309 0:666850d06c9f 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
jhon309 0:666850d06c9f 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
jhon309 0:666850d06c9f 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
jhon309 0:666850d06c9f 114
jhon309 0:666850d06c9f 115 }HAL_DMA_StateTypeDef;
jhon309 0:666850d06c9f 116
jhon309 0:666850d06c9f 117 /**
jhon309 0:666850d06c9f 118 * @brief HAL DMA Error Code structure definition
jhon309 0:666850d06c9f 119 */
jhon309 0:666850d06c9f 120 typedef enum
jhon309 0:666850d06c9f 121 {
jhon309 0:666850d06c9f 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
jhon309 0:666850d06c9f 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
jhon309 0:666850d06c9f 124
jhon309 0:666850d06c9f 125 }HAL_DMA_LevelCompleteTypeDef;
jhon309 0:666850d06c9f 126
jhon309 0:666850d06c9f 127
jhon309 0:666850d06c9f 128 /**
jhon309 0:666850d06c9f 129 * @brief DMA handle Structure definition
jhon309 0:666850d06c9f 130 */
jhon309 0:666850d06c9f 131 typedef struct __DMA_HandleTypeDef
jhon309 0:666850d06c9f 132 {
jhon309 0:666850d06c9f 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
jhon309 0:666850d06c9f 134
jhon309 0:666850d06c9f 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
jhon309 0:666850d06c9f 136
jhon309 0:666850d06c9f 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
jhon309 0:666850d06c9f 138
jhon309 0:666850d06c9f 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
jhon309 0:666850d06c9f 140
jhon309 0:666850d06c9f 141 void *Parent; /*!< Parent object state */
jhon309 0:666850d06c9f 142
jhon309 0:666850d06c9f 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
jhon309 0:666850d06c9f 144
jhon309 0:666850d06c9f 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
jhon309 0:666850d06c9f 146
jhon309 0:666850d06c9f 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
jhon309 0:666850d06c9f 148
jhon309 0:666850d06c9f 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
jhon309 0:666850d06c9f 150
jhon309 0:666850d06c9f 151 } DMA_HandleTypeDef;
jhon309 0:666850d06c9f 152 /**
jhon309 0:666850d06c9f 153 * @}
jhon309 0:666850d06c9f 154 */
jhon309 0:666850d06c9f 155
jhon309 0:666850d06c9f 156 /* Exported constants --------------------------------------------------------*/
jhon309 0:666850d06c9f 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
jhon309 0:666850d06c9f 158 * @{
jhon309 0:666850d06c9f 159 */
jhon309 0:666850d06c9f 160
jhon309 0:666850d06c9f 161 /** @defgroup DMA_Error_Code DMA Error Code
jhon309 0:666850d06c9f 162 * @{
jhon309 0:666850d06c9f 163 */
jhon309 0:666850d06c9f 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
jhon309 0:666850d06c9f 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
jhon309 0:666850d06c9f 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
jhon309 0:666850d06c9f 167 /**
jhon309 0:666850d06c9f 168 * @}
jhon309 0:666850d06c9f 169 */
jhon309 0:666850d06c9f 170
jhon309 0:666850d06c9f 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
jhon309 0:666850d06c9f 172 * @{
jhon309 0:666850d06c9f 173 */
jhon309 0:666850d06c9f 174 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
jhon309 0:666850d06c9f 175 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
jhon309 0:666850d06c9f 176 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
jhon309 0:666850d06c9f 177
jhon309 0:666850d06c9f 178 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
jhon309 0:666850d06c9f 179 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
jhon309 0:666850d06c9f 180 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
jhon309 0:666850d06c9f 181 /**
jhon309 0:666850d06c9f 182 * @}
jhon309 0:666850d06c9f 183 */
jhon309 0:666850d06c9f 184
jhon309 0:666850d06c9f 185 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
jhon309 0:666850d06c9f 186 * @{
jhon309 0:666850d06c9f 187 */
jhon309 0:666850d06c9f 188 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
jhon309 0:666850d06c9f 189 /**
jhon309 0:666850d06c9f 190 * @}
jhon309 0:666850d06c9f 191 */
jhon309 0:666850d06c9f 192
jhon309 0:666850d06c9f 193 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
jhon309 0:666850d06c9f 194 * @{
jhon309 0:666850d06c9f 195 */
jhon309 0:666850d06c9f 196 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
jhon309 0:666850d06c9f 197 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
jhon309 0:666850d06c9f 198
jhon309 0:666850d06c9f 199 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
jhon309 0:666850d06c9f 200 ((STATE) == DMA_PINC_DISABLE))
jhon309 0:666850d06c9f 201 /**
jhon309 0:666850d06c9f 202 * @}
jhon309 0:666850d06c9f 203 */
jhon309 0:666850d06c9f 204
jhon309 0:666850d06c9f 205 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
jhon309 0:666850d06c9f 206 * @{
jhon309 0:666850d06c9f 207 */
jhon309 0:666850d06c9f 208 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
jhon309 0:666850d06c9f 209 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
jhon309 0:666850d06c9f 210
jhon309 0:666850d06c9f 211 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
jhon309 0:666850d06c9f 212 ((STATE) == DMA_MINC_DISABLE))
jhon309 0:666850d06c9f 213 /**
jhon309 0:666850d06c9f 214 * @}
jhon309 0:666850d06c9f 215 */
jhon309 0:666850d06c9f 216
jhon309 0:666850d06c9f 217 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
jhon309 0:666850d06c9f 218 * @{
jhon309 0:666850d06c9f 219 */
jhon309 0:666850d06c9f 220 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
jhon309 0:666850d06c9f 221 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
jhon309 0:666850d06c9f 222 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
jhon309 0:666850d06c9f 223
jhon309 0:666850d06c9f 224 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
jhon309 0:666850d06c9f 225 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
jhon309 0:666850d06c9f 226 ((SIZE) == DMA_PDATAALIGN_WORD))
jhon309 0:666850d06c9f 227 /**
jhon309 0:666850d06c9f 228 * @}
jhon309 0:666850d06c9f 229 */
jhon309 0:666850d06c9f 230
jhon309 0:666850d06c9f 231
jhon309 0:666850d06c9f 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
jhon309 0:666850d06c9f 233 * @{
jhon309 0:666850d06c9f 234 */
jhon309 0:666850d06c9f 235 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
jhon309 0:666850d06c9f 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
jhon309 0:666850d06c9f 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
jhon309 0:666850d06c9f 238
jhon309 0:666850d06c9f 239 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
jhon309 0:666850d06c9f 240 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
jhon309 0:666850d06c9f 241 ((SIZE) == DMA_MDATAALIGN_WORD ))
jhon309 0:666850d06c9f 242 /**
jhon309 0:666850d06c9f 243 * @}
jhon309 0:666850d06c9f 244 */
jhon309 0:666850d06c9f 245
jhon309 0:666850d06c9f 246 /** @defgroup DMA_mode DMA mode
jhon309 0:666850d06c9f 247 * @{
jhon309 0:666850d06c9f 248 */
jhon309 0:666850d06c9f 249 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
jhon309 0:666850d06c9f 250 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
jhon309 0:666850d06c9f 251
jhon309 0:666850d06c9f 252 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
jhon309 0:666850d06c9f 253 ((MODE) == DMA_CIRCULAR))
jhon309 0:666850d06c9f 254 /**
jhon309 0:666850d06c9f 255 * @}
jhon309 0:666850d06c9f 256 */
jhon309 0:666850d06c9f 257
jhon309 0:666850d06c9f 258 /** @defgroup DMA_Priority_level DMA Priority level
jhon309 0:666850d06c9f 259 * @{
jhon309 0:666850d06c9f 260 */
jhon309 0:666850d06c9f 261 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
jhon309 0:666850d06c9f 262 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
jhon309 0:666850d06c9f 263 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
jhon309 0:666850d06c9f 264 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
jhon309 0:666850d06c9f 265
jhon309 0:666850d06c9f 266 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
jhon309 0:666850d06c9f 267 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
jhon309 0:666850d06c9f 268 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
jhon309 0:666850d06c9f 269 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
jhon309 0:666850d06c9f 270 /**
jhon309 0:666850d06c9f 271 * @}
jhon309 0:666850d06c9f 272 */
jhon309 0:666850d06c9f 273
jhon309 0:666850d06c9f 274
jhon309 0:666850d06c9f 275 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
jhon309 0:666850d06c9f 276 * @{
jhon309 0:666850d06c9f 277 */
jhon309 0:666850d06c9f 278
jhon309 0:666850d06c9f 279 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
jhon309 0:666850d06c9f 280 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
jhon309 0:666850d06c9f 281 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
jhon309 0:666850d06c9f 282
jhon309 0:666850d06c9f 283 /**
jhon309 0:666850d06c9f 284 * @}
jhon309 0:666850d06c9f 285 */
jhon309 0:666850d06c9f 286
jhon309 0:666850d06c9f 287 /** @defgroup DMA_flag_definitions DMA flag definitions
jhon309 0:666850d06c9f 288 * @{
jhon309 0:666850d06c9f 289 */
jhon309 0:666850d06c9f 290
jhon309 0:666850d06c9f 291 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
jhon309 0:666850d06c9f 292 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
jhon309 0:666850d06c9f 293 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
jhon309 0:666850d06c9f 294 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
jhon309 0:666850d06c9f 295 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
jhon309 0:666850d06c9f 296 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
jhon309 0:666850d06c9f 297 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
jhon309 0:666850d06c9f 298 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
jhon309 0:666850d06c9f 299 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
jhon309 0:666850d06c9f 300 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
jhon309 0:666850d06c9f 301 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
jhon309 0:666850d06c9f 302 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
jhon309 0:666850d06c9f 303 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
jhon309 0:666850d06c9f 304 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
jhon309 0:666850d06c9f 305 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
jhon309 0:666850d06c9f 306 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
jhon309 0:666850d06c9f 307 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
jhon309 0:666850d06c9f 308 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
jhon309 0:666850d06c9f 309 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
jhon309 0:666850d06c9f 310 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
jhon309 0:666850d06c9f 311 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
jhon309 0:666850d06c9f 312 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
jhon309 0:666850d06c9f 313 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
jhon309 0:666850d06c9f 314 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
jhon309 0:666850d06c9f 315 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
jhon309 0:666850d06c9f 316 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
jhon309 0:666850d06c9f 317 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
jhon309 0:666850d06c9f 318 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
jhon309 0:666850d06c9f 319
jhon309 0:666850d06c9f 320
jhon309 0:666850d06c9f 321 /**
jhon309 0:666850d06c9f 322 * @}
jhon309 0:666850d06c9f 323 */
jhon309 0:666850d06c9f 324
jhon309 0:666850d06c9f 325 /**
jhon309 0:666850d06c9f 326 * @}
jhon309 0:666850d06c9f 327 */
jhon309 0:666850d06c9f 328
jhon309 0:666850d06c9f 329 /* Exported macros -----------------------------------------------------------*/
jhon309 0:666850d06c9f 330 /** @defgroup DMA_Exported_Macros DMA Exported Macros
jhon309 0:666850d06c9f 331 * @{
jhon309 0:666850d06c9f 332 */
jhon309 0:666850d06c9f 333
jhon309 0:666850d06c9f 334 /** @brief Reset DMA handle state
jhon309 0:666850d06c9f 335 * @param __HANDLE__: DMA handle.
jhon309 0:666850d06c9f 336 * @retval None
jhon309 0:666850d06c9f 337 */
jhon309 0:666850d06c9f 338 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
jhon309 0:666850d06c9f 339
jhon309 0:666850d06c9f 340 /**
jhon309 0:666850d06c9f 341 * @brief Enable the specified DMA Channel.
jhon309 0:666850d06c9f 342 * @param __HANDLE__: DMA handle
jhon309 0:666850d06c9f 343 * @retval None.
jhon309 0:666850d06c9f 344 */
jhon309 0:666850d06c9f 345 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
jhon309 0:666850d06c9f 346
jhon309 0:666850d06c9f 347 /**
jhon309 0:666850d06c9f 348 * @brief Disable the specified DMA Channel.
jhon309 0:666850d06c9f 349 * @param __HANDLE__: DMA handle
jhon309 0:666850d06c9f 350 * @retval None.
jhon309 0:666850d06c9f 351 */
jhon309 0:666850d06c9f 352 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
jhon309 0:666850d06c9f 353
jhon309 0:666850d06c9f 354
jhon309 0:666850d06c9f 355 /* Interrupt & Flag management */
jhon309 0:666850d06c9f 356
jhon309 0:666850d06c9f 357 /**
jhon309 0:666850d06c9f 358 * @brief Enables the specified DMA Channel interrupts.
jhon309 0:666850d06c9f 359 * @param __HANDLE__: DMA handle
jhon309 0:666850d06c9f 360 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
jhon309 0:666850d06c9f 361 * This parameter can be any combination of the following values:
jhon309 0:666850d06c9f 362 * @arg DMA_IT_TC: Transfer complete interrupt mask
jhon309 0:666850d06c9f 363 * @arg DMA_IT_HT: Half transfer complete interrupt mask
jhon309 0:666850d06c9f 364 * @arg DMA_IT_TE: Transfer error interrupt mask
jhon309 0:666850d06c9f 365 * @retval None
jhon309 0:666850d06c9f 366 */
jhon309 0:666850d06c9f 367 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
jhon309 0:666850d06c9f 368
jhon309 0:666850d06c9f 369 /**
jhon309 0:666850d06c9f 370 * @brief Disables the specified DMA Channel interrupts.
jhon309 0:666850d06c9f 371 * @param __HANDLE__: DMA handle
jhon309 0:666850d06c9f 372 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
jhon309 0:666850d06c9f 373 * This parameter can be any combination of the following values:
jhon309 0:666850d06c9f 374 * @arg DMA_IT_TC: Transfer complete interrupt mask
jhon309 0:666850d06c9f 375 * @arg DMA_IT_HT: Half transfer complete interrupt mask
jhon309 0:666850d06c9f 376 * @arg DMA_IT_TE: Transfer error interrupt mask
jhon309 0:666850d06c9f 377 * @retval None
jhon309 0:666850d06c9f 378 */
jhon309 0:666850d06c9f 379 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
jhon309 0:666850d06c9f 380
jhon309 0:666850d06c9f 381 /**
jhon309 0:666850d06c9f 382 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
jhon309 0:666850d06c9f 383 * @param __HANDLE__: DMA handle
jhon309 0:666850d06c9f 384 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
jhon309 0:666850d06c9f 385 * This parameter can be one of the following values:
jhon309 0:666850d06c9f 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
jhon309 0:666850d06c9f 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
jhon309 0:666850d06c9f 388 * @arg DMA_IT_TE: Transfer error interrupt mask
jhon309 0:666850d06c9f 389 * @retval The state of DMA_IT (SET or RESET).
jhon309 0:666850d06c9f 390 */
jhon309 0:666850d06c9f 391 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
jhon309 0:666850d06c9f 392
jhon309 0:666850d06c9f 393 /**
jhon309 0:666850d06c9f 394 * @}
jhon309 0:666850d06c9f 395 */
jhon309 0:666850d06c9f 396
jhon309 0:666850d06c9f 397 /* Include DMA HAL Extension module */
jhon309 0:666850d06c9f 398 #include "stm32f0xx_hal_dma_ex.h"
jhon309 0:666850d06c9f 399
jhon309 0:666850d06c9f 400 /* Exported functions --------------------------------------------------------*/
jhon309 0:666850d06c9f 401 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
jhon309 0:666850d06c9f 402 * @{
jhon309 0:666850d06c9f 403 */
jhon309 0:666850d06c9f 404 /** @addtogroup DMA_Exported_Functions_Group1
jhon309 0:666850d06c9f 405 * @brief Initialization and de-initialization functions
jhon309 0:666850d06c9f 406 * @{
jhon309 0:666850d06c9f 407 */
jhon309 0:666850d06c9f 408 /* Initialization and de-initialization functions *****************************/
jhon309 0:666850d06c9f 409 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
jhon309 0:666850d06c9f 410 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
jhon309 0:666850d06c9f 411 /**
jhon309 0:666850d06c9f 412 * @}
jhon309 0:666850d06c9f 413 */
jhon309 0:666850d06c9f 414
jhon309 0:666850d06c9f 415 /** @addtogroup DMA_Exported_Functions_Group2
jhon309 0:666850d06c9f 416 * @brief I/O operation functions
jhon309 0:666850d06c9f 417 * @{
jhon309 0:666850d06c9f 418 */
jhon309 0:666850d06c9f 419 /* IO operation functions *****************************************************/
jhon309 0:666850d06c9f 420 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
jhon309 0:666850d06c9f 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
jhon309 0:666850d06c9f 422 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
jhon309 0:666850d06c9f 423 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
jhon309 0:666850d06c9f 424 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
jhon309 0:666850d06c9f 425 /**
jhon309 0:666850d06c9f 426 * @}
jhon309 0:666850d06c9f 427 */
jhon309 0:666850d06c9f 428
jhon309 0:666850d06c9f 429 /* Peripheral State and Error functions ***************************************/
jhon309 0:666850d06c9f 430 /** @addtogroup DMA_Exported_Functions_Group3
jhon309 0:666850d06c9f 431 * @brief Peripheral State functions
jhon309 0:666850d06c9f 432 * @{
jhon309 0:666850d06c9f 433 */
jhon309 0:666850d06c9f 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
jhon309 0:666850d06c9f 435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
jhon309 0:666850d06c9f 436 /**
jhon309 0:666850d06c9f 437 * @}
jhon309 0:666850d06c9f 438 */
jhon309 0:666850d06c9f 439
jhon309 0:666850d06c9f 440 /**
jhon309 0:666850d06c9f 441 * @}
jhon309 0:666850d06c9f 442 */
jhon309 0:666850d06c9f 443
jhon309 0:666850d06c9f 444 /**
jhon309 0:666850d06c9f 445 * @}
jhon309 0:666850d06c9f 446 */
jhon309 0:666850d06c9f 447
jhon309 0:666850d06c9f 448 /**
jhon309 0:666850d06c9f 449 * @}
jhon309 0:666850d06c9f 450 */
jhon309 0:666850d06c9f 451
jhon309 0:666850d06c9f 452 #ifdef __cplusplus
jhon309 0:666850d06c9f 453 }
jhon309 0:666850d06c9f 454 #endif
jhon309 0:666850d06c9f 455
jhon309 0:666850d06c9f 456 #endif /* __STM32F0xx_HAL_DMA_H */
jhon309 0:666850d06c9f 457
jhon309 0:666850d06c9f 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
jhon309 0:666850d06c9f 459