masa miya / Mbed 2 deprecated GPIB_Controller

GPIB Controller

Dependencies:   TextLCD mbed

GPIB_9914.h@0:5a2a05d43d2a, 2011-06-11 (annotated)

Committer:
jf1vrr
Date:
Sat Jun 11 06:35:38 2011 +0000
Revision:
0:5a2a05d43d2a
Rev 0.01A 2011/06/11 new

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jf1vrr 0:5a2a05d43d2a 1 //GPIB_9914.h
jf1vrr 0:5a2a05d43d2a 2
jf1vrr 0:5a2a05d43d2a 3 //NAT7210 - mbed I/O Port design
jf1vrr 0:5a2a05d43d2a 4 BusInOut DATA(p9, p10, p11, p12, p13, p14, p15, p16); // LSB p9 - MSB p16 data bus
jf1vrr 0:5a2a05d43d2a 5 DigitalOut RD(p18);
jf1vrr 0:5a2a05d43d2a 6 DigitalOut WR(p19);
jf1vrr 0:5a2a05d43d2a 7 BusOut RS(p21, p22, p23); //LSB p21 - MSB p23 address bus
jf1vrr 0:5a2a05d43d2a 8
jf1vrr 0:5a2a05d43d2a 9 //Flags & Macros
jf1vrr 0:5a2a05d43d2a 10 #define _LOW 0
jf1vrr 0:5a2a05d43d2a 11 #define _HIGH 1
jf1vrr 0:5a2a05d43d2a 12 #define _OFF 0
jf1vrr 0:5a2a05d43d2a 13 #define _ON 1
jf1vrr 0:5a2a05d43d2a 14 #define SET_READ DATA.input();
jf1vrr 0:5a2a05d43d2a 15 #define SET_WRITE DATA.output();
jf1vrr 0:5a2a05d43d2a 16
jf1vrr 0:5a2a05d43d2a 17 //NAT7210 9914 Mode READ Registers
jf1vrr 0:5a2a05d43d2a 18 #define ISR0 0 //Interrupt Status Register 0
jf1vrr 0:5a2a05d43d2a 19 #define ISR1 1 //Interrupt Status Register 1
jf1vrr 0:5a2a05d43d2a 20 #define ADSR 2 //Address Register
jf1vrr 0:5a2a05d43d2a 21 #define BSR 3 //Bus Status Register
jf1vrr 0:5a2a05d43d2a 22 #define ISR2 4 //Interrupt Status Register 2(Page-In)
jf1vrr 0:5a2a05d43d2a 23 #define SPSR 5 //Serial Poll Status Register(Page-In)
jf1vrr 0:5a2a05d43d2a 24 #define CPTR 6 //Command Pass Through Register
jf1vrr 0:5a2a05d43d2a 25 #define DIR 7 //Data In Register
jf1vrr 0:5a2a05d43d2a 26
jf1vrr 0:5a2a05d43d2a 27 //NAT7210 9914 Mode WRITE Registers
jf1vrr 0:5a2a05d43d2a 28 #define IMR0 0 //Interrupt Mask Register 0
jf1vrr 0:5a2a05d43d2a 29 #define IMR1 1 //Interrupt Mask Register 1
jf1vrr 0:5a2a05d43d2a 30 #define IMR2 2 //Interrupt Mask register 2(Page-In)
jf1vrr 0:5a2a05d43d2a 31 #define EOSR 2 //End-Of-String Register(Page-In)
jf1vrr 0:5a2a05d43d2a 32 #define BCR 2 //Bus Control Register(Page-In)
jf1vrr 0:5a2a05d43d2a 33 #define ACCR 2 //Accessory Read Register(Page-In)
jf1vrr 0:5a2a05d43d2a 34 #define AUXCR 3 //Auxiliary Command Register
jf1vrr 0:5a2a05d43d2a 35 #define ADR 4 //Address Register
jf1vrr 0:5a2a05d43d2a 36 #define SPMR 5 //Serial Poll Mode Register
jf1vrr 0:5a2a05d43d2a 37 #define PPR 6 //Parallel Poll Register
jf1vrr 0:5a2a05d43d2a 38 #define CDOR 7 //Command/data Out Register
jf1vrr 0:5a2a05d43d2a 39
jf1vrr 0:5a2a05d43d2a 40 #define AUXMR 5 //7210 Auxiliary Mode Register
jf1vrr 0:5a2a05d43d2a 41 #define _sw9914 0x15 //Switch To 9914 Mode(7210 Mode AUXMR)
jf1vrr 0:5a2a05d43d2a 42
jf1vrr 0:5a2a05d43d2a 43 //ACCR Accessory Read register Map
jf1vrr 0:5a2a05d43d2a 44 #define ICR 0x20
jf1vrr 0:5a2a05d43d2a 45 #define ACCA 0x80
jf1vrr 0:5a2a05d43d2a 46 #define ACCB 0xA0
jf1vrr 0:5a2a05d43d2a 47 #define ACCE 0xC0
jf1vrr 0:5a2a05d43d2a 48 #define ACCF 0xD0
jf1vrr 0:5a2a05d43d2a 49 #define ACCI 0xE0
jf1vrr 0:5a2a05d43d2a 50
jf1vrr 0:5a2a05d43d2a 51 //AUXCR Auxiliary Commands
jf1vrr 0:5a2a05d43d2a 52 #define _clr_swrst 0x00 //Clear Software Reset
jf1vrr 0:5a2a05d43d2a 53 #define _set_swrst 0x80 //Set Software Reset
jf1vrr 0:5a2a05d43d2a 54 #define _nonvalid 0x01 //Nonvalid Release DAC Holdoff
jf1vrr 0:5a2a05d43d2a 55 #define _valid 0x81 //Valid Release DAC Holdoff
jf1vrr 0:5a2a05d43d2a 56 #define _rhdf 0x02 //Release RFD Holdoff
jf1vrr 0:5a2a05d43d2a 57 #define _clr_hdfa 0x03 //Clear Holdoff On All data
jf1vrr 0:5a2a05d43d2a 58 #define _set_hdfa 0x83 //Set Holdoff On All Data
jf1vrr 0:5a2a05d43d2a 59 #define _clr_hdfe 0x04 //Clear Holdoff On END Only
jf1vrr 0:5a2a05d43d2a 60 #define _set_hdfe 0x84 //Holdoff On END Only
jf1vrr 0:5a2a05d43d2a 61 #define _nbaf 0x05 //New Byte Available False
jf1vrr 0:5a2a05d43d2a 62 #define _clr_fget 0x06 //Clear Force Group Execute Trigger
jf1vrr 0:5a2a05d43d2a 63 #define _set_fget 0x86 //Set Force Group Execute Trigger
jf1vrr 0:5a2a05d43d2a 64 #define _clr_rtl 0x07 //Clear return To Local
jf1vrr 0:5a2a05d43d2a 65 #define _set_rtl 0x87 //Set Return To Local
jf1vrr 0:5a2a05d43d2a 66 #define _feoi 0x08 //Send EOI With The Next Byte
jf1vrr 0:5a2a05d43d2a 67 #define _clr_lon 0x09 //Clear Listen Only
jf1vrr 0:5a2a05d43d2a 68 #define _set_lon 0x89 //Set Listen only
jf1vrr 0:5a2a05d43d2a 69 #define _clr_ton 0x0A //Clear Talk Only
jf1vrr 0:5a2a05d43d2a 70 #define _set_ton 0x8A //Set Talk Only
jf1vrr 0:5a2a05d43d2a 71 #define _gts 0x0B //Go To Standby
jf1vrr 0:5a2a05d43d2a 72 #define _tca 0x0C //Take Control Asynchronously
jf1vrr 0:5a2a05d43d2a 73 #define _tcs 0x0D //Take Control Synchronously
jf1vrr 0:5a2a05d43d2a 74 #define _clr_rpp 0x0E //Clear Request Parallel Poll
jf1vrr 0:5a2a05d43d2a 75 #define _set_rpp 0x8E //Set Request Parallel Poll
jf1vrr 0:5a2a05d43d2a 76 #define _clr_sic 0x0F //Clear Send Interface Clear
jf1vrr 0:5a2a05d43d2a 77 #define _set_sic 0x8F //Set Send Interface Clear
jf1vrr 0:5a2a05d43d2a 78 #define _clr_sre 0x10 //Clear Send Remote Enable
jf1vrr 0:5a2a05d43d2a 79 #define _set_sre 0x90 //Set Send Remote Enable
jf1vrr 0:5a2a05d43d2a 80 #define _rqc 0x11 //Request Control
jf1vrr 0:5a2a05d43d2a 81 #define _rlc 0x12 //Release Control
jf1vrr 0:5a2a05d43d2a 82 #define _clr_dai 0x13 //Clear Disable IMR2, IMR1, And IMR0 Interrupts
jf1vrr 0:5a2a05d43d2a 83 #define _set_dai 0x93 //Set Disable IMR2, IMR1 And IMR0 Interrupts
jf1vrr 0:5a2a05d43d2a 84 #define _pts 0x14 //Pass Through Next Secondary
jf1vrr 0:5a2a05d43d2a 85 #define _clr_stdl 0x15 //Clear Short T1 Delay
jf1vrr 0:5a2a05d43d2a 86 #define _set_std1 0x95 //Set Short T1 Delay
jf1vrr 0:5a2a05d43d2a 87 #define _clr_shdw 0x16 //Clear Shadow Handshaking
jf1vrr 0:5a2a05d43d2a 88 #define _set_shdw 0x96 //Set Shadow Handshaking
jf1vrr 0:5a2a05d43d2a 89 #define _clr_vstdl 0x17 //Clear Very Short T1 Delay
jf1vrr 0:5a2a05d43d2a 90 #define _set_vstdl 0x97 //Set Very Short T1 Delay
jf1vrr 0:5a2a05d43d2a 91 #define _clr_rsv2 0x18 //Clear Request Service bit 2
jf1vrr 0:5a2a05d43d2a 92 #define _set_rsv2 0x98 //Set Request Service bit 2
jf1vrr 0:5a2a05d43d2a 93 #define _sw7210 0x99 //Switch To 7210 Mode
jf1vrr 0:5a2a05d43d2a 94 #define _reqf 0x1A //Request rsv False
jf1vrr 0:5a2a05d43d2a 95 #define _reqt 0x9A //Request rsv True
jf1vrr 0:5a2a05d43d2a 96 #define _ch_rst 0x1C //Chip Reset
jf1vrr 0:5a2a05d43d2a 97 #define _clr_ist 0x1D //Clear Parallel Poll Flag
jf1vrr 0:5a2a05d43d2a 98 #define _set_ist 0x9D //Set Parallel Poll Flag
jf1vrr 0:5a2a05d43d2a 99 #define _piimr2 0x1E //Page-In Interrupt Mask Register 2
jf1vrr 0:5a2a05d43d2a 100 #define _pibcr 0x1F //Page-In Bus Control Register
jf1vrr 0:5a2a05d43d2a 101 #define _clrpi 0x9C //Clear_Page-In Register
jf1vrr 0:5a2a05d43d2a 102 #define _pieosr 0x9E //Page-In End-Of-String Register
jf1vrr 0:5a2a05d43d2a 103 #define _piaccr 0x9F //Page-In Accessory Register
jf1vrr 0:5a2a05d43d2a 104
jf1vrr 0:5a2a05d43d2a 105 //ISR0 Flags
jf1vrr 0:5a2a05d43d2a 106 #define _BI 0x20
jf1vrr 0:5a2a05d43d2a 107 #define _BO 0x10
jf1vrr 0:5a2a05d43d2a 108
jf1vrr 0:5a2a05d43d2a 109 #define _CR 0x0D //Delemiter(CR) --- ignore
jf1vrr 0:5a2a05d43d2a 110 #define _LF 0x0A //Delimiter(LF)
jf1vrr 0:5a2a05d43d2a 111
jf1vrr 0:5a2a05d43d2a 112 //GPIB Command
jf1vrr 0:5a2a05d43d2a 113 #define _GTL 0x01 //
jf1vrr 0:5a2a05d43d2a 114 #define _SDC 0x04 //
jf1vrr 0:5a2a05d43d2a 115 #define _PPC 0x05 //
jf1vrr 0:5a2a05d43d2a 116 #define _GET 0x08 //
jf1vrr 0:5a2a05d43d2a 117 #define _TCT 0x09 //
jf1vrr 0:5a2a05d43d2a 118 #define _LLO 0x11 //Local Lock Out
jf1vrr 0:5a2a05d43d2a 119 #define _DCL 0x14 //
jf1vrr 0:5a2a05d43d2a 120 #define _PPU 0x15 //
jf1vrr 0:5a2a05d43d2a 121 #define _SPE 0x18 //
jf1vrr 0:5a2a05d43d2a 122 #define _SPD 0x19 //
jf1vrr 0:5a2a05d43d2a 123 #define _UNL 0x3F //Unlisten
jf1vrr 0:5a2a05d43d2a 124 #define _UNT 0x5F //Untalk
jf1vrr 0:5a2a05d43d2a 125
jf1vrr 0:5a2a05d43d2a 126 #define _BUFLEN 16
jf1vrr 0:5a2a05d43d2a 127
jf1vrr 0:5a2a05d43d2a 128 char databyte;
jf1vrr 0:5a2a05d43d2a 129 char databuff[_BUFLEN];
jf1vrr 0:5a2a05d43d2a 130
jf1vrr 0:5a2a05d43d2a 131 //Data write to Internal Register
jf1vrr 0:5a2a05d43d2a 132 //IN: RS = NAT7210 Internal Register Address
jf1vrr 0:5a2a05d43d2a 133 //IN: DATA = data byte to write
jf1vrr 0:5a2a05d43d2a 134 void GPIB_write() {
jf1vrr 0:5a2a05d43d2a 135 WR = _LOW;
jf1vrr 0:5a2a05d43d2a 136 wait_us(100);
jf1vrr 0:5a2a05d43d2a 137 WR = _HIGH;
jf1vrr 0:5a2a05d43d2a 138 }
jf1vrr 0:5a2a05d43d2a 139
jf1vrr 0:5a2a05d43d2a 140 //IN: RS = NAT7210 Internal Register Address
jf1vrr 0:5a2a05d43d2a 141 //OUT: databyte = get data byte
jf1vrr 0:5a2a05d43d2a 142 void GPIB_read() {
jf1vrr 0:5a2a05d43d2a 143 SET_READ;
jf1vrr 0:5a2a05d43d2a 144 RD = _LOW;
jf1vrr 0:5a2a05d43d2a 145 wait_us(100);
jf1vrr 0:5a2a05d43d2a 146 databyte = DATA;
jf1vrr 0:5a2a05d43d2a 147 wait_us(100);
jf1vrr 0:5a2a05d43d2a 148 RD = _HIGH;
jf1vrr 0:5a2a05d43d2a 149 SET_WRITE;
jf1vrr 0:5a2a05d43d2a 150 }
jf1vrr 0:5a2a05d43d2a 151
jf1vrr 0:5a2a05d43d2a 152 void auxcr(unsigned char aux_cmd){
jf1vrr 0:5a2a05d43d2a 153 RS = AUXCR;
jf1vrr 0:5a2a05d43d2a 154 DATA = aux_cmd;
jf1vrr 0:5a2a05d43d2a 155 GPIB_write();
jf1vrr 0:5a2a05d43d2a 156 if(aux_cmd == _gts) wait_ms(10);
jf1vrr 0:5a2a05d43d2a 157 }
jf1vrr 0:5a2a05d43d2a 158
jf1vrr 0:5a2a05d43d2a 159 void GPIB_in(unsigned char gpib_reg){
jf1vrr 0:5a2a05d43d2a 160 RS = gpib_reg;
jf1vrr 0:5a2a05d43d2a 161 GPIB_read();
jf1vrr 0:5a2a05d43d2a 162 }
jf1vrr 0:5a2a05d43d2a 163
jf1vrr 0:5a2a05d43d2a 164 //Data Output to GPIB bus
jf1vrr 0:5a2a05d43d2a 165 //IN: DATA = Data byte to out
jf1vrr 0:5a2a05d43d2a 166 void GPIB_DOUT(){
jf1vrr 0:5a2a05d43d2a 167 RS = CDOR;
jf1vrr 0:5a2a05d43d2a 168 GPIB_write(); //Data out
jf1vrr 0:5a2a05d43d2a 169 __WAIT_DOUT:
jf1vrr 0:5a2a05d43d2a 170 wait_ms(1);
jf1vrr 0:5a2a05d43d2a 171 GPIB_in(ISR0);
jf1vrr 0:5a2a05d43d2a 172 if ((databyte & _BO) == _BO) return; //Wait for buffer out
jf1vrr 0:5a2a05d43d2a 173 else {
jf1vrr 0:5a2a05d43d2a 174 //lcd.locate(0,0);
jf1vrr 0:5a2a05d43d2a 175 //lcd.printf("Waitng BO-1 ");
jf1vrr 0:5a2a05d43d2a 176 goto __WAIT_DOUT;
jf1vrr 0:5a2a05d43d2a 177 }
jf1vrr 0:5a2a05d43d2a 178 }
jf1vrr 0:5a2a05d43d2a 179
jf1vrr 0:5a2a05d43d2a 180 void GPIB_BOWT(){
jf1vrr 0:5a2a05d43d2a 181 __WAIT_DOWT:
jf1vrr 0:5a2a05d43d2a 182 GPIB_in(ISR0);
jf1vrr 0:5a2a05d43d2a 183 if ((databyte & _BO) == _BO) return; //Wait for buffer out
jf1vrr 0:5a2a05d43d2a 184 else {
jf1vrr 0:5a2a05d43d2a 185 //lcd.locate(0,0);
jf1vrr 0:5a2a05d43d2a 186 //lcd.printf("Waitng BO-2 ");
jf1vrr 0:5a2a05d43d2a 187 goto __WAIT_DOWT;
jf1vrr 0:5a2a05d43d2a 188 }
jf1vrr 0:5a2a05d43d2a 189 }
jf1vrr 0:5a2a05d43d2a 190
jf1vrr 0:5a2a05d43d2a 191 char GPIB_BIWT(){
jf1vrr 0:5a2a05d43d2a 192 __WAIT_BIWT:
jf1vrr 0:5a2a05d43d2a 193 GPIB_in(ISR0);
jf1vrr 0:5a2a05d43d2a 194 if((databyte & _BI) == 0) { //wait for Data available
jf1vrr 0:5a2a05d43d2a 195 //lcd.locate(0,1);
jf1vrr 0:5a2a05d43d2a 196 //lcd.printf("Waiting BI ");
jf1vrr 0:5a2a05d43d2a 197 goto __WAIT_BIWT;
jf1vrr 0:5a2a05d43d2a 198 }
jf1vrr 0:5a2a05d43d2a 199 GPIB_in(DIR); //Get data byte
jf1vrr 0:5a2a05d43d2a 200 return databyte;
jf1vrr 0:5a2a05d43d2a 201 }
jf1vrr 0:5a2a05d43d2a 202
jf1vrr 0:5a2a05d43d2a 203 void GPIB_out(unsigned char gpib_cmd){
jf1vrr 0:5a2a05d43d2a 204 DATA = gpib_cmd;
jf1vrr 0:5a2a05d43d2a 205 GPIB_DOUT(); //Out to GPIB data bus
jf1vrr 0:5a2a05d43d2a 206 }
jf1vrr 0:5a2a05d43d2a 207
jf1vrr 0:5a2a05d43d2a 208 void GPIB_OLA(unsigned char listener){
jf1vrr 0:5a2a05d43d2a 209 GPIB_out(0x20 + listener);
jf1vrr 0:5a2a05d43d2a 210 }
jf1vrr 0:5a2a05d43d2a 211
jf1vrr 0:5a2a05d43d2a 212 void GPIB_OTA(unsigned char talker){
jf1vrr 0:5a2a05d43d2a 213 GPIB_out(0x40 + talker);
jf1vrr 0:5a2a05d43d2a 214 }
jf1vrr 0:5a2a05d43d2a 215
jf1vrr 0:5a2a05d43d2a 216 void GPIB_DCL(){
jf1vrr 0:5a2a05d43d2a 217 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 218 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 219 GPIB_out(_UNT);
jf1vrr 0:5a2a05d43d2a 220 GPIB_out(_DCL);
jf1vrr 0:5a2a05d43d2a 221 auxcr(_gts); //ATNH
jf1vrr 0:5a2a05d43d2a 222 }
jf1vrr 0:5a2a05d43d2a 223
jf1vrr 0:5a2a05d43d2a 224 void GPIB_SDC(unsigned char listener){
jf1vrr 0:5a2a05d43d2a 225 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 226 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 227 auxcr(_set_ton); //MTA
jf1vrr 0:5a2a05d43d2a 228 GPIB_OLA(listener);
jf1vrr 0:5a2a05d43d2a 229 GPIB_out(_SDC);
jf1vrr 0:5a2a05d43d2a 230 auxcr(_gts); //ATNH
jf1vrr 0:5a2a05d43d2a 231 }
jf1vrr 0:5a2a05d43d2a 232
jf1vrr 0:5a2a05d43d2a 233 void GPIB_GPOUT(char *send_buffer){
jf1vrr 0:5a2a05d43d2a 234 int i;
jf1vrr 0:5a2a05d43d2a 235 for(i = 0; i < (_BUFLEN - 1); i++){
jf1vrr 0:5a2a05d43d2a 236 if(send_buffer[i] == NULL) goto __GPOUT_EXIT;
jf1vrr 0:5a2a05d43d2a 237 else {
jf1vrr 0:5a2a05d43d2a 238 GPIB_out(send_buffer[i]);
jf1vrr 0:5a2a05d43d2a 239 }
jf1vrr 0:5a2a05d43d2a 240 }
jf1vrr 0:5a2a05d43d2a 241 __GPOUT_EXIT:
jf1vrr 0:5a2a05d43d2a 242 GPIB_out(_CR); //Delimiter
jf1vrr 0:5a2a05d43d2a 243 auxcr(_feoi);
jf1vrr 0:5a2a05d43d2a 244 GPIB_out(_LF);
jf1vrr 0:5a2a05d43d2a 245 }
jf1vrr 0:5a2a05d43d2a 246
jf1vrr 0:5a2a05d43d2a 247 int GPIB_GPIN(char *rcv_buffer){
jf1vrr 0:5a2a05d43d2a 248 int i;
jf1vrr 0:5a2a05d43d2a 249 auxcr(_set_hdfa);
jf1vrr 0:5a2a05d43d2a 250 for(i = 0; i < (_BUFLEN - 1); i++){
jf1vrr 0:5a2a05d43d2a 251 rcv_buffer[i] = GPIB_BIWT(); //Get byte
jf1vrr 0:5a2a05d43d2a 252 if(rcv_buffer[i] == _LF) { //Delimiter?
jf1vrr 0:5a2a05d43d2a 253 rcv_buffer[i] = NULL;
jf1vrr 0:5a2a05d43d2a 254 goto __GPIN_EXIT;
jf1vrr 0:5a2a05d43d2a 255 } else if(rcv_buffer[i] == _CR) { //Ignor
jf1vrr 0:5a2a05d43d2a 256 i--;
jf1vrr 0:5a2a05d43d2a 257 }
jf1vrr 0:5a2a05d43d2a 258 auxcr(_rhdf); //Next
jf1vrr 0:5a2a05d43d2a 259 }
jf1vrr 0:5a2a05d43d2a 260 __GPIN_EXIT:
jf1vrr 0:5a2a05d43d2a 261 auxcr(_rhdf);
jf1vrr 0:5a2a05d43d2a 262 auxcr(_clr_hdfa);
jf1vrr 0:5a2a05d43d2a 263 return i;
jf1vrr 0:5a2a05d43d2a 264 }
jf1vrr 0:5a2a05d43d2a 265
jf1vrr 0:5a2a05d43d2a 266 void GPIB_IFC(){
jf1vrr 0:5a2a05d43d2a 267 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 268 wait_ms(1);
jf1vrr 0:5a2a05d43d2a 269 auxcr(_set_sic);
jf1vrr 0:5a2a05d43d2a 270 wait_us(100);
jf1vrr 0:5a2a05d43d2a 271 auxcr(_clr_sic);
jf1vrr 0:5a2a05d43d2a 272 wait_ms(1);
jf1vrr 0:5a2a05d43d2a 273 auxcr(_gts); //ATNH
jf1vrr 0:5a2a05d43d2a 274 }
jf1vrr 0:5a2a05d43d2a 275
jf1vrr 0:5a2a05d43d2a 276 void GPIB_OUTPUT(char *send_buffer, unsigned char listener){
jf1vrr 0:5a2a05d43d2a 277 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 278 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 279 auxcr(_set_ton); //MTA
jf1vrr 0:5a2a05d43d2a 280 GPIB_OLA(listener);
jf1vrr 0:5a2a05d43d2a 281 auxcr(_gts); //ATNH
jf1vrr 0:5a2a05d43d2a 282 GPIB_BOWT(); //wait talker
jf1vrr 0:5a2a05d43d2a 283 GPIB_GPOUT(send_buffer);
jf1vrr 0:5a2a05d43d2a 284 }
jf1vrr 0:5a2a05d43d2a 285
jf1vrr 0:5a2a05d43d2a 286 int GPIB_ENTER(char *rcv_buffer, unsigned char talker){
jf1vrr 0:5a2a05d43d2a 287 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 288 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 289 GPIB_OTA(talker);
jf1vrr 0:5a2a05d43d2a 290 auxcr(_set_lon); //MLA
jf1vrr 0:5a2a05d43d2a 291 auxcr(_gts);
jf1vrr 0:5a2a05d43d2a 292 return GPIB_GPIN(rcv_buffer);
jf1vrr 0:5a2a05d43d2a 293 }
jf1vrr 0:5a2a05d43d2a 294
jf1vrr 0:5a2a05d43d2a 295 void GPIB_REMOTE(unsigned char listener){
jf1vrr 0:5a2a05d43d2a 296 auxcr(_set_sre); //REN
jf1vrr 0:5a2a05d43d2a 297 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 298 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 299 auxcr(_set_ton); //MTA
jf1vrr 0:5a2a05d43d2a 300 GPIB_OLA(listener);
jf1vrr 0:5a2a05d43d2a 301 auxcr(_gts);
jf1vrr 0:5a2a05d43d2a 302 }
jf1vrr 0:5a2a05d43d2a 303
jf1vrr 0:5a2a05d43d2a 304 void GPIB_LOCAL(unsigned char listener){
jf1vrr 0:5a2a05d43d2a 305 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 306 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 307 auxcr(_set_ton); //MTA
jf1vrr 0:5a2a05d43d2a 308 GPIB_OLA(listener);
jf1vrr 0:5a2a05d43d2a 309 GPIB_out(_GTL);
jf1vrr 0:5a2a05d43d2a 310 auxcr(_gts); //ATNH
jf1vrr 0:5a2a05d43d2a 311 }
jf1vrr 0:5a2a05d43d2a 312
jf1vrr 0:5a2a05d43d2a 313 void GPIB_TRIGER(unsigned char listener){
jf1vrr 0:5a2a05d43d2a 314 auxcr(_tca); //ATNL
jf1vrr 0:5a2a05d43d2a 315 GPIB_out(_UNL);
jf1vrr 0:5a2a05d43d2a 316 auxcr(_set_ton); //MTA
jf1vrr 0:5a2a05d43d2a 317 GPIB_OLA(listener);
jf1vrr 0:5a2a05d43d2a 318 GPIB_out(_GET);
jf1vrr 0:5a2a05d43d2a 319 auxcr(_gts); //ATNH
jf1vrr 0:5a2a05d43d2a 320 }
jf1vrr 0:5a2a05d43d2a 321
jf1vrr 0:5a2a05d43d2a 322 void GPIB_Init(unsigned char my_address){
jf1vrr 0:5a2a05d43d2a 323 SET_WRITE;
jf1vrr 0:5a2a05d43d2a 324
jf1vrr 0:5a2a05d43d2a 325 RD = _HIGH;
jf1vrr 0:5a2a05d43d2a 326 WR = _HIGH;
jf1vrr 0:5a2a05d43d2a 327
jf1vrr 0:5a2a05d43d2a 328 RS = AUXMR;
jf1vrr 0:5a2a05d43d2a 329 DATA = _sw9914; //Switch To 9914 Mode
jf1vrr 0:5a2a05d43d2a 330 GPIB_write();
jf1vrr 0:5a2a05d43d2a 331
jf1vrr 0:5a2a05d43d2a 332 //RS = AUXCR;
jf1vrr 0:5a2a05d43d2a 333 //DATA = _ch_rst; //Chip Reset and pon
jf1vrr 0:5a2a05d43d2a 334 //GPIB_write();
jf1vrr 0:5a2a05d43d2a 335
jf1vrr 0:5a2a05d43d2a 336 RS = AUXCR;
jf1vrr 0:5a2a05d43d2a 337 DATA = _set_swrst; //Set Software Reset
jf1vrr 0:5a2a05d43d2a 338 GPIB_write();
jf1vrr 0:5a2a05d43d2a 339
jf1vrr 0:5a2a05d43d2a 340 wait_ms(1);
jf1vrr 0:5a2a05d43d2a 341
jf1vrr 0:5a2a05d43d2a 342 RS = AUXCR;
jf1vrr 0:5a2a05d43d2a 343 DATA = _clr_swrst; //Clear Software Reset
jf1vrr 0:5a2a05d43d2a 344 GPIB_write();
jf1vrr 0:5a2a05d43d2a 345
jf1vrr 0:5a2a05d43d2a 346 RS = ADR;
jf1vrr 0:5a2a05d43d2a 347 DATA = my_address; //Set My Address
jf1vrr 0:5a2a05d43d2a 348 GPIB_write();
jf1vrr 0:5a2a05d43d2a 349
jf1vrr 0:5a2a05d43d2a 350 RS = AUXCR;
jf1vrr 0:5a2a05d43d2a 351 DATA = _set_dai; //Set Disable All Interrupt
jf1vrr 0:5a2a05d43d2a 352 GPIB_write();
jf1vrr 0:5a2a05d43d2a 353
jf1vrr 0:5a2a05d43d2a 354 RS = ISR0; //Clear Interrupt Status Register 0
jf1vrr 0:5a2a05d43d2a 355 GPIB_read();
jf1vrr 0:5a2a05d43d2a 356
jf1vrr 0:5a2a05d43d2a 357 RS = ISR1; //Clear Interrupt Status Register 1
jf1vrr 0:5a2a05d43d2a 358 GPIB_read();
jf1vrr 0:5a2a05d43d2a 359
jf1vrr 0:5a2a05d43d2a 360 RS = SPMR; //Clear Serial Poll register
jf1vrr 0:5a2a05d43d2a 361 DATA = 0;
jf1vrr 0:5a2a05d43d2a 362 GPIB_write();
jf1vrr 0:5a2a05d43d2a 363
jf1vrr 0:5a2a05d43d2a 364 RS = PPR; //Clear Parallel Poll register
jf1vrr 0:5a2a05d43d2a 365 DATA = 0;
jf1vrr 0:5a2a05d43d2a 366 GPIB_write();
jf1vrr 0:5a2a05d43d2a 367
jf1vrr 0:5a2a05d43d2a 368 RS = IMR0; //Disable interrupt IMR0
jf1vrr 0:5a2a05d43d2a 369 DATA = 0;
jf1vrr 0:5a2a05d43d2a 370 GPIB_write();
jf1vrr 0:5a2a05d43d2a 371
jf1vrr 0:5a2a05d43d2a 372 RS = IMR1; //Disable interrupt IMR1
jf1vrr 0:5a2a05d43d2a 373 DATA = 0;
jf1vrr 0:5a2a05d43d2a 374 GPIB_write();
jf1vrr 0:5a2a05d43d2a 375
jf1vrr 0:5a2a05d43d2a 376 RS = DIR; //Clear Data In Register
jf1vrr 0:5a2a05d43d2a 377 GPIB_read();
jf1vrr 0:5a2a05d43d2a 378
jf1vrr 0:5a2a05d43d2a 379 RS = CDOR; //Clear Command/Data Out Register
jf1vrr 0:5a2a05d43d2a 380 DATA = 0;
jf1vrr 0:5a2a05d43d2a 381 GPIB_write();
jf1vrr 0:5a2a05d43d2a 382
jf1vrr 0:5a2a05d43d2a 383 RS = AUXCR; //Set T1 Delay
jf1vrr 0:5a2a05d43d2a 384 DATA = _set_std1;
jf1vrr 0:5a2a05d43d2a 385 GPIB_write();
jf1vrr 0:5a2a05d43d2a 386 }