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diyembedded nrf24l01 tutorial 2 ported to mbed lpc1768
See diyembedded tutorials for more info
-Pull down p20 for receive mode
-Pull up p20 for transmitter mode
nRF24L01P/nrf24l01.h@0:2286a98ea739, 2012-12-08 (annotated)
- Committer:
- jeroen3
- Date:
- Sat Dec 08 22:11:23 2012 +0000
- Revision:
- 0:2286a98ea739
diyembedded.com nrf24l01 lib with shockburs tutorial 2 on mbed
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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jeroen3 | 0:2286a98ea739 | 1 | /****************************************************************************** |
jeroen3 | 0:2286a98ea739 | 2 | * |
jeroen3 | 0:2286a98ea739 | 3 | * File: nrf24l01.h |
jeroen3 | 0:2286a98ea739 | 4 | * |
jeroen3 | 0:2286a98ea739 | 5 | * Copyright S. Brennen Ball, 2006-2007 |
jeroen3 | 0:2286a98ea739 | 6 | * |
jeroen3 | 0:2286a98ea739 | 7 | * The author provides no guarantees, warantees, or promises, implied or |
jeroen3 | 0:2286a98ea739 | 8 | * otherwise. By using this software you agree to indemnify the author |
jeroen3 | 0:2286a98ea739 | 9 | * of any damages incurred by using it. |
jeroen3 | 0:2286a98ea739 | 10 | * |
jeroen3 | 0:2286a98ea739 | 11 | *****************************************************************************/ |
jeroen3 | 0:2286a98ea739 | 12 | |
jeroen3 | 0:2286a98ea739 | 13 | #ifndef NRF24L01_H_ |
jeroen3 | 0:2286a98ea739 | 14 | #define NRF24L01_H_ |
jeroen3 | 0:2286a98ea739 | 15 | |
jeroen3 | 0:2286a98ea739 | 16 | #include <stddef.h> |
jeroen3 | 0:2286a98ea739 | 17 | |
jeroen3 | 0:2286a98ea739 | 18 | #ifndef bool |
jeroen3 | 0:2286a98ea739 | 19 | #define bool unsigned char |
jeroen3 | 0:2286a98ea739 | 20 | #endif |
jeroen3 | 0:2286a98ea739 | 21 | #ifndef false |
jeroen3 | 0:2286a98ea739 | 22 | #define false 0 |
jeroen3 | 0:2286a98ea739 | 23 | #endif |
jeroen3 | 0:2286a98ea739 | 24 | #ifndef true |
jeroen3 | 0:2286a98ea739 | 25 | #define true !false |
jeroen3 | 0:2286a98ea739 | 26 | #endif |
jeroen3 | 0:2286a98ea739 | 27 | |
jeroen3 | 0:2286a98ea739 | 28 | ///////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 29 | // SPI function requirements |
jeroen3 | 0:2286a98ea739 | 30 | // |
jeroen3 | 0:2286a98ea739 | 31 | // The user must define a function to send one byte of data and also return the |
jeroen3 | 0:2286a98ea739 | 32 | // resulting byte of data data through the SPI port. The function used here |
jeroen3 | 0:2286a98ea739 | 33 | // has the function prototype |
jeroen3 | 0:2286a98ea739 | 34 | // |
jeroen3 | 0:2286a98ea739 | 35 | // unsigned char spi_send_read_byte(unsigned char byte); |
jeroen3 | 0:2286a98ea739 | 36 | // |
jeroen3 | 0:2286a98ea739 | 37 | // This function should take the argument unsigned char byte and send it through |
jeroen3 | 0:2286a98ea739 | 38 | // the SPI port to the 24L01. Then, it should wait until the 24L01 has returned |
jeroen3 | 0:2286a98ea739 | 39 | // its response over SPI. This received byte should be the return value of the |
jeroen3 | 0:2286a98ea739 | 40 | // function. |
jeroen3 | 0:2286a98ea739 | 41 | // |
jeroen3 | 0:2286a98ea739 | 42 | // You should also change the include file name below to whatever the name of your |
jeroen3 | 0:2286a98ea739 | 43 | // SPI include file is. |
jeroen3 | 0:2286a98ea739 | 44 | ////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 45 | //#include "spi1.h" |
jeroen3 | 0:2286a98ea739 | 46 | #define spi_send_read_byte(byte) nRF_spi.write(byte) |
jeroen3 | 0:2286a98ea739 | 47 | |
jeroen3 | 0:2286a98ea739 | 48 | |
jeroen3 | 0:2286a98ea739 | 49 | ///////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 50 | // Delay function requirements |
jeroen3 | 0:2286a98ea739 | 51 | // |
jeroen3 | 0:2286a98ea739 | 52 | // The user must define a function that delays for the specified number of |
jeroen3 | 0:2286a98ea739 | 53 | // microseconds. This function needs to be as precise as possible, and the use |
jeroen3 | 0:2286a98ea739 | 54 | // of a timer module within your microcontroller is highly recommended. The |
jeroen3 | 0:2286a98ea739 | 55 | // function used here has the prototype |
jeroen3 | 0:2286a98ea739 | 56 | // |
jeroen3 | 0:2286a98ea739 | 57 | // void delay_us(unsigned int microseconds); |
jeroen3 | 0:2286a98ea739 | 58 | // |
jeroen3 | 0:2286a98ea739 | 59 | // You should also change the include file name below to whatever the name of your |
jeroen3 | 0:2286a98ea739 | 60 | // delay include file is. |
jeroen3 | 0:2286a98ea739 | 61 | ////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 62 | //#include "delays.h" |
jeroen3 | 0:2286a98ea739 | 63 | #define delay_us(microseconds) wait_us(microseconds) |
jeroen3 | 0:2286a98ea739 | 64 | |
jeroen3 | 0:2286a98ea739 | 65 | |
jeroen3 | 0:2286a98ea739 | 66 | ////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 67 | // IO pin definitions |
jeroen3 | 0:2286a98ea739 | 68 | // |
jeroen3 | 0:2286a98ea739 | 69 | // Below you will find several definitions and includes. The first is an #include |
jeroen3 | 0:2286a98ea739 | 70 | // for your microcontroller's include file to allow you to use register names |
jeroen3 | 0:2286a98ea739 | 71 | // rather than numbers. The next three are to allow you to control the pins on |
jeroen3 | 0:2286a98ea739 | 72 | // the 24L01 that aren't automatically handled by SPI. These are CE, CSN, and |
jeroen3 | 0:2286a98ea739 | 73 | // IRQ. |
jeroen3 | 0:2286a98ea739 | 74 | // |
jeroen3 | 0:2286a98ea739 | 75 | // The general format of these defines is a define for the IO register the pin is |
jeroen3 | 0:2286a98ea739 | 76 | // attached to. The second define is a mask for the pin. For example, say that |
jeroen3 | 0:2286a98ea739 | 77 | // your CE pin is tied to an IO port with the register name IOPORT1. Also, let's |
jeroen3 | 0:2286a98ea739 | 78 | // say that the IO port is 8-bits wide, and you have attached the pin to pin 0 of |
jeroen3 | 0:2286a98ea739 | 79 | // the port. Then your define would look like this: |
jeroen3 | 0:2286a98ea739 | 80 | // |
jeroen3 | 0:2286a98ea739 | 81 | // #define nrf24l01_CE_IOREGISTER IOPORT1 |
jeroen3 | 0:2286a98ea739 | 82 | // #define nrf24l01_CE_PINMASK 0x01 |
jeroen3 | 0:2286a98ea739 | 83 | // |
jeroen3 | 0:2286a98ea739 | 84 | // If you have defines in your include file for individual IO pins, you could use |
jeroen3 | 0:2286a98ea739 | 85 | // this define in this file, as well. Using the previous example, assume that in |
jeroen3 | 0:2286a98ea739 | 86 | // your microcontroller's include file, pin 0 of IOPORT1 has a define like this |
jeroen3 | 0:2286a98ea739 | 87 | // |
jeroen3 | 0:2286a98ea739 | 88 | // #define IOPORT1_PIN0 0x01 |
jeroen3 | 0:2286a98ea739 | 89 | // |
jeroen3 | 0:2286a98ea739 | 90 | // Then, you could make your defines for the CE pin in this file look like this: |
jeroen3 | 0:2286a98ea739 | 91 | // |
jeroen3 | 0:2286a98ea739 | 92 | // #define nrf24l01_CE_IOREGISTER IOPORT1 |
jeroen3 | 0:2286a98ea739 | 93 | // #define nrf24l01_CE_PINMASK IOPORT1_PIN0 |
jeroen3 | 0:2286a98ea739 | 94 | // |
jeroen3 | 0:2286a98ea739 | 95 | // You should also change the include file name below to whatever the name of your |
jeroen3 | 0:2286a98ea739 | 96 | // processor's register definition include file is. |
jeroen3 | 0:2286a98ea739 | 97 | ///////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 98 | //#include "lpc214x.h" |
jeroen3 | 0:2286a98ea739 | 99 | |
jeroen3 | 0:2286a98ea739 | 100 | //defines for uC pins CE pin is connected to |
jeroen3 | 0:2286a98ea739 | 101 | //This is used so that the routines can send TX payload data and |
jeroen3 | 0:2286a98ea739 | 102 | // properly initialize the nrf24l01 in TX and RX states. |
jeroen3 | 0:2286a98ea739 | 103 | //Change these definitions (and then recompile) to suit your particular application. |
jeroen3 | 0:2286a98ea739 | 104 | #define nrf24l01_CE_IOREGISTER pinCE |
jeroen3 | 0:2286a98ea739 | 105 | #define nrf24l01_CE_PINMASK 1 |
jeroen3 | 0:2286a98ea739 | 106 | |
jeroen3 | 0:2286a98ea739 | 107 | //defines for uC pins CSN pin is connected to |
jeroen3 | 0:2286a98ea739 | 108 | //This is used so that the routines can send properly operate the SPI interface |
jeroen3 | 0:2286a98ea739 | 109 | // on the nrf24l01. |
jeroen3 | 0:2286a98ea739 | 110 | //Change these definitions (and then recompile) to suit your particular application. |
jeroen3 | 0:2286a98ea739 | 111 | #define nrf24l01_CSN_IOREGISTER pinCSN |
jeroen3 | 0:2286a98ea739 | 112 | #define nrf24l01_CSN_PINMASK 1 |
jeroen3 | 0:2286a98ea739 | 113 | |
jeroen3 | 0:2286a98ea739 | 114 | //defines for uC pins IRQ pin is connected to |
jeroen3 | 0:2286a98ea739 | 115 | //This is used so that the routines can poll for IRQ or create an ISR. |
jeroen3 | 0:2286a98ea739 | 116 | //Change these definitions (and then recompile) to suit your particular application. |
jeroen3 | 0:2286a98ea739 | 117 | #define nrf24l01_IRQ_IOREGISTER pinIRQ |
jeroen3 | 0:2286a98ea739 | 118 | #define nrf24l01_IRQ_PINMASK 1 |
jeroen3 | 0:2286a98ea739 | 119 | |
jeroen3 | 0:2286a98ea739 | 120 | |
jeroen3 | 0:2286a98ea739 | 121 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 122 | // SPI commands |
jeroen3 | 0:2286a98ea739 | 123 | // |
jeroen3 | 0:2286a98ea739 | 124 | // The following are defines for all of the commands and data masks on the SPI |
jeroen3 | 0:2286a98ea739 | 125 | // interface. |
jeroen3 | 0:2286a98ea739 | 126 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 127 | //SPI command defines |
jeroen3 | 0:2286a98ea739 | 128 | #define nrf24l01_R_REGISTER 0x00 |
jeroen3 | 0:2286a98ea739 | 129 | #define nrf24l01_W_REGISTER 0x20 |
jeroen3 | 0:2286a98ea739 | 130 | #define nrf24l01_R_RX_PAYLOAD 0x61 |
jeroen3 | 0:2286a98ea739 | 131 | #define nrf24l01_W_TX_PAYLOAD 0xA0 |
jeroen3 | 0:2286a98ea739 | 132 | #define nrf24l01_FLUSH_TX 0xE1 |
jeroen3 | 0:2286a98ea739 | 133 | #define nrf24l01_FLUSH_RX 0xE2 |
jeroen3 | 0:2286a98ea739 | 134 | #define nrf24l01_REUSE_TX_PL 0xE3 |
jeroen3 | 0:2286a98ea739 | 135 | #define nrf24l01_NOP 0xFF |
jeroen3 | 0:2286a98ea739 | 136 | |
jeroen3 | 0:2286a98ea739 | 137 | //SPI command data mask defines |
jeroen3 | 0:2286a98ea739 | 138 | #define nrf24l01_R_REGISTER_DATA 0x1F |
jeroen3 | 0:2286a98ea739 | 139 | #define nrf24l01_W_REGISTER_DATA 0x1F |
jeroen3 | 0:2286a98ea739 | 140 | |
jeroen3 | 0:2286a98ea739 | 141 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 142 | // Register definitions |
jeroen3 | 0:2286a98ea739 | 143 | // |
jeroen3 | 0:2286a98ea739 | 144 | // Below are the defines for each register's address in the 24L01. |
jeroen3 | 0:2286a98ea739 | 145 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 146 | #define nrf24l01_CONFIG 0x00 |
jeroen3 | 0:2286a98ea739 | 147 | #define nrf24l01_EN_AA 0x01 |
jeroen3 | 0:2286a98ea739 | 148 | #define nrf24l01_EN_RXADDR 0x02 |
jeroen3 | 0:2286a98ea739 | 149 | #define nrf24l01_SETUP_AW 0x03 |
jeroen3 | 0:2286a98ea739 | 150 | #define nrf24l01_SETUP_RETR 0x04 |
jeroen3 | 0:2286a98ea739 | 151 | #define nrf24l01_RF_CH 0x05 |
jeroen3 | 0:2286a98ea739 | 152 | #define nrf24l01_RF_SETUP 0x06 |
jeroen3 | 0:2286a98ea739 | 153 | #define nrf24l01_STATUS 0x07 |
jeroen3 | 0:2286a98ea739 | 154 | #define nrf24l01_OBSERVE_TX 0x08 |
jeroen3 | 0:2286a98ea739 | 155 | #define nrf24l01_CD 0x09 |
jeroen3 | 0:2286a98ea739 | 156 | #define nrf24l01_RX_ADDR_P0 0x0A |
jeroen3 | 0:2286a98ea739 | 157 | #define nrf24l01_RX_ADDR_P1 0x0B |
jeroen3 | 0:2286a98ea739 | 158 | #define nrf24l01_RX_ADDR_P2 0x0C |
jeroen3 | 0:2286a98ea739 | 159 | #define nrf24l01_RX_ADDR_P3 0x0D |
jeroen3 | 0:2286a98ea739 | 160 | #define nrf24l01_RX_ADDR_P4 0x0E |
jeroen3 | 0:2286a98ea739 | 161 | #define nrf24l01_RX_ADDR_P5 0x0F |
jeroen3 | 0:2286a98ea739 | 162 | #define nrf24l01_TX_ADDR 0x10 |
jeroen3 | 0:2286a98ea739 | 163 | #define nrf24l01_RX_PW_P0 0x11 |
jeroen3 | 0:2286a98ea739 | 164 | #define nrf24l01_RX_PW_P1 0x12 |
jeroen3 | 0:2286a98ea739 | 165 | #define nrf24l01_RX_PW_P2 0x13 |
jeroen3 | 0:2286a98ea739 | 166 | #define nrf24l01_RX_PW_P3 0x14 |
jeroen3 | 0:2286a98ea739 | 167 | #define nrf24l01_RX_PW_P4 0x15 |
jeroen3 | 0:2286a98ea739 | 168 | #define nrf24l01_RX_PW_P5 0x16 |
jeroen3 | 0:2286a98ea739 | 169 | #define nrf24l01_FIFO_STATUS 0x17 |
jeroen3 | 0:2286a98ea739 | 170 | |
jeroen3 | 0:2286a98ea739 | 171 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 172 | // Default register values |
jeroen3 | 0:2286a98ea739 | 173 | // |
jeroen3 | 0:2286a98ea739 | 174 | // Below are the defines for each register's default value in the 24L01. Multi-byte |
jeroen3 | 0:2286a98ea739 | 175 | // registers use notation B<X>, where "B" represents "byte" and <X> is the byte |
jeroen3 | 0:2286a98ea739 | 176 | // number. |
jeroen3 | 0:2286a98ea739 | 177 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 178 | #define nrf24l01_CONFIG_DEFAULT_VAL 0x08 |
jeroen3 | 0:2286a98ea739 | 179 | #define nrf24l01_EN_AA_DEFAULT_VAL 0x3F |
jeroen3 | 0:2286a98ea739 | 180 | #define nrf24l01_EN_RXADDR_DEFAULT_VAL 0x03 |
jeroen3 | 0:2286a98ea739 | 181 | #define nrf24l01_SETUP_AW_DEFAULT_VAL 0x03 |
jeroen3 | 0:2286a98ea739 | 182 | #define nrf24l01_SETUP_RETR_DEFAULT_VAL 0x03 |
jeroen3 | 0:2286a98ea739 | 183 | #define nrf24l01_RF_CH_DEFAULT_VAL 0x02 |
jeroen3 | 0:2286a98ea739 | 184 | #define nrf24l01_RF_SETUP_DEFAULT_VAL 0x0F |
jeroen3 | 0:2286a98ea739 | 185 | #define nrf24l01_STATUS_DEFAULT_VAL 0x0E |
jeroen3 | 0:2286a98ea739 | 186 | #define nrf24l01_OBSERVE_TX_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 187 | #define nrf24l01_CD_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 188 | #define nrf24l01_RX_ADDR_P0_B0_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 189 | #define nrf24l01_RX_ADDR_P0_B1_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 190 | #define nrf24l01_RX_ADDR_P0_B2_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 191 | #define nrf24l01_RX_ADDR_P0_B3_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 192 | #define nrf24l01_RX_ADDR_P0_B4_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 193 | #define nrf24l01_RX_ADDR_P1_B0_DEFAULT_VAL 0xC2 |
jeroen3 | 0:2286a98ea739 | 194 | #define nrf24l01_RX_ADDR_P1_B1_DEFAULT_VAL 0xC2 |
jeroen3 | 0:2286a98ea739 | 195 | #define nrf24l01_RX_ADDR_P1_B2_DEFAULT_VAL 0xC2 |
jeroen3 | 0:2286a98ea739 | 196 | #define nrf24l01_RX_ADDR_P1_B3_DEFAULT_VAL 0xC2 |
jeroen3 | 0:2286a98ea739 | 197 | #define nrf24l01_RX_ADDR_P1_B4_DEFAULT_VAL 0xC2 |
jeroen3 | 0:2286a98ea739 | 198 | #define nrf24l01_RX_ADDR_P2_DEFAULT_VAL 0xC3 |
jeroen3 | 0:2286a98ea739 | 199 | #define nrf24l01_RX_ADDR_P3_DEFAULT_VAL 0xC4 |
jeroen3 | 0:2286a98ea739 | 200 | #define nrf24l01_RX_ADDR_P4_DEFAULT_VAL 0xC5 |
jeroen3 | 0:2286a98ea739 | 201 | #define nrf24l01_RX_ADDR_P5_DEFAULT_VAL 0xC6 |
jeroen3 | 0:2286a98ea739 | 202 | #define nrf24l01_TX_ADDR_B0_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 203 | #define nrf24l01_TX_ADDR_B1_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 204 | #define nrf24l01_TX_ADDR_B2_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 205 | #define nrf24l01_TX_ADDR_B3_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 206 | #define nrf24l01_TX_ADDR_B4_DEFAULT_VAL 0xE7 |
jeroen3 | 0:2286a98ea739 | 207 | #define nrf24l01_RX_PW_P0_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 208 | #define nrf24l01_RX_PW_P1_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 209 | #define nrf24l01_RX_PW_P2_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 210 | #define nrf24l01_RX_PW_P3_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 211 | #define nrf24l01_RX_PW_P4_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 212 | #define nrf24l01_RX_PW_P5_DEFAULT_VAL 0x00 |
jeroen3 | 0:2286a98ea739 | 213 | #define nrf24l01_FIFO_STATUS_DEFAULT_VAL 0x11 |
jeroen3 | 0:2286a98ea739 | 214 | |
jeroen3 | 0:2286a98ea739 | 215 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 216 | // Register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 217 | // |
jeroen3 | 0:2286a98ea739 | 218 | // Below are the defines for each register's bitwise fields in the 24L01. |
jeroen3 | 0:2286a98ea739 | 219 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 220 | //CONFIG register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 221 | #define nrf24l01_CONFIG_RESERVED 0x80 |
jeroen3 | 0:2286a98ea739 | 222 | #define nrf24l01_CONFIG_MASK_RX_DR 0x40 |
jeroen3 | 0:2286a98ea739 | 223 | #define nrf24l01_CONFIG_MASK_TX_DS 0x20 |
jeroen3 | 0:2286a98ea739 | 224 | #define nrf24l01_CONFIG_MASK_MAX_RT 0x10 |
jeroen3 | 0:2286a98ea739 | 225 | #define nrf24l01_CONFIG_EN_CRC 0x08 |
jeroen3 | 0:2286a98ea739 | 226 | #define nrf24l01_CONFIG_CRCO 0x04 |
jeroen3 | 0:2286a98ea739 | 227 | #define nrf24l01_CONFIG_PWR_UP 0x02 |
jeroen3 | 0:2286a98ea739 | 228 | #define nrf24l01_CONFIG_PRIM_RX 0x01 |
jeroen3 | 0:2286a98ea739 | 229 | |
jeroen3 | 0:2286a98ea739 | 230 | //EN_AA register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 231 | #define nrf24l01_EN_AA_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 232 | #define nrf24l01_EN_AA_ENAA_ALL 0x3F |
jeroen3 | 0:2286a98ea739 | 233 | #define nrf24l01_EN_AA_ENAA_P5 0x20 |
jeroen3 | 0:2286a98ea739 | 234 | #define nrf24l01_EN_AA_ENAA_P4 0x10 |
jeroen3 | 0:2286a98ea739 | 235 | #define nrf24l01_EN_AA_ENAA_P3 0x08 |
jeroen3 | 0:2286a98ea739 | 236 | #define nrf24l01_EN_AA_ENAA_P2 0x04 |
jeroen3 | 0:2286a98ea739 | 237 | #define nrf24l01_EN_AA_ENAA_P1 0x02 |
jeroen3 | 0:2286a98ea739 | 238 | #define nrf24l01_EN_AA_ENAA_P0 0x01 |
jeroen3 | 0:2286a98ea739 | 239 | #define nrf24l01_EN_AA_ENAA_NONE 0x00 |
jeroen3 | 0:2286a98ea739 | 240 | |
jeroen3 | 0:2286a98ea739 | 241 | //EN_RXADDR register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 242 | #define nrf24l01_EN_RXADDR_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 243 | #define nrf24l01_EN_RXADDR_ERX_ALL 0x3F |
jeroen3 | 0:2286a98ea739 | 244 | #define nrf24l01_EN_RXADDR_ERX_P5 0x20 |
jeroen3 | 0:2286a98ea739 | 245 | #define nrf24l01_EN_RXADDR_ERX_P4 0x10 |
jeroen3 | 0:2286a98ea739 | 246 | #define nrf24l01_EN_RXADDR_ERX_P3 0x08 |
jeroen3 | 0:2286a98ea739 | 247 | #define nrf24l01_EN_RXADDR_ERX_P2 0x04 |
jeroen3 | 0:2286a98ea739 | 248 | #define nrf24l01_EN_RXADDR_ERX_P1 0x02 |
jeroen3 | 0:2286a98ea739 | 249 | #define nrf24l01_EN_RXADDR_ERX_P0 0x01 |
jeroen3 | 0:2286a98ea739 | 250 | #define nrf24l01_EN_RXADDR_ERX_NONE 0x00 |
jeroen3 | 0:2286a98ea739 | 251 | |
jeroen3 | 0:2286a98ea739 | 252 | //SETUP_AW register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 253 | #define nrf24l01_SETUP_AW_RESERVED 0xFC |
jeroen3 | 0:2286a98ea739 | 254 | #define nrf24l01_SETUP_AW 0x03 |
jeroen3 | 0:2286a98ea739 | 255 | #define nrf24l01_SETUP_AW_5BYTES 0x03 |
jeroen3 | 0:2286a98ea739 | 256 | #define nrf24l01_SETUP_AW_4BYTES 0x02 |
jeroen3 | 0:2286a98ea739 | 257 | #define nrf24l01_SETUP_AW_3BYTES 0x01 |
jeroen3 | 0:2286a98ea739 | 258 | #define nrf24l01_SETUP_AW_ILLEGAL 0x00 |
jeroen3 | 0:2286a98ea739 | 259 | |
jeroen3 | 0:2286a98ea739 | 260 | //SETUP_RETR register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 261 | #define nrf24l01_SETUP_RETR_ARD 0xF0 |
jeroen3 | 0:2286a98ea739 | 262 | #define nrf24l01_SETUP_RETR_ARD_4000 0xF0 |
jeroen3 | 0:2286a98ea739 | 263 | #define nrf24l01_SETUP_RETR_ARD_3750 0xE0 |
jeroen3 | 0:2286a98ea739 | 264 | #define nrf24l01_SETUP_RETR_ARD_3500 0xD0 |
jeroen3 | 0:2286a98ea739 | 265 | #define nrf24l01_SETUP_RETR_ARD_3250 0xC0 |
jeroen3 | 0:2286a98ea739 | 266 | #define nrf24l01_SETUP_RETR_ARD_3000 0xB0 |
jeroen3 | 0:2286a98ea739 | 267 | #define nrf24l01_SETUP_RETR_ARD_2750 0xA0 |
jeroen3 | 0:2286a98ea739 | 268 | #define nrf24l01_SETUP_RETR_ARD_2500 0x90 |
jeroen3 | 0:2286a98ea739 | 269 | #define nrf24l01_SETUP_RETR_ARD_2250 0x80 |
jeroen3 | 0:2286a98ea739 | 270 | #define nrf24l01_SETUP_RETR_ARD_2000 0x70 |
jeroen3 | 0:2286a98ea739 | 271 | #define nrf24l01_SETUP_RETR_ARD_1750 0x60 |
jeroen3 | 0:2286a98ea739 | 272 | #define nrf24l01_SETUP_RETR_ARD_1500 0x50 |
jeroen3 | 0:2286a98ea739 | 273 | #define nrf24l01_SETUP_RETR_ARD_1250 0x40 |
jeroen3 | 0:2286a98ea739 | 274 | #define nrf24l01_SETUP_RETR_ARD_1000 0x30 |
jeroen3 | 0:2286a98ea739 | 275 | #define nrf24l01_SETUP_RETR_ARD_750 0x20 |
jeroen3 | 0:2286a98ea739 | 276 | #define nrf24l01_SETUP_RETR_ARD_500 0x10 |
jeroen3 | 0:2286a98ea739 | 277 | #define nrf24l01_SETUP_RETR_ARD_250 0x00 |
jeroen3 | 0:2286a98ea739 | 278 | #define nrf24l01_SETUP_RETR_ARC 0x0F |
jeroen3 | 0:2286a98ea739 | 279 | #define nrf24l01_SETUP_RETR_ARC_15 0x0F |
jeroen3 | 0:2286a98ea739 | 280 | #define nrf24l01_SETUP_RETR_ARC_14 0x0E |
jeroen3 | 0:2286a98ea739 | 281 | #define nrf24l01_SETUP_RETR_ARC_13 0x0D |
jeroen3 | 0:2286a98ea739 | 282 | #define nrf24l01_SETUP_RETR_ARC_12 0x0C |
jeroen3 | 0:2286a98ea739 | 283 | #define nrf24l01_SETUP_RETR_ARC_11 0x0B |
jeroen3 | 0:2286a98ea739 | 284 | #define nrf24l01_SETUP_RETR_ARC_10 0x0A |
jeroen3 | 0:2286a98ea739 | 285 | #define nrf24l01_SETUP_RETR_ARC_9 0x09 |
jeroen3 | 0:2286a98ea739 | 286 | #define nrf24l01_SETUP_RETR_ARC_8 0x08 |
jeroen3 | 0:2286a98ea739 | 287 | #define nrf24l01_SETUP_RETR_ARC_7 0x07 |
jeroen3 | 0:2286a98ea739 | 288 | #define nrf24l01_SETUP_RETR_ARC_6 0x06 |
jeroen3 | 0:2286a98ea739 | 289 | #define nrf24l01_SETUP_RETR_ARC_5 0x05 |
jeroen3 | 0:2286a98ea739 | 290 | #define nrf24l01_SETUP_RETR_ARC_4 0x04 |
jeroen3 | 0:2286a98ea739 | 291 | #define nrf24l01_SETUP_RETR_ARC_3 0x03 |
jeroen3 | 0:2286a98ea739 | 292 | #define nrf24l01_SETUP_RETR_ARC_2 0x02 |
jeroen3 | 0:2286a98ea739 | 293 | #define nrf24l01_SETUP_RETR_ARC_1 0x01 |
jeroen3 | 0:2286a98ea739 | 294 | #define nrf24l01_SETUP_RETR_ARC_0 0x00 |
jeroen3 | 0:2286a98ea739 | 295 | |
jeroen3 | 0:2286a98ea739 | 296 | //RF_CH register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 297 | #define nrf24l01_RF_CH_RESERVED 0x80 |
jeroen3 | 0:2286a98ea739 | 298 | |
jeroen3 | 0:2286a98ea739 | 299 | //RF_SETUP register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 300 | #define nrf24l01_RF_SETUP_RESERVED 0xE0 |
jeroen3 | 0:2286a98ea739 | 301 | #define nrf24l01_RF_SETUP_PLL_LOCK 0x10 |
jeroen3 | 0:2286a98ea739 | 302 | #define nrf24l01_RF_SETUP_RF_DR 0x08 |
jeroen3 | 0:2286a98ea739 | 303 | #define nrf24l01_RF_SETUP_RF_PWR 0x06 |
jeroen3 | 0:2286a98ea739 | 304 | #define nrf24l01_RF_SETUP_RF_PWR_0 0x06 |
jeroen3 | 0:2286a98ea739 | 305 | #define nrf24l01_RF_SETUP_RF_PWR_6 0x04 |
jeroen3 | 0:2286a98ea739 | 306 | #define nrf24l01_RF_SETUP_RF_PWR_12 0x02 |
jeroen3 | 0:2286a98ea739 | 307 | #define nrf24l01_RF_SETUP_RF_PWR_18 0x00 |
jeroen3 | 0:2286a98ea739 | 308 | #define nrf24l01_RF_SETUP_LNA_HCURR 0x01 |
jeroen3 | 0:2286a98ea739 | 309 | |
jeroen3 | 0:2286a98ea739 | 310 | //STATUS register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 311 | #define nrf24l01_STATUS_RESERVED 0x80 |
jeroen3 | 0:2286a98ea739 | 312 | #define nrf24l01_STATUS_RX_DR 0x40 |
jeroen3 | 0:2286a98ea739 | 313 | #define nrf24l01_STATUS_TX_DS 0x20 |
jeroen3 | 0:2286a98ea739 | 314 | #define nrf24l01_STATUS_MAX_RT 0x10 |
jeroen3 | 0:2286a98ea739 | 315 | #define nrf24l01_STATUS_RX_P_NO 0x0E |
jeroen3 | 0:2286a98ea739 | 316 | #define nrf24l01_STATUS_RX_P_NO_RX_FIFO_NOT_EMPTY 0x0E |
jeroen3 | 0:2286a98ea739 | 317 | #define nrf24l01_STATUS_RX_P_NO_UNUSED 0x0C |
jeroen3 | 0:2286a98ea739 | 318 | #define nrf24l01_STATUS_RX_P_NO_5 0x0A |
jeroen3 | 0:2286a98ea739 | 319 | #define nrf24l01_STATUS_RX_P_NO_4 0x08 |
jeroen3 | 0:2286a98ea739 | 320 | #define nrf24l01_STATUS_RX_P_NO_3 0x06 |
jeroen3 | 0:2286a98ea739 | 321 | #define nrf24l01_STATUS_RX_P_NO_2 0x04 |
jeroen3 | 0:2286a98ea739 | 322 | #define nrf24l01_STATUS_RX_P_NO_1 0x02 |
jeroen3 | 0:2286a98ea739 | 323 | #define nrf24l01_STATUS_RX_P_NO_0 0x00 |
jeroen3 | 0:2286a98ea739 | 324 | #define nrf24l01_STATUS_TX_FULL 0x01 |
jeroen3 | 0:2286a98ea739 | 325 | |
jeroen3 | 0:2286a98ea739 | 326 | //OBSERVE_TX register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 327 | #define nrf24l01_OBSERVE_TX_PLOS_CNT 0xF0 |
jeroen3 | 0:2286a98ea739 | 328 | #define nrf24l01_OBSERVE_TX_ARC_CNT 0x0F |
jeroen3 | 0:2286a98ea739 | 329 | |
jeroen3 | 0:2286a98ea739 | 330 | //CD register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 331 | #define nrf24l01_CD_RESERVED 0xFE |
jeroen3 | 0:2286a98ea739 | 332 | #define nrf24l01_CD_CD 0x01 |
jeroen3 | 0:2286a98ea739 | 333 | |
jeroen3 | 0:2286a98ea739 | 334 | //RX_PW_P0 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 335 | #define nrf24l01_RX_PW_P0_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 336 | |
jeroen3 | 0:2286a98ea739 | 337 | //RX_PW_P0 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 338 | #define nrf24l01_RX_PW_P0_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 339 | |
jeroen3 | 0:2286a98ea739 | 340 | //RX_PW_P1 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 341 | #define nrf24l01_RX_PW_P1_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 342 | |
jeroen3 | 0:2286a98ea739 | 343 | //RX_PW_P2 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 344 | #define nrf24l01_RX_PW_P2_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 345 | |
jeroen3 | 0:2286a98ea739 | 346 | //RX_PW_P3 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 347 | #define nrf24l01_RX_PW_P3_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 348 | |
jeroen3 | 0:2286a98ea739 | 349 | //RX_PW_P4 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 350 | #define nrf24l01_RX_PW_P4_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 351 | |
jeroen3 | 0:2286a98ea739 | 352 | //RX_PW_P5 register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 353 | #define nrf24l01_RX_PW_P5_RESERVED 0xC0 |
jeroen3 | 0:2286a98ea739 | 354 | |
jeroen3 | 0:2286a98ea739 | 355 | //FIFO_STATUS register bitwise definitions |
jeroen3 | 0:2286a98ea739 | 356 | #define nrf24l01_FIFO_STATUS_RESERVED 0x8C |
jeroen3 | 0:2286a98ea739 | 357 | #define nrf24l01_FIFO_STATUS_TX_REUSE 0x40 |
jeroen3 | 0:2286a98ea739 | 358 | #define nrf24l01_FIFO_STATUS_TX_FULL 0x20 |
jeroen3 | 0:2286a98ea739 | 359 | #define nrf24l01_FIFO_STATUS_TX_EMPTY 0x10 |
jeroen3 | 0:2286a98ea739 | 360 | #define nrf24l01_FIFO_STATUS_RX_FULL 0x02 |
jeroen3 | 0:2286a98ea739 | 361 | #define nrf24l01_FIFO_STATUS_RX_EMPTY 0x01 |
jeroen3 | 0:2286a98ea739 | 362 | |
jeroen3 | 0:2286a98ea739 | 363 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 364 | // Function declarations |
jeroen3 | 0:2286a98ea739 | 365 | // |
jeroen3 | 0:2286a98ea739 | 366 | // Below are all function definitions contained in the library. Please see |
jeroen3 | 0:2286a98ea739 | 367 | // nrf24l01.c for comments regarding the usage of each function. |
jeroen3 | 0:2286a98ea739 | 368 | //////////////////////////////////////////////////////////////////////////////////// |
jeroen3 | 0:2286a98ea739 | 369 | //initialization functions |
jeroen3 | 0:2286a98ea739 | 370 | void nrf24l01_initialize(unsigned char config, |
jeroen3 | 0:2286a98ea739 | 371 | unsigned char opt_rx_standby_mode, |
jeroen3 | 0:2286a98ea739 | 372 | unsigned char en_aa, |
jeroen3 | 0:2286a98ea739 | 373 | unsigned char en_rxaddr, |
jeroen3 | 0:2286a98ea739 | 374 | unsigned char setup_aw, |
jeroen3 | 0:2286a98ea739 | 375 | unsigned char setup_retr, |
jeroen3 | 0:2286a98ea739 | 376 | unsigned char rf_ch, |
jeroen3 | 0:2286a98ea739 | 377 | unsigned char rf_setup, |
jeroen3 | 0:2286a98ea739 | 378 | unsigned char * rx_addr_p0, |
jeroen3 | 0:2286a98ea739 | 379 | unsigned char * rx_addr_p1, |
jeroen3 | 0:2286a98ea739 | 380 | unsigned char rx_addr_p2, |
jeroen3 | 0:2286a98ea739 | 381 | unsigned char rx_addr_p3, |
jeroen3 | 0:2286a98ea739 | 382 | unsigned char rx_addr_p4, |
jeroen3 | 0:2286a98ea739 | 383 | unsigned char rx_addr_p5, |
jeroen3 | 0:2286a98ea739 | 384 | unsigned char * tx_addr, |
jeroen3 | 0:2286a98ea739 | 385 | unsigned char rx_pw_p0, |
jeroen3 | 0:2286a98ea739 | 386 | unsigned char rx_pw_p1, |
jeroen3 | 0:2286a98ea739 | 387 | unsigned char rx_pw_p2, |
jeroen3 | 0:2286a98ea739 | 388 | unsigned char rx_pw_p3, |
jeroen3 | 0:2286a98ea739 | 389 | unsigned char rx_pw_p4, |
jeroen3 | 0:2286a98ea739 | 390 | unsigned char rx_pw_p5); |
jeroen3 | 0:2286a98ea739 | 391 | void nrf24l01_initialize_debug(bool rx, unsigned char p0_payload_width, bool enable_auto_ack); |
jeroen3 | 0:2286a98ea739 | 392 | void nrf24l01_initialize_debug_lite(bool rx, unsigned char p0_payload_width); |
jeroen3 | 0:2286a98ea739 | 393 | |
jeroen3 | 0:2286a98ea739 | 394 | //power-up, power-down functions |
jeroen3 | 0:2286a98ea739 | 395 | void nrf24l01_power_up(bool rx_active_mode); |
jeroen3 | 0:2286a98ea739 | 396 | void nrf24l01_power_up_param(bool rx_active_mode, unsigned char config); |
jeroen3 | 0:2286a98ea739 | 397 | void nrf24l01_power_down(void); |
jeroen3 | 0:2286a98ea739 | 398 | void nrf24l01_power_down_param(unsigned char config); |
jeroen3 | 0:2286a98ea739 | 399 | |
jeroen3 | 0:2286a98ea739 | 400 | //SPI commands defined by the spec |
jeroen3 | 0:2286a98ea739 | 401 | //for regnumber values, see section above titled "register definitions" |
jeroen3 | 0:2286a98ea739 | 402 | //all functions return the STATUS register |
jeroen3 | 0:2286a98ea739 | 403 | unsigned char nrf24l01_write_register(unsigned char regnumber, unsigned char * data, unsigned int len); |
jeroen3 | 0:2286a98ea739 | 404 | unsigned char nrf24l01_read_register(unsigned char regnumber, unsigned char * data, unsigned int len); |
jeroen3 | 0:2286a98ea739 | 405 | unsigned char nrf24l01_write_tx_payload(unsigned char * data, unsigned int len, bool transmit); |
jeroen3 | 0:2286a98ea739 | 406 | unsigned char nrf24l01_read_rx_payload(unsigned char * data, unsigned int len); |
jeroen3 | 0:2286a98ea739 | 407 | unsigned char nrf24l01_flush_tx(void); |
jeroen3 | 0:2286a98ea739 | 408 | unsigned char nrf24l01_flush_rx(void); |
jeroen3 | 0:2286a98ea739 | 409 | unsigned char nrf24l01_reuse_tx_pl(void); |
jeroen3 | 0:2286a98ea739 | 410 | unsigned char nrf24l01_nop(void); |
jeroen3 | 0:2286a98ea739 | 411 | |
jeroen3 | 0:2286a98ea739 | 412 | //RX/TX setting functions |
jeroen3 | 0:2286a98ea739 | 413 | void nrf24l01_set_as_rx(bool rx_active_mode); |
jeroen3 | 0:2286a98ea739 | 414 | void nrf24l01_set_as_rx_param(bool rx_active_mode, unsigned char config); |
jeroen3 | 0:2286a98ea739 | 415 | void nrf24l01_rx_standby_to_active(void); |
jeroen3 | 0:2286a98ea739 | 416 | void nrf24l01_rx_active_to_standby(void); |
jeroen3 | 0:2286a98ea739 | 417 | void nrf24l01_set_as_tx(void); |
jeroen3 | 0:2286a98ea739 | 418 | void nrf24l01_set_as_tx_param(unsigned char config); |
jeroen3 | 0:2286a98ea739 | 419 | |
jeroen3 | 0:2286a98ea739 | 420 | //register-oriented get/set functions for commonly-used registers during operation |
jeroen3 | 0:2286a98ea739 | 421 | unsigned char nrf24l01_get_config(void); |
jeroen3 | 0:2286a98ea739 | 422 | void nrf24l01_set_config(unsigned char config); |
jeroen3 | 0:2286a98ea739 | 423 | unsigned char nrf24l01_get_rf_ch(void); |
jeroen3 | 0:2286a98ea739 | 424 | void nrf24l01_set_rf_ch(unsigned char channel); |
jeroen3 | 0:2286a98ea739 | 425 | unsigned char nrf24l01_get_status(void); |
jeroen3 | 0:2286a98ea739 | 426 | unsigned char nrf24l01_get_observe_tx(void); |
jeroen3 | 0:2286a98ea739 | 427 | void nrf24l01_set_rx_addr(unsigned char * address, unsigned int len, unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 428 | void nrf24l01_set_tx_addr(unsigned char * address, unsigned int len); |
jeroen3 | 0:2286a98ea739 | 429 | void nrf24l01_set_rx_pw(unsigned char payloadwidth, unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 430 | unsigned char nrf24l01_get_rx_pw(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 431 | unsigned char nrf24l01_get_fifo_status(void); |
jeroen3 | 0:2286a98ea739 | 432 | |
jeroen3 | 0:2286a98ea739 | 433 | //auto-ack and pipe-related functions |
jeroen3 | 0:2286a98ea739 | 434 | bool nrf24l01_aa_enabled(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 435 | void nrf24l01_aa_enable(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 436 | void nrf24l01_aa_disable(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 437 | bool nrf24l01_rx_pipe_enabled(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 438 | void nrf24l01_rx_pipe_enable(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 439 | void nrf24l01_rx_pipe_disable(unsigned char rxpipenum); |
jeroen3 | 0:2286a98ea739 | 440 | unsigned char nrf24l01_get_plos_cnt(void); |
jeroen3 | 0:2286a98ea739 | 441 | void nrf24l01_clear_plos_cnt(void); |
jeroen3 | 0:2286a98ea739 | 442 | void nrf24l01_clear_plos_cnt_param(unsigned char rf_ch); |
jeroen3 | 0:2286a98ea739 | 443 | unsigned char nrf24l01_get_arc_cnt(void); |
jeroen3 | 0:2286a98ea739 | 444 | |
jeroen3 | 0:2286a98ea739 | 445 | //utility functions |
jeroen3 | 0:2286a98ea739 | 446 | bool nrf24l01_cd_active(void); |
jeroen3 | 0:2286a98ea739 | 447 | void nrf24l01_clear_flush(void); |
jeroen3 | 0:2286a98ea739 | 448 | unsigned char nrf24l01_get_rx_pipe(void); |
jeroen3 | 0:2286a98ea739 | 449 | unsigned char nrf24l01_get_rx_pipe_from_status(unsigned char status); |
jeroen3 | 0:2286a98ea739 | 450 | void nrf24l01_get_all_registers(unsigned char * data); |
jeroen3 | 0:2286a98ea739 | 451 | |
jeroen3 | 0:2286a98ea739 | 452 | //interrupt check/clear functions |
jeroen3 | 0:2286a98ea739 | 453 | bool nrf24l01_irq_pin_active(void); |
jeroen3 | 0:2286a98ea739 | 454 | bool nrf24l01_irq_rx_dr_active(void); |
jeroen3 | 0:2286a98ea739 | 455 | bool nrf24l01_irq_tx_ds_active(void); |
jeroen3 | 0:2286a98ea739 | 456 | bool nrf24l01_irq_max_rt_active(void); |
jeroen3 | 0:2286a98ea739 | 457 | void nrf24l01_irq_clear_all(void); |
jeroen3 | 0:2286a98ea739 | 458 | void nrf24l01_irq_clear_rx_dr(void); |
jeroen3 | 0:2286a98ea739 | 459 | void nrf24l01_irq_clear_tx_ds(void); |
jeroen3 | 0:2286a98ea739 | 460 | void nrf24l01_irq_clear_max_rt(void); |
jeroen3 | 0:2286a98ea739 | 461 | |
jeroen3 | 0:2286a98ea739 | 462 | //FIFO_STATUS check functions |
jeroen3 | 0:2286a98ea739 | 463 | bool nrf24l01_fifo_tx_reuse(void); |
jeroen3 | 0:2286a98ea739 | 464 | bool nrf24l01_fifo_tx_full(void); |
jeroen3 | 0:2286a98ea739 | 465 | bool nrf24l01_fifo_tx_empty(void); |
jeroen3 | 0:2286a98ea739 | 466 | bool nrf24l01_fifo_rx_full(void); |
jeroen3 | 0:2286a98ea739 | 467 | bool nrf24l01_fifo_rx_empty(void); |
jeroen3 | 0:2286a98ea739 | 468 | |
jeroen3 | 0:2286a98ea739 | 469 | //IO interface-related functions |
jeroen3 | 0:2286a98ea739 | 470 | void nrf24l01_transmit(void); |
jeroen3 | 0:2286a98ea739 | 471 | void nrf24l01_clear_ce(void); |
jeroen3 | 0:2286a98ea739 | 472 | void nrf24l01_set_ce(void); |
jeroen3 | 0:2286a98ea739 | 473 | void nrf24l01_clear_csn(void); |
jeroen3 | 0:2286a98ea739 | 474 | void nrf24l01_set_csn(void); |
jeroen3 | 0:2286a98ea739 | 475 | bool nrf24l01_ce_pin_active(void); |
jeroen3 | 0:2286a98ea739 | 476 | bool nrf24l01_csn_pin_active(void); |
jeroen3 | 0:2286a98ea739 | 477 | |
jeroen3 | 0:2286a98ea739 | 478 | //low-level functions for library use only |
jeroen3 | 0:2286a98ea739 | 479 | unsigned char nrf24l01_execute_command(unsigned char instruction, unsigned char * data, unsigned int len, bool copydata); |
jeroen3 | 0:2286a98ea739 | 480 | void nrf24l01_spi_send_read(unsigned char * data, unsigned int len, bool copydata); |
jeroen3 | 0:2286a98ea739 | 481 | |
jeroen3 | 0:2286a98ea739 | 482 | #endif /*NRF24L01_H_*/ |