Jeff Craighead / CY14B101P

Encapsulates access to the Cypress CY14B101P nvSRAM module.

CY14B101P.cpp@2:50ca90120eb6, 2011-07-11 (annotated)

Committer:
jeffcraighead
Date:
Mon Jul 11 17:10:14 2011 +0000
Revision:
2:50ca90120eb6
Parent:
1:0f4063d68380
Child:
4:e5c61356fb09
Added Example to CY14B101P.cpp

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jeffcraighead 2:50ca90120eb6 1 /* This library encapsulates (or will when completely implemented)
jeffcraighead 2:50ca90120eb6 2 * all software functions for reading and writing to the Cypress Semiconductor
jeffcraighead 2:50ca90120eb6 3 * CY14B101P nvSRAM module.
jeffcraighead 2:50ca90120eb6 4 *
jeffcraighead 2:50ca90120eb6 5 * As of July 11, 2011 RTC functions are not implemented.
jeffcraighead 2:50ca90120eb6 6 *
jeffcraighead 2:50ca90120eb6 7 * Author: Dr. Jeffrey Craighead
jeffcraighead 2:50ca90120eb6 8 * Copyright 2011
jeffcraighead 2:50ca90120eb6 9 */
jeffcraighead 2:50ca90120eb6 10
jeffcraighead 2:50ca90120eb6 11 /** Example:
jeffcraighead 2:50ca90120eb6 12 * @code
jeffcraighead 2:50ca90120eb6 13 * #include "CY14B101P.h"
jeffcraighead 2:50ca90120eb6 14 * #include "mbed.h"
jeffcraighead 2:50ca90120eb6 15 *
jeffcraighead 2:50ca90120eb6 16 * NVSRAM mem(p11,p12,p13,p14,40000000,8,0);
jeffcraighead 2:50ca90120eb6 17 * Serial pc(USBTX,USBRX);
jeffcraighead 2:50ca90120eb6 18 *
jeffcraighead 2:50ca90120eb6 19 * int main() {
jeffcraighead 2:50ca90120eb6 20 * static char myString[] = "A Test String!\r\n";
jeffcraighead 2:50ca90120eb6 21 * char readString[sizeof(myString)];
jeffcraighead 2:50ca90120eb6 22 *
jeffcraighead 2:50ca90120eb6 23 * Timer s; //This timer is just to monitor read & write speed
jeffcraighead 2:50ca90120eb6 24 * s.start();
jeffcraighead 2:50ca90120eb6 25 * s.reset();
jeffcraighead 2:50ca90120eb6 26 *
jeffcraighead 2:50ca90120eb6 27 * mem.init();
jeffcraighead 2:50ca90120eb6 28 * while (true) {
jeffcraighead 2:50ca90120eb6 29 * int start = s.read_us();
jeffcraighead 2:50ca90120eb6 30 * //Write bytes
jeffcraighead 2:50ca90120eb6 31 * mem.writeBytes(myString,0,sizeof(myString));
jeffcraighead 2:50ca90120eb6 32 * int writeEnd = s.read_us();
jeffcraighead 2:50ca90120eb6 33 *
jeffcraighead 2:50ca90120eb6 34 * //Read bytes
jeffcraighead 2:50ca90120eb6 35 * mem.readBytes(readString,0,sizeof(readString));
jeffcraighead 2:50ca90120eb6 36 * int end = s.read_us();
jeffcraighead 2:50ca90120eb6 37 *
jeffcraighead 2:50ca90120eb6 38 * //Print read bytes to Serial to verify correctness
jeffcraighead 2:50ca90120eb6 39 * for (int i=0; i<sizeof(readString); i++) pc.printf("%c",readString[i]);
jeffcraighead 2:50ca90120eb6 40 * pc.printf("\r\n");
jeffcraighead 2:50ca90120eb6 41 * pc.printf("Write completed in %d microsecs.\r\n",writeEnd-start);
jeffcraighead 2:50ca90120eb6 42 * pc.printf("Read completed in %d microsecs.\r\n",end-writeEnd);
jeffcraighead 2:50ca90120eb6 43 * pc.printf("Status byte: 0x%x\r\n",mem.readStatusRegister());
jeffcraighead 2:50ca90120eb6 44 * wait(0.5);
jeffcraighead 2:50ca90120eb6 45 * }
jeffcraighead 2:50ca90120eb6 46 *}
jeffcraighead 2:50ca90120eb6 47 *@endcode
jeffcraighead 2:50ca90120eb6 48 */
jeffcraighead 2:50ca90120eb6 49
jeffcraighead 2:50ca90120eb6 50
jeffcraighead 2:50ca90120eb6 51
jeffcraighead 2:50ca90120eb6 52
jeffcraighead 0:eec14545c442 53 #include "CY14B101P.h"
jeffcraighead 0:eec14545c442 54
jeffcraighead 0:eec14545c442 55 Serial pc_(USBTX,USBRX);
jeffcraighead 0:eec14545c442 56 //Constructor - specify mbed pins for SPI connection to memory and the SPI clock rate
jeffcraighead 1:0f4063d68380 57 NVSRAM::NVSRAM(PinName mosi, PinName miso, PinName sclk, PinName csel, int spifrequency) : spi_(mosi, miso, sclk), chipSel_(csel) {
jeffcraighead 0:eec14545c442 58
jeffcraighead 0:eec14545c442 59 //chipSel_(csel);
jeffcraighead 0:eec14545c442 60
jeffcraighead 1:0f4063d68380 61 spi_.format(8,0);
jeffcraighead 0:eec14545c442 62 spi_.frequency(spifrequency);
jeffcraighead 0:eec14545c442 63 spifreq = spifrequency;
jeffcraighead 0:eec14545c442 64 chipSel_=1;
jeffcraighead 0:eec14545c442 65 }
jeffcraighead 0:eec14545c442 66
jeffcraighead 0:eec14545c442 67 void NVSRAM::init(){
jeffcraighead 0:eec14545c442 68 writeStatusRegister(0x00);
jeffcraighead 0:eec14545c442 69 }
jeffcraighead 0:eec14545c442 70
jeffcraighead 0:eec14545c442 71 void NVSRAM::writeBytes(char *bytes, unsigned int address, int length){
jeffcraighead 0:eec14545c442 72 chipSel_ = 0;
jeffcraighead 0:eec14545c442 73 spi_.write(WREN);
jeffcraighead 0:eec14545c442 74 chipSel_ = 1;
jeffcraighead 0:eec14545c442 75
jeffcraighead 0:eec14545c442 76 chipSel_ = 0;
jeffcraighead 0:eec14545c442 77
jeffcraighead 0:eec14545c442 78 spi_.write(WRITE);
jeffcraighead 0:eec14545c442 79
jeffcraighead 0:eec14545c442 80 spi_.write( (char)(0x00010000 & address)>>16 );
jeffcraighead 0:eec14545c442 81 spi_.write( (char)(0x0000FF00 & address)>>8 );
jeffcraighead 0:eec14545c442 82 spi_.write( (char)(0x000000FF & address) );
jeffcraighead 0:eec14545c442 83
jeffcraighead 0:eec14545c442 84 for(int i=0; i<length; i++) spi_.write(bytes[i]);
jeffcraighead 0:eec14545c442 85
jeffcraighead 0:eec14545c442 86 chipSel_ = 1;
jeffcraighead 0:eec14545c442 87 }
jeffcraighead 0:eec14545c442 88
jeffcraighead 0:eec14545c442 89 void NVSRAM::readBytes(char *bytes, unsigned int address, int length){
jeffcraighead 0:eec14545c442 90 chipSel_ = 0;
jeffcraighead 0:eec14545c442 91
jeffcraighead 0:eec14545c442 92 spi_.write(READ);
jeffcraighead 0:eec14545c442 93
jeffcraighead 0:eec14545c442 94 spi_.write( (char)(0x00010000 & address)>>16 );
jeffcraighead 0:eec14545c442 95 spi_.write( (char)(0x0000FF00 & address)>>8 );
jeffcraighead 0:eec14545c442 96 spi_.write( (char)(0x000000FF & address) );
jeffcraighead 0:eec14545c442 97
jeffcraighead 0:eec14545c442 98 for(int i=0; i<length; i++) bytes[i] = spi_.write(0x00);
jeffcraighead 0:eec14545c442 99
jeffcraighead 0:eec14545c442 100 chipSel_ = 1;
jeffcraighead 0:eec14545c442 101 }
jeffcraighead 0:eec14545c442 102
jeffcraighead 0:eec14545c442 103 void NVSRAM::setRTC(int century, int year, int month, int dayofmonth, int dayofweek, int hour, int minute, int second){
jeffcraighead 0:eec14545c442 104 //RTC SPI frequency must be no greater than 25MHz, so just use half of the SRAM frequency since that has a max of 40MHz
jeffcraighead 0:eec14545c442 105 spi_.frequency(spifreq/2);
jeffcraighead 0:eec14545c442 106 chipSel_=0;
jeffcraighead 0:eec14545c442 107 spi_.write(WREN);
jeffcraighead 0:eec14545c442 108 chipSel_=1;
jeffcraighead 0:eec14545c442 109
jeffcraighead 0:eec14545c442 110
jeffcraighead 0:eec14545c442 111 //Set the SPI frequency back to the requested rate for NVRAM access.
jeffcraighead 0:eec14545c442 112 spi_.frequency(spifreq);
jeffcraighead 0:eec14545c442 113 }
jeffcraighead 0:eec14545c442 114
jeffcraighead 0:eec14545c442 115 int NVSRAM::readRTC(){
jeffcraighead 0:eec14545c442 116 //RTC SPI frequency must be no greater than 25MHz, so just use half of the SRAM frequency since that has a max of 40MHz
jeffcraighead 0:eec14545c442 117 spi_.frequency(spifreq/2);
jeffcraighead 0:eec14545c442 118
jeffcraighead 0:eec14545c442 119
jeffcraighead 0:eec14545c442 120
jeffcraighead 0:eec14545c442 121 //Set the SPI frequency back to the requested rate for NVRAM access.
jeffcraighead 0:eec14545c442 122 spi_.frequency(spifreq);
jeffcraighead 0:eec14545c442 123
jeffcraighead 0:eec14545c442 124
jeffcraighead 0:eec14545c442 125 return 0;
jeffcraighead 0:eec14545c442 126 }
jeffcraighead 0:eec14545c442 127
jeffcraighead 0:eec14545c442 128 void NVSRAM::nvStore(){
jeffcraighead 0:eec14545c442 129 chipSel_=0;
jeffcraighead 0:eec14545c442 130 spi_.write(WREN);
jeffcraighead 0:eec14545c442 131 chipSel_=1;
jeffcraighead 0:eec14545c442 132 chipSel_=0;
jeffcraighead 0:eec14545c442 133 spi_.write(STORE);
jeffcraighead 0:eec14545c442 134 chipSel_=1;
jeffcraighead 0:eec14545c442 135 }
jeffcraighead 0:eec14545c442 136
jeffcraighead 0:eec14545c442 137 void NVSRAM::nvRecall(){
jeffcraighead 0:eec14545c442 138 chipSel_=0;
jeffcraighead 0:eec14545c442 139 spi_.write(WREN);
jeffcraighead 0:eec14545c442 140 chipSel_=1;
jeffcraighead 0:eec14545c442 141 chipSel_=0;
jeffcraighead 0:eec14545c442 142 spi_.write(RECALL);
jeffcraighead 0:eec14545c442 143 chipSel_=1;
jeffcraighead 0:eec14545c442 144 }
jeffcraighead 0:eec14545c442 145
jeffcraighead 0:eec14545c442 146 void NVSRAM::enableAutoStore(bool enable){
jeffcraighead 0:eec14545c442 147 chipSel_=0;
jeffcraighead 0:eec14545c442 148 spi_.write(WREN);
jeffcraighead 0:eec14545c442 149 chipSel_=1;
jeffcraighead 0:eec14545c442 150 chipSel_=0;
jeffcraighead 0:eec14545c442 151 if(enable) spi_.write(ASENB);
jeffcraighead 0:eec14545c442 152 else spi_.write(ASDISB);
jeffcraighead 0:eec14545c442 153 chipSel_=1;
jeffcraighead 0:eec14545c442 154 }
jeffcraighead 0:eec14545c442 155
jeffcraighead 0:eec14545c442 156 void NVSRAM::writeStatusRegister(char status){
jeffcraighead 0:eec14545c442 157 chipSel_=0;
jeffcraighead 0:eec14545c442 158 spi_.write(WREN);
jeffcraighead 0:eec14545c442 159 chipSel_=1;
jeffcraighead 0:eec14545c442 160 chipSel_=0;
jeffcraighead 0:eec14545c442 161 spi_.write(WRSR);
jeffcraighead 0:eec14545c442 162 spi_.write(status);
jeffcraighead 0:eec14545c442 163 chipSel_=1;
jeffcraighead 0:eec14545c442 164 }
jeffcraighead 0:eec14545c442 165
jeffcraighead 0:eec14545c442 166 char NVSRAM::readStatusRegister(){
jeffcraighead 0:eec14545c442 167 chipSel_ = 0;
jeffcraighead 0:eec14545c442 168 spi_.write(RDSR);
jeffcraighead 0:eec14545c442 169 char out = spi_.write(0x00);
jeffcraighead 0:eec14545c442 170 chipSel_ = 1;
jeffcraighead 0:eec14545c442 171
jeffcraighead 0:eec14545c442 172 return out;
jeffcraighead 0:eec14545c442 173 }