jeong chanmi / WIZnetInterface_

modify for blynk

Fork of WIZnetInterface by WIZnet

arch/int/W7500x_toe.cpp@30:206920aceb69, 2017-11-27 (annotated)

Committer:
jcm931213
Date:
Mon Nov 27 11:49:56 2017 +0000
Revision:
30:206920aceb69
Parent:
29:c91884bd2713 
modify for blynk

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Soohwan Kim 0:6f28332c466f 1 /* Copyright (C) 2012 mbed.org, MIT License
Soohwan Kim 0:6f28332c466f 2 *
Soohwan Kim 0:6f28332c466f 3 * and associated documentation files (the "Software"), to deal in the Software without restriction,
Soohwan Kim 0:6f28332c466f 4 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
Soohwan Kim 0:6f28332c466f 5 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
Soohwan Kim 0:6f28332c466f 6 * furnished to do so, subject to the following conditions:
Soohwan Kim 0:6f28332c466f 7 *
Soohwan Kim 0:6f28332c466f 8 * The above copyright notice and this permission notice shall be included in all copies or
Soohwan Kim 0:6f28332c466f 9 * substantial portions of the Software.
Soohwan Kim 0:6f28332c466f 10 *
Soohwan Kim 0:6f28332c466f 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Soohwan Kim 0:6f28332c466f 12 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Soohwan Kim 0:6f28332c466f 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Soohwan Kim 0:6f28332c466f 14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Soohwan Kim 0:6f28332c466f 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Soohwan Kim 0:6f28332c466f 16 */
embeddist 3:f8c6efc8bf83 17 #include "eth_arch.h"
embeddist 28:200e63e513a8 18 #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500P) || defined(TARGET_WIZwiki_W7500ECO)
hjjeon 26:d07c80e18b27 19
Soohwan Kim 0:6f28332c466f 20
Soohwan Kim 0:6f28332c466f 21 #include "mbed.h"
Soohwan Kim 0:6f28332c466f 22 #include "mbed_debug.h"
Soohwan Kim 0:6f28332c466f 23 #include "DNSClient.h"
Soohwan Kim 0:6f28332c466f 24
Soohwan Kim 0:6f28332c466f 25
Soohwan Kim 0:6f28332c466f 26 /*
Soohwan Kim 0:6f28332c466f 27 * MDIO via GPIO
Soohwan Kim 0:6f28332c466f 28 * mdio via gpio is supported and related functions as follows.
Soohwan Kim 0:6f28332c466f 29 * - mdio_init(),mdio_read(),mdio_write()
Soohwan Kim 0:6f28332c466f 30 * - input_MDIO(),output_MDIO(),turnaroud_MDIO(),idle_MDIO()
Soohwan Kim 0:6f28332c466f 31 * called by ethernet_link() and ethernet_set_link()
Soohwan Kim 0:6f28332c466f 32 */
hjjeon 26:d07c80e18b27 33
embeddist 28:200e63e513a8 34 #if defined (TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)
hjjeon 26:d07c80e18b27 35
Soohwan Kim 0:6f28332c466f 36 #define MDIO GPIO_Pin_14
Soohwan Kim 0:6f28332c466f 37 #define MDC GPIO_Pin_15
Soohwan Kim 0:6f28332c466f 38 #define GPIO_MDC GPIOB
Soohwan Kim 0:6f28332c466f 39 #define PHY_ADDR_IP101G 0x07
Soohwan Kim 0:6f28332c466f 40 #define PHY_ADDR PHY_ADDR_IP101G
Soohwan Kim 0:6f28332c466f 41 #define SVAL 0x2 //right shift val = 2
Soohwan Kim 0:6f28332c466f 42 #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)
Soohwan Kim 0:6f28332c466f 43 #define PHYREG_STATUS 0x1 //Status Register address (Status basic register)
Soohwan Kim 0:6f28332c466f 44 #define CNTL_DUPLEX (0x01ul<< 7)
Soohwan Kim 0:6f28332c466f 45 #define CNTL_AUTONEGO (0x01ul<<11)
Soohwan Kim 0:6f28332c466f 46 #define CNTL_SPEED (0x01ul<<12)
Soohwan Kim 0:6f28332c466f 47 #define MDC_WAIT (1)
hjjeon 26:d07c80e18b27 48
embeddist 28:200e63e513a8 49 #elif defined (TARGET_WIZwiki_W7500P)
hjjeon 26:d07c80e18b27 50
hjjeon 26:d07c80e18b27 51 #define MDIO GPIO_Pin_15
hjjeon 26:d07c80e18b27 52 #define MDC GPIO_Pin_14
hjjeon 26:d07c80e18b27 53 #define GPIO_MDC GPIOB
hjjeon 26:d07c80e18b27 54 #define PHY_ADDR_IP101G 0x01
hjjeon 26:d07c80e18b27 55 #define PHY_ADDR PHY_ADDR_IP101G
hjjeon 26:d07c80e18b27 56 #define SVAL 0x2 //right shift val = 2
hjjeon 26:d07c80e18b27 57 #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)
hjjeon 26:d07c80e18b27 58 #define PHYREG_STATUS 0x1 //Status Register address (Status basic register)
hjjeon 26:d07c80e18b27 59 #define CNTL_DUPLEX (0x01ul<< 7)
hjjeon 26:d07c80e18b27 60 #define CNTL_AUTONEGO (0x01ul<<11)
hjjeon 26:d07c80e18b27 61 #define CNTL_SPEED (0x01ul<<12)
hjjeon 26:d07c80e18b27 62 #define MDC_WAIT (1)
hjjeon 26:d07c80e18b27 63
hjjeon 26:d07c80e18b27 64 #endif
hjjeon 26:d07c80e18b27 65
Soohwan Kim 0:6f28332c466f 66 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO);
Soohwan Kim 0:6f28332c466f 67 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val);
Soohwan Kim 0:6f28332c466f 68 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr);
Soohwan Kim 0:6f28332c466f 69
Soohwan Kim 0:6f28332c466f 70 WIZnet_Chip* WIZnet_Chip::inst;
Soohwan Kim 0:6f28332c466f 71
Soohwan Kim 0:6f28332c466f 72 WIZnet_Chip::WIZnet_Chip()
Soohwan Kim 0:6f28332c466f 73 {
Soohwan Kim 0:6f28332c466f 74 inst = this;
Soohwan Kim 0:6f28332c466f 75 }
Soohwan Kim 0:6f28332c466f 76
Soohwan Kim 8:4c02de1dbf3a 77 bool WIZnet_Chip::setmac()
Soohwan Kim 8:4c02de1dbf3a 78 {
embeddist 29:c91884bd2713 79 reg_wr_mac(SHAR, mac);
Soohwan Kim 8:4c02de1dbf3a 80 return true;
Soohwan Kim 8:4c02de1dbf3a 81 }
Soohwan Kim 8:4c02de1dbf3a 82
Soohwan Kim 0:6f28332c466f 83 // Set the IP
Soohwan Kim 0:6f28332c466f 84 bool WIZnet_Chip::setip()
Soohwan Kim 0:6f28332c466f 85 {
Soohwan Kim 0:6f28332c466f 86 reg_wr<uint32_t>(SIPR, ip);
Soohwan Kim 0:6f28332c466f 87 reg_wr<uint32_t>(GAR, gateway);
Soohwan Kim 0:6f28332c466f 88 reg_wr<uint32_t>(SUBR, netmask);
Soohwan Kim 0:6f28332c466f 89 return true;
Soohwan Kim 0:6f28332c466f 90 }
Soohwan Kim 0:6f28332c466f 91
Soohwan Kim 0:6f28332c466f 92 bool WIZnet_Chip::setProtocol(int socket, Protocol p)
Soohwan Kim 0:6f28332c466f 93 {
Soohwan Kim 0:6f28332c466f 94 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 95 return false;
Soohwan Kim 0:6f28332c466f 96 }
Soohwan Kim 0:6f28332c466f 97 sreg<uint8_t>(socket, Sn_MR, p);
Soohwan Kim 0:6f28332c466f 98 return true;
Soohwan Kim 0:6f28332c466f 99 }
Soohwan Kim 0:6f28332c466f 100
Soohwan Kim 0:6f28332c466f 101 bool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms)
Soohwan Kim 0:6f28332c466f 102 {
Soohwan Kim 0:6f28332c466f 103 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 104 return false;
Soohwan Kim 0:6f28332c466f 105 }
Soohwan Kim 0:6f28332c466f 106 sreg<uint8_t>(socket, Sn_MR, TCP);
Soohwan Kim 0:6f28332c466f 107 scmd(socket, OPEN);
Soohwan Kim 0:6f28332c466f 108 sreg_ip(socket, Sn_DIPR, host);
Soohwan Kim 0:6f28332c466f 109 sreg<uint16_t>(socket, Sn_DPORT, port);
Soohwan Kim 0:6f28332c466f 110 sreg<uint16_t>(socket, Sn_PORT, new_port());
Soohwan Kim 0:6f28332c466f 111 scmd(socket, CONNECT);
Soohwan Kim 0:6f28332c466f 112 Timer t;
Soohwan Kim 0:6f28332c466f 113 t.reset();
Soohwan Kim 0:6f28332c466f 114 t.start();
Soohwan Kim 0:6f28332c466f 115 while(!is_connected(socket)) {
Soohwan Kim 0:6f28332c466f 116 if (t.read_ms() > timeout_ms) {
Soohwan Kim 0:6f28332c466f 117 return false;
Soohwan Kim 0:6f28332c466f 118 }
Soohwan Kim 0:6f28332c466f 119 }
Soohwan Kim 0:6f28332c466f 120 return true;
Soohwan Kim 0:6f28332c466f 121 }
Soohwan Kim 0:6f28332c466f 122
Soohwan Kim 0:6f28332c466f 123 bool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip)
Soohwan Kim 0:6f28332c466f 124 {
Soohwan Kim 0:6f28332c466f 125 uint32_t addr = str_to_ip(host);
Soohwan Kim 0:6f28332c466f 126 char buf[17];
Soohwan Kim 0:6f28332c466f 127 snprintf(buf, sizeof(buf), "%d.%d.%d.%d",
Soohwan Kim 0:6f28332c466f 128 (uint8_t)((addr>>24)&0xff),
Soohwan Kim 0:6f28332c466f 129 (uint8_t)((addr>>16)&0xff),
Soohwan Kim 0:6f28332c466f 130 (uint8_t)((addr>>8)&0xff),
Soohwan Kim 0:6f28332c466f 131 (uint8_t)(addr&0xff));
Soohwan Kim 0:6f28332c466f 132 if (strcmp(buf, host) == 0) {
Soohwan Kim 0:6f28332c466f 133 *ip = addr;
Soohwan Kim 0:6f28332c466f 134 return true;
Soohwan Kim 0:6f28332c466f 135 }
Soohwan Kim 0:6f28332c466f 136 DNSClient client;
Soohwan Kim 0:6f28332c466f 137 if(client.lookup(host)) {
Soohwan Kim 0:6f28332c466f 138 *ip = client.ip;
Soohwan Kim 0:6f28332c466f 139 return true;
Soohwan Kim 0:6f28332c466f 140 }
Soohwan Kim 0:6f28332c466f 141 return false;
Soohwan Kim 0:6f28332c466f 142 }
Soohwan Kim 0:6f28332c466f 143
Soohwan Kim 0:6f28332c466f 144
Soohwan Kim 0:6f28332c466f 145 bool WIZnet_Chip::is_connected(int socket)
Soohwan Kim 0:6f28332c466f 146 {
Soohwan Kim 0:6f28332c466f 147 /*
Soohwan Kim 0:6f28332c466f 148 if (sreg<uint8_t>(socket, Sn_SR) == SOCK_ESTABLISHED) {
Soohwan Kim 0:6f28332c466f 149 return true;
Soohwan Kim 0:6f28332c466f 150 }
Soohwan Kim 0:6f28332c466f 151 */
Soohwan Kim 0:6f28332c466f 152 uint8_t tmpSn_SR;
Soohwan Kim 0:6f28332c466f 153 tmpSn_SR = sreg<uint8_t>(socket, Sn_SR);
Soohwan Kim 0:6f28332c466f 154 // packet sending is possible, when state is SOCK_CLOSE_WAIT.
Soohwan Kim 0:6f28332c466f 155 if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) {
Soohwan Kim 0:6f28332c466f 156 return true;
Soohwan Kim 0:6f28332c466f 157 }
Soohwan Kim 0:6f28332c466f 158 return false;
Soohwan Kim 0:6f28332c466f 159 }
Soohwan Kim 0:6f28332c466f 160 // Reset the chip & set the buffer
Soohwan Kim 0:6f28332c466f 161 void WIZnet_Chip::reset()
Soohwan Kim 0:6f28332c466f 162 {
Soohwan Kim 0:6f28332c466f 163 /* S/W Reset PHY */
Soohwan Kim 0:6f28332c466f 164 mdio_write(GPIO_MDC, PHYREG_CONTROL, 0x8000);
Soohwan Kim 0:6f28332c466f 165 wait_ms(10);//for S/W reset
Soohwan Kim 0:6f28332c466f 166 wait_ms(10);//for MDC I/F RDY
Soohwan Kim 0:6f28332c466f 167
embeddist 15:24a9f2df2145 168 mdio_init(GPIO_MDC, MDC, MDIO);
embeddist 15:24a9f2df2145 169
Soohwan Kim 0:6f28332c466f 170 /* S/W Reset WZTOE */
Soohwan Kim 0:6f28332c466f 171 reg_wr<uint8_t>(MR, MR_RST);
Soohwan Kim 0:6f28332c466f 172 // set PAD strengh and pull-up for TXD[3:0] and TXE
Soohwan Kim 0:6f28332c466f 173 #ifdef __DEF_USED_IC101AG__ //For using IC+101AG
hjjeon 26:d07c80e18b27 174
embeddist 28:200e63e513a8 175 #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)
hjjeon 26:d07c80e18b27 176
Soohwan Kim 0:6f28332c466f 177 *(volatile uint32_t *)(0x41003068) = 0x64; //TXD0
Soohwan Kim 0:6f28332c466f 178 *(volatile uint32_t *)(0x4100306C) = 0x64; //TXD1
Soohwan Kim 0:6f28332c466f 179 *(volatile uint32_t *)(0x41003070) = 0x64; //TXD2
Soohwan Kim 0:6f28332c466f 180 *(volatile uint32_t *)(0x41003074) = 0x64; //TXD3
Soohwan Kim 0:6f28332c466f 181 *(volatile uint32_t *)(0x41003050) = 0x64; //TXE
hjjeon 26:d07c80e18b27 182 #endif
hjjeon 26:d07c80e18b27 183
Soohwan Kim 0:6f28332c466f 184 #endif
hjjeon 26:d07c80e18b27 185
Soohwan Kim 0:6f28332c466f 186 // set ticker counter
Soohwan Kim 0:6f28332c466f 187 reg_wr<uint32_t>(TIC100US, (SystemCoreClock/10000));
Soohwan Kim 0:6f28332c466f 188 // write MAC address inside the WZTOE MAC address register
Soohwan Kim 0:6f28332c466f 189 reg_wr_mac(SHAR, mac);
Soohwan Kim 0:6f28332c466f 190 /*
Soohwan Kim 0:6f28332c466f 191 * set RX and TX buffer size
Soohwan Kim 0:6f28332c466f 192 * for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {
Soohwan Kim 0:6f28332c466f 193 * sreg<uint8_t>(socket, Sn_RXBUF_SIZE, 2);
Soohwan Kim 0:6f28332c466f 194 * sreg<uint8_t>(socket, Sn_TXBUF_SIZE, 2);
Soohwan Kim 0:6f28332c466f 195 * }
Soohwan Kim 0:6f28332c466f 196 */
Soohwan Kim 0:6f28332c466f 197 }
Soohwan Kim 0:6f28332c466f 198
Soohwan Kim 0:6f28332c466f 199
Soohwan Kim 0:6f28332c466f 200 bool WIZnet_Chip::close(int socket)
Soohwan Kim 0:6f28332c466f 201 {
Soohwan Kim 0:6f28332c466f 202 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 203 return false;
Soohwan Kim 0:6f28332c466f 204 }
Soohwan Kim 0:6f28332c466f 205 // if SOCK_CLOSED, return
Soohwan Kim 0:6f28332c466f 206 if (sreg<uint8_t>(socket, Sn_SR) == SOCK_CLOSED) {
Soohwan Kim 0:6f28332c466f 207 return true;
Soohwan Kim 0:6f28332c466f 208 }
Soohwan Kim 0:6f28332c466f 209 // if SOCK_ESTABLISHED, send FIN-Packet to peer
Soohwan Kim 0:6f28332c466f 210 if (sreg<uint8_t>(socket, Sn_MR) == TCP) {
Soohwan Kim 0:6f28332c466f 211 scmd(socket, DISCON);
Soohwan Kim 0:6f28332c466f 212 }
Soohwan Kim 0:6f28332c466f 213 // close socket
Soohwan Kim 0:6f28332c466f 214 scmd(socket, CLOSE);
Soohwan Kim 0:6f28332c466f 215 // clear Socket Interrupt Register
Soohwan Kim 0:6f28332c466f 216 sreg<uint8_t>(socket, Sn_ICR, 0xff);
Soohwan Kim 0:6f28332c466f 217 return true;
Soohwan Kim 0:6f28332c466f 218 }
Soohwan Kim 0:6f28332c466f 219
Soohwan Kim 0:6f28332c466f 220 int WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size)
Soohwan Kim 0:6f28332c466f 221 {
Soohwan Kim 0:6f28332c466f 222 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 223 return -1;
Soohwan Kim 0:6f28332c466f 224 }
Soohwan Kim 0:6f28332c466f 225 Timer t;
Soohwan Kim 0:6f28332c466f 226 t.reset();
Soohwan Kim 0:6f28332c466f 227 t.start();
Soohwan Kim 0:6f28332c466f 228 while(1) {
Soohwan Kim 0:6f28332c466f 229 int size = sreg<uint16_t>(socket, Sn_RX_RSR);
Soohwan Kim 0:6f28332c466f 230 if (size > req_size) {
Soohwan Kim 0:6f28332c466f 231 return size;
Soohwan Kim 0:6f28332c466f 232 }
Soohwan Kim 0:6f28332c466f 233 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 234 break;
Soohwan Kim 0:6f28332c466f 235 }
Soohwan Kim 0:6f28332c466f 236 }
Soohwan Kim 0:6f28332c466f 237 return -1;
Soohwan Kim 0:6f28332c466f 238 }
Soohwan Kim 0:6f28332c466f 239
Soohwan Kim 0:6f28332c466f 240 int WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size)
Soohwan Kim 0:6f28332c466f 241 {
Soohwan Kim 0:6f28332c466f 242 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 243 return -1;
Soohwan Kim 0:6f28332c466f 244 }
Soohwan Kim 0:6f28332c466f 245 Timer t;
Soohwan Kim 0:6f28332c466f 246 t.reset();
Soohwan Kim 0:6f28332c466f 247 t.start();
Soohwan Kim 0:6f28332c466f 248 while(1) {
Soohwan Kim 0:6f28332c466f 249 int size = sreg<uint16_t>(socket, Sn_TX_FSR);
Soohwan Kim 0:6f28332c466f 250 if (size > req_size) {
Soohwan Kim 0:6f28332c466f 251 return size;
Soohwan Kim 0:6f28332c466f 252 }
Soohwan Kim 0:6f28332c466f 253 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 254 break;
Soohwan Kim 0:6f28332c466f 255 }
Soohwan Kim 0:6f28332c466f 256 }
Soohwan Kim 0:6f28332c466f 257 return -1;
Soohwan Kim 0:6f28332c466f 258 }
Soohwan Kim 0:6f28332c466f 259
Soohwan Kim 0:6f28332c466f 260 int WIZnet_Chip::send(int socket, const char * str, int len)
Soohwan Kim 0:6f28332c466f 261 {
Soohwan Kim 0:6f28332c466f 262 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 263 return -1;
Soohwan Kim 0:6f28332c466f 264 }
Soohwan Kim 0:6f28332c466f 265
Soohwan Kim 0:6f28332c466f 266 uint16_t ptr = sreg<uint16_t>(socket, Sn_TX_WR);
Soohwan Kim 0:6f28332c466f 267 uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18);
Soohwan Kim 0:6f28332c466f 268
Soohwan Kim 0:6f28332c466f 269 for(int i=0; i<len; i++)
Soohwan Kim 0:6f28332c466f 270 *(volatile uint8_t *)(sn_tx_base + ((ptr+i)&0xFFFF)) = str[i];
Soohwan Kim 0:6f28332c466f 271
Soohwan Kim 0:6f28332c466f 272 sreg<uint16_t>(socket, Sn_TX_WR, ptr + len);
Soohwan Kim 0:6f28332c466f 273 scmd(socket, SEND);
Soohwan Kim 0:6f28332c466f 274
Soohwan Kim 0:6f28332c466f 275 uint8_t tmp_Sn_IR;
Soohwan Kim 0:6f28332c466f 276 while (( (tmp_Sn_IR = sreg<uint8_t>(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {
Soohwan Kim 0:6f28332c466f 277 // @Jul.10, 2014 fix contant name, and udp sendto function.
Soohwan Kim 0:6f28332c466f 278 switch (sreg<uint8_t>(socket, Sn_SR)) {
Soohwan Kim 0:6f28332c466f 279 case SOCK_CLOSED :
Soohwan Kim 0:6f28332c466f 280 close(socket);
Soohwan Kim 0:6f28332c466f 281 return 0;
Soohwan Kim 0:6f28332c466f 282 //break;
Soohwan Kim 0:6f28332c466f 283 case SOCK_UDP :
Soohwan Kim 0:6f28332c466f 284 // ARP timeout is possible.
Soohwan Kim 0:6f28332c466f 285 if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {
Soohwan Kim 0:6f28332c466f 286 sreg<uint8_t>(socket, Sn_ICR, INT_TIMEOUT);
Soohwan Kim 0:6f28332c466f 287 return 0;
Soohwan Kim 0:6f28332c466f 288 }
Soohwan Kim 0:6f28332c466f 289 break;
Soohwan Kim 0:6f28332c466f 290 default :
Soohwan Kim 0:6f28332c466f 291 break;
Soohwan Kim 0:6f28332c466f 292 }
Soohwan Kim 0:6f28332c466f 293 }
Soohwan Kim 0:6f28332c466f 294
Soohwan Kim 0:6f28332c466f 295 sreg<uint8_t>(socket, Sn_ICR, INT_SEND_OK);
Soohwan Kim 0:6f28332c466f 296
Soohwan Kim 0:6f28332c466f 297 return len;
Soohwan Kim 0:6f28332c466f 298 }
Soohwan Kim 0:6f28332c466f 299
Soohwan Kim 0:6f28332c466f 300 int WIZnet_Chip::recv(int socket, char* buf, int len)
Soohwan Kim 0:6f28332c466f 301 {
Soohwan Kim 0:6f28332c466f 302 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 303 return -1;
Soohwan Kim 0:6f28332c466f 304 }
Soohwan Kim 0:6f28332c466f 305 uint16_t ptr = sreg<uint16_t>(socket, Sn_RX_RD);
Soohwan Kim 0:6f28332c466f 306 uint32_t sn_rx_base = W7500x_RXMEM_BASE + (uint32_t)(socket<<18);
Soohwan Kim 0:6f28332c466f 307
Soohwan Kim 0:6f28332c466f 308 for(int i=0; i<len; i++)
Soohwan Kim 0:6f28332c466f 309 buf[i] = *(volatile uint8_t *)(sn_rx_base + ((ptr+i)&0xFFFF));
Soohwan Kim 0:6f28332c466f 310
Soohwan Kim 0:6f28332c466f 311 sreg<uint16_t>(socket, Sn_RX_RD, ptr + len);
Soohwan Kim 0:6f28332c466f 312 scmd(socket, RECV);
Soohwan Kim 0:6f28332c466f 313
Soohwan Kim 0:6f28332c466f 314 return len;
Soohwan Kim 0:6f28332c466f 315 }
Soohwan Kim 0:6f28332c466f 316
Soohwan Kim 0:6f28332c466f 317 int WIZnet_Chip::new_socket()
Soohwan Kim 0:6f28332c466f 318 {
Soohwan Kim 0:6f28332c466f 319 for(int s = 0; s < MAX_SOCK_NUM; s++) {
Soohwan Kim 0:6f28332c466f 320 if (sreg<uint8_t>(s, Sn_SR) == SOCK_CLOSED) {
Soohwan Kim 0:6f28332c466f 321 return s;
Soohwan Kim 0:6f28332c466f 322 }
Soohwan Kim 0:6f28332c466f 323 }
Soohwan Kim 0:6f28332c466f 324 return -1;
Soohwan Kim 0:6f28332c466f 325 }
Soohwan Kim 0:6f28332c466f 326
Soohwan Kim 0:6f28332c466f 327 uint16_t WIZnet_Chip::new_port()
Soohwan Kim 0:6f28332c466f 328 {
Soohwan Kim 0:6f28332c466f 329 uint16_t port = rand();
Soohwan Kim 0:6f28332c466f 330 port |= 49152;
Soohwan Kim 0:6f28332c466f 331 return port;
Soohwan Kim 0:6f28332c466f 332 }
Soohwan Kim 0:6f28332c466f 333
Soohwan Kim 0:6f28332c466f 334 bool WIZnet_Chip::link(int wait_time_ms)
Soohwan Kim 0:6f28332c466f 335 {
Soohwan Kim 0:6f28332c466f 336 Timer t;
Soohwan Kim 0:6f28332c466f 337 t.reset();
Soohwan Kim 0:6f28332c466f 338 t.start();
Soohwan Kim 0:6f28332c466f 339 while(1) {
Soohwan Kim 0:6f28332c466f 340 int is_link = ethernet_link();
hjjeon 19:d8773cd4edc5 341
Soohwan Kim 0:6f28332c466f 342 if (is_link) {
Soohwan Kim 0:6f28332c466f 343 return true;
Soohwan Kim 0:6f28332c466f 344 }
Soohwan Kim 0:6f28332c466f 345 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 346 break;
Soohwan Kim 0:6f28332c466f 347 }
Soohwan Kim 0:6f28332c466f 348 }
Soohwan Kim 0:6f28332c466f 349 return 0;
Soohwan Kim 0:6f28332c466f 350 }
Soohwan Kim 0:6f28332c466f 351
Soohwan Kim 0:6f28332c466f 352 void WIZnet_Chip::set_link(PHYMode phymode)
Soohwan Kim 0:6f28332c466f 353 {
Soohwan Kim 0:6f28332c466f 354 int speed = -1;
Soohwan Kim 0:6f28332c466f 355 int duplex = 0;
Soohwan Kim 0:6f28332c466f 356
Soohwan Kim 0:6f28332c466f 357 switch(phymode) {
Soohwan Kim 0:6f28332c466f 358 case AutoNegotiate : speed = -1; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 359 case HalfDuplex10 : speed = 0; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 360 case FullDuplex10 : speed = 0; duplex = 1; break;
Soohwan Kim 0:6f28332c466f 361 case HalfDuplex100 : speed = 1; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 362 case FullDuplex100 : speed = 1; duplex = 1; break;
Soohwan Kim 0:6f28332c466f 363 }
Soohwan Kim 0:6f28332c466f 364
Soohwan Kim 0:6f28332c466f 365 ethernet_set_link(speed, duplex);
Soohwan Kim 0:6f28332c466f 366 }
Soohwan Kim 0:6f28332c466f 367
Soohwan Kim 0:6f28332c466f 368 uint32_t str_to_ip(const char* str)
Soohwan Kim 0:6f28332c466f 369 {
Soohwan Kim 0:6f28332c466f 370 uint32_t ip = 0;
Soohwan Kim 0:6f28332c466f 371 char* p = (char*)str;
Soohwan Kim 0:6f28332c466f 372 for(int i = 0; i < 4; i++) {
Soohwan Kim 0:6f28332c466f 373 ip |= atoi(p);
Soohwan Kim 0:6f28332c466f 374 p = strchr(p, '.');
Soohwan Kim 0:6f28332c466f 375 if (p == NULL) {
Soohwan Kim 0:6f28332c466f 376 break;
Soohwan Kim 0:6f28332c466f 377 }
Soohwan Kim 0:6f28332c466f 378 ip <<= 8;
Soohwan Kim 0:6f28332c466f 379 p++;
Soohwan Kim 0:6f28332c466f 380 }
Soohwan Kim 0:6f28332c466f 381 return ip;
Soohwan Kim 0:6f28332c466f 382 }
Soohwan Kim 0:6f28332c466f 383
Soohwan Kim 0:6f28332c466f 384 void printfBytes(char* str, uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 385 {
Soohwan Kim 0:6f28332c466f 386 printf("%s %d:", str, len);
Soohwan Kim 0:6f28332c466f 387 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 388 printf(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 389 }
Soohwan Kim 0:6f28332c466f 390 printf("\n");
Soohwan Kim 0:6f28332c466f 391 }
Soohwan Kim 0:6f28332c466f 392
Soohwan Kim 0:6f28332c466f 393 void printHex(uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 394 {
Soohwan Kim 0:6f28332c466f 395 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 396 if ((i%16) == 0) {
Soohwan Kim 0:6f28332c466f 397 printf("%p", buf+i);
Soohwan Kim 0:6f28332c466f 398 }
Soohwan Kim 0:6f28332c466f 399 printf(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 400 if ((i%16) == 15) {
Soohwan Kim 0:6f28332c466f 401 printf("\n");
Soohwan Kim 0:6f28332c466f 402 }
Soohwan Kim 0:6f28332c466f 403 }
Soohwan Kim 0:6f28332c466f 404 printf("\n");
Soohwan Kim 0:6f28332c466f 405 }
Soohwan Kim 0:6f28332c466f 406
Soohwan Kim 0:6f28332c466f 407 void debug_hex(uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 408 {
Soohwan Kim 0:6f28332c466f 409 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 410 if ((i%16) == 0) {
Soohwan Kim 0:6f28332c466f 411 debug("%p", buf+i);
Soohwan Kim 0:6f28332c466f 412 }
Soohwan Kim 0:6f28332c466f 413 debug(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 414 if ((i%16) == 15) {
Soohwan Kim 0:6f28332c466f 415 debug("\n");
Soohwan Kim 0:6f28332c466f 416 }
Soohwan Kim 0:6f28332c466f 417 }
Soohwan Kim 0:6f28332c466f 418 debug("\n");
Soohwan Kim 0:6f28332c466f 419 }
Soohwan Kim 0:6f28332c466f 420
Soohwan Kim 0:6f28332c466f 421 void WIZnet_Chip::scmd(int socket, Command cmd)
Soohwan Kim 0:6f28332c466f 422 {
Soohwan Kim 0:6f28332c466f 423 sreg<uint8_t>(socket, Sn_CR, cmd);
Soohwan Kim 0:6f28332c466f 424 while(sreg<uint8_t>(socket, Sn_CR));
Soohwan Kim 0:6f28332c466f 425 }
Soohwan Kim 0:6f28332c466f 426
Soohwan Kim 0:6f28332c466f 427
Soohwan Kim 0:6f28332c466f 428 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO)
Soohwan Kim 0:6f28332c466f 429 {
Soohwan Kim 0:6f28332c466f 430 /* Set GPIOs for MDIO and MDC */
Soohwan Kim 0:6f28332c466f 431 GPIO_InitTypeDef MDIO_InitDef;
Soohwan Kim 0:6f28332c466f 432 HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1);
Soohwan Kim 0:6f28332c466f 433 HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1);
Soohwan Kim 0:6f28332c466f 434 MDIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO;
Soohwan Kim 0:6f28332c466f 435 MDIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
Soohwan Kim 0:6f28332c466f 436 HAL_GPIO_Init(GPIOx, &MDIO_InitDef);
Soohwan Kim 0:6f28332c466f 437 }
Soohwan Kim 0:6f28332c466f 438
Soohwan Kim 0:6f28332c466f 439 void output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n)
Soohwan Kim 0:6f28332c466f 440 {
Soohwan Kim 0:6f28332c466f 441 for(val <<= (32-n); n; val<<=1, n--)
Soohwan Kim 0:6f28332c466f 442 {
Soohwan Kim 0:6f28332c466f 443 if(val & 0x80000000)
Soohwan Kim 0:6f28332c466f 444 HAL_GPIO_SetBits(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 445 else
Soohwan Kim 0:6f28332c466f 446 HAL_GPIO_ResetBits(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 447
Soohwan Kim 0:6f28332c466f 448 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 449 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 450 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 451 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 452 }
Soohwan Kim 0:6f28332c466f 453 }
Soohwan Kim 0:6f28332c466f 454
Soohwan Kim 0:6f28332c466f 455 uint32_t input_MDIO( GPIO_TypeDef* GPIOx )
Soohwan Kim 0:6f28332c466f 456 {
Soohwan Kim 0:6f28332c466f 457 uint32_t i, val=0;
Soohwan Kim 0:6f28332c466f 458 for(i=0; i<16; i++)
Soohwan Kim 0:6f28332c466f 459 {
Soohwan Kim 0:6f28332c466f 460 val <<=1;
Soohwan Kim 0:6f28332c466f 461 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 462 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 463 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 464 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 465 val |= HAL_GPIO_ReadInputDataBit(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 466 }
Soohwan Kim 0:6f28332c466f 467 return (val);
Soohwan Kim 0:6f28332c466f 468 }
Soohwan Kim 0:6f28332c466f 469
Soohwan Kim 0:6f28332c466f 470 void turnaround_MDIO( GPIO_TypeDef* GPIOx)
Soohwan Kim 0:6f28332c466f 471 {
Soohwan Kim 0:6f28332c466f 472 GPIOx->OUTENCLR = MDIO ;
Soohwan Kim 0:6f28332c466f 473 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 474 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 475 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 476 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 477 }
Soohwan Kim 0:6f28332c466f 478
Soohwan Kim 0:6f28332c466f 479 void idle_MDIO( GPIO_TypeDef* GPIOx )
Soohwan Kim 0:6f28332c466f 480 {
Soohwan Kim 0:6f28332c466f 481 GPIOx->OUTENSET = MDIO ;
Soohwan Kim 0:6f28332c466f 482 HAL_GPIO_SetBits(GPIOx,MDC);
Soohwan Kim 0:6f28332c466f 483 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 484 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 485 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 486 }
Soohwan Kim 0:6f28332c466f 487
Soohwan Kim 0:6f28332c466f 488 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr)
Soohwan Kim 0:6f28332c466f 489 {
Soohwan Kim 0:6f28332c466f 490 output_MDIO(GPIOx, 0xFFFFFFFF, 32);
Soohwan Kim 0:6f28332c466f 491 output_MDIO(GPIOx, 0x06, 4);
Soohwan Kim 0:6f28332c466f 492 output_MDIO(GPIOx, PHY_ADDR, 5);
Soohwan Kim 0:6f28332c466f 493 output_MDIO(GPIOx, PhyRegAddr, 5);
Soohwan Kim 0:6f28332c466f 494 turnaround_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 495 uint32_t val = input_MDIO(GPIOx );
Soohwan Kim 0:6f28332c466f 496 idle_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 497 return val;
Soohwan Kim 0:6f28332c466f 498 }
Soohwan Kim 0:6f28332c466f 499
Soohwan Kim 0:6f28332c466f 500 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val)
Soohwan Kim 0:6f28332c466f 501 {
Soohwan Kim 0:6f28332c466f 502 output_MDIO(GPIOx, 0xFFFFFFFF, 32);
Soohwan Kim 0:6f28332c466f 503 output_MDIO(GPIOx, 0x05, 4);
Soohwan Kim 0:6f28332c466f 504 output_MDIO(GPIOx, PHY_ADDR, 5);
Soohwan Kim 0:6f28332c466f 505 output_MDIO(GPIOx, PhyRegAddr, 5);
Soohwan Kim 0:6f28332c466f 506 output_MDIO(GPIOx, 0x02, 2);
Soohwan Kim 0:6f28332c466f 507 output_MDIO(GPIOx, val, 16);
Soohwan Kim 0:6f28332c466f 508 idle_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 509 }
Soohwan Kim 0:6f28332c466f 510
embeddist 14:2101ab5ee40f 511 int WIZnet_Chip::ethernet_link(void) {
Soohwan Kim 0:6f28332c466f 512 return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01);
Soohwan Kim 0:6f28332c466f 513 }
Soohwan Kim 0:6f28332c466f 514
embeddist 14:2101ab5ee40f 515 void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
Soohwan Kim 0:6f28332c466f 516 uint32_t val=0;
Soohwan Kim 0:6f28332c466f 517 if((speed < 0) || (speed > 1)) {
Soohwan Kim 0:6f28332c466f 518 val = CNTL_AUTONEGO;
Soohwan Kim 0:6f28332c466f 519 } else {
Soohwan Kim 0:6f28332c466f 520 val = ((CNTL_SPEED&(speed<<11))|(CNTL_DUPLEX&(duplex<<7)));
Soohwan Kim 0:6f28332c466f 521 }
Soohwan Kim 0:6f28332c466f 522 mdio_write(GPIO_MDC, PHYREG_CONTROL, val);
Soohwan Kim 0:6f28332c466f 523 }
embeddist 14:2101ab5ee40f 524
embeddist 14:2101ab5ee40f 525 void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data)
embeddist 14:2101ab5ee40f 526 {
embeddist 14:2101ab5ee40f 527 data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
embeddist 14:2101ab5ee40f 528 data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
embeddist 14:2101ab5ee40f 529 data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
embeddist 14:2101ab5ee40f 530 data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
embeddist 14:2101ab5ee40f 531 data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
embeddist 14:2101ab5ee40f 532 data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
embeddist 14:2101ab5ee40f 533 }
embeddist 14:2101ab5ee40f 534
embeddist 14:2101ab5ee40f 535 void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)
embeddist 14:2101ab5ee40f 536 {
embeddist 14:2101ab5ee40f 537 uint8_t buf[4]={0,};
embeddist 14:2101ab5ee40f 538 uint32_t wr_ip = 0;
embeddist 14:2101ab5ee40f 539 char* p = (char*)ip;
embeddist 14:2101ab5ee40f 540
embeddist 14:2101ab5ee40f 541 for(int i = 0; i < 4; i++) {
embeddist 14:2101ab5ee40f 542 wr_ip = (wr_ip<<8);
embeddist 14:2101ab5ee40f 543 buf[i] = atoi(p);
embeddist 14:2101ab5ee40f 544 wr_ip |= buf[i];
embeddist 14:2101ab5ee40f 545 p = strchr(p, '.');
embeddist 14:2101ab5ee40f 546 if (p == NULL) break;
embeddist 14:2101ab5ee40f 547 p++;
embeddist 14:2101ab5ee40f 548 }
embeddist 14:2101ab5ee40f 549 *(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
embeddist 14:2101ab5ee40f 550 }
embeddist 14:2101ab5ee40f 551
embeddist 14:2101ab5ee40f 552 void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
embeddist 14:2101ab5ee40f 553 reg_wr_ip(addr, (uint8_t)(0x01+(socket<<2)), ip);
embeddist 14:2101ab5ee40f 554 }
embeddist 14:2101ab5ee40f 555
Soohwan Kim 0:6f28332c466f 556 #endif
Soohwan Kim 0:6f28332c466f 557
embeddist 28:200e63e513a8 558