Julien Cassette / mbed-dev

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targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c@79:9f34958201cc, 2016-03-14 (annotated)

Committer:
jcassette
Date:
Mon Mar 14 14:20:17 2016 +0000
Revision:
79:9f34958201cc
Parent:
0:9b334a45a8ff 
FRDM-K64F AnalogIn: add support for ADC channels with no mapped pins

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2015 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include "sleep_api.h"
bogdanm 0:9b334a45a8ff 17 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 //Normal wait mode
bogdanm 0:9b334a45a8ff 20 void sleep(void)
bogdanm 0:9b334a45a8ff 21 {
bogdanm 0:9b334a45a8ff 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 //Normal sleep mode for ARM core:
bogdanm 0:9b334a45a8ff 25 SCB->SCR = 0;
bogdanm 0:9b334a45a8ff 26 __WFI();
bogdanm 0:9b334a45a8ff 27 }
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 //Very low-power stop mode
bogdanm 0:9b334a45a8ff 30 void deepsleep(void)
bogdanm 0:9b334a45a8ff 31 {
bogdanm 0:9b334a45a8ff 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
bogdanm 0:9b334a45a8ff 33 uint8_t ADC_HSC = 0;
bogdanm 0:9b334a45a8ff 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
bogdanm 0:9b334a45a8ff 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
bogdanm 0:9b334a45a8ff 36 ADC_HSC = 1;
bogdanm 0:9b334a45a8ff 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
bogdanm 0:9b334a45a8ff 38 }
bogdanm 0:9b334a45a8ff 39 }
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 //Check if PLL/FLL is enabled:
bogdanm 0:9b334a45a8ff 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
bogdanm 0:9b334a45a8ff 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 //Deep sleep for ARM core:
bogdanm 0:9b334a45a8ff 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 __WFI();
bogdanm 0:9b334a45a8ff 51 //Switch back to PLL as clock source if needed
bogdanm 0:9b334a45a8ff 52 //The interrupt that woke up the device will run at reduced speed
bogdanm 0:9b334a45a8ff 53 if (PLL_FLL_en) {
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #if defined (TARGET_K20D50M)
bogdanm 0:9b334a45a8ff 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
bogdanm 0:9b334a45a8ff 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
bogdanm 0:9b334a45a8ff 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
bogdanm 0:9b334a45a8ff 59 #else
bogdanm 0:9b334a45a8ff 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
bogdanm 0:9b334a45a8ff 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
bogdanm 0:9b334a45a8ff 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
bogdanm 0:9b334a45a8ff 63 MCG->C6 = MCG_C6_VDIV0(0);
bogdanm 0:9b334a45a8ff 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
bogdanm 0:9b334a45a8ff 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
bogdanm 0:9b334a45a8ff 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
bogdanm 0:9b334a45a8ff 67 MCG->C5 = MCG_C5_PRDIV0(5);
bogdanm 0:9b334a45a8ff 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
bogdanm 0:9b334a45a8ff 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
bogdanm 0:9b334a45a8ff 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
bogdanm 0:9b334a45a8ff 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
bogdanm 0:9b334a45a8ff 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
bogdanm 0:9b334a45a8ff 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
bogdanm 0:9b334a45a8ff 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
bogdanm 0:9b334a45a8ff 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
bogdanm 0:9b334a45a8ff 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
bogdanm 0:9b334a45a8ff 77 #endif
bogdanm 0:9b334a45a8ff 78 }
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 if (ADC_HSC) {
bogdanm 0:9b334a45a8ff 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
bogdanm 0:9b334a45a8ff 82 }
bogdanm 0:9b334a45a8ff 83 }