Program to control an accelerometer, motors and a rangefinder using the ScmRTOS ported to mbed. (Work in progress and buggy)
scmRTOS/CortexM3/OS_Target_asm.s@0:9b057566f9ee, 2010-11-01 (annotated)
- Committer:
- jberry
- Date:
- Mon Nov 01 20:39:01 2010 +0000
- Revision:
- 0:9b057566f9ee
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
jberry | 0:9b057566f9ee | 1 | ; ****************************************************************************** |
jberry | 0:9b057566f9ee | 2 | ; * |
jberry | 0:9b057566f9ee | 3 | ; * FULLNAME: Single-Chip Microcontroller Real-Time Operating System |
jberry | 0:9b057566f9ee | 4 | ; * |
jberry | 0:9b057566f9ee | 5 | ; * NICKNAME: scmRTOS |
jberry | 0:9b057566f9ee | 6 | ; * |
jberry | 0:9b057566f9ee | 7 | ; * PROCESSOR: ARM Cortex-M3 |
jberry | 0:9b057566f9ee | 8 | ; * |
jberry | 0:9b057566f9ee | 9 | ; * TOOLKIT: EWARM (IAR Systems) |
jberry | 0:9b057566f9ee | 10 | ; * |
jberry | 0:9b057566f9ee | 11 | ; * PURPOSE: Target Dependent Low-Level Stuff |
jberry | 0:9b057566f9ee | 12 | ; * |
jberry | 0:9b057566f9ee | 13 | ; * Version: 3.10 |
jberry | 0:9b057566f9ee | 14 | ; * |
jberry | 0:9b057566f9ee | 15 | ; * $Revision: 195 $ |
jberry | 0:9b057566f9ee | 16 | ; * $Date:: 2008-06-19 #$ |
jberry | 0:9b057566f9ee | 17 | ; * |
jberry | 0:9b057566f9ee | 18 | ; * Copyright (c) 2003-2010, Harry E. Zhurov |
jberry | 0:9b057566f9ee | 19 | ; * |
jberry | 0:9b057566f9ee | 20 | ; * Permission is hereby granted, free of charge, to any person |
jberry | 0:9b057566f9ee | 21 | ; * obtaining a copy of this software and associated documentation |
jberry | 0:9b057566f9ee | 22 | ; * files (the "Software"), to deal in the Software without restriction, |
jberry | 0:9b057566f9ee | 23 | ; * including without limitation the rights to use, copy, modify, merge, |
jberry | 0:9b057566f9ee | 24 | ; * publish, distribute, sublicense, and/or sell copies of the Software, |
jberry | 0:9b057566f9ee | 25 | ; * and to permit persons to whom the Software is furnished to do so, |
jberry | 0:9b057566f9ee | 26 | ; * subject to the following conditions: |
jberry | 0:9b057566f9ee | 27 | ; * |
jberry | 0:9b057566f9ee | 28 | ; * The above copyright notice and this permission notice shall be included |
jberry | 0:9b057566f9ee | 29 | ; * in all copies or substantial portions of the Software. |
jberry | 0:9b057566f9ee | 30 | ; * |
jberry | 0:9b057566f9ee | 31 | ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
jberry | 0:9b057566f9ee | 32 | ; * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
jberry | 0:9b057566f9ee | 33 | ; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
jberry | 0:9b057566f9ee | 34 | ; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
jberry | 0:9b057566f9ee | 35 | ; * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
jberry | 0:9b057566f9ee | 36 | ; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH |
jberry | 0:9b057566f9ee | 37 | ; * THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
jberry | 0:9b057566f9ee | 38 | ; * |
jberry | 0:9b057566f9ee | 39 | ; * ================================================================= |
jberry | 0:9b057566f9ee | 40 | ; * See http://scmrtos.sourceforge.net for documentation, latest |
jberry | 0:9b057566f9ee | 41 | ; * information, license and contact details. |
jberry | 0:9b057566f9ee | 42 | ; * ================================================================= |
jberry | 0:9b057566f9ee | 43 | ; * |
jberry | 0:9b057566f9ee | 44 | ; ****************************************************************************** |
jberry | 0:9b057566f9ee | 45 | ; * Ported by Andrey Chuikin, Copyright (c) 2008-2010 |
jberry | 0:9b057566f9ee | 46 | |
jberry | 0:9b057566f9ee | 47 | ; #include "scmRTOS_TARGET_CFG.h" |
jberry | 0:9b057566f9ee | 48 | |
jberry | 0:9b057566f9ee | 49 | ; ----------------------------------------------------------------------------- |
jberry | 0:9b057566f9ee | 50 | ; PUBLIC FUNCTIONS |
jberry | 0:9b057566f9ee | 51 | ; |
jberry | 0:9b057566f9ee | 52 | EXTERN OS_ContextSwitchHook |
jberry | 0:9b057566f9ee | 53 | |
jberry | 0:9b057566f9ee | 54 | EXPORT OS_Start |
jberry | 0:9b057566f9ee | 55 | EXPORT PendSV_Handler |
jberry | 0:9b057566f9ee | 56 | |
jberry | 0:9b057566f9ee | 57 | ; ----------------------------------------------------------------------------- |
jberry | 0:9b057566f9ee | 58 | ; EQUATES |
jberry | 0:9b057566f9ee | 59 | ; |
jberry | 0:9b057566f9ee | 60 | NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register. |
jberry | 0:9b057566f9ee | 61 | NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. |
jberry | 0:9b057566f9ee | 62 | |
jberry | 0:9b057566f9ee | 63 | NVIC_SYSPRI14 EQU 0xE000ED22 ; System priority register (priority 14). |
jberry | 0:9b057566f9ee | 64 | NVIC_PENDSV_PRI EQU 0xFF ; PendSV priority value (lowest). |
jberry | 0:9b057566f9ee | 65 | NVIC_SYSPRI15 EQU 0xE000ED23 ; System priority register (priority 15). |
jberry | 0:9b057566f9ee | 66 | NVIC_ST_PRI EQU 0xFF ; SysTick priority value (lowest). |
jberry | 0:9b057566f9ee | 67 | |
jberry | 0:9b057566f9ee | 68 | NVIC_ST_CTRL EQU 0xE000E010 ; SysTick Ctrl & Status Reg. |
jberry | 0:9b057566f9ee | 69 | NVIC_ST_RELOAD EQU 0xE000E014 ; SysTick Reload Value Reg. |
jberry | 0:9b057566f9ee | 70 | NVIC_ST_CTRL_CLK_SRC EQU 0x00000004 ; Clock Source. |
jberry | 0:9b057566f9ee | 71 | NVIC_ST_CTRL_INTEN EQU 0x00000002 ; Interrupt enable. |
jberry | 0:9b057566f9ee | 72 | NVIC_ST_CTRL_ENABLE EQU 0x00000001 ; Counter mode. |
jberry | 0:9b057566f9ee | 73 | |
jberry | 0:9b057566f9ee | 74 | ; should be the same as in scmRTOS_TARGET_CFG.h |
jberry | 0:9b057566f9ee | 75 | SYSTICKFREQ EQU 100000000 |
jberry | 0:9b057566f9ee | 76 | SYSTICKINTRATE EQU 1000 |
jberry | 0:9b057566f9ee | 77 | |
jberry | 0:9b057566f9ee | 78 | ; ----------------------------------------------------------------------------- |
jberry | 0:9b057566f9ee | 79 | ; CODE GENERATION DIRECTIVES |
jberry | 0:9b057566f9ee | 80 | ; |
jberry | 0:9b057566f9ee | 81 | AREA TEXT, CODE, READONLY |
jberry | 0:9b057566f9ee | 82 | THUMB |
jberry | 0:9b057566f9ee | 83 | |
jberry | 0:9b057566f9ee | 84 | ; ----------------------------------------------------------------------------- |
jberry | 0:9b057566f9ee | 85 | ; HANDLE PendSV EXCEPTION |
jberry | 0:9b057566f9ee | 86 | ; void PendSV_Handler(void) |
jberry | 0:9b057566f9ee | 87 | ; |
jberry | 0:9b057566f9ee | 88 | ; Note(s) : 1) PendSV is used to cause a context switch. This is a recommended method for performing |
jberry | 0:9b057566f9ee | 89 | ; context switches with Cortex-M3. This is because the Cortex-M3 auto-saves half of the |
jberry | 0:9b057566f9ee | 90 | ; processor context on any exception, and restores same on return from exception. So only |
jberry | 0:9b057566f9ee | 91 | ; saving of R4-R11 is required and fixing up the stack pointers. Using the PendSV exception |
jberry | 0:9b057566f9ee | 92 | ; this way means that context saving and restoring is identical whether it is initiated from |
jberry | 0:9b057566f9ee | 93 | ; a thread or occurs due to an interrupt or exception. |
jberry | 0:9b057566f9ee | 94 | ; |
jberry | 0:9b057566f9ee | 95 | ; 2) Pseudo-code is: |
jberry | 0:9b057566f9ee | 96 | ; a) Get the process SP, if 0 then skip (goto f) the saving part (first context switch); |
jberry | 0:9b057566f9ee | 97 | ; b) Save remaining regs r4-r11 on process stack; |
jberry | 0:9b057566f9ee | 98 | ; c) Call OS_ContextSwitchHook for save current task SP and get new task SP; |
jberry | 0:9b057566f9ee | 99 | ; d) Restore R4-R11 from new process stack; |
jberry | 0:9b057566f9ee | 100 | ; e) Perform exception return which will restore remaining context. |
jberry | 0:9b057566f9ee | 101 | ; f) Get SP for the first context switch (R2 hold it); |
jberry | 0:9b057566f9ee | 102 | ; run SysTick; goto d); |
jberry | 0:9b057566f9ee | 103 | ; |
jberry | 0:9b057566f9ee | 104 | ; 3) On entry into PendSV handler: |
jberry | 0:9b057566f9ee | 105 | ; a) The following have been saved on the process stack (by processor): |
jberry | 0:9b057566f9ee | 106 | ; xPSR, PC, LR, R12, R0-R3 |
jberry | 0:9b057566f9ee | 107 | ; b) Processor mode is switched to Handler mode (from Thread mode) |
jberry | 0:9b057566f9ee | 108 | ; c) Stack is Main stack (switched from Process stack) |
jberry | 0:9b057566f9ee | 109 | ; |
jberry | 0:9b057566f9ee | 110 | ; 4) Since PendSV is set to lowest priority in the system (by OS_Start() below), we |
jberry | 0:9b057566f9ee | 111 | ; know that it will only be run when no other exception or interrupt is active, and |
jberry | 0:9b057566f9ee | 112 | ; therefore safe to assume that context being switched out was using the process stack (PSP). |
jberry | 0:9b057566f9ee | 113 | ; |
jberry | 0:9b057566f9ee | 114 | PendSV_Handler |
jberry | 0:9b057566f9ee | 115 | CPSID I ; Prevent interruption during context switch |
jberry | 0:9b057566f9ee | 116 | MRS R0, PSP ; PSP is process stack pointer |
jberry | 0:9b057566f9ee | 117 | CBZ R0, nosave ; Skip register save the first time |
jberry | 0:9b057566f9ee | 118 | |
jberry | 0:9b057566f9ee | 119 | STMDB R0!, {R4-R11} ; Save remaining regs r4-11 on process stack |
jberry | 0:9b057566f9ee | 120 | ; At this point, entire context of process has been saved |
jberry | 0:9b057566f9ee | 121 | |
jberry | 0:9b057566f9ee | 122 | PUSH {R14} ; Save LR exc_return value |
jberry | 0:9b057566f9ee | 123 | LDR R1, =OS_ContextSwitchHook ; OS_ContextSwitchHook(); |
jberry | 0:9b057566f9ee | 124 | BLX R1 |
jberry | 0:9b057566f9ee | 125 | POP {R14} |
jberry | 0:9b057566f9ee | 126 | |
jberry | 0:9b057566f9ee | 127 | ContextRestore |
jberry | 0:9b057566f9ee | 128 | ; R0 is new process SP; |
jberry | 0:9b057566f9ee | 129 | LDMIA R0!, {R4-R11} ; Restore r4-11 from new process stack |
jberry | 0:9b057566f9ee | 130 | MSR PSP, R0 ; Load PSP with new process SP |
jberry | 0:9b057566f9ee | 131 | ORR LR, LR, #0x04 ; Ensure exception return uses process stack |
jberry | 0:9b057566f9ee | 132 | CPSIE I |
jberry | 0:9b057566f9ee | 133 | BX LR ; Exception return will restore remaining context |
jberry | 0:9b057566f9ee | 134 | nosave |
jberry | 0:9b057566f9ee | 135 | MOV R0, R2 ; R2 hold the first task SP |
jberry | 0:9b057566f9ee | 136 | |
jberry | 0:9b057566f9ee | 137 | LDR R1, =NVIC_ST_CTRL ; Enable and run SysTick |
jberry | 0:9b057566f9ee | 138 | LDR R2, =(NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_INTEN | NVIC_ST_CTRL_ENABLE) |
jberry | 0:9b057566f9ee | 139 | STR R2, [R1] |
jberry | 0:9b057566f9ee | 140 | |
jberry | 0:9b057566f9ee | 141 | B ContextRestore |
jberry | 0:9b057566f9ee | 142 | |
jberry | 0:9b057566f9ee | 143 | |
jberry | 0:9b057566f9ee | 144 | ; ----------------------------------------------------------------------------- |
jberry | 0:9b057566f9ee | 145 | ; START MULTITASKING |
jberry | 0:9b057566f9ee | 146 | ; void OS_Start(TStackItem* sp) |
jberry | 0:9b057566f9ee | 147 | ; |
jberry | 0:9b057566f9ee | 148 | ; Note(s) : 1) OS_Start() MUST: |
jberry | 0:9b057566f9ee | 149 | ; a) Setup PendSV and SysTick exception priority to lowest; |
jberry | 0:9b057566f9ee | 150 | ; b) Setup SysTick (reload value); |
jberry | 0:9b057566f9ee | 151 | ; c) Enable interrupts (tasks will run with interrupts enabled). |
jberry | 0:9b057566f9ee | 152 | ; |
jberry | 0:9b057566f9ee | 153 | OS_Start |
jberry | 0:9b057566f9ee | 154 | LDR R1, =NVIC_SYSPRI14 ; Set the PendSV exception priority (lowest) |
jberry | 0:9b057566f9ee | 155 | LDR R2, =NVIC_PENDSV_PRI |
jberry | 0:9b057566f9ee | 156 | STRB R2, [R1] |
jberry | 0:9b057566f9ee | 157 | LDR R1, =NVIC_SYSPRI15 ; Set the SysTick exception priority (lowest) |
jberry | 0:9b057566f9ee | 158 | LDR R2, =NVIC_ST_PRI |
jberry | 0:9b057566f9ee | 159 | STRB R2, [R1] |
jberry | 0:9b057566f9ee | 160 | |
jberry | 0:9b057566f9ee | 161 | LDR R1, =NVIC_ST_RELOAD ; Setup SysTick |
jberry | 0:9b057566f9ee | 162 | LDR R2, =(SYSTICKFREQ/SYSTICKINTRATE-1) |
jberry | 0:9b057566f9ee | 163 | STR R2, [R1] |
jberry | 0:9b057566f9ee | 164 | |
jberry | 0:9b057566f9ee | 165 | MOV R2, R0 ; Save the first task stack |
jberry | 0:9b057566f9ee | 166 | MOVS R0, #0 ; Set the PSP to 0 for initial context switch call |
jberry | 0:9b057566f9ee | 167 | MSR PSP, R0 |
jberry | 0:9b057566f9ee | 168 | |
jberry | 0:9b057566f9ee | 169 | LDR R0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch) |
jberry | 0:9b057566f9ee | 170 | LDR R1, =NVIC_PENDSVSET |
jberry | 0:9b057566f9ee | 171 | STR R1, [R0] |
jberry | 0:9b057566f9ee | 172 | |
jberry | 0:9b057566f9ee | 173 | CPSIE I ; Enable interrupts at processor level |
jberry | 0:9b057566f9ee | 174 | loop |
jberry | 0:9b057566f9ee | 175 | B loop ; Should never get here |
jberry | 0:9b057566f9ee | 176 | |
jberry | 0:9b057566f9ee | 177 | |
jberry | 0:9b057566f9ee | 178 | END |