scmRTOS_test - Program to control an accelerometer, motors and a…

Users » jberry » Code » scmRTOS_test

Greg Kuhn / Mbed 2 deprecated scmRTOS_test

Program to control an accelerometer, motors and a rangefinder using the ScmRTOS ported to mbed. (Work in progress and buggy)

Dependencies: mbed

scmRTOS/CortexM3/OS_Target.h@0:9b057566f9ee, 2010-11-01 (annotated)

Committer:: jberry
Date:: Mon Nov 01 20:39:01 2010 +0000
Revision:: 0:9b057566f9ee

Who changed what in which revision?

User	Revision	Line number	New contents of line
jberry	0:9b057566f9ee	1	//******************************************************************************
jberry	0:9b057566f9ee	2	//*
jberry	0:9b057566f9ee	3	//* FULLNAME: Single-Chip Microcontroller Real-Time Operating System
jberry	0:9b057566f9ee	4	//*
jberry	0:9b057566f9ee	5	//* NICKNAME: scmRTOS
jberry	0:9b057566f9ee	6	//*
jberry	0:9b057566f9ee	7	//* PROCESSOR: ARM Cortex-M3
jberry	0:9b057566f9ee	8	//*
jberry	0:9b057566f9ee	9	//* TOOLKIT: RVCT (ARM)
jberry	0:9b057566f9ee	10	//*
jberry	0:9b057566f9ee	11	//* PURPOSE: Target Dependent Stuff Header. Declarations And Definitions
jberry	0:9b057566f9ee	12	//*
jberry	0:9b057566f9ee	13	//* Version: 3.10
jberry	0:9b057566f9ee	14	//*
jberry	0:9b057566f9ee	15	//* $Revision: 195 $
jberry	0:9b057566f9ee	16	//* $Date:: 2008-06-19 #$
jberry	0:9b057566f9ee	17	//*
jberry	0:9b057566f9ee	18	//* Copyright (c) 2003-2010, Harry E. Zhurov
jberry	0:9b057566f9ee	19	//*
jberry	0:9b057566f9ee	20	//* Permission is hereby granted, free of charge, to any person
jberry	0:9b057566f9ee	21	//* obtaining a copy of this software and associated documentation
jberry	0:9b057566f9ee	22	//* files (the "Software"), to deal in the Software without restriction,
jberry	0:9b057566f9ee	23	//* including without limitation the rights to use, copy, modify, merge,
jberry	0:9b057566f9ee	24	//* publish, distribute, sublicense, and/or sell copies of the Software,
jberry	0:9b057566f9ee	25	//* and to permit persons to whom the Software is furnished to do so,
jberry	0:9b057566f9ee	26	//* subject to the following conditions:
jberry	0:9b057566f9ee	27	//*
jberry	0:9b057566f9ee	28	//* The above copyright notice and this permission notice shall be included
jberry	0:9b057566f9ee	29	//* in all copies or substantial portions of the Software.
jberry	0:9b057566f9ee	30	//*
jberry	0:9b057566f9ee	31	//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
jberry	0:9b057566f9ee	32	//* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
jberry	0:9b057566f9ee	33	//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
jberry	0:9b057566f9ee	34	//* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
jberry	0:9b057566f9ee	35	//* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
jberry	0:9b057566f9ee	36	//* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
jberry	0:9b057566f9ee	37	//* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
jberry	0:9b057566f9ee	38	//*
jberry	0:9b057566f9ee	39	//* =================================================================
jberry	0:9b057566f9ee	40	//* See http://scmrtos.sourceforge.net for documentation, latest
jberry	0:9b057566f9ee	41	//* information, license and contact details.
jberry	0:9b057566f9ee	42	//* =================================================================
jberry	0:9b057566f9ee	43	//*
jberry	0:9b057566f9ee	44	//******************************************************************************
jberry	0:9b057566f9ee	45	//* Ported by Andrey Chuikin, Copyright (c) 2008-2010
jberry	0:9b057566f9ee	46
jberry	0:9b057566f9ee	47	#ifndef scmRTOS_CORTEXM3_H
jberry	0:9b057566f9ee	48	#define scmRTOS_CORTEXM3_H
jberry	0:9b057566f9ee	49
jberry	0:9b057566f9ee	50	#include <commdefs.h>
jberry	0:9b057566f9ee	51
jberry	0:9b057566f9ee	52	//------------------------------------------------------------------------------
jberry	0:9b057566f9ee	53	//
jberry	0:9b057566f9ee	54	// Compiler and Target checks
jberry	0:9b057566f9ee	55	//
jberry	0:9b057566f9ee	56	//
jberry	0:9b057566f9ee	57	#ifndef __ARMCC_VERSION
jberry	0:9b057566f9ee	58	#error "This file should only be compiled with ARM RVCT Compiler"
jberry	0:9b057566f9ee	59	#endif // __ARMCC_VERSION
jberry	0:9b057566f9ee	60
jberry	0:9b057566f9ee	61	#if __TARGET_ARCH_ARM != 0 \|\| __TARGET_ARCH_THUMB != 4
jberry	0:9b057566f9ee	62	#error "This file must be compiled for ARMv7-M (Cortex-M3) processor only."
jberry	0:9b057566f9ee	63	#endif
jberry	0:9b057566f9ee	64
jberry	0:9b057566f9ee	65	//------------------------------------------------------------------------------
jberry	0:9b057566f9ee	66	//
jberry	0:9b057566f9ee	67	// Target specific types
jberry	0:9b057566f9ee	68	//
jberry	0:9b057566f9ee	69	//
jberry	0:9b057566f9ee	70	typedef dword TStackItem;
jberry	0:9b057566f9ee	71	typedef dword TStatusReg;
jberry	0:9b057566f9ee	72
jberry	0:9b057566f9ee	73	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	74	//
jberry	0:9b057566f9ee	75	// Configuration macros
jberry	0:9b057566f9ee	76	//
jberry	0:9b057566f9ee	77	//
jberry	0:9b057566f9ee	78	#define OS_PROCESS __attribute__((__noreturn__))
jberry	0:9b057566f9ee	79	#define OS_INTERRUPT
jberry	0:9b057566f9ee	80	#define DUMMY_INSTR() __NOP()
jberry	0:9b057566f9ee	81	#define INLINE_PROCESS_CTOR INLINE inline
jberry	0:9b057566f9ee	82
jberry	0:9b057566f9ee	83	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	84	//
jberry	0:9b057566f9ee	85	// Uncomment macro value below for SystemTimer() run in critical section
jberry	0:9b057566f9ee	86	//
jberry	0:9b057566f9ee	87	// This is useful (and necessary) when target processor has hardware
jberry	0:9b057566f9ee	88	// enabled nested interrups. Cortex-M3 have such interrupts.
jberry	0:9b057566f9ee	89	//
jberry	0:9b057566f9ee	90	#define SYS_TIMER_CRIT_SECT() TCritSect cs
jberry	0:9b057566f9ee	91
jberry	0:9b057566f9ee	92	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	93	// Separate return stack not required
jberry	0:9b057566f9ee	94	#define SEPARATE_RETURN_STACK 0
jberry	0:9b057566f9ee	95
jberry	0:9b057566f9ee	96	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	97	// Software interrupt stack switching not supported in Cortex-M3 port
jberry	0:9b057566f9ee	98	// because processor implements hardware stack switching.
jberry	0:9b057566f9ee	99	// So, system timer isr wrapper can't be choosen at project level
jberry	0:9b057566f9ee	100	//
jberry	0:9b057566f9ee	101	#define scmRTOS_ISRW_TYPE TISRW
jberry	0:9b057566f9ee	102
jberry	0:9b057566f9ee	103	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	104	//
jberry	0:9b057566f9ee	105	// scmRTOS Context Switch Scheme
jberry	0:9b057566f9ee	106	//
jberry	0:9b057566f9ee	107	// The macro defines a context switch manner. Value 0 sets direct context
jberry	0:9b057566f9ee	108	// switch in the scheduler and in the OS ISRs. This is the primary method.
jberry	0:9b057566f9ee	109	// Value 1 sets the second way to switch context - by using of software
jberry	0:9b057566f9ee	110	// interrupt. See documentation fo details.
jberry	0:9b057566f9ee	111	// Cortex-M3 port supports software interrupt switch method only.
jberry	0:9b057566f9ee	112	//
jberry	0:9b057566f9ee	113	#define scmRTOS_CONTEXT_SWITCH_SCHEME 1
jberry	0:9b057566f9ee	114
jberry	0:9b057566f9ee	115	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	116	//
jberry	0:9b057566f9ee	117	// Include project-level configurations
jberry	0:9b057566f9ee	118	// !!! The order of includes is important !!!
jberry	0:9b057566f9ee	119	//
jberry	0:9b057566f9ee	120	#include "../scmRTOS_config.h"
jberry	0:9b057566f9ee	121	#include "../scmRTOS_TARGET_CFG.h"
jberry	0:9b057566f9ee	122	#include <scmRTOS_defs.h>
jberry	0:9b057566f9ee	123	#include <LPC17xx.h>
jberry	0:9b057566f9ee	124
jberry	0:9b057566f9ee	125	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	126	//
jberry	0:9b057566f9ee	127	// The Critital Section Wrapper
jberry	0:9b057566f9ee	128	//
jberry	0:9b057566f9ee	129	//
jberry	0:9b057566f9ee	130	#define __enable_interrupt() __enable_irq()
jberry	0:9b057566f9ee	131	#define __disable_interrupt() __disable_irq()
jberry	0:9b057566f9ee	132
jberry	0:9b057566f9ee	133	#define __set_interrupt_state(status) __set_PRIMASK(status)
jberry	0:9b057566f9ee	134	#define __get_interrupt_state() __get_PRIMASK()
jberry	0:9b057566f9ee	135
jberry	0:9b057566f9ee	136	class TCritSect
jberry	0:9b057566f9ee	137	{
jberry	0:9b057566f9ee	138	public:
jberry	0:9b057566f9ee	139	TCritSect () : StatusReg(__get_interrupt_state()) { __disable_interrupt(); }
jberry	0:9b057566f9ee	140	~TCritSect() { __set_interrupt_state(StatusReg); }
jberry	0:9b057566f9ee	141
jberry	0:9b057566f9ee	142	private:
jberry	0:9b057566f9ee	143	TStatusReg StatusReg;
jberry	0:9b057566f9ee	144	};
jberry	0:9b057566f9ee	145	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	146
jberry	0:9b057566f9ee	147	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	148	//
jberry	0:9b057566f9ee	149	// Priority stuff
jberry	0:9b057566f9ee	150	//
jberry	0:9b057566f9ee	151	//
jberry	0:9b057566f9ee	152	namespace OS
jberry	0:9b057566f9ee	153	{
jberry	0:9b057566f9ee	154	INLINE inline OS::TProcessMap GetPrioTag(const byte pr) { return static_cast<OS::TProcessMap> (1 << pr); }
jberry	0:9b057566f9ee	155
jberry	0:9b057566f9ee	156	#if scmRTOS_PRIORITY_ORDER == 0
jberry	0:9b057566f9ee	157	INLINE inline byte GetHighPriority(TProcessMap pm)
jberry	0:9b057566f9ee	158	{
jberry	0:9b057566f9ee	159	byte pr = 0;
jberry	0:9b057566f9ee	160
jberry	0:9b057566f9ee	161	while( !(pm & 0x0001) )
jberry	0:9b057566f9ee	162	{
jberry	0:9b057566f9ee	163	pr++;
jberry	0:9b057566f9ee	164	pm >>= 1;
jberry	0:9b057566f9ee	165	}
jberry	0:9b057566f9ee	166	return pr;
jberry	0:9b057566f9ee	167	}
jberry	0:9b057566f9ee	168	#else
jberry	0:9b057566f9ee	169	INLINE inline byte GetHighPriority(TProcessMap pm) { return (31 - __clz(pm)); }
jberry	0:9b057566f9ee	170	#endif // scmRTOS_PRIORITY_ORDER
jberry	0:9b057566f9ee	171	}
jberry	0:9b057566f9ee	172
jberry	0:9b057566f9ee	173	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	174	//
jberry	0:9b057566f9ee	175	// Interrupt and Interrupt Service Routines support
jberry	0:9b057566f9ee	176	//
jberry	0:9b057566f9ee	177	INLINE inline TStatusReg GetInterruptState( ) { return __get_interrupt_state(); }
jberry	0:9b057566f9ee	178	INLINE inline void SetInterruptState(TStatusReg sr) { __set_interrupt_state(sr); }
jberry	0:9b057566f9ee	179
jberry	0:9b057566f9ee	180	INLINE inline void EnableInterrupts() { __enable_interrupt(); }
jberry	0:9b057566f9ee	181	INLINE inline void DisableInterrupts() { __disable_interrupt(); }
jberry	0:9b057566f9ee	182
jberry	0:9b057566f9ee	183
jberry	0:9b057566f9ee	184	namespace OS
jberry	0:9b057566f9ee	185	{
jberry	0:9b057566f9ee	186	INLINE inline void EnableContextSwitch() { EnableInterrupts(); }
jberry	0:9b057566f9ee	187	INLINE inline void DisableContextSwitch() { DisableInterrupts(); }
jberry	0:9b057566f9ee	188	}
jberry	0:9b057566f9ee	189
jberry	0:9b057566f9ee	190	#include <OS_Kernel.h>
jberry	0:9b057566f9ee	191
jberry	0:9b057566f9ee	192	namespace OS
jberry	0:9b057566f9ee	193	{
jberry	0:9b057566f9ee	194	//--------------------------------------------------------------------------
jberry	0:9b057566f9ee	195	//
jberry	0:9b057566f9ee	196	// NAME : OS ISR support
jberry	0:9b057566f9ee	197	//
jberry	0:9b057566f9ee	198	// PURPOSE : Implements common actions on interrupt enter and exit
jberry	0:9b057566f9ee	199	// under the OS
jberry	0:9b057566f9ee	200	//
jberry	0:9b057566f9ee	201	// DESCRIPTION:
jberry	0:9b057566f9ee	202	//
jberry	0:9b057566f9ee	203	//
jberry	0:9b057566f9ee	204	class TISRW
jberry	0:9b057566f9ee	205	{
jberry	0:9b057566f9ee	206	public:
jberry	0:9b057566f9ee	207	INLINE TISRW() { ISR_Enter(); }
jberry	0:9b057566f9ee	208	INLINE ~TISRW() { ISR_Exit(); }
jberry	0:9b057566f9ee	209
jberry	0:9b057566f9ee	210	private:
jberry	0:9b057566f9ee	211	//-----------------------------------------------------
jberry	0:9b057566f9ee	212	INLINE void ISR_Enter()
jberry	0:9b057566f9ee	213	{
jberry	0:9b057566f9ee	214	TCritSect cs;
jberry	0:9b057566f9ee	215	Kernel.ISR_NestCount++;
jberry	0:9b057566f9ee	216	}
jberry	0:9b057566f9ee	217	//-----------------------------------------------------
jberry	0:9b057566f9ee	218	INLINE void ISR_Exit()
jberry	0:9b057566f9ee	219	{
jberry	0:9b057566f9ee	220	TCritSect cs;
jberry	0:9b057566f9ee	221	if(--Kernel.ISR_NestCount) return;
jberry	0:9b057566f9ee	222	Kernel.SchedISR();
jberry	0:9b057566f9ee	223	}
jberry	0:9b057566f9ee	224	//-----------------------------------------------------
jberry	0:9b057566f9ee	225	};
jberry	0:9b057566f9ee	226
jberry	0:9b057566f9ee	227	// No software interrupt stack switching provided,
jberry	0:9b057566f9ee	228	// TISRW_SS declared to be the same as TISRW for porting compability
jberry	0:9b057566f9ee	229	#define TISRW_SS TISRW
jberry	0:9b057566f9ee	230
jberry	0:9b057566f9ee	231	} // ns OS
jberry	0:9b057566f9ee	232	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	233
jberry	0:9b057566f9ee	234	#endif // scmRTOS_CORTEXM3_H
jberry	0:9b057566f9ee	235	//-----------------------------------------------------------------------------
jberry	0:9b057566f9ee	236

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	01 Nov 2010
Imports:	6
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

scmRTOS/CortexM3/OS_Target.h@0:9b057566f9ee, 2010-11-01 (annotated)

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