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MCP23017.cpp@22:c024b20a0e2d, 2018-06-13 (annotated)

Committer:
jasminealice
Date:
Wed Jun 13 09:06:55 2018 +0000
Revision:
22:c024b20a0e2d
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jasminealice 22:c024b20a0e2d 1 /* MCP23017 - drive the Microchip MCP23017 16-bit Port Extender using I2C
jasminealice 22:c024b20a0e2d 2 * Copyright (c) 2010 Wim Huiskamp, Romilly Cocking (original version for SPI)
jasminealice 22:c024b20a0e2d 3 *
jasminealice 22:c024b20a0e2d 4 * Released under the MIT License: http://mbed.org/license/mit
jasminealice 22:c024b20a0e2d 5 *
jasminealice 22:c024b20a0e2d 6 * version 0.2 Initial Release
jasminealice 22:c024b20a0e2d 7 * version 0.3 Cleaned up
jasminealice 22:c024b20a0e2d 8 * version 0.4 Fixed problem with _read method
jasminealice 22:c024b20a0e2d 9 * version 0.5 Added support for 'Banked' access to registers
jasminealice 22:c024b20a0e2d 10 */
jasminealice 22:c024b20a0e2d 11
jasminealice 22:c024b20a0e2d 12 #include "mbed.h"
jasminealice 22:c024b20a0e2d 13 #include "MCP23017.h"
jasminealice 22:c024b20a0e2d 14
jasminealice 22:c024b20a0e2d 15 /** Create an MCP23017 object connected to the specified I2C object and using the specified deviceAddress
jasminealice 22:c024b20a0e2d 16 *
jasminealice 22:c024b20a0e2d 17 * @param I2C &i2c the I2C port to connect to
jasminealice 22:c024b20a0e2d 18 * @param char deviceAddress the address of the MCP23017
jasminealice 22:c024b20a0e2d 19 */
jasminealice 22:c024b20a0e2d 20 MCP23017::MCP23017(I2C &i2c, char deviceAddress) : _i2c(i2c) {
jasminealice 22:c024b20a0e2d 21 _writeOpcode = deviceAddress & 0xFE; // low order bit = 0 for write
jasminealice 22:c024b20a0e2d 22 _readOpcode = deviceAddress | 0x01; // low order bit = 1 for read
jasminealice 22:c024b20a0e2d 23 _init();
jasminealice 22:c024b20a0e2d 24 }
jasminealice 22:c024b20a0e2d 25
jasminealice 22:c024b20a0e2d 26 /** Read from specified MCP23017 register
jasminealice 22:c024b20a0e2d 27 *
jasminealice 22:c024b20a0e2d 28 * @param char address the internal registeraddress of the MCP23017
jasminealice 22:c024b20a0e2d 29 * @returns data from register
jasminealice 22:c024b20a0e2d 30 */
jasminealice 22:c024b20a0e2d 31 char MCP23017::_read(char address) {
jasminealice 22:c024b20a0e2d 32 char data[2];
jasminealice 22:c024b20a0e2d 33
jasminealice 22:c024b20a0e2d 34 data[0] = address;
jasminealice 22:c024b20a0e2d 35 _i2c.write(_writeOpcode, data, 1); // Select Register for reading
jasminealice 22:c024b20a0e2d 36 _i2c.read(_readOpcode, data, 1); // Read from selected Register
jasminealice 22:c024b20a0e2d 37
jasminealice 22:c024b20a0e2d 38 return data[0];
jasminealice 22:c024b20a0e2d 39 }
jasminealice 22:c024b20a0e2d 40
jasminealice 22:c024b20a0e2d 41
jasminealice 22:c024b20a0e2d 42 /** Write to specified MCP23017 register
jasminealice 22:c024b20a0e2d 43 *
jasminealice 22:c024b20a0e2d 44 * @param char address the internal registeraddress of the MCP23017
jasminealice 22:c024b20a0e2d 45 */
jasminealice 22:c024b20a0e2d 46 void MCP23017::_write(char address, char byte) {
jasminealice 22:c024b20a0e2d 47 char data[2];
jasminealice 22:c024b20a0e2d 48
jasminealice 22:c024b20a0e2d 49 data[0] = address;
jasminealice 22:c024b20a0e2d 50 data[1] = byte;
jasminealice 22:c024b20a0e2d 51 _i2c.write(_writeOpcode, data, 2); // Write data to selected Register
jasminealice 22:c024b20a0e2d 52 }
jasminealice 22:c024b20a0e2d 53
jasminealice 22:c024b20a0e2d 54
jasminealice 22:c024b20a0e2d 55 /** Init MCP23017
jasminealice 22:c024b20a0e2d 56 *
jasminealice 22:c024b20a0e2d 57 * @param
jasminealice 22:c024b20a0e2d 58 * @returns
jasminealice 22:c024b20a0e2d 59 */
jasminealice 22:c024b20a0e2d 60 void MCP23017::_init() {
jasminealice 22:c024b20a0e2d 61
jasminealice 22:c024b20a0e2d 62 _bankMode = NOT_BNK; // This may not be true after software reset without hardware reset !!!
jasminealice 22:c024b20a0e2d 63
jasminealice 22:c024b20a0e2d 64 _write(IOCON_AB[_bankMode][PORT_A], (IOCON_BYTE_MODE | IOCON_HAEN )); // Hardware addressing on, no-autoincrement, 16 bit mode (operations toggle between A and B registers)
jasminealice 22:c024b20a0e2d 65
jasminealice 22:c024b20a0e2d 66 }
jasminealice 22:c024b20a0e2d 67
jasminealice 22:c024b20a0e2d 68 /** Set I/O direction of specified MCP23017 Port
jasminealice 22:c024b20a0e2d 69 *
jasminealice 22:c024b20a0e2d 70 * @param Port Port address (Port_A or Port_B)
jasminealice 22:c024b20a0e2d 71 * @param char direction pin direction (0 = output, 1 = input)
jasminealice 22:c024b20a0e2d 72 */
jasminealice 22:c024b20a0e2d 73 void MCP23017::direction(Port port, char direction) {
jasminealice 22:c024b20a0e2d 74 _write(IODIR_AB[_bankMode][port], direction);
jasminealice 22:c024b20a0e2d 75 }
jasminealice 22:c024b20a0e2d 76
jasminealice 22:c024b20a0e2d 77 /** Set Pull-Up Resistors on specified MCP23017 Port
jasminealice 22:c024b20a0e2d 78 *
jasminealice 22:c024b20a0e2d 79 * @param Port Port address (Port_A or Port_B)
jasminealice 22:c024b20a0e2d 80 * @param char offOrOn per pin (0 = off, 1 = on)
jasminealice 22:c024b20a0e2d 81 */
jasminealice 22:c024b20a0e2d 82 void MCP23017::configurePullUps(Port port, char offOrOn) {
jasminealice 22:c024b20a0e2d 83
jasminealice 22:c024b20a0e2d 84 _write(GPPU_AB[_bankMode][port], offOrOn);
jasminealice 22:c024b20a0e2d 85 }
jasminealice 22:c024b20a0e2d 86
jasminealice 22:c024b20a0e2d 87 /** Configere the Banked or Non-Banked mode
jasminealice 22:c024b20a0e2d 88 *
jasminealice 22:c024b20a0e2d 89 * @param Bank bankMode
jasminealice 22:c024b20a0e2d 90 * @param char offOrOn per pin (0 = off, 1 = on)
jasminealice 22:c024b20a0e2d 91 */
jasminealice 22:c024b20a0e2d 92 void MCP23017::configureBanked(Bank bankMode) {
jasminealice 22:c024b20a0e2d 93
jasminealice 22:c024b20a0e2d 94 if (bankMode == NOT_BNK) {
jasminealice 22:c024b20a0e2d 95 // Non-Banked sequential registers (default POR)
jasminealice 22:c024b20a0e2d 96 // Hardware addressing on, , no-autoincrement, 16 bit mode (operations do toggle between A and B registers)
jasminealice 22:c024b20a0e2d 97 _write(IOCON_AB[_bankMode][PORT_A], (IOCON_BYTE_MODE | IOCON_HAEN ));
jasminealice 22:c024b20a0e2d 98 _bankMode = NOT_BNK;
jasminealice 22:c024b20a0e2d 99 }
jasminealice 22:c024b20a0e2d 100 else {
jasminealice 22:c024b20a0e2d 101 // Banked registers
jasminealice 22:c024b20a0e2d 102 // Hardware addressing on, no-autoincrement, 8 bit mode
jasminealice 22:c024b20a0e2d 103 _write(IOCON_AB[_bankMode][PORT_A], (IOCON_BANK | IOCON_BYTE_MODE | IOCON_HAEN ));
jasminealice 22:c024b20a0e2d 104 _bankMode = BNK;
jasminealice 22:c024b20a0e2d 105 }
jasminealice 22:c024b20a0e2d 106 }
jasminealice 22:c024b20a0e2d 107
jasminealice 22:c024b20a0e2d 108
jasminealice 22:c024b20a0e2d 109 void MCP23017::interruptEnable(Port port, char interruptsEnabledMask) {
jasminealice 22:c024b20a0e2d 110
jasminealice 22:c024b20a0e2d 111 _write(GPINTEN_AB[_bankMode][port], interruptsEnabledMask);
jasminealice 22:c024b20a0e2d 112
jasminealice 22:c024b20a0e2d 113 }
jasminealice 22:c024b20a0e2d 114
jasminealice 22:c024b20a0e2d 115 void MCP23017::mirrorInterrupts(bool mirror) {
jasminealice 22:c024b20a0e2d 116 char iocon = _read(IOCON_AB[_bankMode][PORT_A]);
jasminealice 22:c024b20a0e2d 117
jasminealice 22:c024b20a0e2d 118 if (mirror) {
jasminealice 22:c024b20a0e2d 119 iocon = iocon | INTERRUPT_MIRROR_BIT;
jasminealice 22:c024b20a0e2d 120 }
jasminealice 22:c024b20a0e2d 121 else {
jasminealice 22:c024b20a0e2d 122 iocon = iocon & ~INTERRUPT_MIRROR_BIT;
jasminealice 22:c024b20a0e2d 123 }
jasminealice 22:c024b20a0e2d 124
jasminealice 22:c024b20a0e2d 125 _write(IOCON_AB[_bankMode][PORT_A], iocon);
jasminealice 22:c024b20a0e2d 126
jasminealice 22:c024b20a0e2d 127 }
jasminealice 22:c024b20a0e2d 128
jasminealice 22:c024b20a0e2d 129 void MCP23017::interruptPolarity(Polarity polarity) {
jasminealice 22:c024b20a0e2d 130 char iocon = _read(IOCON_AB[_bankMode][PORT_A]);
jasminealice 22:c024b20a0e2d 131
jasminealice 22:c024b20a0e2d 132 if (polarity == ACTIVE_LOW) {
jasminealice 22:c024b20a0e2d 133 iocon = iocon & ~INTERRUPT_POLARITY_BIT;
jasminealice 22:c024b20a0e2d 134 } else {
jasminealice 22:c024b20a0e2d 135 iocon = iocon | INTERRUPT_POLARITY_BIT;
jasminealice 22:c024b20a0e2d 136 }
jasminealice 22:c024b20a0e2d 137 _write(IOCON_AB[_bankMode][PORT_A], iocon);
jasminealice 22:c024b20a0e2d 138 }
jasminealice 22:c024b20a0e2d 139
jasminealice 22:c024b20a0e2d 140 void MCP23017::defaultValue(Port port, char valuesToCompare) {
jasminealice 22:c024b20a0e2d 141
jasminealice 22:c024b20a0e2d 142 _write(DEFVAL_AB[_bankMode][port], valuesToCompare);
jasminealice 22:c024b20a0e2d 143
jasminealice 22:c024b20a0e2d 144 }
jasminealice 22:c024b20a0e2d 145
jasminealice 22:c024b20a0e2d 146 void MCP23017::interruptControl(Port port, char interruptControlBits) {
jasminealice 22:c024b20a0e2d 147
jasminealice 22:c024b20a0e2d 148 _write(INTCON_AB[_bankMode][port], interruptControlBits);
jasminealice 22:c024b20a0e2d 149
jasminealice 22:c024b20a0e2d 150 }
jasminealice 22:c024b20a0e2d 151
jasminealice 22:c024b20a0e2d 152 /** Write to specified MCP23017 Port
jasminealice 22:c024b20a0e2d 153 *
jasminealice 22:c024b20a0e2d 154 * @param Port Port address (Port_A or Port_B)
jasminealice 22:c024b20a0e2d 155 * @param char byte data to write
jasminealice 22:c024b20a0e2d 156 */
jasminealice 22:c024b20a0e2d 157 void MCP23017::write(Port port, char byte) {
jasminealice 22:c024b20a0e2d 158 _write(OLAT_AB[_bankMode][port], byte);
jasminealice 22:c024b20a0e2d 159 }
jasminealice 22:c024b20a0e2d 160
jasminealice 22:c024b20a0e2d 161 /** Read from specified MCP23017 Port
jasminealice 22:c024b20a0e2d 162 *
jasminealice 22:c024b20a0e2d 163 * @param Port Port address (Port_A or Port_B)
jasminealice 22:c024b20a0e2d 164 * @returns data from Port
jasminealice 22:c024b20a0e2d 165 */
jasminealice 22:c024b20a0e2d 166 char MCP23017::read(Port port) {
jasminealice 22:c024b20a0e2d 167 return _read(GPIO_AB[_bankMode][port]);
jasminealice 22:c024b20a0e2d 168 }
jasminealice 22:c024b20a0e2d 169