Jari Ojanen / RF12B

RFM12B radio module driver library

Dependents:   HaTemp

Fork of RF12B by Andrew Lindsay

RF12B.cpp@1:984e7620084e, 2015-08-13 (annotated)

Committer:
jari
Date:
Thu Aug 13 13:50:12 2015 +0000
Revision:
1:984e7620084e
Parent:
0:e724d8251cdc
Child:
2:a5808054ac5f
Removed LED4 (Doesn't work with current board)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
SomeRandomBloke 0:e724d8251cdc 1 /* RF12B Library. Based on work done by JeeLabs.org ported to mbed by SK Pang.
SomeRandomBloke 0:e724d8251cdc 2 http://jeelabs.net/projects/cafe/wiki/RF12
SomeRandomBloke 0:e724d8251cdc 3
SomeRandomBloke 0:e724d8251cdc 4 http://opensource.org/licenses/mit-license.php
SomeRandomBloke 0:e724d8251cdc 5
SomeRandomBloke 0:e724d8251cdc 6 Jan 2012 skpang.co.uk
SomeRandomBloke 0:e724d8251cdc 7
SomeRandomBloke 0:e724d8251cdc 8 Modified by Andrew Lindsay (andrew [at] thiseldo [dot] co [dot] uk)
SomeRandomBloke 0:e724d8251cdc 9
SomeRandomBloke 0:e724d8251cdc 10 Permission is hereby granted, free of charge, to any person obtaining a copy
SomeRandomBloke 0:e724d8251cdc 11 of this software and associated documentation files (the "Software"), to deal
SomeRandomBloke 0:e724d8251cdc 12 in the Software without restriction, including without limitation the rights
SomeRandomBloke 0:e724d8251cdc 13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
SomeRandomBloke 0:e724d8251cdc 14 copies of the Software, and to permit persons to whom the Software is
SomeRandomBloke 0:e724d8251cdc 15 furnished to do so, subject to the following conditions:
SomeRandomBloke 0:e724d8251cdc 16
SomeRandomBloke 0:e724d8251cdc 17 The above copyright notice and this permission notice shall be included in
SomeRandomBloke 0:e724d8251cdc 18 all copies or substantial portions of the Software.
SomeRandomBloke 0:e724d8251cdc 19
SomeRandomBloke 0:e724d8251cdc 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
SomeRandomBloke 0:e724d8251cdc 21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
SomeRandomBloke 0:e724d8251cdc 22 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
SomeRandomBloke 0:e724d8251cdc 23 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
SomeRandomBloke 0:e724d8251cdc 24 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
SomeRandomBloke 0:e724d8251cdc 25 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
SomeRandomBloke 0:e724d8251cdc 26 THE SOFTWARE.
SomeRandomBloke 0:e724d8251cdc 27 */
SomeRandomBloke 0:e724d8251cdc 28
SomeRandomBloke 0:e724d8251cdc 29 #include "RF12B.h"
SomeRandomBloke 0:e724d8251cdc 30
SomeRandomBloke 0:e724d8251cdc 31 // RF12 command codes
SomeRandomBloke 0:e724d8251cdc 32 #define RF_RECEIVER_ON 0x82DD
SomeRandomBloke 0:e724d8251cdc 33 #define RF_XMITTER_ON 0x823D
SomeRandomBloke 0:e724d8251cdc 34 #define RF_IDLE_MODE 0x820D
SomeRandomBloke 0:e724d8251cdc 35 #define RF_SLEEP_MODE 0x8205
SomeRandomBloke 0:e724d8251cdc 36 #define RF_WAKEUP_MODE 0x8207
SomeRandomBloke 0:e724d8251cdc 37 #define RF_TXREG_WRITE 0xB800
SomeRandomBloke 0:e724d8251cdc 38 #define RF_RX_FIFO_READ 0xB000
SomeRandomBloke 0:e724d8251cdc 39 #define RF_WAKEUP_TIMER 0xE000
SomeRandomBloke 0:e724d8251cdc 40
SomeRandomBloke 0:e724d8251cdc 41 // RF12 status bits
SomeRandomBloke 0:e724d8251cdc 42 #define RF_LBD_BIT 0x0400
SomeRandomBloke 0:e724d8251cdc 43 #define RF_RSSI_BIT 0x0100
SomeRandomBloke 0:e724d8251cdc 44
SomeRandomBloke 0:e724d8251cdc 45 // bits in the node id configuration byte
SomeRandomBloke 0:e724d8251cdc 46 #define NODE_BAND 0xC0 // frequency band
SomeRandomBloke 0:e724d8251cdc 47 #define NODE_ACKANY 0x20 // ack on broadcast packets if set
SomeRandomBloke 0:e724d8251cdc 48 #define NODE_ID 0x1F // id of this node, as A..Z or 1..31
SomeRandomBloke 0:e724d8251cdc 49
SomeRandomBloke 0:e724d8251cdc 50 // transceiver states, these determine what to do with each interrupt
SomeRandomBloke 0:e724d8251cdc 51 enum {
SomeRandomBloke 0:e724d8251cdc 52 TXCRC1, TXCRC2, TXTAIL, TXDONE, TXIDLE,
SomeRandomBloke 0:e724d8251cdc 53 TXRECV,
SomeRandomBloke 0:e724d8251cdc 54 TXPRE1, TXPRE2, TXPRE3, TXSYN1, TXSYN2,
SomeRandomBloke 0:e724d8251cdc 55 };
SomeRandomBloke 0:e724d8251cdc 56
SomeRandomBloke 0:e724d8251cdc 57 RF12B::RF12B(PinName _SDI,
SomeRandomBloke 0:e724d8251cdc 58 PinName _SDO,
SomeRandomBloke 0:e724d8251cdc 59 PinName _SCK,
SomeRandomBloke 0:e724d8251cdc 60 PinName _NCS,
SomeRandomBloke 0:e724d8251cdc 61 PinName _NIRQ):spi(_SDI, _SDO, _SCK),
SomeRandomBloke 0:e724d8251cdc 62 NCS(_NCS), NIRQ(_NIRQ), NIRQ_in(_NIRQ) {
SomeRandomBloke 0:e724d8251cdc 63
SomeRandomBloke 0:e724d8251cdc 64 /* SPI frequency, 8 bit word length, polarity and phase */
SomeRandomBloke 0:e724d8251cdc 65 spi.format(8,0);
SomeRandomBloke 0:e724d8251cdc 66 spi.frequency(2000000);
SomeRandomBloke 0:e724d8251cdc 67
SomeRandomBloke 0:e724d8251cdc 68 /* Set ~CS high */
SomeRandomBloke 0:e724d8251cdc 69 NCS = 1;
SomeRandomBloke 0:e724d8251cdc 70
SomeRandomBloke 0:e724d8251cdc 71 /* Setup interrupt to happen on falling edge of NIRQ */
SomeRandomBloke 0:e724d8251cdc 72 NIRQ.fall(this, &RF12B::rxISR);
SomeRandomBloke 0:e724d8251cdc 73 }
SomeRandomBloke 0:e724d8251cdc 74
SomeRandomBloke 0:e724d8251cdc 75
SomeRandomBloke 0:e724d8251cdc 76 /**********************************************************************
SomeRandomBloke 0:e724d8251cdc 77 * PRIVATE FUNCTIONS
SomeRandomBloke 0:e724d8251cdc 78 *********************************************************************/
SomeRandomBloke 0:e724d8251cdc 79
SomeRandomBloke 0:e724d8251cdc 80 /* Initialises the RF12B module */
SomeRandomBloke 0:e724d8251cdc 81 void RF12B::init(uint8_t id, uint8_t band, uint8_t g) {
SomeRandomBloke 0:e724d8251cdc 82
SomeRandomBloke 0:e724d8251cdc 83 nodeid = id;
SomeRandomBloke 0:e724d8251cdc 84 group = g;
SomeRandomBloke 0:e724d8251cdc 85 rf12_grp = g;
SomeRandomBloke 0:e724d8251cdc 86
SomeRandomBloke 0:e724d8251cdc 87 writeCmd(0x0000); // intitial SPI transfer added to avoid power-up problem
SomeRandomBloke 0:e724d8251cdc 88 writeCmd(RF_SLEEP_MODE); // DC (disable clk pin), enable lbd
SomeRandomBloke 0:e724d8251cdc 89
SomeRandomBloke 0:e724d8251cdc 90 // wait until RFM12B is out of power-up reset, this takes several *seconds*
SomeRandomBloke 0:e724d8251cdc 91 writeCmd(RF_TXREG_WRITE); // in case we're still in OOK mode
SomeRandomBloke 0:e724d8251cdc 92
SomeRandomBloke 0:e724d8251cdc 93 while (NIRQ == 0) writeCmd(0x0000);
SomeRandomBloke 0:e724d8251cdc 94
SomeRandomBloke 0:e724d8251cdc 95 // TODO: Have band specific parameters to optimise settings
SomeRandomBloke 0:e724d8251cdc 96
SomeRandomBloke 0:e724d8251cdc 97 writeCmd(0x80C7 | (band << 4)); // EL (ena TX), EF (ena RX FIFO), 12.0pF
SomeRandomBloke 0:e724d8251cdc 98 writeCmd(0xA640); // 868MHz
SomeRandomBloke 0:e724d8251cdc 99 writeCmd(0xC606); // approx 49.2 Kbps, i.e. 10000/29/(1+6) Kbps
SomeRandomBloke 0:e724d8251cdc 100 writeCmd(0x94A2); // VDI,FAST,134kHz,0dBm,-91dBm
SomeRandomBloke 0:e724d8251cdc 101 writeCmd(0xC2AC); // AL,!ml,DIG,DQD4
SomeRandomBloke 0:e724d8251cdc 102 if (group != 0) {
SomeRandomBloke 0:e724d8251cdc 103 writeCmd(0xCA83); // FIFO8,2-SYNC,!ff,DR
SomeRandomBloke 0:e724d8251cdc 104 writeCmd(0xCE00 | group); // SYNC=2DXX
SomeRandomBloke 0:e724d8251cdc 105 } else {
SomeRandomBloke 0:e724d8251cdc 106 writeCmd(0xCA8B); // FIFO8,1-SYNC,!ff,DR
SomeRandomBloke 0:e724d8251cdc 107 writeCmd(0xCE2D); // SYNC=2D
SomeRandomBloke 0:e724d8251cdc 108 }
SomeRandomBloke 0:e724d8251cdc 109
SomeRandomBloke 0:e724d8251cdc 110 writeCmd(0xC483); // @PWR,NO RSTRIC,!st,!fi,OE,EN
SomeRandomBloke 0:e724d8251cdc 111 writeCmd(0x9850); // !mp,90kHz,MAX OUT
SomeRandomBloke 0:e724d8251cdc 112 writeCmd(0xCC77); // OB1, OB0, LPX, ddy, DDIT, BW0
SomeRandomBloke 0:e724d8251cdc 113 writeCmd(0xE000); // NOT USE
SomeRandomBloke 0:e724d8251cdc 114 writeCmd(0xC800); // NOT USE
SomeRandomBloke 0:e724d8251cdc 115 writeCmd(0xC049); // 1.66MHz,3.1V
SomeRandomBloke 0:e724d8251cdc 116
SomeRandomBloke 0:e724d8251cdc 117 rxstate = TXIDLE;
SomeRandomBloke 0:e724d8251cdc 118
SomeRandomBloke 0:e724d8251cdc 119 }
SomeRandomBloke 0:e724d8251cdc 120
SomeRandomBloke 0:e724d8251cdc 121 int RF12B::available( void ) {
SomeRandomBloke 0:e724d8251cdc 122
SomeRandomBloke 0:e724d8251cdc 123 return (rf12_recvDone() && (check_crc() == 0) && length() < 66) ? length() : 0;
SomeRandomBloke 0:e724d8251cdc 124 }
SomeRandomBloke 0:e724d8251cdc 125
SomeRandomBloke 0:e724d8251cdc 126 /* Write a command to the RF Module */
SomeRandomBloke 0:e724d8251cdc 127 int RF12B::writeCmd(int cmd) {
SomeRandomBloke 0:e724d8251cdc 128 NCS = 0;
SomeRandomBloke 0:e724d8251cdc 129 int recv = spi.write(cmd >>8);
SomeRandomBloke 0:e724d8251cdc 130 recv = spi.write(cmd);
SomeRandomBloke 0:e724d8251cdc 131 NCS = 1;
SomeRandomBloke 0:e724d8251cdc 132 return recv;
SomeRandomBloke 0:e724d8251cdc 133 }
SomeRandomBloke 0:e724d8251cdc 134
SomeRandomBloke 0:e724d8251cdc 135 /* Sends a byte of data across RF */
SomeRandomBloke 0:e724d8251cdc 136 void RF12B::send(uint8_t data) {
SomeRandomBloke 0:e724d8251cdc 137 while (NIRQ);
SomeRandomBloke 0:e724d8251cdc 138 writeCmd(0xB800 + data);
SomeRandomBloke 0:e724d8251cdc 139 }
SomeRandomBloke 0:e724d8251cdc 140
SomeRandomBloke 0:e724d8251cdc 141
SomeRandomBloke 0:e724d8251cdc 142 /* Interrupt routine for data reception and Txing */
SomeRandomBloke 0:e724d8251cdc 143 void RF12B::rxISR() {
SomeRandomBloke 0:e724d8251cdc 144 // a transfer of 2x 16 bits @ 2 MHz over SPI takes 2x 8 us inside this ISR
SomeRandomBloke 0:e724d8251cdc 145 writeCmd(0x0000);
SomeRandomBloke 0:e724d8251cdc 146
SomeRandomBloke 0:e724d8251cdc 147 if (rxstate == TXRECV) {
SomeRandomBloke 0:e724d8251cdc 148 uint8_t in = rf12_xfer(RF_RX_FIFO_READ);
SomeRandomBloke 0:e724d8251cdc 149
SomeRandomBloke 0:e724d8251cdc 150 if (rxfill == 0 && group != 0)
SomeRandomBloke 0:e724d8251cdc 151 rf12_buf[rxfill++] = group;
SomeRandomBloke 0:e724d8251cdc 152
SomeRandomBloke 0:e724d8251cdc 153 rf12_buf[rxfill++] = in;
SomeRandomBloke 0:e724d8251cdc 154 rf12_crc = _crc16_update(rf12_crc, in);
SomeRandomBloke 0:e724d8251cdc 155
SomeRandomBloke 0:e724d8251cdc 156 if (rxfill >= rf12_len + 5 || rxfill >= RF_MAX)
SomeRandomBloke 0:e724d8251cdc 157 rf12_xfer(RF_IDLE_MODE);
SomeRandomBloke 0:e724d8251cdc 158 } else {
SomeRandomBloke 0:e724d8251cdc 159 uint8_t out;
SomeRandomBloke 0:e724d8251cdc 160
SomeRandomBloke 0:e724d8251cdc 161 if (rxstate < 0) {
SomeRandomBloke 0:e724d8251cdc 162 uint8_t pos = 3 + rf12_len + rxstate++;
SomeRandomBloke 0:e724d8251cdc 163 out = rf12_buf[pos];
SomeRandomBloke 0:e724d8251cdc 164 rf12_crc = _crc16_update(rf12_crc, out);
SomeRandomBloke 0:e724d8251cdc 165 } else {
SomeRandomBloke 0:e724d8251cdc 166 switch (rxstate++) {
SomeRandomBloke 0:e724d8251cdc 167 case TXSYN1:
SomeRandomBloke 0:e724d8251cdc 168 out = 0x2D;
SomeRandomBloke 0:e724d8251cdc 169 break;
SomeRandomBloke 0:e724d8251cdc 170 case TXSYN2:
SomeRandomBloke 0:e724d8251cdc 171 out = rf12_grp;
SomeRandomBloke 0:e724d8251cdc 172 rxstate = - (2 + rf12_len);
SomeRandomBloke 0:e724d8251cdc 173 break;
SomeRandomBloke 0:e724d8251cdc 174 case TXCRC1:
SomeRandomBloke 0:e724d8251cdc 175 out = rf12_crc;
SomeRandomBloke 0:e724d8251cdc 176 break;
SomeRandomBloke 0:e724d8251cdc 177 case TXCRC2:
SomeRandomBloke 0:e724d8251cdc 178 out = rf12_crc >> 8;
SomeRandomBloke 0:e724d8251cdc 179 break;
SomeRandomBloke 0:e724d8251cdc 180 case TXDONE:
SomeRandomBloke 0:e724d8251cdc 181 rf12_xfer(RF_IDLE_MODE); // fall through
SomeRandomBloke 0:e724d8251cdc 182 default:
SomeRandomBloke 0:e724d8251cdc 183 out = 0xAA;
SomeRandomBloke 0:e724d8251cdc 184 }
SomeRandomBloke 0:e724d8251cdc 185 }
SomeRandomBloke 0:e724d8251cdc 186 rf12_xfer(RF_TXREG_WRITE + out);
SomeRandomBloke 0:e724d8251cdc 187 }
SomeRandomBloke 0:e724d8251cdc 188 }
SomeRandomBloke 0:e724d8251cdc 189
SomeRandomBloke 0:e724d8251cdc 190
SomeRandomBloke 0:e724d8251cdc 191 void RF12B::rf12_sendStart (uint8_t hdr, const void* ptr, uint8_t len) {
SomeRandomBloke 0:e724d8251cdc 192 rf12_len = len;
SomeRandomBloke 0:e724d8251cdc 193 memcpy((void*) rf12_data, ptr, len);
SomeRandomBloke 0:e724d8251cdc 194 rf12_sendStart(hdr);
SomeRandomBloke 0:e724d8251cdc 195 }
SomeRandomBloke 0:e724d8251cdc 196
SomeRandomBloke 0:e724d8251cdc 197 //void RF12B::rf12_sendStart2 (uint8_t hdr) {
SomeRandomBloke 0:e724d8251cdc 198 void RF12B::rf12_sendStart (uint8_t hdr) {
SomeRandomBloke 0:e724d8251cdc 199 rf12_hdr = hdr & RF12_HDR_DST ? hdr :
SomeRandomBloke 0:e724d8251cdc 200 (hdr & ~RF12_HDR_MASK) + (nodeid & NODE_ID);
SomeRandomBloke 0:e724d8251cdc 201
SomeRandomBloke 0:e724d8251cdc 202 /*
SomeRandomBloke 0:e724d8251cdc 203 if (crypter != 0)
SomeRandomBloke 0:e724d8251cdc 204 crypter(1);
SomeRandomBloke 0:e724d8251cdc 205 */
SomeRandomBloke 0:e724d8251cdc 206 rf12_crc = ~0;
SomeRandomBloke 0:e724d8251cdc 207
SomeRandomBloke 0:e724d8251cdc 208 rf12_crc = _crc16_update(rf12_crc, rf12_grp);
SomeRandomBloke 0:e724d8251cdc 209 rxstate = TXPRE1;
SomeRandomBloke 0:e724d8251cdc 210
SomeRandomBloke 0:e724d8251cdc 211 rf12_xfer(RF_XMITTER_ON); // bytes will be fed via interrupts
SomeRandomBloke 0:e724d8251cdc 212 }
SomeRandomBloke 0:e724d8251cdc 213
SomeRandomBloke 0:e724d8251cdc 214
SomeRandomBloke 0:e724d8251cdc 215 uint16_t RF12B::rf12_xfer (uint16_t cmd) {
SomeRandomBloke 0:e724d8251cdc 216 NCS = 0;
SomeRandomBloke 0:e724d8251cdc 217 uint16_t reply = rf12_byte(cmd >> 8) << 8;
SomeRandomBloke 0:e724d8251cdc 218 reply |= rf12_byte(cmd);
SomeRandomBloke 0:e724d8251cdc 219 NCS = 1;
SomeRandomBloke 0:e724d8251cdc 220 return reply;
SomeRandomBloke 0:e724d8251cdc 221 }
SomeRandomBloke 0:e724d8251cdc 222
SomeRandomBloke 0:e724d8251cdc 223 void RF12B::rf12_recvStart (void) {
SomeRandomBloke 0:e724d8251cdc 224 rxfill = rf12_len = 0;
SomeRandomBloke 0:e724d8251cdc 225 rf12_crc = ~0;
SomeRandomBloke 0:e724d8251cdc 226
SomeRandomBloke 0:e724d8251cdc 227 if (group != 0)
SomeRandomBloke 0:e724d8251cdc 228 rf12_crc = _crc16_update(~0, group);
SomeRandomBloke 0:e724d8251cdc 229
SomeRandomBloke 0:e724d8251cdc 230 rxstate = TXRECV;
SomeRandomBloke 0:e724d8251cdc 231 rf12_xfer(RF_RECEIVER_ON);
SomeRandomBloke 0:e724d8251cdc 232 }
SomeRandomBloke 0:e724d8251cdc 233
SomeRandomBloke 0:e724d8251cdc 234 uint16_t RF12B::check_crc(void) {
SomeRandomBloke 0:e724d8251cdc 235 return rf12_crc;
SomeRandomBloke 0:e724d8251cdc 236 }
SomeRandomBloke 0:e724d8251cdc 237
SomeRandomBloke 0:e724d8251cdc 238 uint8_t RF12B::length(void) {
SomeRandomBloke 0:e724d8251cdc 239 return rf12_len;
SomeRandomBloke 0:e724d8251cdc 240 }
SomeRandomBloke 0:e724d8251cdc 241
SomeRandomBloke 0:e724d8251cdc 242 uint8_t* RF12B::get_data(void) {
SomeRandomBloke 0:e724d8251cdc 243 return (uint8_t*)rf12_buf;
SomeRandomBloke 0:e724d8251cdc 244 }
SomeRandomBloke 0:e724d8251cdc 245
SomeRandomBloke 0:e724d8251cdc 246 uint8_t* RF12B::get_payload(void) {
SomeRandomBloke 0:e724d8251cdc 247 return (uint8_t*)rf12_data;
SomeRandomBloke 0:e724d8251cdc 248 }
SomeRandomBloke 0:e724d8251cdc 249
SomeRandomBloke 0:e724d8251cdc 250 uint8_t RF12B::rf12_recvDone (void) {
SomeRandomBloke 0:e724d8251cdc 251
SomeRandomBloke 0:e724d8251cdc 252 if (rxstate == TXRECV && (rxfill >= rf12_len + 5 || rxfill >= RF_MAX)) {
SomeRandomBloke 0:e724d8251cdc 253 rxstate = TXIDLE;
SomeRandomBloke 0:e724d8251cdc 254
SomeRandomBloke 0:e724d8251cdc 255 if (rf12_len > RF12_MAXDATA)
SomeRandomBloke 0:e724d8251cdc 256 rf12_crc = 1; // force bad crc if packet length is invalid
SomeRandomBloke 0:e724d8251cdc 257 if (!(rf12_hdr & RF12_HDR_DST) || (nodeid & NODE_ID) == 31 ||
SomeRandomBloke 0:e724d8251cdc 258 (rf12_hdr & RF12_HDR_MASK) == (nodeid & NODE_ID)) {
SomeRandomBloke 0:e724d8251cdc 259 /*
SomeRandomBloke 0:e724d8251cdc 260 printf("RX Len: %d ", rf12_len+6);
SomeRandomBloke 0:e724d8251cdc 261 for (int i=0; i<rf12_len+6; i++) {
SomeRandomBloke 0:e724d8251cdc 262 printf("%02X ",rf12_buf[i]);
SomeRandomBloke 0:e724d8251cdc 263 }
SomeRandomBloke 0:e724d8251cdc 264 printf(" crc:%x\n",rf12_crc);
SomeRandomBloke 0:e724d8251cdc 265 */
SomeRandomBloke 0:e724d8251cdc 266 /*
SomeRandomBloke 0:e724d8251cdc 267 if (rf12_crc == 0 && crypter != 0)
SomeRandomBloke 0:e724d8251cdc 268 crypter(0);
SomeRandomBloke 0:e724d8251cdc 269 else
SomeRandomBloke 0:e724d8251cdc 270 rf12_seq = -1;
SomeRandomBloke 0:e724d8251cdc 271 */
SomeRandomBloke 0:e724d8251cdc 272 return 1; // it's a broadcast packet or it's addressed to this node
SomeRandomBloke 0:e724d8251cdc 273
SomeRandomBloke 0:e724d8251cdc 274 }
SomeRandomBloke 0:e724d8251cdc 275 }
SomeRandomBloke 0:e724d8251cdc 276 if (rxstate == TXIDLE)
SomeRandomBloke 0:e724d8251cdc 277 rf12_recvStart();
SomeRandomBloke 0:e724d8251cdc 278 return 0;
SomeRandomBloke 0:e724d8251cdc 279 }
SomeRandomBloke 0:e724d8251cdc 280
SomeRandomBloke 0:e724d8251cdc 281 uint8_t RF12B::rf12_byte(uint8_t out) {
SomeRandomBloke 0:e724d8251cdc 282 // unsigned char recv = spi.write(out);
SomeRandomBloke 0:e724d8251cdc 283 // return recv;
SomeRandomBloke 0:e724d8251cdc 284 return spi.write(out);
SomeRandomBloke 0:e724d8251cdc 285 }
SomeRandomBloke 0:e724d8251cdc 286
SomeRandomBloke 0:e724d8251cdc 287 uint16_t RF12B::_crc16_update(uint16_t crc, uint8_t data) {
SomeRandomBloke 0:e724d8251cdc 288 int i;
SomeRandomBloke 0:e724d8251cdc 289
SomeRandomBloke 0:e724d8251cdc 290 crc ^= data;
SomeRandomBloke 0:e724d8251cdc 291 for (i = 0; i < 8; ++i) {
SomeRandomBloke 0:e724d8251cdc 292 if (crc & 1)
SomeRandomBloke 0:e724d8251cdc 293 crc = (crc >> 1) ^ 0xA001;
SomeRandomBloke 0:e724d8251cdc 294 else
SomeRandomBloke 0:e724d8251cdc 295 crc = (crc >> 1);
SomeRandomBloke 0:e724d8251cdc 296 }
SomeRandomBloke 0:e724d8251cdc 297
SomeRandomBloke 0:e724d8251cdc 298 return crc;
SomeRandomBloke 0:e724d8251cdc 299 }