mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.c@106:ced8cbb51063, 2014-02-26 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Feb 26 09:45:12 2014 +0000
- Revision:
- 106:ced8cbb51063
- Parent:
- 87:085cde657901
- Child:
- 226:b062af740e40
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd
Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/
[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 87:085cde657901 | 1 | /** |
mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_rcc_ex.c |
mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
mbed_official | 106:ced8cbb51063 | 5 | * @version V1.0.0 |
mbed_official | 106:ced8cbb51063 | 6 | * @date 18-February-2014 |
mbed_official | 87:085cde657901 | 7 | * @brief Extension RCC HAL module driver. |
mbed_official | 87:085cde657901 | 8 | * This file provides firmware functions to manage the following |
mbed_official | 87:085cde657901 | 9 | * functionalities RCC extension peripheral: |
mbed_official | 87:085cde657901 | 10 | * + Extended Peripheral Control functions |
mbed_official | 87:085cde657901 | 11 | * |
mbed_official | 87:085cde657901 | 12 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 13 | * @attention |
mbed_official | 87:085cde657901 | 14 | * |
mbed_official | 87:085cde657901 | 15 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 87:085cde657901 | 16 | * |
mbed_official | 87:085cde657901 | 17 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 87:085cde657901 | 18 | * are permitted provided that the following conditions are met: |
mbed_official | 87:085cde657901 | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 87:085cde657901 | 20 | * this list of conditions and the following disclaimer. |
mbed_official | 87:085cde657901 | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 87:085cde657901 | 22 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 87:085cde657901 | 23 | * and/or other materials provided with the distribution. |
mbed_official | 87:085cde657901 | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 87:085cde657901 | 25 | * may be used to endorse or promote products derived from this software |
mbed_official | 87:085cde657901 | 26 | * without specific prior written permission. |
mbed_official | 87:085cde657901 | 27 | * |
mbed_official | 87:085cde657901 | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 87:085cde657901 | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 87:085cde657901 | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 87:085cde657901 | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 87:085cde657901 | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 87:085cde657901 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 87:085cde657901 | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 87:085cde657901 | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 87:085cde657901 | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 87:085cde657901 | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 87:085cde657901 | 38 | * |
mbed_official | 87:085cde657901 | 39 | ****************************************************************************** |
mbed_official | 87:085cde657901 | 40 | */ |
mbed_official | 87:085cde657901 | 41 | |
mbed_official | 87:085cde657901 | 42 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 43 | #include "stm32f4xx_hal.h" |
mbed_official | 87:085cde657901 | 44 | |
mbed_official | 87:085cde657901 | 45 | /** @addtogroup STM32F4xx_HAL_Driver |
mbed_official | 87:085cde657901 | 46 | * @{ |
mbed_official | 87:085cde657901 | 47 | */ |
mbed_official | 87:085cde657901 | 48 | |
mbed_official | 87:085cde657901 | 49 | /** @defgroup RCC |
mbed_official | 87:085cde657901 | 50 | * @brief RCC HAL module driver |
mbed_official | 87:085cde657901 | 51 | * @{ |
mbed_official | 87:085cde657901 | 52 | */ |
mbed_official | 87:085cde657901 | 53 | |
mbed_official | 87:085cde657901 | 54 | #ifdef HAL_RCC_MODULE_ENABLED |
mbed_official | 87:085cde657901 | 55 | |
mbed_official | 87:085cde657901 | 56 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 57 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 58 | #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
mbed_official | 87:085cde657901 | 59 | #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ |
mbed_official | 87:085cde657901 | 60 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 61 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 62 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 63 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 87:085cde657901 | 64 | |
mbed_official | 87:085cde657901 | 65 | /** @defgroup RCCEx_Private_Functions |
mbed_official | 87:085cde657901 | 66 | * @{ |
mbed_official | 87:085cde657901 | 67 | */ |
mbed_official | 87:085cde657901 | 68 | |
mbed_official | 87:085cde657901 | 69 | /** @defgroup RCCEx_Group1 Extended Peripheral Control functions |
mbed_official | 87:085cde657901 | 70 | * @brief Extended Peripheral Control functions |
mbed_official | 87:085cde657901 | 71 | * |
mbed_official | 87:085cde657901 | 72 | @verbatim |
mbed_official | 87:085cde657901 | 73 | =============================================================================== |
mbed_official | 87:085cde657901 | 74 | ##### Extended Peripheral Control functions ##### |
mbed_official | 87:085cde657901 | 75 | =============================================================================== |
mbed_official | 87:085cde657901 | 76 | [..] |
mbed_official | 87:085cde657901 | 77 | This subsection provides a set of functions allowing to control the RCC Clocks |
mbed_official | 87:085cde657901 | 78 | frequencies. |
mbed_official | 106:ced8cbb51063 | 79 | [..] |
mbed_official | 106:ced8cbb51063 | 80 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
mbed_official | 106:ced8cbb51063 | 81 | select the RTC clock source; in this case the Backup domain will be reset in |
mbed_official | 106:ced8cbb51063 | 82 | order to modify the RTC Clock source, as consequence RTC registers (including |
mbed_official | 106:ced8cbb51063 | 83 | the backup registers) and RCC_BDCR register are set to their reset values. |
mbed_official | 87:085cde657901 | 84 | |
mbed_official | 87:085cde657901 | 85 | @endverbatim |
mbed_official | 87:085cde657901 | 86 | * @{ |
mbed_official | 87:085cde657901 | 87 | */ |
mbed_official | 87:085cde657901 | 88 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
mbed_official | 87:085cde657901 | 89 | /** |
mbed_official | 106:ced8cbb51063 | 90 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
mbed_official | 106:ced8cbb51063 | 91 | * parameters in the RCC_PeriphCLKInitTypeDef. |
mbed_official | 87:085cde657901 | 92 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
mbed_official | 106:ced8cbb51063 | 93 | * contains the configuration information for the Extended Peripherals |
mbed_official | 106:ced8cbb51063 | 94 | * clocks(I2S, SAI, LTDC RTC and TIM). |
mbed_official | 106:ced8cbb51063 | 95 | * |
mbed_official | 106:ced8cbb51063 | 96 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
mbed_official | 106:ced8cbb51063 | 97 | * the RTC clock source; in this case the Backup domain will be reset in |
mbed_official | 106:ced8cbb51063 | 98 | * order to modify the RTC Clock source, as consequence RTC registers (including |
mbed_official | 106:ced8cbb51063 | 99 | * the backup registers) and RCC_BDCR register are set to their reset values. |
mbed_official | 106:ced8cbb51063 | 100 | * |
mbed_official | 87:085cde657901 | 101 | * @retval HAL status |
mbed_official | 87:085cde657901 | 102 | */ |
mbed_official | 87:085cde657901 | 103 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
mbed_official | 87:085cde657901 | 104 | { |
mbed_official | 87:085cde657901 | 105 | uint32_t timeout = 0; |
mbed_official | 87:085cde657901 | 106 | uint32_t tmpreg = 0; |
mbed_official | 87:085cde657901 | 107 | |
mbed_official | 87:085cde657901 | 108 | /* Check the parameters */ |
mbed_official | 87:085cde657901 | 109 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
mbed_official | 87:085cde657901 | 110 | |
mbed_official | 87:085cde657901 | 111 | /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/ |
mbed_official | 87:085cde657901 | 112 | |
mbed_official | 87:085cde657901 | 113 | /*----------------------- Common configuration SAI/I2S ---------------------------*/ |
mbed_official | 87:085cde657901 | 114 | /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division |
mbed_official | 87:085cde657901 | 115 | factor is common parameters for both peripherals */ |
mbed_official | 87:085cde657901 | 116 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || |
mbed_official | 87:085cde657901 | 117 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S)) |
mbed_official | 87:085cde657901 | 118 | { |
mbed_official | 87:085cde657901 | 119 | /* check for Parameters */ |
mbed_official | 87:085cde657901 | 120 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
mbed_official | 87:085cde657901 | 121 | |
mbed_official | 87:085cde657901 | 122 | /* Disable the PLLI2S */ |
mbed_official | 87:085cde657901 | 123 | __HAL_RCC_PLLI2S_DISABLE(); |
mbed_official | 87:085cde657901 | 124 | /* Get new Timeout value */ |
mbed_official | 87:085cde657901 | 125 | timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; |
mbed_official | 87:085cde657901 | 126 | /* Wait till PLLI2S is disabled */ |
mbed_official | 87:085cde657901 | 127 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
mbed_official | 87:085cde657901 | 128 | { |
mbed_official | 87:085cde657901 | 129 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 130 | { |
mbed_official | 87:085cde657901 | 131 | /* return in case of Timeout detected */ |
mbed_official | 87:085cde657901 | 132 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 133 | } |
mbed_official | 87:085cde657901 | 134 | } |
mbed_official | 87:085cde657901 | 135 | |
mbed_official | 87:085cde657901 | 136 | /*---------------------------- I2S configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 137 | /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added |
mbed_official | 87:085cde657901 | 138 | only for I2S configuration */ |
mbed_official | 87:085cde657901 | 139 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) |
mbed_official | 87:085cde657901 | 140 | { |
mbed_official | 87:085cde657901 | 141 | /* check for Parameters */ |
mbed_official | 87:085cde657901 | 142 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
mbed_official | 87:085cde657901 | 143 | /* Configure the PLLI2S division factors */ |
mbed_official | 87:085cde657901 | 144 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */ |
mbed_official | 87:085cde657901 | 145 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
mbed_official | 87:085cde657901 | 146 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); |
mbed_official | 87:085cde657901 | 147 | } |
mbed_official | 87:085cde657901 | 148 | |
mbed_official | 87:085cde657901 | 149 | /*---------------------------- SAI configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 150 | /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must |
mbed_official | 87:085cde657901 | 151 | be added only for SAI configuration */ |
mbed_official | 87:085cde657901 | 152 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) |
mbed_official | 87:085cde657901 | 153 | { |
mbed_official | 87:085cde657901 | 154 | /* Check the PLLI2S division factors */ |
mbed_official | 87:085cde657901 | 155 | assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); |
mbed_official | 87:085cde657901 | 156 | assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); |
mbed_official | 87:085cde657901 | 157 | |
mbed_official | 87:085cde657901 | 158 | /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ |
mbed_official | 87:085cde657901 | 159 | tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
mbed_official | 87:085cde657901 | 160 | /* Configure the PLLI2S division factors */ |
mbed_official | 87:085cde657901 | 161 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
mbed_official | 87:085cde657901 | 162 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
mbed_official | 87:085cde657901 | 163 | /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ |
mbed_official | 87:085cde657901 | 164 | __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg); |
mbed_official | 87:085cde657901 | 165 | /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ |
mbed_official | 87:085cde657901 | 166 | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); |
mbed_official | 87:085cde657901 | 167 | } |
mbed_official | 87:085cde657901 | 168 | |
mbed_official | 87:085cde657901 | 169 | /* Enable the PLLI2S */ |
mbed_official | 87:085cde657901 | 170 | __HAL_RCC_PLLI2S_ENABLE(); |
mbed_official | 87:085cde657901 | 171 | /* Get new Timeout value */ |
mbed_official | 87:085cde657901 | 172 | timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; |
mbed_official | 87:085cde657901 | 173 | /* Wait till PLLI2S is ready */ |
mbed_official | 87:085cde657901 | 174 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
mbed_official | 87:085cde657901 | 175 | { |
mbed_official | 87:085cde657901 | 176 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 177 | { |
mbed_official | 87:085cde657901 | 178 | /* return in case of Timeout detected */ |
mbed_official | 87:085cde657901 | 179 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 180 | } |
mbed_official | 87:085cde657901 | 181 | } |
mbed_official | 87:085cde657901 | 182 | } |
mbed_official | 87:085cde657901 | 183 | |
mbed_official | 87:085cde657901 | 184 | /*----------------------- SAI/LTDC Configuration (PLLSAI) -------------------------*/ |
mbed_official | 87:085cde657901 | 185 | |
mbed_official | 87:085cde657901 | 186 | /*----------------------- Common configuration SAI/LTDC ---------------------------*/ |
mbed_official | 87:085cde657901 | 187 | /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division |
mbed_official | 87:085cde657901 | 188 | factor is common parameters for both peripherals */ |
mbed_official | 87:085cde657901 | 189 | if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || |
mbed_official | 87:085cde657901 | 190 | (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) |
mbed_official | 87:085cde657901 | 191 | { |
mbed_official | 87:085cde657901 | 192 | /* Check the PLLSAI division factors */ |
mbed_official | 87:085cde657901 | 193 | assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); |
mbed_official | 87:085cde657901 | 194 | |
mbed_official | 87:085cde657901 | 195 | /* Disable PLLSAI Clock */ |
mbed_official | 87:085cde657901 | 196 | __HAL_RCC_PLLSAI_DISABLE(); |
mbed_official | 87:085cde657901 | 197 | /* Get new Timeout value */ |
mbed_official | 87:085cde657901 | 198 | timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE; |
mbed_official | 87:085cde657901 | 199 | /* Wait till PLLSAI is disabled */ |
mbed_official | 87:085cde657901 | 200 | while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) |
mbed_official | 87:085cde657901 | 201 | { |
mbed_official | 87:085cde657901 | 202 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 203 | { |
mbed_official | 87:085cde657901 | 204 | /* return in case of Timeout detected */ |
mbed_official | 87:085cde657901 | 205 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 206 | } |
mbed_official | 87:085cde657901 | 207 | } |
mbed_official | 87:085cde657901 | 208 | |
mbed_official | 87:085cde657901 | 209 | /*---------------------------- SAI configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 210 | /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must |
mbed_official | 87:085cde657901 | 211 | be added only for SAI configuration */ |
mbed_official | 87:085cde657901 | 212 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) |
mbed_official | 87:085cde657901 | 213 | { |
mbed_official | 87:085cde657901 | 214 | assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); |
mbed_official | 87:085cde657901 | 215 | assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); |
mbed_official | 87:085cde657901 | 216 | |
mbed_official | 87:085cde657901 | 217 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ |
mbed_official | 87:085cde657901 | 218 | tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
mbed_official | 87:085cde657901 | 219 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
mbed_official | 87:085cde657901 | 220 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
mbed_official | 87:085cde657901 | 221 | /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ |
mbed_official | 87:085cde657901 | 222 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg); |
mbed_official | 87:085cde657901 | 223 | /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ |
mbed_official | 87:085cde657901 | 224 | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); |
mbed_official | 87:085cde657901 | 225 | } |
mbed_official | 87:085cde657901 | 226 | |
mbed_official | 87:085cde657901 | 227 | /*---------------------------- LTDC configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 228 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) |
mbed_official | 87:085cde657901 | 229 | { |
mbed_official | 87:085cde657901 | 230 | assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); |
mbed_official | 87:085cde657901 | 231 | assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); |
mbed_official | 87:085cde657901 | 232 | |
mbed_official | 87:085cde657901 | 233 | /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ |
mbed_official | 87:085cde657901 | 234 | tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
mbed_official | 87:085cde657901 | 235 | /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ |
mbed_official | 87:085cde657901 | 236 | /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ |
mbed_official | 87:085cde657901 | 237 | /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ |
mbed_official | 87:085cde657901 | 238 | __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR); |
mbed_official | 87:085cde657901 | 239 | /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ |
mbed_official | 87:085cde657901 | 240 | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); |
mbed_official | 87:085cde657901 | 241 | } |
mbed_official | 87:085cde657901 | 242 | /* Enable PLLSAI Clock */ |
mbed_official | 87:085cde657901 | 243 | __HAL_RCC_PLLSAI_ENABLE(); |
mbed_official | 87:085cde657901 | 244 | /* Get new Timeout value */ |
mbed_official | 87:085cde657901 | 245 | timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE; |
mbed_official | 87:085cde657901 | 246 | /* Wait till PLLSAI is ready */ |
mbed_official | 87:085cde657901 | 247 | while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) |
mbed_official | 87:085cde657901 | 248 | { |
mbed_official | 87:085cde657901 | 249 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 250 | { |
mbed_official | 87:085cde657901 | 251 | /* return in case of Timeout detected */ |
mbed_official | 87:085cde657901 | 252 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 253 | } |
mbed_official | 87:085cde657901 | 254 | } |
mbed_official | 87:085cde657901 | 255 | } |
mbed_official | 87:085cde657901 | 256 | |
mbed_official | 87:085cde657901 | 257 | |
mbed_official | 87:085cde657901 | 258 | /*---------------------------- RTC configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 259 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
mbed_official | 87:085cde657901 | 260 | { |
mbed_official | 106:ced8cbb51063 | 261 | /* Enable Power Clock*/ |
mbed_official | 106:ced8cbb51063 | 262 | __PWR_CLK_ENABLE(); |
mbed_official | 106:ced8cbb51063 | 263 | |
mbed_official | 106:ced8cbb51063 | 264 | /* Enable write access to Backup domain */ |
mbed_official | 106:ced8cbb51063 | 265 | PWR->CR |= PWR_CR_DBP; |
mbed_official | 106:ced8cbb51063 | 266 | |
mbed_official | 106:ced8cbb51063 | 267 | /* Wait for Backup domain Write protection disable */ |
mbed_official | 106:ced8cbb51063 | 268 | timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; |
mbed_official | 106:ced8cbb51063 | 269 | |
mbed_official | 106:ced8cbb51063 | 270 | while((PWR->CR & PWR_CR_DBP) == RESET) |
mbed_official | 106:ced8cbb51063 | 271 | { |
mbed_official | 106:ced8cbb51063 | 272 | if(HAL_GetTick() >= timeout) |
mbed_official | 106:ced8cbb51063 | 273 | { |
mbed_official | 106:ced8cbb51063 | 274 | return HAL_TIMEOUT; |
mbed_official | 106:ced8cbb51063 | 275 | } |
mbed_official | 106:ced8cbb51063 | 276 | } |
mbed_official | 106:ced8cbb51063 | 277 | |
mbed_official | 106:ced8cbb51063 | 278 | /* Reset the Backup domain only if the RTC Clock source selction is modified */ |
mbed_official | 106:ced8cbb51063 | 279 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
mbed_official | 106:ced8cbb51063 | 280 | { |
mbed_official | 106:ced8cbb51063 | 281 | /* Store the content of BDCR register before the reset of Backup Domain */ |
mbed_official | 106:ced8cbb51063 | 282 | tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
mbed_official | 106:ced8cbb51063 | 283 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
mbed_official | 106:ced8cbb51063 | 284 | __HAL_RCC_BACKUPRESET_FORCE(); |
mbed_official | 106:ced8cbb51063 | 285 | __HAL_RCC_BACKUPRESET_RELEASE(); |
mbed_official | 106:ced8cbb51063 | 286 | /* Restore the Content of BDCR register */ |
mbed_official | 106:ced8cbb51063 | 287 | RCC->BDCR = tmpreg; |
mbed_official | 106:ced8cbb51063 | 288 | } |
mbed_official | 106:ced8cbb51063 | 289 | |
mbed_official | 106:ced8cbb51063 | 290 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
mbed_official | 106:ced8cbb51063 | 291 | if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) |
mbed_official | 106:ced8cbb51063 | 292 | { |
mbed_official | 106:ced8cbb51063 | 293 | /* Get timeout */ |
mbed_official | 106:ced8cbb51063 | 294 | timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; |
mbed_official | 106:ced8cbb51063 | 295 | |
mbed_official | 106:ced8cbb51063 | 296 | /* Wait till LSE is ready */ |
mbed_official | 106:ced8cbb51063 | 297 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
mbed_official | 106:ced8cbb51063 | 298 | { |
mbed_official | 106:ced8cbb51063 | 299 | if(HAL_GetTick() >= timeout) |
mbed_official | 106:ced8cbb51063 | 300 | { |
mbed_official | 106:ced8cbb51063 | 301 | return HAL_TIMEOUT; |
mbed_official | 106:ced8cbb51063 | 302 | } |
mbed_official | 106:ced8cbb51063 | 303 | } |
mbed_official | 106:ced8cbb51063 | 304 | } |
mbed_official | 106:ced8cbb51063 | 305 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
mbed_official | 87:085cde657901 | 306 | } |
mbed_official | 87:085cde657901 | 307 | |
mbed_official | 87:085cde657901 | 308 | /*---------------------------- TIM configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 309 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) |
mbed_official | 87:085cde657901 | 310 | { |
mbed_official | 87:085cde657901 | 311 | __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); |
mbed_official | 87:085cde657901 | 312 | } |
mbed_official | 87:085cde657901 | 313 | return HAL_OK; |
mbed_official | 87:085cde657901 | 314 | } |
mbed_official | 87:085cde657901 | 315 | |
mbed_official | 87:085cde657901 | 316 | /** |
mbed_official | 87:085cde657901 | 317 | * @brief Configures the RCC_OscInitStruct according to the internal |
mbed_official | 87:085cde657901 | 318 | * RCC configuration registers. |
mbed_official | 87:085cde657901 | 319 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 87:085cde657901 | 320 | * will be configured. |
mbed_official | 87:085cde657901 | 321 | * @retval None |
mbed_official | 87:085cde657901 | 322 | */ |
mbed_official | 87:085cde657901 | 323 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
mbed_official | 87:085cde657901 | 324 | { |
mbed_official | 87:085cde657901 | 325 | uint32_t tempreg; |
mbed_official | 87:085cde657901 | 326 | |
mbed_official | 87:085cde657901 | 327 | /* Set all possible values for the extended clock type parameter------------*/ |
mbed_official | 87:085cde657901 | 328 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; |
mbed_official | 87:085cde657901 | 329 | |
mbed_official | 87:085cde657901 | 330 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 331 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); |
mbed_official | 87:085cde657901 | 332 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
mbed_official | 87:085cde657901 | 333 | PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); |
mbed_official | 87:085cde657901 | 334 | /* Get the PLLSAI Clock configuration -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 335 | PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); |
mbed_official | 87:085cde657901 | 336 | PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); |
mbed_official | 87:085cde657901 | 337 | PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); |
mbed_official | 87:085cde657901 | 338 | /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 339 | PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); |
mbed_official | 87:085cde657901 | 340 | PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); |
mbed_official | 87:085cde657901 | 341 | PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); |
mbed_official | 87:085cde657901 | 342 | /* Get the RTC Clock configuration -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 343 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); |
mbed_official | 87:085cde657901 | 344 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); |
mbed_official | 87:085cde657901 | 345 | |
mbed_official | 87:085cde657901 | 346 | if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) |
mbed_official | 87:085cde657901 | 347 | { |
mbed_official | 87:085cde657901 | 348 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; |
mbed_official | 87:085cde657901 | 349 | } |
mbed_official | 87:085cde657901 | 350 | else |
mbed_official | 87:085cde657901 | 351 | { |
mbed_official | 87:085cde657901 | 352 | PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; |
mbed_official | 87:085cde657901 | 353 | } |
mbed_official | 87:085cde657901 | 354 | } |
mbed_official | 87:085cde657901 | 355 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
mbed_official | 87:085cde657901 | 356 | |
mbed_official | 87:085cde657901 | 357 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) |
mbed_official | 87:085cde657901 | 358 | /** |
mbed_official | 87:085cde657901 | 359 | * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the |
mbed_official | 87:085cde657901 | 360 | * RCC_PeriphCLKInitTypeDef. |
mbed_official | 87:085cde657901 | 361 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
mbed_official | 87:085cde657901 | 362 | * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). |
mbed_official | 106:ced8cbb51063 | 363 | * |
mbed_official | 106:ced8cbb51063 | 364 | * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case |
mbed_official | 106:ced8cbb51063 | 365 | * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup |
mbed_official | 106:ced8cbb51063 | 366 | * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset |
mbed_official | 106:ced8cbb51063 | 367 | * |
mbed_official | 87:085cde657901 | 368 | * @retval HAL status |
mbed_official | 87:085cde657901 | 369 | */ |
mbed_official | 87:085cde657901 | 370 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
mbed_official | 87:085cde657901 | 371 | { |
mbed_official | 87:085cde657901 | 372 | uint32_t timeout = 0; |
mbed_official | 106:ced8cbb51063 | 373 | uint32_t tmpreg = 0; |
mbed_official | 87:085cde657901 | 374 | |
mbed_official | 87:085cde657901 | 375 | /* Check the parameters */ |
mbed_official | 87:085cde657901 | 376 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
mbed_official | 87:085cde657901 | 377 | |
mbed_official | 87:085cde657901 | 378 | /*---------------------------- I2S configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 379 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) |
mbed_official | 87:085cde657901 | 380 | { |
mbed_official | 87:085cde657901 | 381 | /* check for Parameters */ |
mbed_official | 87:085cde657901 | 382 | assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); |
mbed_official | 87:085cde657901 | 383 | assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); |
mbed_official | 87:085cde657901 | 384 | |
mbed_official | 87:085cde657901 | 385 | /* Disable the PLLI2S */ |
mbed_official | 87:085cde657901 | 386 | __HAL_RCC_PLLI2S_DISABLE(); |
mbed_official | 87:085cde657901 | 387 | /* Get new Timeout value */ |
mbed_official | 87:085cde657901 | 388 | timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; |
mbed_official | 87:085cde657901 | 389 | /* Wait till PLLI2S is disabled */ |
mbed_official | 87:085cde657901 | 390 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
mbed_official | 87:085cde657901 | 391 | { |
mbed_official | 87:085cde657901 | 392 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 393 | { |
mbed_official | 87:085cde657901 | 394 | /* return in case of Timeout detected */ |
mbed_official | 87:085cde657901 | 395 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 396 | } |
mbed_official | 87:085cde657901 | 397 | } |
mbed_official | 87:085cde657901 | 398 | /* Configure the PLLI2S division factors */ |
mbed_official | 87:085cde657901 | 399 | /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */ |
mbed_official | 87:085cde657901 | 400 | /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ |
mbed_official | 87:085cde657901 | 401 | __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); |
mbed_official | 87:085cde657901 | 402 | |
mbed_official | 87:085cde657901 | 403 | /* Enable the PLLI2S */ |
mbed_official | 87:085cde657901 | 404 | __HAL_RCC_PLLI2S_ENABLE(); |
mbed_official | 87:085cde657901 | 405 | /* Get new Timeout value */ |
mbed_official | 87:085cde657901 | 406 | timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE; |
mbed_official | 87:085cde657901 | 407 | /* Wait till PLLI2S is ready */ |
mbed_official | 87:085cde657901 | 408 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
mbed_official | 87:085cde657901 | 409 | { |
mbed_official | 87:085cde657901 | 410 | if(HAL_GetTick() >= timeout) |
mbed_official | 87:085cde657901 | 411 | { |
mbed_official | 87:085cde657901 | 412 | /* return in case of Timeout detected */ |
mbed_official | 87:085cde657901 | 413 | return HAL_TIMEOUT; |
mbed_official | 87:085cde657901 | 414 | } |
mbed_official | 87:085cde657901 | 415 | } |
mbed_official | 87:085cde657901 | 416 | } |
mbed_official | 87:085cde657901 | 417 | |
mbed_official | 87:085cde657901 | 418 | /*---------------------------- RTC configuration -------------------------------*/ |
mbed_official | 87:085cde657901 | 419 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
mbed_official | 87:085cde657901 | 420 | { |
mbed_official | 106:ced8cbb51063 | 421 | /* Enable Power Clock*/ |
mbed_official | 106:ced8cbb51063 | 422 | __PWR_CLK_ENABLE(); |
mbed_official | 106:ced8cbb51063 | 423 | |
mbed_official | 106:ced8cbb51063 | 424 | /* Enable write access to Backup domain */ |
mbed_official | 106:ced8cbb51063 | 425 | PWR->CR |= PWR_CR_DBP; |
mbed_official | 106:ced8cbb51063 | 426 | |
mbed_official | 106:ced8cbb51063 | 427 | /* Wait for Backup domain Write protection disable */ |
mbed_official | 106:ced8cbb51063 | 428 | timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; |
mbed_official | 106:ced8cbb51063 | 429 | |
mbed_official | 106:ced8cbb51063 | 430 | while((PWR->CR & PWR_CR_DBP) == RESET) |
mbed_official | 106:ced8cbb51063 | 431 | { |
mbed_official | 106:ced8cbb51063 | 432 | if(HAL_GetTick() >= timeout) |
mbed_official | 106:ced8cbb51063 | 433 | { |
mbed_official | 106:ced8cbb51063 | 434 | return HAL_TIMEOUT; |
mbed_official | 106:ced8cbb51063 | 435 | } |
mbed_official | 106:ced8cbb51063 | 436 | } |
mbed_official | 106:ced8cbb51063 | 437 | |
mbed_official | 106:ced8cbb51063 | 438 | /* Reset the Backup domain only if the RTC Clock source selction is modified */ |
mbed_official | 106:ced8cbb51063 | 439 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
mbed_official | 106:ced8cbb51063 | 440 | { |
mbed_official | 106:ced8cbb51063 | 441 | /* Store the content of BDCR register before the reset of Backup Domain */ |
mbed_official | 106:ced8cbb51063 | 442 | tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
mbed_official | 106:ced8cbb51063 | 443 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
mbed_official | 106:ced8cbb51063 | 444 | __HAL_RCC_BACKUPRESET_FORCE(); |
mbed_official | 106:ced8cbb51063 | 445 | __HAL_RCC_BACKUPRESET_RELEASE(); |
mbed_official | 106:ced8cbb51063 | 446 | /* Restore the Content of BDCR register */ |
mbed_official | 106:ced8cbb51063 | 447 | RCC->BDCR = tmpreg; |
mbed_official | 106:ced8cbb51063 | 448 | } |
mbed_official | 106:ced8cbb51063 | 449 | |
mbed_official | 106:ced8cbb51063 | 450 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
mbed_official | 106:ced8cbb51063 | 451 | if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) |
mbed_official | 106:ced8cbb51063 | 452 | { |
mbed_official | 106:ced8cbb51063 | 453 | /* Get timeout */ |
mbed_official | 106:ced8cbb51063 | 454 | timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE; |
mbed_official | 106:ced8cbb51063 | 455 | |
mbed_official | 106:ced8cbb51063 | 456 | /* Wait till LSE is ready */ |
mbed_official | 106:ced8cbb51063 | 457 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
mbed_official | 106:ced8cbb51063 | 458 | { |
mbed_official | 106:ced8cbb51063 | 459 | if(HAL_GetTick() >= timeout) |
mbed_official | 106:ced8cbb51063 | 460 | { |
mbed_official | 106:ced8cbb51063 | 461 | return HAL_TIMEOUT; |
mbed_official | 106:ced8cbb51063 | 462 | } |
mbed_official | 106:ced8cbb51063 | 463 | } |
mbed_official | 106:ced8cbb51063 | 464 | } |
mbed_official | 106:ced8cbb51063 | 465 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
mbed_official | 87:085cde657901 | 466 | } |
mbed_official | 87:085cde657901 | 467 | |
mbed_official | 87:085cde657901 | 468 | return HAL_OK; |
mbed_official | 87:085cde657901 | 469 | } |
mbed_official | 87:085cde657901 | 470 | |
mbed_official | 87:085cde657901 | 471 | /** |
mbed_official | 87:085cde657901 | 472 | * @brief Configures the RCC_OscInitStruct according to the internal |
mbed_official | 87:085cde657901 | 473 | * RCC configuration registers. |
mbed_official | 87:085cde657901 | 474 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 87:085cde657901 | 475 | * will be configured. |
mbed_official | 87:085cde657901 | 476 | * @retval None |
mbed_official | 87:085cde657901 | 477 | */ |
mbed_official | 87:085cde657901 | 478 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
mbed_official | 87:085cde657901 | 479 | { |
mbed_official | 87:085cde657901 | 480 | uint32_t tempreg; |
mbed_official | 87:085cde657901 | 481 | |
mbed_official | 87:085cde657901 | 482 | /* Set all possible values for the extended clock type parameter------------*/ |
mbed_official | 87:085cde657901 | 483 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; |
mbed_official | 87:085cde657901 | 484 | |
mbed_official | 87:085cde657901 | 485 | /* Get the PLLI2S Clock configuration -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 486 | PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); |
mbed_official | 87:085cde657901 | 487 | PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); |
mbed_official | 87:085cde657901 | 488 | |
mbed_official | 87:085cde657901 | 489 | /* Get the RTC Clock configuration -----------------------------------------------*/ |
mbed_official | 87:085cde657901 | 490 | tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); |
mbed_official | 87:085cde657901 | 491 | PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); |
mbed_official | 87:085cde657901 | 492 | |
mbed_official | 87:085cde657901 | 493 | } |
mbed_official | 87:085cde657901 | 494 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */ |
mbed_official | 87:085cde657901 | 495 | /** |
mbed_official | 87:085cde657901 | 496 | * @} |
mbed_official | 87:085cde657901 | 497 | */ |
mbed_official | 87:085cde657901 | 498 | |
mbed_official | 87:085cde657901 | 499 | /** |
mbed_official | 87:085cde657901 | 500 | * @} |
mbed_official | 87:085cde657901 | 501 | */ |
mbed_official | 87:085cde657901 | 502 | |
mbed_official | 87:085cde657901 | 503 | #endif /* HAL_RCC_MODULE_ENABLED */ |
mbed_official | 87:085cde657901 | 504 | /** |
mbed_official | 87:085cde657901 | 505 | * @} |
mbed_official | 87:085cde657901 | 506 | */ |
mbed_official | 87:085cde657901 | 507 | |
mbed_official | 87:085cde657901 | 508 | /** |
mbed_official | 87:085cde657901 | 509 | * @} |
mbed_official | 87:085cde657901 | 510 | */ |
mbed_official | 87:085cde657901 | 511 | |
mbed_official | 87:085cde657901 | 512 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |