mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_dma.h
- Committer:
- mbed_official
- Date:
- 2014-02-26
- Revision:
- 106:ced8cbb51063
- Parent:
- 76:aeb1df146756
File content as of revision 106:ced8cbb51063:
/** ****************************************************************************** * @file stm32f0xx_dma.h * @author MCD Application Team * @version V1.3.0 * @date 16-January-2014 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0XX_DMA_H #define __STM32F0XX_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx.h" /** @addtogroup STM32F0xx_StdPeriph_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DMA Init structures definition */ typedef struct { uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. This parameter can be a value of @ref DMA_data_transfer_direction */ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction */ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. This parameter can be a value of @ref DMA_memory_incremented_mode */ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_peripheral_data_size */ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_memory_data_size */ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_circular_normal_mode @note: The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_priority_level */ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of @ref DMA_memory_to_memory */ }DMA_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants * @{ */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ ((PERIPH) == DMA1_Channel2) || \ ((PERIPH) == DMA1_Channel3) || \ ((PERIPH) == DMA1_Channel4) || \ ((PERIPH) == DMA1_Channel5) || \ ((PERIPH) == DMA1_Channel6) || \ ((PERIPH) == DMA1_Channel7)) /** @defgroup DMA_data_transfer_direction * @{ */ #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) #define DMA_DIR_PeripheralDST DMA_CCR_DIR #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ ((DIR) == DMA_DIR_PeripheralDST)) /** * @} */ /** @defgroup DMA_peripheral_incremented_mode * @{ */ #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define DMA_PeripheralInc_Enable DMA_CCR_PINC #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ ((STATE) == DMA_PeripheralInc_Enable)) /** * @} */ /** @defgroup DMA_memory_incremented_mode * @{ */ #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define DMA_MemoryInc_Enable DMA_CCR_MINC #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ ((STATE) == DMA_MemoryInc_Enable)) /** * @} */ /** @defgroup DMA_peripheral_data_size * @{ */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ ((SIZE) == DMA_PeripheralDataSize_Word)) /** * @} */ /** @defgroup DMA_memory_data_size * @{ */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ ((SIZE) == DMA_MemoryDataSize_Word)) /** * @} */ /** @defgroup DMA_circular_normal_mode * @{ */ #define DMA_Mode_Normal ((uint32_t)0x00000000) #define DMA_Mode_Circular DMA_CCR_CIRC #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) /** * @} */ /** @defgroup DMA_priority_level * @{ */ #define DMA_Priority_VeryHigh DMA_CCR_PL #define DMA_Priority_High DMA_CCR_PL_1 #define DMA_Priority_Medium DMA_CCR_PL_0 #define DMA_Priority_Low ((uint32_t)0x00000000) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ ((PRIORITY) == DMA_Priority_High) || \ ((PRIORITY) == DMA_Priority_Medium) || \ ((PRIORITY) == DMA_Priority_Low)) /** * @} */ /** @defgroup DMA_memory_to_memory * @{ */ #define DMA_M2M_Disable ((uint32_t)0x00000000) #define DMA_M2M_Enable DMA_CCR_MEM2MEM #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) /** * @} */ /** @defgroup DMA_interrupts_definition * @{ */ #define DMA_IT_TC DMA_CCR_TCIE #define DMA_IT_HT DMA_CCR_HTIE #define DMA_IT_TE DMA_CCR_TEIE #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) #define DMA1_IT_GL1 DMA_ISR_GIF1 #define DMA1_IT_TC1 DMA_ISR_TCIF1 #define DMA1_IT_HT1 DMA_ISR_HTIF1 #define DMA1_IT_TE1 DMA_ISR_TEIF1 #define DMA1_IT_GL2 DMA_ISR_GIF2 #define DMA1_IT_TC2 DMA_ISR_TCIF2 #define DMA1_IT_HT2 DMA_ISR_HTIF2 #define DMA1_IT_TE2 DMA_ISR_TEIF2 #define DMA1_IT_GL3 DMA_ISR_GIF3 #define DMA1_IT_TC3 DMA_ISR_TCIF3 #define DMA1_IT_HT3 DMA_ISR_HTIF3 #define DMA1_IT_TE3 DMA_ISR_TEIF3 #define DMA1_IT_GL4 DMA_ISR_GIF4 #define DMA1_IT_TC4 DMA_ISR_TCIF4 #define DMA1_IT_HT4 DMA_ISR_HTIF4 #define DMA1_IT_TE4 DMA_ISR_TEIF4 #define DMA1_IT_GL5 DMA_ISR_GIF5 #define DMA1_IT_TC5 DMA_ISR_TCIF5 #define DMA1_IT_HT5 DMA_ISR_HTIF5 #define DMA1_IT_TE5 DMA_ISR_TEIF5 #define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */ #define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */ #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00)) #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7)) /** * @} */ /** @defgroup DMA_flags_definition * @{ */ #define DMA1_FLAG_GL1 DMA_ISR_GIF1 #define DMA1_FLAG_TC1 DMA_ISR_TCIF1 #define DMA1_FLAG_HT1 DMA_ISR_HTIF1 #define DMA1_FLAG_TE1 DMA_ISR_TEIF1 #define DMA1_FLAG_GL2 DMA_ISR_GIF2 #define DMA1_FLAG_TC2 DMA_ISR_TCIF2 #define DMA1_FLAG_HT2 DMA_ISR_HTIF2 #define DMA1_FLAG_TE2 DMA_ISR_TEIF2 #define DMA1_FLAG_GL3 DMA_ISR_GIF3 #define DMA1_FLAG_TC3 DMA_ISR_TCIF3 #define DMA1_FLAG_HT3 DMA_ISR_HTIF3 #define DMA1_FLAG_TE3 DMA_ISR_TEIF3 #define DMA1_FLAG_GL4 DMA_ISR_GIF4 #define DMA1_FLAG_TC4 DMA_ISR_TCIF4 #define DMA1_FLAG_HT4 DMA_ISR_HTIF4 #define DMA1_FLAG_TE4 DMA_ISR_TEIF4 #define DMA1_FLAG_GL5 DMA_ISR_GIF5 #define DMA1_FLAG_TC5 DMA_ISR_TCIF5 #define DMA1_FLAG_HT5 DMA_ISR_HTIF5 #define DMA1_FLAG_TE5 DMA_ISR_TEIF5 #define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */ #define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */ #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7)) /** * @} */ /** @defgroup DMA_Buffer_Size * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the DMA configuration to the default reset state ******/ void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); /* Initialization and Configuration functions *********************************/ void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); /* Data Counter functions******************************************************/ void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); /* Interrupts and flags management functions **********************************/ void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); void DMA_ClearFlag(uint32_t DMA_FLAG); ITStatus DMA_GetITStatus(uint32_t DMA_IT); void DMA_ClearITPendingBit(uint32_t DMA_IT); #ifdef __cplusplus } #endif #endif /*__STM32F0XX_DMA_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/