Diff: targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c

Revision:

167:d5744491c362

Parent:

139:e3413eddde57

--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c	Tue Apr 22 16:00:06 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c	Wed Apr 23 11:00:08 2014 +0100
@@ -147,8 +147,6 @@
   * @{
   */
 
-void SetSysClock(void);
-
 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 #endif
@@ -223,15 +221,15 @@
   #endif /* DATA_IN_ExtSRAM */
 #endif 
 
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
+#endif
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
 }
 
 /**
@@ -609,3 +607,4 @@
   */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+