mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/system_stm32f0xx.c@167:d5744491c362, 2014-04-23 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Apr 23 11:00:08 2014 +0100
- Revision:
- 167:d5744491c362
- Parent:
- 166:cb4253f91ada
Synchronized with git revision 6cf73e2e267b625c71cbf586a1d74e7e4972a369
Full URL: https://github.com/mbedmicro/mbed/commit/6cf73e2e267b625c71cbf586a1d74e7e4972a369/
[NUCLEO_F030R8/F302R8] Move back SetSysClock() call in SystemInit()
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 76:aeb1df146756 | 1 | /** |
mbed_official | 76:aeb1df146756 | 2 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 3 | * @file system_stm32f0xx.c |
mbed_official | 76:aeb1df146756 | 4 | * @author MCD Application Team |
mbed_official | 76:aeb1df146756 | 5 | * @version V1.0.1 |
mbed_official | 76:aeb1df146756 | 6 | * @date 12-January-2014 |
mbed_official | 76:aeb1df146756 | 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. |
mbed_official | 76:aeb1df146756 | 8 | * This file contains the system clock configuration for STM32F0xx devices, |
mbed_official | 76:aeb1df146756 | 9 | * and is generated by the clock configuration tool |
mbed_official | 76:aeb1df146756 | 10 | * STM32F0xx_Clock_Configuration_V1.0.1.xls |
mbed_official | 76:aeb1df146756 | 11 | * |
mbed_official | 76:aeb1df146756 | 12 | * 1. This file provides two functions and one global variable to be called from |
mbed_official | 76:aeb1df146756 | 13 | * user application: |
mbed_official | 76:aeb1df146756 | 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
mbed_official | 76:aeb1df146756 | 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), |
mbed_official | 76:aeb1df146756 | 16 | * depending on the configuration made in the clock xls tool. |
mbed_official | 76:aeb1df146756 | 17 | * This function is called at startup just after reset and |
mbed_official | 76:aeb1df146756 | 18 | * before branch to main program. This call is made inside |
mbed_official | 76:aeb1df146756 | 19 | * the "startup_stm32f0xx.s" file. |
mbed_official | 76:aeb1df146756 | 20 | * |
mbed_official | 76:aeb1df146756 | 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 76:aeb1df146756 | 22 | * by the user application to setup the SysTick |
mbed_official | 76:aeb1df146756 | 23 | * timer or configure other parameters. |
mbed_official | 76:aeb1df146756 | 24 | * |
mbed_official | 76:aeb1df146756 | 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 76:aeb1df146756 | 26 | * be called whenever the core clock is changed |
mbed_official | 76:aeb1df146756 | 27 | * during program execution. |
mbed_official | 76:aeb1df146756 | 28 | * |
mbed_official | 76:aeb1df146756 | 29 | * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. |
mbed_official | 76:aeb1df146756 | 30 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to |
mbed_official | 76:aeb1df146756 | 31 | * configure the system clock before to branch to main program. |
mbed_official | 76:aeb1df146756 | 32 | * |
mbed_official | 76:aeb1df146756 | 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() |
mbed_official | 76:aeb1df146756 | 34 | * function will do nothing and HSI still used as system clock source. User can |
mbed_official | 76:aeb1df146756 | 35 | * add some code to deal with this issue inside the SetSysClock() function. |
mbed_official | 76:aeb1df146756 | 36 | * |
mbed_official | 76:aeb1df146756 | 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define |
mbed_official | 76:aeb1df146756 | 38 | * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or |
mbed_official | 76:aeb1df146756 | 39 | * through PLL, and you are using different crystal you have to adapt the HSE |
mbed_official | 76:aeb1df146756 | 40 | * value to your own configuration. |
mbed_official | 76:aeb1df146756 | 41 | * |
mbed_official | 76:aeb1df146756 | 42 | * 5. This file configures the system clock as follows: |
mbed_official | 76:aeb1df146756 | 43 | *----------------------------------------------------------------------------- |
mbed_official | 166:cb4253f91ada | 44 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
mbed_official | 166:cb4253f91ada | 45 | * | (external 8 MHz clock) | (internal 8 MHz) |
mbed_official | 166:cb4253f91ada | 46 | * | 2- PLL_HSE_XTAL | |
mbed_official | 166:cb4253f91ada | 47 | * | (external 8 MHz xtal) | |
mbed_official | 76:aeb1df146756 | 48 | *----------------------------------------------------------------------------- |
mbed_official | 166:cb4253f91ada | 49 | * SYSCLK(MHz) | 48 | 48 |
mbed_official | 76:aeb1df146756 | 50 | *----------------------------------------------------------------------------- |
mbed_official | 166:cb4253f91ada | 51 | * AHBCLK (MHz) | 48 | 48 |
mbed_official | 76:aeb1df146756 | 52 | *----------------------------------------------------------------------------- |
mbed_official | 166:cb4253f91ada | 53 | * APBCLK (MHz) | 48 | 48 |
mbed_official | 76:aeb1df146756 | 54 | *----------------------------------------------------------------------------- |
mbed_official | 76:aeb1df146756 | 55 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 56 | * @attention |
mbed_official | 76:aeb1df146756 | 57 | * |
mbed_official | 106:ced8cbb51063 | 58 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 76:aeb1df146756 | 59 | * |
mbed_official | 106:ced8cbb51063 | 60 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 106:ced8cbb51063 | 61 | * are permitted provided that the following conditions are met: |
mbed_official | 106:ced8cbb51063 | 62 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 106:ced8cbb51063 | 63 | * this list of conditions and the following disclaimer. |
mbed_official | 106:ced8cbb51063 | 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 106:ced8cbb51063 | 65 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 106:ced8cbb51063 | 66 | * and/or other materials provided with the distribution. |
mbed_official | 106:ced8cbb51063 | 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 106:ced8cbb51063 | 68 | * may be used to endorse or promote products derived from this software |
mbed_official | 106:ced8cbb51063 | 69 | * without specific prior written permission. |
mbed_official | 76:aeb1df146756 | 70 | * |
mbed_official | 106:ced8cbb51063 | 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 106:ced8cbb51063 | 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 106:ced8cbb51063 | 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 106:ced8cbb51063 | 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 106:ced8cbb51063 | 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 106:ced8cbb51063 | 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 106:ced8cbb51063 | 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 106:ced8cbb51063 | 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 106:ced8cbb51063 | 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 106:ced8cbb51063 | 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 76:aeb1df146756 | 81 | * |
mbed_official | 76:aeb1df146756 | 82 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 83 | */ |
mbed_official | 76:aeb1df146756 | 84 | |
mbed_official | 76:aeb1df146756 | 85 | /** @addtogroup CMSIS |
mbed_official | 76:aeb1df146756 | 86 | * @{ |
mbed_official | 76:aeb1df146756 | 87 | */ |
mbed_official | 76:aeb1df146756 | 88 | |
mbed_official | 76:aeb1df146756 | 89 | /** @addtogroup stm32f0xx_system |
mbed_official | 76:aeb1df146756 | 90 | * @{ |
mbed_official | 76:aeb1df146756 | 91 | */ |
mbed_official | 76:aeb1df146756 | 92 | |
mbed_official | 76:aeb1df146756 | 93 | /** @addtogroup STM32F0xx_System_Private_Includes |
mbed_official | 76:aeb1df146756 | 94 | * @{ |
mbed_official | 76:aeb1df146756 | 95 | */ |
mbed_official | 76:aeb1df146756 | 96 | |
mbed_official | 76:aeb1df146756 | 97 | #include "stm32f0xx.h" |
mbed_official | 76:aeb1df146756 | 98 | |
mbed_official | 76:aeb1df146756 | 99 | /** |
mbed_official | 76:aeb1df146756 | 100 | * @} |
mbed_official | 76:aeb1df146756 | 101 | */ |
mbed_official | 76:aeb1df146756 | 102 | |
mbed_official | 76:aeb1df146756 | 103 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions |
mbed_official | 76:aeb1df146756 | 104 | * @{ |
mbed_official | 76:aeb1df146756 | 105 | */ |
mbed_official | 76:aeb1df146756 | 106 | |
mbed_official | 76:aeb1df146756 | 107 | /** |
mbed_official | 76:aeb1df146756 | 108 | * @} |
mbed_official | 76:aeb1df146756 | 109 | */ |
mbed_official | 76:aeb1df146756 | 110 | |
mbed_official | 76:aeb1df146756 | 111 | /** @addtogroup STM32F0xx_System_Private_Defines |
mbed_official | 76:aeb1df146756 | 112 | * @{ |
mbed_official | 76:aeb1df146756 | 113 | */ |
mbed_official | 76:aeb1df146756 | 114 | /** |
mbed_official | 76:aeb1df146756 | 115 | * @} |
mbed_official | 76:aeb1df146756 | 116 | */ |
mbed_official | 76:aeb1df146756 | 117 | |
mbed_official | 76:aeb1df146756 | 118 | /** @addtogroup STM32F0xx_System_Private_Macros |
mbed_official | 76:aeb1df146756 | 119 | * @{ |
mbed_official | 76:aeb1df146756 | 120 | */ |
mbed_official | 76:aeb1df146756 | 121 | |
mbed_official | 166:cb4253f91ada | 122 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
mbed_official | 166:cb4253f91ada | 123 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
mbed_official | 166:cb4253f91ada | 124 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
mbed_official | 166:cb4253f91ada | 125 | |
mbed_official | 76:aeb1df146756 | 126 | /** |
mbed_official | 76:aeb1df146756 | 127 | * @} |
mbed_official | 76:aeb1df146756 | 128 | */ |
mbed_official | 76:aeb1df146756 | 129 | |
mbed_official | 76:aeb1df146756 | 130 | /** @addtogroup STM32F0xx_System_Private_Variables |
mbed_official | 76:aeb1df146756 | 131 | * @{ |
mbed_official | 76:aeb1df146756 | 132 | */ |
mbed_official | 166:cb4253f91ada | 133 | |
mbed_official | 166:cb4253f91ada | 134 | uint32_t SystemCoreClock = 48000000; |
mbed_official | 76:aeb1df146756 | 135 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 76:aeb1df146756 | 136 | |
mbed_official | 76:aeb1df146756 | 137 | /** |
mbed_official | 76:aeb1df146756 | 138 | * @} |
mbed_official | 76:aeb1df146756 | 139 | */ |
mbed_official | 76:aeb1df146756 | 140 | |
mbed_official | 76:aeb1df146756 | 141 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes |
mbed_official | 76:aeb1df146756 | 142 | * @{ |
mbed_official | 76:aeb1df146756 | 143 | */ |
mbed_official | 76:aeb1df146756 | 144 | |
mbed_official | 166:cb4253f91ada | 145 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 166:cb4253f91ada | 146 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
mbed_official | 166:cb4253f91ada | 147 | #endif |
mbed_official | 166:cb4253f91ada | 148 | |
mbed_official | 166:cb4253f91ada | 149 | uint8_t SetSysClock_PLL_HSI(void); |
mbed_official | 76:aeb1df146756 | 150 | |
mbed_official | 76:aeb1df146756 | 151 | /** |
mbed_official | 76:aeb1df146756 | 152 | * @} |
mbed_official | 76:aeb1df146756 | 153 | */ |
mbed_official | 76:aeb1df146756 | 154 | |
mbed_official | 76:aeb1df146756 | 155 | /** @addtogroup STM32F0xx_System_Private_Functions |
mbed_official | 76:aeb1df146756 | 156 | * @{ |
mbed_official | 76:aeb1df146756 | 157 | */ |
mbed_official | 76:aeb1df146756 | 158 | |
mbed_official | 76:aeb1df146756 | 159 | /** |
mbed_official | 76:aeb1df146756 | 160 | * @brief Setup the microcontroller system. |
mbed_official | 76:aeb1df146756 | 161 | * Initialize the Embedded Flash Interface, the PLL and update the |
mbed_official | 76:aeb1df146756 | 162 | * SystemCoreClock variable. |
mbed_official | 76:aeb1df146756 | 163 | * @param None |
mbed_official | 76:aeb1df146756 | 164 | * @retval None |
mbed_official | 76:aeb1df146756 | 165 | */ |
mbed_official | 76:aeb1df146756 | 166 | void SystemInit (void) |
mbed_official | 76:aeb1df146756 | 167 | { |
mbed_official | 76:aeb1df146756 | 168 | /* Set HSION bit */ |
mbed_official | 76:aeb1df146756 | 169 | RCC->CR |= (uint32_t)0x00000001; |
mbed_official | 76:aeb1df146756 | 170 | |
mbed_official | 76:aeb1df146756 | 171 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ |
mbed_official | 76:aeb1df146756 | 172 | RCC->CFGR &= (uint32_t)0xF8FFB80C; |
mbed_official | 76:aeb1df146756 | 173 | |
mbed_official | 76:aeb1df146756 | 174 | /* Reset HSEON, CSSON and PLLON bits */ |
mbed_official | 76:aeb1df146756 | 175 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
mbed_official | 76:aeb1df146756 | 176 | |
mbed_official | 76:aeb1df146756 | 177 | /* Reset HSEBYP bit */ |
mbed_official | 76:aeb1df146756 | 178 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 76:aeb1df146756 | 179 | |
mbed_official | 76:aeb1df146756 | 180 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
mbed_official | 76:aeb1df146756 | 181 | RCC->CFGR &= (uint32_t)0xFFC0FFFF; |
mbed_official | 76:aeb1df146756 | 182 | |
mbed_official | 76:aeb1df146756 | 183 | /* Reset PREDIV1[3:0] bits */ |
mbed_official | 76:aeb1df146756 | 184 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; |
mbed_official | 76:aeb1df146756 | 185 | |
mbed_official | 76:aeb1df146756 | 186 | /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ |
mbed_official | 76:aeb1df146756 | 187 | RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; |
mbed_official | 76:aeb1df146756 | 188 | |
mbed_official | 76:aeb1df146756 | 189 | /* Reset HSI14 bit */ |
mbed_official | 76:aeb1df146756 | 190 | RCC->CR2 &= (uint32_t)0xFFFFFFFE; |
mbed_official | 76:aeb1df146756 | 191 | |
mbed_official | 76:aeb1df146756 | 192 | /* Disable all interrupts */ |
mbed_official | 76:aeb1df146756 | 193 | RCC->CIR = 0x00000000; |
mbed_official | 167:d5744491c362 | 194 | |
mbed_official | 167:d5744491c362 | 195 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 167:d5744491c362 | 196 | AHB/APBx prescalers and Flash settings */ |
mbed_official | 167:d5744491c362 | 197 | SetSysClock(); |
mbed_official | 76:aeb1df146756 | 198 | } |
mbed_official | 76:aeb1df146756 | 199 | |
mbed_official | 76:aeb1df146756 | 200 | /** |
mbed_official | 76:aeb1df146756 | 201 | * @brief Update SystemCoreClock according to Clock Register Values |
mbed_official | 76:aeb1df146756 | 202 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 76:aeb1df146756 | 203 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 76:aeb1df146756 | 204 | * other parameters. |
mbed_official | 76:aeb1df146756 | 205 | * |
mbed_official | 76:aeb1df146756 | 206 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 76:aeb1df146756 | 207 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 76:aeb1df146756 | 208 | * based on this variable will be incorrect. |
mbed_official | 76:aeb1df146756 | 209 | * |
mbed_official | 76:aeb1df146756 | 210 | * @note - The system frequency computed by this function is not the real |
mbed_official | 76:aeb1df146756 | 211 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 76:aeb1df146756 | 212 | * constant and the selected clock source: |
mbed_official | 76:aeb1df146756 | 213 | * |
mbed_official | 76:aeb1df146756 | 214 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 76:aeb1df146756 | 215 | * |
mbed_official | 76:aeb1df146756 | 216 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 76:aeb1df146756 | 217 | * |
mbed_official | 76:aeb1df146756 | 218 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 76:aeb1df146756 | 219 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 76:aeb1df146756 | 220 | * |
mbed_official | 76:aeb1df146756 | 221 | * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value |
mbed_official | 76:aeb1df146756 | 222 | * 8 MHz) but the real value may vary depending on the variations |
mbed_official | 76:aeb1df146756 | 223 | * in voltage and temperature. |
mbed_official | 76:aeb1df146756 | 224 | * |
mbed_official | 76:aeb1df146756 | 225 | * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value |
mbed_official | 76:aeb1df146756 | 226 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 76:aeb1df146756 | 227 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 76:aeb1df146756 | 228 | * have wrong result. |
mbed_official | 76:aeb1df146756 | 229 | * |
mbed_official | 76:aeb1df146756 | 230 | * - The result of this function could be not correct when using fractional |
mbed_official | 76:aeb1df146756 | 231 | * value for HSE crystal. |
mbed_official | 76:aeb1df146756 | 232 | * @param None |
mbed_official | 76:aeb1df146756 | 233 | * @retval None |
mbed_official | 76:aeb1df146756 | 234 | */ |
mbed_official | 76:aeb1df146756 | 235 | void SystemCoreClockUpdate (void) |
mbed_official | 76:aeb1df146756 | 236 | { |
mbed_official | 76:aeb1df146756 | 237 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; |
mbed_official | 76:aeb1df146756 | 238 | |
mbed_official | 76:aeb1df146756 | 239 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 240 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 76:aeb1df146756 | 241 | |
mbed_official | 76:aeb1df146756 | 242 | switch (tmp) |
mbed_official | 76:aeb1df146756 | 243 | { |
mbed_official | 76:aeb1df146756 | 244 | case 0x00: /* HSI used as system clock */ |
mbed_official | 76:aeb1df146756 | 245 | SystemCoreClock = HSI_VALUE; |
mbed_official | 76:aeb1df146756 | 246 | break; |
mbed_official | 76:aeb1df146756 | 247 | case 0x04: /* HSE used as system clock */ |
mbed_official | 76:aeb1df146756 | 248 | SystemCoreClock = HSE_VALUE; |
mbed_official | 76:aeb1df146756 | 249 | break; |
mbed_official | 76:aeb1df146756 | 250 | case 0x08: /* PLL used as system clock */ |
mbed_official | 76:aeb1df146756 | 251 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 76:aeb1df146756 | 252 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
mbed_official | 76:aeb1df146756 | 253 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 76:aeb1df146756 | 254 | pllmull = ( pllmull >> 18) + 2; |
mbed_official | 76:aeb1df146756 | 255 | |
mbed_official | 76:aeb1df146756 | 256 | if (pllsource == 0x00) |
mbed_official | 76:aeb1df146756 | 257 | { |
mbed_official | 76:aeb1df146756 | 258 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
mbed_official | 76:aeb1df146756 | 259 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
mbed_official | 76:aeb1df146756 | 260 | } |
mbed_official | 76:aeb1df146756 | 261 | else |
mbed_official | 76:aeb1df146756 | 262 | { |
mbed_official | 76:aeb1df146756 | 263 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
mbed_official | 76:aeb1df146756 | 264 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
mbed_official | 76:aeb1df146756 | 265 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
mbed_official | 76:aeb1df146756 | 266 | } |
mbed_official | 76:aeb1df146756 | 267 | break; |
mbed_official | 76:aeb1df146756 | 268 | default: /* HSI used as system clock */ |
mbed_official | 76:aeb1df146756 | 269 | SystemCoreClock = HSI_VALUE; |
mbed_official | 76:aeb1df146756 | 270 | break; |
mbed_official | 76:aeb1df146756 | 271 | } |
mbed_official | 76:aeb1df146756 | 272 | /* Compute HCLK clock frequency ----------------*/ |
mbed_official | 76:aeb1df146756 | 273 | /* Get HCLK prescaler */ |
mbed_official | 76:aeb1df146756 | 274 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 76:aeb1df146756 | 275 | /* HCLK clock frequency */ |
mbed_official | 76:aeb1df146756 | 276 | SystemCoreClock >>= tmp; |
mbed_official | 76:aeb1df146756 | 277 | } |
mbed_official | 76:aeb1df146756 | 278 | |
mbed_official | 76:aeb1df146756 | 279 | /** |
mbed_official | 166:cb4253f91ada | 280 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. |
mbed_official | 76:aeb1df146756 | 281 | * @param None |
mbed_official | 76:aeb1df146756 | 282 | * @retval None |
mbed_official | 76:aeb1df146756 | 283 | */ |
mbed_official | 166:cb4253f91ada | 284 | void SetSysClock(void) |
mbed_official | 76:aeb1df146756 | 285 | { |
mbed_official | 166:cb4253f91ada | 286 | /* 1- Try to start with HSE and external clock */ |
mbed_official | 166:cb4253f91ada | 287 | #if USE_PLL_HSE_EXTC != 0 |
mbed_official | 166:cb4253f91ada | 288 | if (SetSysClock_PLL_HSE(1) == 0) |
mbed_official | 166:cb4253f91ada | 289 | #endif |
mbed_official | 166:cb4253f91ada | 290 | { |
mbed_official | 166:cb4253f91ada | 291 | /* 2- If fail try to start with HSE and external xtal */ |
mbed_official | 166:cb4253f91ada | 292 | #if USE_PLL_HSE_XTAL != 0 |
mbed_official | 166:cb4253f91ada | 293 | if (SetSysClock_PLL_HSE(0) == 0) |
mbed_official | 166:cb4253f91ada | 294 | #endif |
mbed_official | 166:cb4253f91ada | 295 | { |
mbed_official | 166:cb4253f91ada | 296 | /* 3- If fail start with HSI clock */ |
mbed_official | 166:cb4253f91ada | 297 | if (SetSysClock_PLL_HSI() == 0) |
mbed_official | 166:cb4253f91ada | 298 | { |
mbed_official | 166:cb4253f91ada | 299 | while(1) |
mbed_official | 166:cb4253f91ada | 300 | { |
mbed_official | 166:cb4253f91ada | 301 | // [TODO] Put something here to tell the user that a problem occured... |
mbed_official | 166:cb4253f91ada | 302 | } |
mbed_official | 166:cb4253f91ada | 303 | } |
mbed_official | 166:cb4253f91ada | 304 | } |
mbed_official | 166:cb4253f91ada | 305 | } |
mbed_official | 166:cb4253f91ada | 306 | |
mbed_official | 166:cb4253f91ada | 307 | // Output clock on MCO pin (PA8) for debugging purpose |
mbed_official | 166:cb4253f91ada | 308 | /* |
mbed_official | 166:cb4253f91ada | 309 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); |
mbed_official | 166:cb4253f91ada | 310 | GPIO_InitTypeDef GPIO_InitStructure; |
mbed_official | 166:cb4253f91ada | 311 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
mbed_official | 166:cb4253f91ada | 312 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
mbed_official | 166:cb4253f91ada | 313 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
mbed_official | 166:cb4253f91ada | 314 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; |
mbed_official | 166:cb4253f91ada | 315 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; |
mbed_official | 166:cb4253f91ada | 316 | GPIO_Init(GPIOA, &GPIO_InitStructure); |
mbed_official | 166:cb4253f91ada | 317 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_0); |
mbed_official | 166:cb4253f91ada | 318 | // Output clock on MCO pin |
mbed_official | 166:cb4253f91ada | 319 | // Warning: only RCC_MCOPrescaler_1 is available on STM32F030x8 devices |
mbed_official | 166:cb4253f91ada | 320 | RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1); |
mbed_official | 166:cb4253f91ada | 321 | */ |
mbed_official | 166:cb4253f91ada | 322 | } |
mbed_official | 166:cb4253f91ada | 323 | |
mbed_official | 166:cb4253f91ada | 324 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 76:aeb1df146756 | 325 | /******************************************************************************/ |
mbed_official | 166:cb4253f91ada | 326 | /* PLL (clocked by HSE) used as System clock source */ |
mbed_official | 76:aeb1df146756 | 327 | /******************************************************************************/ |
mbed_official | 166:cb4253f91ada | 328 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
mbed_official | 166:cb4253f91ada | 329 | { |
mbed_official | 166:cb4253f91ada | 330 | __IO uint32_t StartUpCounter = 0; |
mbed_official | 166:cb4253f91ada | 331 | __IO uint32_t HSEStatus = 0; |
mbed_official | 76:aeb1df146756 | 332 | |
mbed_official | 166:cb4253f91ada | 333 | /* Bypass HSE: can be done only if HSE is OFF */ |
mbed_official | 166:cb4253f91ada | 334 | RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */ |
mbed_official | 166:cb4253f91ada | 335 | if (bypass != 0) |
mbed_official | 166:cb4253f91ada | 336 | { |
mbed_official | 166:cb4253f91ada | 337 | RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); |
mbed_official | 166:cb4253f91ada | 338 | } |
mbed_official | 166:cb4253f91ada | 339 | else |
mbed_official | 166:cb4253f91ada | 340 | { |
mbed_official | 166:cb4253f91ada | 341 | RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP); |
mbed_official | 166:cb4253f91ada | 342 | } |
mbed_official | 166:cb4253f91ada | 343 | |
mbed_official | 166:cb4253f91ada | 344 | /* Enable HSE */ |
mbed_official | 166:cb4253f91ada | 345 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
mbed_official | 166:cb4253f91ada | 346 | |
mbed_official | 166:cb4253f91ada | 347 | /* Wait till HSE is ready */ |
mbed_official | 166:cb4253f91ada | 348 | do |
mbed_official | 166:cb4253f91ada | 349 | { |
mbed_official | 166:cb4253f91ada | 350 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
mbed_official | 166:cb4253f91ada | 351 | StartUpCounter++; |
mbed_official | 166:cb4253f91ada | 352 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
mbed_official | 76:aeb1df146756 | 353 | |
mbed_official | 166:cb4253f91ada | 354 | /* Check if HSE has started correctly */ |
mbed_official | 166:cb4253f91ada | 355 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
mbed_official | 166:cb4253f91ada | 356 | { |
mbed_official | 166:cb4253f91ada | 357 | /* Enable Prefetch Buffer */ |
mbed_official | 166:cb4253f91ada | 358 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
mbed_official | 166:cb4253f91ada | 359 | |
mbed_official | 166:cb4253f91ada | 360 | /* Enable Prefetch Buffer and set Flash Latency */ |
mbed_official | 166:cb4253f91ada | 361 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; |
mbed_official | 166:cb4253f91ada | 362 | |
mbed_official | 166:cb4253f91ada | 363 | /* PLL configuration |
mbed_official | 166:cb4253f91ada | 364 | PLLCLK = 48 MHz (xtal 8 MHz * 6) */ |
mbed_official | 166:cb4253f91ada | 365 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
mbed_official | 166:cb4253f91ada | 366 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6 |
mbed_official | 166:cb4253f91ada | 367 | | RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */ |
mbed_official | 166:cb4253f91ada | 368 | | RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */ |
mbed_official | 166:cb4253f91ada | 369 | |
mbed_official | 166:cb4253f91ada | 370 | /* Enable PLL */ |
mbed_official | 166:cb4253f91ada | 371 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 166:cb4253f91ada | 372 | |
mbed_official | 166:cb4253f91ada | 373 | /* Wait till PLL is ready */ |
mbed_official | 166:cb4253f91ada | 374 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 166:cb4253f91ada | 375 | { |
mbed_official | 166:cb4253f91ada | 376 | } |
mbed_official | 166:cb4253f91ada | 377 | |
mbed_official | 166:cb4253f91ada | 378 | /* Select PLL as system clock source */ |
mbed_official | 166:cb4253f91ada | 379 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 166:cb4253f91ada | 380 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 166:cb4253f91ada | 381 | |
mbed_official | 166:cb4253f91ada | 382 | /* Wait till PLL is used as system clock source */ |
mbed_official | 166:cb4253f91ada | 383 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 166:cb4253f91ada | 384 | { |
mbed_official | 166:cb4253f91ada | 385 | } |
mbed_official | 76:aeb1df146756 | 386 | |
mbed_official | 166:cb4253f91ada | 387 | return 1; // OK |
mbed_official | 166:cb4253f91ada | 388 | } |
mbed_official | 166:cb4253f91ada | 389 | else |
mbed_official | 166:cb4253f91ada | 390 | { |
mbed_official | 166:cb4253f91ada | 391 | return 0; // FAIL |
mbed_official | 166:cb4253f91ada | 392 | } |
mbed_official | 166:cb4253f91ada | 393 | } |
mbed_official | 166:cb4253f91ada | 394 | #endif |
mbed_official | 166:cb4253f91ada | 395 | |
mbed_official | 166:cb4253f91ada | 396 | /******************************************************************************/ |
mbed_official | 166:cb4253f91ada | 397 | /* PLL (clocked by HSI) used as System clock source */ |
mbed_official | 166:cb4253f91ada | 398 | /******************************************************************************/ |
mbed_official | 166:cb4253f91ada | 399 | uint8_t SetSysClock_PLL_HSI(void) |
mbed_official | 166:cb4253f91ada | 400 | { |
mbed_official | 166:cb4253f91ada | 401 | /* Enable Prefetch Buffer and set Flash Latency */ |
mbed_official | 166:cb4253f91ada | 402 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; |
mbed_official | 76:aeb1df146756 | 403 | |
mbed_official | 166:cb4253f91ada | 404 | /* PLL configuration |
mbed_official | 166:cb4253f91ada | 405 | PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) */ |
mbed_official | 166:cb4253f91ada | 406 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
mbed_official | 166:cb4253f91ada | 407 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12 |
mbed_official | 166:cb4253f91ada | 408 | | RCC_CFGR_HPRE_DIV1 /* HCLK = 48 MHz */ |
mbed_official | 166:cb4253f91ada | 409 | | RCC_CFGR_PPRE_DIV1); /* PCLK = 48 MHz */ |
mbed_official | 166:cb4253f91ada | 410 | |
mbed_official | 166:cb4253f91ada | 411 | /* Enable PLL */ |
mbed_official | 166:cb4253f91ada | 412 | RCC->CR |= RCC_CR_PLLON; |
mbed_official | 76:aeb1df146756 | 413 | |
mbed_official | 166:cb4253f91ada | 414 | /* Wait till PLL is ready */ |
mbed_official | 166:cb4253f91ada | 415 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
mbed_official | 166:cb4253f91ada | 416 | { |
mbed_official | 166:cb4253f91ada | 417 | } |
mbed_official | 166:cb4253f91ada | 418 | |
mbed_official | 166:cb4253f91ada | 419 | /* Select PLL as system clock source */ |
mbed_official | 166:cb4253f91ada | 420 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
mbed_official | 166:cb4253f91ada | 421 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
mbed_official | 166:cb4253f91ada | 422 | |
mbed_official | 166:cb4253f91ada | 423 | /* Wait till PLL is used as system clock source */ |
mbed_official | 166:cb4253f91ada | 424 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
mbed_official | 166:cb4253f91ada | 425 | { |
mbed_official | 166:cb4253f91ada | 426 | } |
mbed_official | 166:cb4253f91ada | 427 | |
mbed_official | 166:cb4253f91ada | 428 | return 1; // OK |
mbed_official | 76:aeb1df146756 | 429 | } |
mbed_official | 76:aeb1df146756 | 430 | |
mbed_official | 76:aeb1df146756 | 431 | /** |
mbed_official | 76:aeb1df146756 | 432 | * @} |
mbed_official | 76:aeb1df146756 | 433 | */ |
mbed_official | 76:aeb1df146756 | 434 | |
mbed_official | 76:aeb1df146756 | 435 | /** |
mbed_official | 76:aeb1df146756 | 436 | * @} |
mbed_official | 76:aeb1df146756 | 437 | */ |
mbed_official | 76:aeb1df146756 | 438 | |
mbed_official | 76:aeb1df146756 | 439 | /** |
mbed_official | 76:aeb1df146756 | 440 | * @} |
mbed_official | 76:aeb1df146756 | 441 | */ |
mbed_official | 76:aeb1df146756 | 442 | |
mbed_official | 76:aeb1df146756 | 443 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
mbed_official | 76:aeb1df146756 | 444 |