mbed-src-openwear - mbed library sources modified for open wear

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mbed library sources modified for open wear

Dependents: openwear-lifelogger-example

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.h@133:d4dda5c437f0, 2014-03-24 (annotated)

Committer:: mbed_official
Date:: Mon Mar 24 17:45:07 2014 +0000
Revision:: 133:d4dda5c437f0
Child:: 242:7074e42da0b2

Synchronized with git revision 47b961246bed973fe4cb8932781ffc8025b78a61



Full URL: https://github.com/mbedmicro/mbed/commit/47b961246bed973fe4cb8932781ffc8025b78a61/



[STM32F4-Discovery (STM32F407VG)] initial port

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_ll_fmc.h
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	133:d4dda5c437f0	5	* @version V1.0.0
mbed_official	133:d4dda5c437f0	6	* @date 18-February-2014
mbed_official	133:d4dda5c437f0	7	* @brief Header file of FMC HAL module.
mbed_official	133:d4dda5c437f0	8	******************************************************************************
mbed_official	133:d4dda5c437f0	9	* @attention
mbed_official	133:d4dda5c437f0	10	*
mbed_official	133:d4dda5c437f0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	12	*
mbed_official	133:d4dda5c437f0	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	14	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	16	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	19	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	21	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	22	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	23	*
mbed_official	133:d4dda5c437f0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	34	*
mbed_official	133:d4dda5c437f0	35	******************************************************************************
mbed_official	133:d4dda5c437f0	36	*/
mbed_official	133:d4dda5c437f0	37
mbed_official	133:d4dda5c437f0	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	133:d4dda5c437f0	39	#ifndef __STM32F4xx_LL_FMC_H
mbed_official	133:d4dda5c437f0	40	#define __STM32F4xx_LL_FMC_H
mbed_official	133:d4dda5c437f0	41
mbed_official	133:d4dda5c437f0	42	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	43	extern "C" {
mbed_official	133:d4dda5c437f0	44	#endif
mbed_official	133:d4dda5c437f0	45
mbed_official	133:d4dda5c437f0	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	47
mbed_official	133:d4dda5c437f0	48	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	49	#include "stm32f4xx_hal_def.h"
mbed_official	133:d4dda5c437f0	50
mbed_official	133:d4dda5c437f0	51	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	133:d4dda5c437f0	52	* @{
mbed_official	133:d4dda5c437f0	53	*/
mbed_official	133:d4dda5c437f0	54
mbed_official	133:d4dda5c437f0	55	/** @addtogroup FMC
mbed_official	133:d4dda5c437f0	56	* @{
mbed_official	133:d4dda5c437f0	57	*/
mbed_official	133:d4dda5c437f0	58
mbed_official	133:d4dda5c437f0	59	/* Exported typedef ----------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official	133:d4dda5c437f0	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official	133:d4dda5c437f0	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
mbed_official	133:d4dda5c437f0	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official	133:d4dda5c437f0	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
mbed_official	133:d4dda5c437f0	65
mbed_official	133:d4dda5c437f0	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official	133:d4dda5c437f0	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official	133:d4dda5c437f0	68	#define FMC_NAND_DEVICE FMC_Bank2_3
mbed_official	133:d4dda5c437f0	69	#define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official	133:d4dda5c437f0	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
mbed_official	133:d4dda5c437f0	71
mbed_official	133:d4dda5c437f0	72
mbed_official	133:d4dda5c437f0	73	/**
mbed_official	133:d4dda5c437f0	74	* @brief FMC_NORSRAM Configuration Structure definition
mbed_official	133:d4dda5c437f0	75	*/
mbed_official	133:d4dda5c437f0	76	typedef struct
mbed_official	133:d4dda5c437f0	77	{
mbed_official	133:d4dda5c437f0	78	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	133:d4dda5c437f0	79	This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official	133:d4dda5c437f0	80
mbed_official	133:d4dda5c437f0	81	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	133:d4dda5c437f0	82	multiplexed on the data bus or not.
mbed_official	133:d4dda5c437f0	83	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official	133:d4dda5c437f0	84
mbed_official	133:d4dda5c437f0	85	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	133:d4dda5c437f0	86	the corresponding memory device.
mbed_official	133:d4dda5c437f0	87	This parameter can be a value of @ref FMC_Memory_Type */
mbed_official	133:d4dda5c437f0	88
mbed_official	133:d4dda5c437f0	89	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	133:d4dda5c437f0	90	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official	133:d4dda5c437f0	91
mbed_official	133:d4dda5c437f0	92	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	133:d4dda5c437f0	93	valid only with synchronous burst Flash memories.
mbed_official	133:d4dda5c437f0	94	This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official	133:d4dda5c437f0	95
mbed_official	133:d4dda5c437f0	96	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	133:d4dda5c437f0	97	the Flash memory in burst mode.
mbed_official	133:d4dda5c437f0	98	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official	133:d4dda5c437f0	99
mbed_official	133:d4dda5c437f0	100	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	133:d4dda5c437f0	101	memory, valid only when accessing Flash memories in burst mode.
mbed_official	133:d4dda5c437f0	102	This parameter can be a value of @ref FMC_Wrap_Mode */
mbed_official	133:d4dda5c437f0	103
mbed_official	133:d4dda5c437f0	104	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	133:d4dda5c437f0	105	clock cycle before the wait state or during the wait state,
mbed_official	133:d4dda5c437f0	106	valid only when accessing memories in burst mode.
mbed_official	133:d4dda5c437f0	107	This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official	133:d4dda5c437f0	108
mbed_official	133:d4dda5c437f0	109	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official	133:d4dda5c437f0	110	This parameter can be a value of @ref FMC_Write_Operation */
mbed_official	133:d4dda5c437f0	111
mbed_official	133:d4dda5c437f0	112	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	133:d4dda5c437f0	113	signal, valid for Flash memory access in burst mode.
mbed_official	133:d4dda5c437f0	114	This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official	133:d4dda5c437f0	115
mbed_official	133:d4dda5c437f0	116	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	133:d4dda5c437f0	117	This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official	133:d4dda5c437f0	118
mbed_official	133:d4dda5c437f0	119	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	133:d4dda5c437f0	120	valid only with asynchronous Flash memories.
mbed_official	133:d4dda5c437f0	121	This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official	133:d4dda5c437f0	122
mbed_official	133:d4dda5c437f0	123	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	133:d4dda5c437f0	124	This parameter can be a value of @ref FMC_Write_Burst */
mbed_official	133:d4dda5c437f0	125
mbed_official	133:d4dda5c437f0	126	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official	133:d4dda5c437f0	127	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	133:d4dda5c437f0	128	through FMC_BCR2..4 registers.
mbed_official	133:d4dda5c437f0	129	This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official	133:d4dda5c437f0	130
mbed_official	133:d4dda5c437f0	131	}FMC_NORSRAM_InitTypeDef;
mbed_official	133:d4dda5c437f0	132
mbed_official	133:d4dda5c437f0	133	/**
mbed_official	133:d4dda5c437f0	134	* @brief FMC_NORSRAM Timing parameters structure definition
mbed_official	133:d4dda5c437f0	135	*/
mbed_official	133:d4dda5c437f0	136	typedef struct
mbed_official	133:d4dda5c437f0	137	{
mbed_official	133:d4dda5c437f0	138	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	133:d4dda5c437f0	139	the duration of the address setup time.
mbed_official	133:d4dda5c437f0	140	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	141	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	133:d4dda5c437f0	142
mbed_official	133:d4dda5c437f0	143	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	133:d4dda5c437f0	144	the duration of the address hold time.
mbed_official	133:d4dda5c437f0	145	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	146	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	133:d4dda5c437f0	147
mbed_official	133:d4dda5c437f0	148	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	133:d4dda5c437f0	149	the duration of the data setup time.
mbed_official	133:d4dda5c437f0	150	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	133:d4dda5c437f0	151	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	133:d4dda5c437f0	152	NOR Flash memories. */
mbed_official	133:d4dda5c437f0	153
mbed_official	133:d4dda5c437f0	154	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	133:d4dda5c437f0	155	the duration of the bus turnaround.
mbed_official	133:d4dda5c437f0	156	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	157	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	133:d4dda5c437f0	158
mbed_official	133:d4dda5c437f0	159	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	133:d4dda5c437f0	160	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	133:d4dda5c437f0	161	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	133:d4dda5c437f0	162	accesses. */
mbed_official	133:d4dda5c437f0	163
mbed_official	133:d4dda5c437f0	164	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	133:d4dda5c437f0	165	to the memory before getting the first data.
mbed_official	133:d4dda5c437f0	166	The parameter value depends on the memory type as shown below:
mbed_official	133:d4dda5c437f0	167	- It must be set to 0 in case of a CRAM
mbed_official	133:d4dda5c437f0	168	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	133:d4dda5c437f0	169	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	133:d4dda5c437f0	170	with synchronous burst mode enable */
mbed_official	133:d4dda5c437f0	171
mbed_official	133:d4dda5c437f0	172	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	133:d4dda5c437f0	173	This parameter can be a value of @ref FMC_Access_Mode */
mbed_official	133:d4dda5c437f0	174
mbed_official	133:d4dda5c437f0	175	}FMC_NORSRAM_TimingTypeDef;
mbed_official	133:d4dda5c437f0	176
mbed_official	133:d4dda5c437f0	177	/**
mbed_official	133:d4dda5c437f0	178	* @brief FMC_NAND Configuration Structure definition
mbed_official	133:d4dda5c437f0	179	*/
mbed_official	133:d4dda5c437f0	180	typedef struct
mbed_official	133:d4dda5c437f0	181	{
mbed_official	133:d4dda5c437f0	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	133:d4dda5c437f0	183	This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official	133:d4dda5c437f0	184
mbed_official	133:d4dda5c437f0	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	133:d4dda5c437f0	186	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	133:d4dda5c437f0	187
mbed_official	133:d4dda5c437f0	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	133:d4dda5c437f0	189	This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official	133:d4dda5c437f0	190
mbed_official	133:d4dda5c437f0	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	133:d4dda5c437f0	192	This parameter can be any value of @ref FMC_ECC */
mbed_official	133:d4dda5c437f0	193
mbed_official	133:d4dda5c437f0	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	133:d4dda5c437f0	195	This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official	133:d4dda5c437f0	196
mbed_official	133:d4dda5c437f0	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	133:d4dda5c437f0	198	delay between CLE low and RE low.
mbed_official	133:d4dda5c437f0	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	200
mbed_official	133:d4dda5c437f0	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	133:d4dda5c437f0	202	delay between ALE low and RE low.
mbed_official	133:d4dda5c437f0	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	204
mbed_official	133:d4dda5c437f0	205	}FMC_NAND_InitTypeDef;
mbed_official	133:d4dda5c437f0	206
mbed_official	133:d4dda5c437f0	207	/**
mbed_official	133:d4dda5c437f0	208	* @brief FMC_NAND_PCCARD Timing parameters structure definition
mbed_official	133:d4dda5c437f0	209	*/
mbed_official	133:d4dda5c437f0	210	typedef struct
mbed_official	133:d4dda5c437f0	211	{
mbed_official	133:d4dda5c437f0	212	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	133:d4dda5c437f0	213	the command assertion for NAND-Flash read or write access
mbed_official	133:d4dda5c437f0	214	to common/Attribute or I/O memory space (depending on
mbed_official	133:d4dda5c437f0	215	the memory space timing to be configured).
mbed_official	133:d4dda5c437f0	216	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	217
mbed_official	133:d4dda5c437f0	218	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	133:d4dda5c437f0	219	command for NAND-Flash read or write access to
mbed_official	133:d4dda5c437f0	220	common/Attribute or I/O memory space (depending on the
mbed_official	133:d4dda5c437f0	221	memory space timing to be configured).
mbed_official	133:d4dda5c437f0	222	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	223
mbed_official	133:d4dda5c437f0	224	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	133:d4dda5c437f0	225	(and data for write access) after the command de-assertion
mbed_official	133:d4dda5c437f0	226	for NAND-Flash read or write access to common/Attribute
mbed_official	133:d4dda5c437f0	227	or I/O memory space (depending on the memory space timing
mbed_official	133:d4dda5c437f0	228	to be configured).
mbed_official	133:d4dda5c437f0	229	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	230
mbed_official	133:d4dda5c437f0	231	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	133:d4dda5c437f0	232	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	133:d4dda5c437f0	233	write access to common/Attribute or I/O memory space (depending
mbed_official	133:d4dda5c437f0	234	on the memory space timing to be configured).
mbed_official	133:d4dda5c437f0	235	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	236
mbed_official	133:d4dda5c437f0	237	}FMC_NAND_PCC_TimingTypeDef;
mbed_official	133:d4dda5c437f0	238
mbed_official	133:d4dda5c437f0	239	/**
mbed_official	133:d4dda5c437f0	240	* @brief FMC_NAND Configuration Structure definition
mbed_official	133:d4dda5c437f0	241	*/
mbed_official	133:d4dda5c437f0	242	typedef struct
mbed_official	133:d4dda5c437f0	243	{
mbed_official	133:d4dda5c437f0	244	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official	133:d4dda5c437f0	245	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	133:d4dda5c437f0	246
mbed_official	133:d4dda5c437f0	247	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	133:d4dda5c437f0	248	delay between CLE low and RE low.
mbed_official	133:d4dda5c437f0	249	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	250
mbed_official	133:d4dda5c437f0	251	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	133:d4dda5c437f0	252	delay between ALE low and RE low.
mbed_official	133:d4dda5c437f0	253	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	133:d4dda5c437f0	254
mbed_official	133:d4dda5c437f0	255	}FMC_PCCARD_InitTypeDef;
mbed_official	133:d4dda5c437f0	256
mbed_official	133:d4dda5c437f0	257	/**
mbed_official	133:d4dda5c437f0	258	* @brief FMC_SDRAM Configuration Structure definition
mbed_official	133:d4dda5c437f0	259	*/
mbed_official	133:d4dda5c437f0	260	typedef struct
mbed_official	133:d4dda5c437f0	261	{
mbed_official	133:d4dda5c437f0	262	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
mbed_official	133:d4dda5c437f0	263	This parameter can be a value of @ref FMC_SDRAM_Bank */
mbed_official	133:d4dda5c437f0	264
mbed_official	133:d4dda5c437f0	265	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	133:d4dda5c437f0	266	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
mbed_official	133:d4dda5c437f0	267
mbed_official	133:d4dda5c437f0	268	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	133:d4dda5c437f0	269	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
mbed_official	133:d4dda5c437f0	270
mbed_official	133:d4dda5c437f0	271	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
mbed_official	133:d4dda5c437f0	272	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
mbed_official	133:d4dda5c437f0	273
mbed_official	133:d4dda5c437f0	274	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
mbed_official	133:d4dda5c437f0	275	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
mbed_official	133:d4dda5c437f0	276
mbed_official	133:d4dda5c437f0	277	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
mbed_official	133:d4dda5c437f0	278	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
mbed_official	133:d4dda5c437f0	279
mbed_official	133:d4dda5c437f0	280	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
mbed_official	133:d4dda5c437f0	281	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
mbed_official	133:d4dda5c437f0	282
mbed_official	133:d4dda5c437f0	283	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
mbed_official	133:d4dda5c437f0	284	to disable the clock before changing frequency.
mbed_official	133:d4dda5c437f0	285	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
mbed_official	133:d4dda5c437f0	286
mbed_official	133:d4dda5c437f0	287	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
mbed_official	133:d4dda5c437f0	288	commands during the CAS latency and stores data in the Read FIFO.
mbed_official	133:d4dda5c437f0	289	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
mbed_official	133:d4dda5c437f0	290
mbed_official	133:d4dda5c437f0	291	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
mbed_official	133:d4dda5c437f0	292	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
mbed_official	133:d4dda5c437f0	293
mbed_official	133:d4dda5c437f0	294	}FMC_SDRAM_InitTypeDef;
mbed_official	133:d4dda5c437f0	295
mbed_official	133:d4dda5c437f0	296	/**
mbed_official	133:d4dda5c437f0	297	* @brief FMC_SDRAM Timing parameters structure definition
mbed_official	133:d4dda5c437f0	298	*/
mbed_official	133:d4dda5c437f0	299	typedef struct
mbed_official	133:d4dda5c437f0	300	{
mbed_official	133:d4dda5c437f0	301	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
mbed_official	133:d4dda5c437f0	302	an active or Refresh command in number of memory clock cycles.
mbed_official	133:d4dda5c437f0	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	304
mbed_official	133:d4dda5c437f0	305	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
mbed_official	133:d4dda5c437f0	306	issuing the Activate command in number of memory clock cycles.
mbed_official	133:d4dda5c437f0	307	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	308
mbed_official	133:d4dda5c437f0	309	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
mbed_official	133:d4dda5c437f0	310	cycles.
mbed_official	133:d4dda5c437f0	311	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	312
mbed_official	133:d4dda5c437f0	313	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
mbed_official	133:d4dda5c437f0	314	and the delay between two consecutive Refresh commands in number of
mbed_official	133:d4dda5c437f0	315	memory clock cycles.
mbed_official	133:d4dda5c437f0	316	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	317
mbed_official	133:d4dda5c437f0	318	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
mbed_official	133:d4dda5c437f0	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	320
mbed_official	133:d4dda5c437f0	321	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
mbed_official	133:d4dda5c437f0	322	in number of memory clock cycles.
mbed_official	133:d4dda5c437f0	323	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	324
mbed_official	133:d4dda5c437f0	325	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
mbed_official	133:d4dda5c437f0	326	command in number of memory clock cycles.
mbed_official	133:d4dda5c437f0	327	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	328
mbed_official	133:d4dda5c437f0	329	}FMC_SDRAM_TimingTypeDef;
mbed_official	133:d4dda5c437f0	330
mbed_official	133:d4dda5c437f0	331	/**
mbed_official	133:d4dda5c437f0	332	* @brief SDRAM command parameters structure definition
mbed_official	133:d4dda5c437f0	333	*/
mbed_official	133:d4dda5c437f0	334	typedef struct
mbed_official	133:d4dda5c437f0	335	{
mbed_official	133:d4dda5c437f0	336	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
mbed_official	133:d4dda5c437f0	337	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
mbed_official	133:d4dda5c437f0	338
mbed_official	133:d4dda5c437f0	339	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
mbed_official	133:d4dda5c437f0	340	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
mbed_official	133:d4dda5c437f0	341
mbed_official	133:d4dda5c437f0	342	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
mbed_official	133:d4dda5c437f0	343	in auto refresh mode.
mbed_official	133:d4dda5c437f0	344	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	133:d4dda5c437f0	345
mbed_official	133:d4dda5c437f0	346	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
mbed_official	133:d4dda5c437f0	347
mbed_official	133:d4dda5c437f0	348	}FMC_SDRAM_CommandTypeDef;
mbed_official	133:d4dda5c437f0	349
mbed_official	133:d4dda5c437f0	350	/* Exported constants --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	351
mbed_official	133:d4dda5c437f0	352	/** @defgroup FMC_NOR_SRAM_Controller
mbed_official	133:d4dda5c437f0	353	* @{
mbed_official	133:d4dda5c437f0	354	*/
mbed_official	133:d4dda5c437f0	355
mbed_official	133:d4dda5c437f0	356	/** @defgroup FMC_NORSRAM_Bank
mbed_official	133:d4dda5c437f0	357	* @{
mbed_official	133:d4dda5c437f0	358	*/
mbed_official	133:d4dda5c437f0	359	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	360	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	361	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	362	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	133:d4dda5c437f0	363
mbed_official	133:d4dda5c437f0	364	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
mbed_official	133:d4dda5c437f0	365	((BANK) == FMC_NORSRAM_BANK2) \|\| \
mbed_official	133:d4dda5c437f0	366	((BANK) == FMC_NORSRAM_BANK3) \|\| \
mbed_official	133:d4dda5c437f0	367	((BANK) == FMC_NORSRAM_BANK4))
mbed_official	133:d4dda5c437f0	368	/**
mbed_official	133:d4dda5c437f0	369	* @}
mbed_official	133:d4dda5c437f0	370	*/
mbed_official	133:d4dda5c437f0	371
mbed_official	133:d4dda5c437f0	372	/** @defgroup FMC_Data_Address_Bus_Multiplexing
mbed_official	133:d4dda5c437f0	373	* @{
mbed_official	133:d4dda5c437f0	374	*/
mbed_official	133:d4dda5c437f0	375	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	376	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	377
mbed_official	133:d4dda5c437f0	378	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	379	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	133:d4dda5c437f0	380	/**
mbed_official	133:d4dda5c437f0	381	* @}
mbed_official	133:d4dda5c437f0	382	*/
mbed_official	133:d4dda5c437f0	383
mbed_official	133:d4dda5c437f0	384	/** @defgroup FMC_Memory_Type
mbed_official	133:d4dda5c437f0	385	* @{
mbed_official	133:d4dda5c437f0	386	*/
mbed_official	133:d4dda5c437f0	387	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	388	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	389	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	390
mbed_official	133:d4dda5c437f0	391	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	133:d4dda5c437f0	392	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	133:d4dda5c437f0	393	((MEMORY) == FMC_MEMORY_TYPE_NOR))
mbed_official	133:d4dda5c437f0	394	/**
mbed_official	133:d4dda5c437f0	395	* @}
mbed_official	133:d4dda5c437f0	396	*/
mbed_official	133:d4dda5c437f0	397
mbed_official	133:d4dda5c437f0	398	/** @defgroup FMC_NORSRAM_Data_Width
mbed_official	133:d4dda5c437f0	399	* @{
mbed_official	133:d4dda5c437f0	400	*/
mbed_official	133:d4dda5c437f0	401	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	402	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	403	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	133:d4dda5c437f0	404
mbed_official	133:d4dda5c437f0	405	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	133:d4dda5c437f0	406	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	133:d4dda5c437f0	407	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	133:d4dda5c437f0	408	/**
mbed_official	133:d4dda5c437f0	409	* @}
mbed_official	133:d4dda5c437f0	410	*/
mbed_official	133:d4dda5c437f0	411
mbed_official	133:d4dda5c437f0	412	/** @defgroup FMC_NORSRAM_Flash_Access
mbed_official	133:d4dda5c437f0	413	* @{
mbed_official	133:d4dda5c437f0	414	*/
mbed_official	133:d4dda5c437f0	415	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	133:d4dda5c437f0	416	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	417	/**
mbed_official	133:d4dda5c437f0	418	* @}
mbed_official	133:d4dda5c437f0	419	*/
mbed_official	133:d4dda5c437f0	420
mbed_official	133:d4dda5c437f0	421	/** @defgroup FMC_Burst_Access_Mode
mbed_official	133:d4dda5c437f0	422	* @{
mbed_official	133:d4dda5c437f0	423	*/
mbed_official	133:d4dda5c437f0	424	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	425	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	133:d4dda5c437f0	426
mbed_official	133:d4dda5c437f0	427	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	428	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	133:d4dda5c437f0	429	/**
mbed_official	133:d4dda5c437f0	430	* @}
mbed_official	133:d4dda5c437f0	431	*/
mbed_official	133:d4dda5c437f0	432
mbed_official	133:d4dda5c437f0	433
mbed_official	133:d4dda5c437f0	434	/** @defgroup FMC_Wait_Signal_Polarity
mbed_official	133:d4dda5c437f0	435	* @{
mbed_official	133:d4dda5c437f0	436	*/
mbed_official	133:d4dda5c437f0	437	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	438	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	133:d4dda5c437f0	439
mbed_official	133:d4dda5c437f0	440	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	133:d4dda5c437f0	441	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	133:d4dda5c437f0	442	/**
mbed_official	133:d4dda5c437f0	443	* @}
mbed_official	133:d4dda5c437f0	444	*/
mbed_official	133:d4dda5c437f0	445
mbed_official	133:d4dda5c437f0	446	/** @defgroup FMC_Wrap_Mode
mbed_official	133:d4dda5c437f0	447	* @{
mbed_official	133:d4dda5c437f0	448	*/
mbed_official	133:d4dda5c437f0	449	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	450	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official	133:d4dda5c437f0	451
mbed_official	133:d4dda5c437f0	452	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	453	((MODE) == FMC_WRAP_MODE_ENABLE))
mbed_official	133:d4dda5c437f0	454	/**
mbed_official	133:d4dda5c437f0	455	* @}
mbed_official	133:d4dda5c437f0	456	*/
mbed_official	133:d4dda5c437f0	457
mbed_official	133:d4dda5c437f0	458	/** @defgroup FMC_Wait_Timing
mbed_official	133:d4dda5c437f0	459	* @{
mbed_official	133:d4dda5c437f0	460	*/
mbed_official	133:d4dda5c437f0	461	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	462	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	133:d4dda5c437f0	463
mbed_official	133:d4dda5c437f0	464	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	133:d4dda5c437f0	465	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
mbed_official	133:d4dda5c437f0	466	/**
mbed_official	133:d4dda5c437f0	467	* @}
mbed_official	133:d4dda5c437f0	468	*/
mbed_official	133:d4dda5c437f0	469
mbed_official	133:d4dda5c437f0	470	/** @defgroup FMC_Write_Operation
mbed_official	133:d4dda5c437f0	471	* @{
mbed_official	133:d4dda5c437f0	472	*/
mbed_official	133:d4dda5c437f0	473	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	474	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	133:d4dda5c437f0	475
mbed_official	133:d4dda5c437f0	476	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	477	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
mbed_official	133:d4dda5c437f0	478	/**
mbed_official	133:d4dda5c437f0	479	* @}
mbed_official	133:d4dda5c437f0	480	*/
mbed_official	133:d4dda5c437f0	481
mbed_official	133:d4dda5c437f0	482	/** @defgroup FMC_Wait_Signal
mbed_official	133:d4dda5c437f0	483	* @{
mbed_official	133:d4dda5c437f0	484	*/
mbed_official	133:d4dda5c437f0	485	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	486	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	133:d4dda5c437f0	487
mbed_official	133:d4dda5c437f0	488	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	489	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official	133:d4dda5c437f0	490	/**
mbed_official	133:d4dda5c437f0	491	* @}
mbed_official	133:d4dda5c437f0	492	*/
mbed_official	133:d4dda5c437f0	493
mbed_official	133:d4dda5c437f0	494	/** @defgroup FMC_Extended_Mode
mbed_official	133:d4dda5c437f0	495	* @{
mbed_official	133:d4dda5c437f0	496	*/
mbed_official	133:d4dda5c437f0	497	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	498	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	133:d4dda5c437f0	499
mbed_official	133:d4dda5c437f0	500	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	501	((MODE) == FMC_EXTENDED_MODE_ENABLE))
mbed_official	133:d4dda5c437f0	502	/**
mbed_official	133:d4dda5c437f0	503	* @}
mbed_official	133:d4dda5c437f0	504	*/
mbed_official	133:d4dda5c437f0	505
mbed_official	133:d4dda5c437f0	506	/** @defgroup FMC_AsynchronousWait
mbed_official	133:d4dda5c437f0	507	* @{
mbed_official	133:d4dda5c437f0	508	*/
mbed_official	133:d4dda5c437f0	509	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	510	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	133:d4dda5c437f0	511
mbed_official	133:d4dda5c437f0	512	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	513	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	133:d4dda5c437f0	514	/**
mbed_official	133:d4dda5c437f0	515	* @}
mbed_official	133:d4dda5c437f0	516	*/
mbed_official	133:d4dda5c437f0	517
mbed_official	133:d4dda5c437f0	518	/** @defgroup FMC_Write_Burst
mbed_official	133:d4dda5c437f0	519	* @{
mbed_official	133:d4dda5c437f0	520	*/
mbed_official	133:d4dda5c437f0	521	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	522	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	133:d4dda5c437f0	523
mbed_official	133:d4dda5c437f0	524	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	525	((BURST) == FMC_WRITE_BURST_ENABLE))
mbed_official	133:d4dda5c437f0	526	/**
mbed_official	133:d4dda5c437f0	527	* @}
mbed_official	133:d4dda5c437f0	528	*/
mbed_official	133:d4dda5c437f0	529
mbed_official	133:d4dda5c437f0	530	/** @defgroup FMC_Continous_Clock
mbed_official	133:d4dda5c437f0	531	* @{
mbed_official	133:d4dda5c437f0	532	*/
mbed_official	133:d4dda5c437f0	533	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	534	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	133:d4dda5c437f0	535
mbed_official	133:d4dda5c437f0	536	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	133:d4dda5c437f0	537	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	133:d4dda5c437f0	538	/**
mbed_official	133:d4dda5c437f0	539	* @}
mbed_official	133:d4dda5c437f0	540	*/
mbed_official	133:d4dda5c437f0	541
mbed_official	133:d4dda5c437f0	542	/** @defgroup FMC_Address_Setup_Time
mbed_official	133:d4dda5c437f0	543	* @{
mbed_official	133:d4dda5c437f0	544	*/
mbed_official	133:d4dda5c437f0	545	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
mbed_official	133:d4dda5c437f0	546	/**
mbed_official	133:d4dda5c437f0	547	* @}
mbed_official	133:d4dda5c437f0	548	*/
mbed_official	133:d4dda5c437f0	549
mbed_official	133:d4dda5c437f0	550	/** @defgroup FMC_Address_Hold_Time
mbed_official	133:d4dda5c437f0	551	* @{
mbed_official	133:d4dda5c437f0	552	*/
mbed_official	133:d4dda5c437f0	553	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
mbed_official	133:d4dda5c437f0	554	/**
mbed_official	133:d4dda5c437f0	555	* @}
mbed_official	133:d4dda5c437f0	556	*/
mbed_official	133:d4dda5c437f0	557
mbed_official	133:d4dda5c437f0	558	/** @defgroup FMC_Data_Setup_Time
mbed_official	133:d4dda5c437f0	559	* @{
mbed_official	133:d4dda5c437f0	560	*/
mbed_official	133:d4dda5c437f0	561	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
mbed_official	133:d4dda5c437f0	562	/**
mbed_official	133:d4dda5c437f0	563	* @}
mbed_official	133:d4dda5c437f0	564	*/
mbed_official	133:d4dda5c437f0	565
mbed_official	133:d4dda5c437f0	566	/** @defgroup FMC_Bus_Turn_around_Duration
mbed_official	133:d4dda5c437f0	567	* @{
mbed_official	133:d4dda5c437f0	568	*/
mbed_official	133:d4dda5c437f0	569	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
mbed_official	133:d4dda5c437f0	570	/**
mbed_official	133:d4dda5c437f0	571	* @}
mbed_official	133:d4dda5c437f0	572	*/
mbed_official	133:d4dda5c437f0	573
mbed_official	133:d4dda5c437f0	574	/** @defgroup FMC_CLK_Division
mbed_official	133:d4dda5c437f0	575	* @{
mbed_official	133:d4dda5c437f0	576	*/
mbed_official	133:d4dda5c437f0	577	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	133:d4dda5c437f0	578	/**
mbed_official	133:d4dda5c437f0	579	* @}
mbed_official	133:d4dda5c437f0	580	*/
mbed_official	133:d4dda5c437f0	581
mbed_official	133:d4dda5c437f0	582	/** @defgroup FMC_Data_Latency
mbed_official	133:d4dda5c437f0	583	* @{
mbed_official	133:d4dda5c437f0	584	*/
mbed_official	133:d4dda5c437f0	585	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
mbed_official	133:d4dda5c437f0	586	/**
mbed_official	133:d4dda5c437f0	587	* @}
mbed_official	133:d4dda5c437f0	588	*/
mbed_official	133:d4dda5c437f0	589
mbed_official	133:d4dda5c437f0	590	/** @defgroup FMC_Access_Mode
mbed_official	133:d4dda5c437f0	591	* @{
mbed_official	133:d4dda5c437f0	592	*/
mbed_official	133:d4dda5c437f0	593	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	594	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	133:d4dda5c437f0	595	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	133:d4dda5c437f0	596	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	133:d4dda5c437f0	597
mbed_official	133:d4dda5c437f0	598	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
mbed_official	133:d4dda5c437f0	599	((MODE) == FMC_ACCESS_MODE_B) \|\| \
mbed_official	133:d4dda5c437f0	600	((MODE) == FMC_ACCESS_MODE_C) \|\| \
mbed_official	133:d4dda5c437f0	601	((MODE) == FMC_ACCESS_MODE_D))
mbed_official	133:d4dda5c437f0	602	/**
mbed_official	133:d4dda5c437f0	603	* @}
mbed_official	133:d4dda5c437f0	604	*/
mbed_official	133:d4dda5c437f0	605
mbed_official	133:d4dda5c437f0	606	/**
mbed_official	133:d4dda5c437f0	607	* @}
mbed_official	133:d4dda5c437f0	608	*/
mbed_official	133:d4dda5c437f0	609
mbed_official	133:d4dda5c437f0	610	/** @defgroup FMC_NAND_Controller
mbed_official	133:d4dda5c437f0	611	* @{
mbed_official	133:d4dda5c437f0	612	*/
mbed_official	133:d4dda5c437f0	613
mbed_official	133:d4dda5c437f0	614	/** @defgroup FMC_NAND_Bank
mbed_official	133:d4dda5c437f0	615	* @{
mbed_official	133:d4dda5c437f0	616	*/
mbed_official	133:d4dda5c437f0	617	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	618	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	133:d4dda5c437f0	619
mbed_official	133:d4dda5c437f0	620	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
mbed_official	133:d4dda5c437f0	621	((BANK) == FMC_NAND_BANK3))
mbed_official	133:d4dda5c437f0	622	/**
mbed_official	133:d4dda5c437f0	623	* @}
mbed_official	133:d4dda5c437f0	624	*/
mbed_official	133:d4dda5c437f0	625
mbed_official	133:d4dda5c437f0	626	/** @defgroup FMC_Wait_feature
mbed_official	133:d4dda5c437f0	627	* @{
mbed_official	133:d4dda5c437f0	628	*/
mbed_official	133:d4dda5c437f0	629	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	630	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	631
mbed_official	133:d4dda5c437f0	632	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	633	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official	133:d4dda5c437f0	634	/**
mbed_official	133:d4dda5c437f0	635	* @}
mbed_official	133:d4dda5c437f0	636	*/
mbed_official	133:d4dda5c437f0	637
mbed_official	133:d4dda5c437f0	638	/** @defgroup FMC_PCR_Memory_Type
mbed_official	133:d4dda5c437f0	639	* @{
mbed_official	133:d4dda5c437f0	640	*/
mbed_official	133:d4dda5c437f0	641	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	642	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	643	/**
mbed_official	133:d4dda5c437f0	644	* @}
mbed_official	133:d4dda5c437f0	645	*/
mbed_official	133:d4dda5c437f0	646
mbed_official	133:d4dda5c437f0	647	/** @defgroup FMC_NAND_Data_Width
mbed_official	133:d4dda5c437f0	648	* @{
mbed_official	133:d4dda5c437f0	649	*/
mbed_official	133:d4dda5c437f0	650	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	651	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	652
mbed_official	133:d4dda5c437f0	653	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
mbed_official	133:d4dda5c437f0	654	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official	133:d4dda5c437f0	655	/**
mbed_official	133:d4dda5c437f0	656	* @}
mbed_official	133:d4dda5c437f0	657	*/
mbed_official	133:d4dda5c437f0	658
mbed_official	133:d4dda5c437f0	659	/** @defgroup FMC_ECC
mbed_official	133:d4dda5c437f0	660	* @{
mbed_official	133:d4dda5c437f0	661	*/
mbed_official	133:d4dda5c437f0	662	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	663	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	133:d4dda5c437f0	664
mbed_official	133:d4dda5c437f0	665	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	666	((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official	133:d4dda5c437f0	667	/**
mbed_official	133:d4dda5c437f0	668	* @}
mbed_official	133:d4dda5c437f0	669	*/
mbed_official	133:d4dda5c437f0	670
mbed_official	133:d4dda5c437f0	671	/** @defgroup FMC_ECC_Page_Size
mbed_official	133:d4dda5c437f0	672	* @{
mbed_official	133:d4dda5c437f0	673	*/
mbed_official	133:d4dda5c437f0	674	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	675	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	133:d4dda5c437f0	676	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	133:d4dda5c437f0	677	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	133:d4dda5c437f0	678	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	133:d4dda5c437f0	679	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	133:d4dda5c437f0	680
mbed_official	133:d4dda5c437f0	681	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	133:d4dda5c437f0	682	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	133:d4dda5c437f0	683	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	133:d4dda5c437f0	684	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	133:d4dda5c437f0	685	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	133:d4dda5c437f0	686	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	133:d4dda5c437f0	687	/**
mbed_official	133:d4dda5c437f0	688	* @}
mbed_official	133:d4dda5c437f0	689	*/
mbed_official	133:d4dda5c437f0	690
mbed_official	133:d4dda5c437f0	691	/** @defgroup FMC_TCLR_Setup_Time
mbed_official	133:d4dda5c437f0	692	* @{
mbed_official	133:d4dda5c437f0	693	*/
mbed_official	133:d4dda5c437f0	694	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official	133:d4dda5c437f0	695	/**
mbed_official	133:d4dda5c437f0	696	* @}
mbed_official	133:d4dda5c437f0	697	*/
mbed_official	133:d4dda5c437f0	698
mbed_official	133:d4dda5c437f0	699	/** @defgroup FMC_TAR_Setup_Time
mbed_official	133:d4dda5c437f0	700	* @{
mbed_official	133:d4dda5c437f0	701	*/
mbed_official	133:d4dda5c437f0	702	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	133:d4dda5c437f0	703	/**
mbed_official	133:d4dda5c437f0	704	* @}
mbed_official	133:d4dda5c437f0	705	*/
mbed_official	133:d4dda5c437f0	706
mbed_official	133:d4dda5c437f0	707	/** @defgroup FMC_Setup_Time
mbed_official	133:d4dda5c437f0	708	* @{
mbed_official	133:d4dda5c437f0	709	*/
mbed_official	133:d4dda5c437f0	710	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	133:d4dda5c437f0	711	/**
mbed_official	133:d4dda5c437f0	712	* @}
mbed_official	133:d4dda5c437f0	713	*/
mbed_official	133:d4dda5c437f0	714
mbed_official	133:d4dda5c437f0	715	/** @defgroup FMC_Wait_Setup_Time
mbed_official	133:d4dda5c437f0	716	* @{
mbed_official	133:d4dda5c437f0	717	*/
mbed_official	133:d4dda5c437f0	718	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	133:d4dda5c437f0	719	/**
mbed_official	133:d4dda5c437f0	720	* @}
mbed_official	133:d4dda5c437f0	721	*/
mbed_official	133:d4dda5c437f0	722
mbed_official	133:d4dda5c437f0	723	/** @defgroup FMC_Hold_Setup_Time
mbed_official	133:d4dda5c437f0	724	* @{
mbed_official	133:d4dda5c437f0	725	*/
mbed_official	133:d4dda5c437f0	726	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	133:d4dda5c437f0	727	/**
mbed_official	133:d4dda5c437f0	728	* @}
mbed_official	133:d4dda5c437f0	729	*/
mbed_official	133:d4dda5c437f0	730
mbed_official	133:d4dda5c437f0	731	/** @defgroup FMC_HiZ_Setup_Time
mbed_official	133:d4dda5c437f0	732	* @{
mbed_official	133:d4dda5c437f0	733	*/
mbed_official	133:d4dda5c437f0	734	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	133:d4dda5c437f0	735	/**
mbed_official	133:d4dda5c437f0	736	* @}
mbed_official	133:d4dda5c437f0	737	*/
mbed_official	133:d4dda5c437f0	738
mbed_official	133:d4dda5c437f0	739	/**
mbed_official	133:d4dda5c437f0	740	* @}
mbed_official	133:d4dda5c437f0	741	*/
mbed_official	133:d4dda5c437f0	742
mbed_official	133:d4dda5c437f0	743	/** @defgroup FMC_SDRAM_Controller
mbed_official	133:d4dda5c437f0	744	* @{
mbed_official	133:d4dda5c437f0	745	*/
mbed_official	133:d4dda5c437f0	746
mbed_official	133:d4dda5c437f0	747	/** @defgroup FMC_SDRAM_Bank
mbed_official	133:d4dda5c437f0	748	* @{
mbed_official	133:d4dda5c437f0	749	*/
mbed_official	133:d4dda5c437f0	750	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	751	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	752
mbed_official	133:d4dda5c437f0	753	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
mbed_official	133:d4dda5c437f0	754	((BANK) == FMC_SDRAM_BANK2))
mbed_official	133:d4dda5c437f0	755	/**
mbed_official	133:d4dda5c437f0	756	* @}
mbed_official	133:d4dda5c437f0	757	*/
mbed_official	133:d4dda5c437f0	758
mbed_official	133:d4dda5c437f0	759	/** @defgroup FMC_SDRAM_Column_Bits_number
mbed_official	133:d4dda5c437f0	760	* @{
mbed_official	133:d4dda5c437f0	761	*/
mbed_official	133:d4dda5c437f0	762	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	763	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	764	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	765	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
mbed_official	133:d4dda5c437f0	766
mbed_official	133:d4dda5c437f0	767	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
mbed_official	133:d4dda5c437f0	768	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
mbed_official	133:d4dda5c437f0	769	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
mbed_official	133:d4dda5c437f0	770	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
mbed_official	133:d4dda5c437f0	771	/**
mbed_official	133:d4dda5c437f0	772	* @}
mbed_official	133:d4dda5c437f0	773	*/
mbed_official	133:d4dda5c437f0	774
mbed_official	133:d4dda5c437f0	775	/** @defgroup FMC_SDRAM_Row_Bits_number
mbed_official	133:d4dda5c437f0	776	* @{
mbed_official	133:d4dda5c437f0	777	*/
mbed_official	133:d4dda5c437f0	778	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	779	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	780	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	781
mbed_official	133:d4dda5c437f0	782	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
mbed_official	133:d4dda5c437f0	783	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
mbed_official	133:d4dda5c437f0	784	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
mbed_official	133:d4dda5c437f0	785	/**
mbed_official	133:d4dda5c437f0	786	* @}
mbed_official	133:d4dda5c437f0	787	*/
mbed_official	133:d4dda5c437f0	788
mbed_official	133:d4dda5c437f0	789	/** @defgroup FMC_SDRAM_Memory_Bus_Width
mbed_official	133:d4dda5c437f0	790	* @{
mbed_official	133:d4dda5c437f0	791	*/
mbed_official	133:d4dda5c437f0	792	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	793	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	794	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	133:d4dda5c437f0	795
mbed_official	133:d4dda5c437f0	796	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	133:d4dda5c437f0	797	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	133:d4dda5c437f0	798	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
mbed_official	133:d4dda5c437f0	799	/**
mbed_official	133:d4dda5c437f0	800	* @}
mbed_official	133:d4dda5c437f0	801	*/
mbed_official	133:d4dda5c437f0	802
mbed_official	133:d4dda5c437f0	803	/** @defgroup FMC_SDRAM_Internal_Banks_Number
mbed_official	133:d4dda5c437f0	804	* @{
mbed_official	133:d4dda5c437f0	805	*/
mbed_official	133:d4dda5c437f0	806	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	807	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
mbed_official	133:d4dda5c437f0	808
mbed_official	133:d4dda5c437f0	809	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
mbed_official	133:d4dda5c437f0	810	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
mbed_official	133:d4dda5c437f0	811	/**
mbed_official	133:d4dda5c437f0	812	* @}
mbed_official	133:d4dda5c437f0	813	*/
mbed_official	133:d4dda5c437f0	814
mbed_official	133:d4dda5c437f0	815	/** @defgroup FMC_SDRAM_CAS_Latency
mbed_official	133:d4dda5c437f0	816	* @{
mbed_official	133:d4dda5c437f0	817	*/
mbed_official	133:d4dda5c437f0	818	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
mbed_official	133:d4dda5c437f0	819	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
mbed_official	133:d4dda5c437f0	820	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
mbed_official	133:d4dda5c437f0	821
mbed_official	133:d4dda5c437f0	822	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
mbed_official	133:d4dda5c437f0	823	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
mbed_official	133:d4dda5c437f0	824	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
mbed_official	133:d4dda5c437f0	825	/**
mbed_official	133:d4dda5c437f0	826	* @}
mbed_official	133:d4dda5c437f0	827	*/
mbed_official	133:d4dda5c437f0	828
mbed_official	133:d4dda5c437f0	829	/** @defgroup FMC_SDRAM_Write_Protection
mbed_official	133:d4dda5c437f0	830	* @{
mbed_official	133:d4dda5c437f0	831	*/
mbed_official	133:d4dda5c437f0	832	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	833	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
mbed_official	133:d4dda5c437f0	834
mbed_official	133:d4dda5c437f0	835	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	836	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
mbed_official	133:d4dda5c437f0	837	/**
mbed_official	133:d4dda5c437f0	838	* @}
mbed_official	133:d4dda5c437f0	839	*/
mbed_official	133:d4dda5c437f0	840
mbed_official	133:d4dda5c437f0	841	/** @defgroup FMC_SDRAM_Clock_Period
mbed_official	133:d4dda5c437f0	842	* @{
mbed_official	133:d4dda5c437f0	843	*/
mbed_official	133:d4dda5c437f0	844	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	845	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
mbed_official	133:d4dda5c437f0	846	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
mbed_official	133:d4dda5c437f0	847
mbed_official	133:d4dda5c437f0	848	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	849	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
mbed_official	133:d4dda5c437f0	850	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
mbed_official	133:d4dda5c437f0	851	/**
mbed_official	133:d4dda5c437f0	852	* @}
mbed_official	133:d4dda5c437f0	853	*/
mbed_official	133:d4dda5c437f0	854
mbed_official	133:d4dda5c437f0	855	/** @defgroup FMC_SDRAM_Read_Burst
mbed_official	133:d4dda5c437f0	856	* @{
mbed_official	133:d4dda5c437f0	857	*/
mbed_official	133:d4dda5c437f0	858	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	859	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
mbed_official	133:d4dda5c437f0	860
mbed_official	133:d4dda5c437f0	861	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	862	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
mbed_official	133:d4dda5c437f0	863	/**
mbed_official	133:d4dda5c437f0	864	* @}
mbed_official	133:d4dda5c437f0	865	*/
mbed_official	133:d4dda5c437f0	866
mbed_official	133:d4dda5c437f0	867	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
mbed_official	133:d4dda5c437f0	868	* @{
mbed_official	133:d4dda5c437f0	869	*/
mbed_official	133:d4dda5c437f0	870	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	871	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
mbed_official	133:d4dda5c437f0	872	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
mbed_official	133:d4dda5c437f0	873
mbed_official	133:d4dda5c437f0	874	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
mbed_official	133:d4dda5c437f0	875	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
mbed_official	133:d4dda5c437f0	876	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
mbed_official	133:d4dda5c437f0	877	/**
mbed_official	133:d4dda5c437f0	878	* @}
mbed_official	133:d4dda5c437f0	879	*/
mbed_official	133:d4dda5c437f0	880
mbed_official	133:d4dda5c437f0	881	/** @defgroup FMC_SDRAM_LoadToActive_Delay
mbed_official	133:d4dda5c437f0	882	* @{
mbed_official	133:d4dda5c437f0	883	*/
mbed_official	133:d4dda5c437f0	884	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	133:d4dda5c437f0	885	/**
mbed_official	133:d4dda5c437f0	886	* @}
mbed_official	133:d4dda5c437f0	887	*/
mbed_official	133:d4dda5c437f0	888
mbed_official	133:d4dda5c437f0	889	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
mbed_official	133:d4dda5c437f0	890	* @{
mbed_official	133:d4dda5c437f0	891	*/
mbed_official	133:d4dda5c437f0	892	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	133:d4dda5c437f0	893	/**
mbed_official	133:d4dda5c437f0	894	* @}
mbed_official	133:d4dda5c437f0	895	*/
mbed_official	133:d4dda5c437f0	896
mbed_official	133:d4dda5c437f0	897	/** @defgroup FMC_SDRAM_SelfRefresh_Time
mbed_official	133:d4dda5c437f0	898	* @{
mbed_official	133:d4dda5c437f0	899	*/
mbed_official	133:d4dda5c437f0	900	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	133:d4dda5c437f0	901	/**
mbed_official	133:d4dda5c437f0	902	* @}
mbed_official	133:d4dda5c437f0	903	*/
mbed_official	133:d4dda5c437f0	904
mbed_official	133:d4dda5c437f0	905	/** @defgroup FMC_SDRAM_RowCycle_Delay
mbed_official	133:d4dda5c437f0	906	* @{
mbed_official	133:d4dda5c437f0	907	*/
mbed_official	133:d4dda5c437f0	908	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	133:d4dda5c437f0	909	/**
mbed_official	133:d4dda5c437f0	910	* @}
mbed_official	133:d4dda5c437f0	911	*/
mbed_official	133:d4dda5c437f0	912
mbed_official	133:d4dda5c437f0	913	/** @defgroup FMC_SDRAM_Write_Recovery_Time
mbed_official	133:d4dda5c437f0	914	* @{
mbed_official	133:d4dda5c437f0	915	*/
mbed_official	133:d4dda5c437f0	916	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	133:d4dda5c437f0	917	/**
mbed_official	133:d4dda5c437f0	918	* @}
mbed_official	133:d4dda5c437f0	919	*/
mbed_official	133:d4dda5c437f0	920
mbed_official	133:d4dda5c437f0	921	/** @defgroup FMC_SDRAM_RP_Delay
mbed_official	133:d4dda5c437f0	922	* @{
mbed_official	133:d4dda5c437f0	923	*/
mbed_official	133:d4dda5c437f0	924	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	133:d4dda5c437f0	925	/**
mbed_official	133:d4dda5c437f0	926	* @}
mbed_official	133:d4dda5c437f0	927	*/
mbed_official	133:d4dda5c437f0	928
mbed_official	133:d4dda5c437f0	929	/** @defgroup FMC_SDRAM_RCD_Delay
mbed_official	133:d4dda5c437f0	930	* @{
mbed_official	133:d4dda5c437f0	931	*/
mbed_official	133:d4dda5c437f0	932	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	133:d4dda5c437f0	933
mbed_official	133:d4dda5c437f0	934	/**
mbed_official	133:d4dda5c437f0	935	* @}
mbed_official	133:d4dda5c437f0	936	*/
mbed_official	133:d4dda5c437f0	937
mbed_official	133:d4dda5c437f0	938	/** @defgroup FMC_SDRAM_Command_Mode
mbed_official	133:d4dda5c437f0	939	* @{
mbed_official	133:d4dda5c437f0	940	*/
mbed_official	133:d4dda5c437f0	941	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	942	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	943	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	944	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
mbed_official	133:d4dda5c437f0	945	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	946	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
mbed_official	133:d4dda5c437f0	947	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
mbed_official	133:d4dda5c437f0	948
mbed_official	133:d4dda5c437f0	949	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
mbed_official	133:d4dda5c437f0	950	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	951	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
mbed_official	133:d4dda5c437f0	952	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
mbed_official	133:d4dda5c437f0	953	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
mbed_official	133:d4dda5c437f0	954	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
mbed_official	133:d4dda5c437f0	955	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
mbed_official	133:d4dda5c437f0	956	/**
mbed_official	133:d4dda5c437f0	957	* @}
mbed_official	133:d4dda5c437f0	958	*/
mbed_official	133:d4dda5c437f0	959
mbed_official	133:d4dda5c437f0	960	/** @defgroup FMC_SDRAM_Command_Target
mbed_official	133:d4dda5c437f0	961	* @{
mbed_official	133:d4dda5c437f0	962	*/
mbed_official	133:d4dda5c437f0	963	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
mbed_official	133:d4dda5c437f0	964	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
mbed_official	133:d4dda5c437f0	965	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
mbed_official	133:d4dda5c437f0	966
mbed_official	133:d4dda5c437f0	967	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
mbed_official	133:d4dda5c437f0	968	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
mbed_official	133:d4dda5c437f0	969	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
mbed_official	133:d4dda5c437f0	970	/**
mbed_official	133:d4dda5c437f0	971	* @}
mbed_official	133:d4dda5c437f0	972	*/
mbed_official	133:d4dda5c437f0	973
mbed_official	133:d4dda5c437f0	974	/** @defgroup FMC_SDRAM_AutoRefresh_Number
mbed_official	133:d4dda5c437f0	975	* @{
mbed_official	133:d4dda5c437f0	976	*/
mbed_official	133:d4dda5c437f0	977	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
mbed_official	133:d4dda5c437f0	978	/**
mbed_official	133:d4dda5c437f0	979	* @}
mbed_official	133:d4dda5c437f0	980	*/
mbed_official	133:d4dda5c437f0	981
mbed_official	133:d4dda5c437f0	982	/** @defgroup FMC_SDRAM_ModeRegister_Definition
mbed_official	133:d4dda5c437f0	983	* @{
mbed_official	133:d4dda5c437f0	984	*/
mbed_official	133:d4dda5c437f0	985	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
mbed_official	133:d4dda5c437f0	986	/**
mbed_official	133:d4dda5c437f0	987	* @}
mbed_official	133:d4dda5c437f0	988	*/
mbed_official	133:d4dda5c437f0	989
mbed_official	133:d4dda5c437f0	990	/** @defgroup FMC_SDRAM_Refresh_rate
mbed_official	133:d4dda5c437f0	991	* @{
mbed_official	133:d4dda5c437f0	992	*/
mbed_official	133:d4dda5c437f0	993	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
mbed_official	133:d4dda5c437f0	994	/**
mbed_official	133:d4dda5c437f0	995	* @}
mbed_official	133:d4dda5c437f0	996	*/
mbed_official	133:d4dda5c437f0	997
mbed_official	133:d4dda5c437f0	998	/** @defgroup FMC_SDRAM_Mode_Status
mbed_official	133:d4dda5c437f0	999	* @{
mbed_official	133:d4dda5c437f0	1000	*/
mbed_official	133:d4dda5c437f0	1001	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	1002	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
mbed_official	133:d4dda5c437f0	1003	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
mbed_official	133:d4dda5c437f0	1004	/**
mbed_official	133:d4dda5c437f0	1005	* @}
mbed_official	133:d4dda5c437f0	1006	*/
mbed_official	133:d4dda5c437f0	1007
mbed_official	133:d4dda5c437f0	1008	/** @defgroup FMC_NORSRAM_Device_Instance
mbed_official	133:d4dda5c437f0	1009	* @{
mbed_official	133:d4dda5c437f0	1010	*/
mbed_official	133:d4dda5c437f0	1011	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
mbed_official	133:d4dda5c437f0	1012	/**
mbed_official	133:d4dda5c437f0	1013	* @}
mbed_official	133:d4dda5c437f0	1014	*/
mbed_official	133:d4dda5c437f0	1015
mbed_official	133:d4dda5c437f0	1016	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
mbed_official	133:d4dda5c437f0	1017	* @{
mbed_official	133:d4dda5c437f0	1018	*/
mbed_official	133:d4dda5c437f0	1019	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	133:d4dda5c437f0	1020	/**
mbed_official	133:d4dda5c437f0	1021	* @}
mbed_official	133:d4dda5c437f0	1022	*/
mbed_official	133:d4dda5c437f0	1023
mbed_official	133:d4dda5c437f0	1024	/** @defgroup FMC_NAND_Device_Instance
mbed_official	133:d4dda5c437f0	1025	* @{
mbed_official	133:d4dda5c437f0	1026	*/
mbed_official	133:d4dda5c437f0	1027	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
mbed_official	133:d4dda5c437f0	1028	/**
mbed_official	133:d4dda5c437f0	1029	* @}
mbed_official	133:d4dda5c437f0	1030	*/
mbed_official	133:d4dda5c437f0	1031
mbed_official	133:d4dda5c437f0	1032	/** @defgroup FMC_PCCARD_Device_Instance
mbed_official	133:d4dda5c437f0	1033	* @{
mbed_official	133:d4dda5c437f0	1034	*/
mbed_official	133:d4dda5c437f0	1035	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
mbed_official	133:d4dda5c437f0	1036	/**
mbed_official	133:d4dda5c437f0	1037	* @}
mbed_official	133:d4dda5c437f0	1038	*/
mbed_official	133:d4dda5c437f0	1039
mbed_official	133:d4dda5c437f0	1040	/** @defgroup FMC_SDRAM_Device_Instance
mbed_official	133:d4dda5c437f0	1041	* @{
mbed_official	133:d4dda5c437f0	1042	*/
mbed_official	133:d4dda5c437f0	1043	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
mbed_official	133:d4dda5c437f0	1044	/**
mbed_official	133:d4dda5c437f0	1045	* @}
mbed_official	133:d4dda5c437f0	1046	*/
mbed_official	133:d4dda5c437f0	1047
mbed_official	133:d4dda5c437f0	1048	/**
mbed_official	133:d4dda5c437f0	1049	* @}
mbed_official	133:d4dda5c437f0	1050	*/
mbed_official	133:d4dda5c437f0	1051
mbed_official	133:d4dda5c437f0	1052	/** @defgroup FMC_Interrupt_definition
mbed_official	133:d4dda5c437f0	1053	* @brief FMC Interrupt definition
mbed_official	133:d4dda5c437f0	1054	* @{
mbed_official	133:d4dda5c437f0	1055	*/
mbed_official	133:d4dda5c437f0	1056	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	1057	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	1058	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	133:d4dda5c437f0	1059	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	133:d4dda5c437f0	1060
mbed_official	133:d4dda5c437f0	1061	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	133:d4dda5c437f0	1062
mbed_official	133:d4dda5c437f0	1063	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
mbed_official	133:d4dda5c437f0	1064	((IT) == FMC_IT_LEVEL) \|\| \
mbed_official	133:d4dda5c437f0	1065	((IT) == FMC_IT_FALLING_EDGE) \|\| \
mbed_official	133:d4dda5c437f0	1066	((IT) == FMC_IT_REFRESH_ERROR))
mbed_official	133:d4dda5c437f0	1067	/**
mbed_official	133:d4dda5c437f0	1068	* @}
mbed_official	133:d4dda5c437f0	1069	*/
mbed_official	133:d4dda5c437f0	1070
mbed_official	133:d4dda5c437f0	1071	/** @defgroup FMC_Flag_definition
mbed_official	133:d4dda5c437f0	1072	* @brief FMC Flag definition
mbed_official	133:d4dda5c437f0	1073	* @{
mbed_official	133:d4dda5c437f0	1074	*/
mbed_official	133:d4dda5c437f0	1075	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	1076	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	1077	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	1078	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	133:d4dda5c437f0	1079	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
mbed_official	133:d4dda5c437f0	1080	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
mbed_official	133:d4dda5c437f0	1081	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
mbed_official	133:d4dda5c437f0	1082
mbed_official	133:d4dda5c437f0	1083	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
mbed_official	133:d4dda5c437f0	1084	((FLAG) == FMC_FLAG_LEVEL) \|\| \
mbed_official	133:d4dda5c437f0	1085	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
mbed_official	133:d4dda5c437f0	1086	((FLAG) == FMC_FLAG_FEMPT) \|\| \
mbed_official	133:d4dda5c437f0	1087	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
mbed_official	133:d4dda5c437f0	1088	((FLAG) == FMC_SDRAM_FLAG_BUSY))
mbed_official	133:d4dda5c437f0	1089
mbed_official	133:d4dda5c437f0	1090	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official	133:d4dda5c437f0	1091	/**
mbed_official	133:d4dda5c437f0	1092	* @}
mbed_official	133:d4dda5c437f0	1093	*/
mbed_official	133:d4dda5c437f0	1094
mbed_official	133:d4dda5c437f0	1095	/* Exported macro ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	1096
mbed_official	133:d4dda5c437f0	1097	/** @defgroup FMC_NOR_Macros
mbed_official	133:d4dda5c437f0	1098	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	133:d4dda5c437f0	1099	* @{
mbed_official	133:d4dda5c437f0	1100	*/
mbed_official	133:d4dda5c437f0	1101
mbed_official	133:d4dda5c437f0	1102	/**
mbed_official	133:d4dda5c437f0	1103	* @brief Enable the NORSRAM device access.
mbed_official	133:d4dda5c437f0	1104	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	133:d4dda5c437f0	1105	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	133:d4dda5c437f0	1106	* @retval None
mbed_official	133:d4dda5c437f0	1107	*/
mbed_official	133:d4dda5c437f0	1108	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
mbed_official	133:d4dda5c437f0	1109
mbed_official	133:d4dda5c437f0	1110	/**
mbed_official	133:d4dda5c437f0	1111	* @brief Disable the NORSRAM device access.
mbed_official	133:d4dda5c437f0	1112	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	133:d4dda5c437f0	1113	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	133:d4dda5c437f0	1114	* @retval None
mbed_official	133:d4dda5c437f0	1115	*/
mbed_official	133:d4dda5c437f0	1116	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official	133:d4dda5c437f0	1117
mbed_official	133:d4dda5c437f0	1118	/**
mbed_official	133:d4dda5c437f0	1119	* @}
mbed_official	133:d4dda5c437f0	1120	*/
mbed_official	133:d4dda5c437f0	1121
mbed_official	133:d4dda5c437f0	1122	/** @defgroup FMC_NAND_Macros
mbed_official	133:d4dda5c437f0	1123	* @brief macros to handle NAND device enable/disable
mbed_official	133:d4dda5c437f0	1124	* @{
mbed_official	133:d4dda5c437f0	1125	*/
mbed_official	133:d4dda5c437f0	1126
mbed_official	133:d4dda5c437f0	1127	/**
mbed_official	133:d4dda5c437f0	1128	* @brief Enable the NAND device access.
mbed_official	133:d4dda5c437f0	1129	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	133:d4dda5c437f0	1130	* @param __BANK__: FMC_NAND Bank
mbed_official	133:d4dda5c437f0	1131	* @retval None
mbed_official	133:d4dda5c437f0	1132	*/
mbed_official	133:d4dda5c437f0	1133	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
mbed_official	133:d4dda5c437f0	1134	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
mbed_official	133:d4dda5c437f0	1135
mbed_official	133:d4dda5c437f0	1136	/**
mbed_official	133:d4dda5c437f0	1137	* @brief Disable the NAND device access.
mbed_official	133:d4dda5c437f0	1138	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	133:d4dda5c437f0	1139	* @param __BANK__: FMC_NAND Bank
mbed_official	133:d4dda5c437f0	1140	* @retval None
mbed_official	133:d4dda5c437f0	1141	*/
mbed_official	133:d4dda5c437f0	1142	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
mbed_official	133:d4dda5c437f0	1143	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
mbed_official	133:d4dda5c437f0	1144	/**
mbed_official	133:d4dda5c437f0	1145	* @}
mbed_official	133:d4dda5c437f0	1146	*/
mbed_official	133:d4dda5c437f0	1147
mbed_official	133:d4dda5c437f0	1148	/** @defgroup FMC_PCCARD_Macros
mbed_official	133:d4dda5c437f0	1149	* @brief macros to handle SRAM read/write operations
mbed_official	133:d4dda5c437f0	1150	* @{
mbed_official	133:d4dda5c437f0	1151	*/
mbed_official	133:d4dda5c437f0	1152
mbed_official	133:d4dda5c437f0	1153	/**
mbed_official	133:d4dda5c437f0	1154	* @brief Enable the PCCARD device access.
mbed_official	133:d4dda5c437f0	1155	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	133:d4dda5c437f0	1156	* @retval None
mbed_official	133:d4dda5c437f0	1157	*/
mbed_official	133:d4dda5c437f0	1158	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
mbed_official	133:d4dda5c437f0	1159
mbed_official	133:d4dda5c437f0	1160	/**
mbed_official	133:d4dda5c437f0	1161	* @brief Disable the PCCARD device access.
mbed_official	133:d4dda5c437f0	1162	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	133:d4dda5c437f0	1163	* @retval None
mbed_official	133:d4dda5c437f0	1164	*/
mbed_official	133:d4dda5c437f0	1165	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
mbed_official	133:d4dda5c437f0	1166	/**
mbed_official	133:d4dda5c437f0	1167	* @}
mbed_official	133:d4dda5c437f0	1168	*/
mbed_official	133:d4dda5c437f0	1169
mbed_official	133:d4dda5c437f0	1170	/** @defgroup FMC_Interrupt
mbed_official	133:d4dda5c437f0	1171	* @brief macros to handle FMC interrupts
mbed_official	133:d4dda5c437f0	1172	* @{
mbed_official	133:d4dda5c437f0	1173	*/
mbed_official	133:d4dda5c437f0	1174
mbed_official	133:d4dda5c437f0	1175	/**
mbed_official	133:d4dda5c437f0	1176	* @brief Enable the NAND device interrupt.
mbed_official	133:d4dda5c437f0	1177	* @param __INSTANCE__: FMC_NAND instance
mbed_official	133:d4dda5c437f0	1178	* @param __BANK__: FMC_NAND Bank
mbed_official	133:d4dda5c437f0	1179	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	133:d4dda5c437f0	1180	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1181	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	133:d4dda5c437f0	1182	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	133:d4dda5c437f0	1183	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	133:d4dda5c437f0	1184	* @retval None
mbed_official	133:d4dda5c437f0	1185	*/
mbed_official	133:d4dda5c437f0	1186	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
mbed_official	133:d4dda5c437f0	1187	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
mbed_official	133:d4dda5c437f0	1188
mbed_official	133:d4dda5c437f0	1189	/**
mbed_official	133:d4dda5c437f0	1190	* @brief Disable the NAND device interrupt.
mbed_official	133:d4dda5c437f0	1191	* @param __INSTANCE__: FMC_NAND handle
mbed_official	133:d4dda5c437f0	1192	* @param __BANK__: FMC_NAND Bank
mbed_official	133:d4dda5c437f0	1193	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	133:d4dda5c437f0	1194	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1195	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	133:d4dda5c437f0	1196	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	133:d4dda5c437f0	1197	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	133:d4dda5c437f0	1198	* @retval None
mbed_official	133:d4dda5c437f0	1199	*/
mbed_official	133:d4dda5c437f0	1200	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official	133:d4dda5c437f0	1201	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official	133:d4dda5c437f0	1202
mbed_official	133:d4dda5c437f0	1203	/**
mbed_official	133:d4dda5c437f0	1204	* @brief Get flag status of the NAND device.
mbed_official	133:d4dda5c437f0	1205	* @param __INSTANCE__: FMC_NAND handle
mbed_official	133:d4dda5c437f0	1206	* @param __BANK__: FMC_NAND Bank
mbed_official	133:d4dda5c437f0	1207	* @param __FLAG__: FMC_NAND flag
mbed_official	133:d4dda5c437f0	1208	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1209	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	133:d4dda5c437f0	1210	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	133:d4dda5c437f0	1211	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	133:d4dda5c437f0	1212	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	133:d4dda5c437f0	1213	* @retval The state of FLAG (SET or RESET).
mbed_official	133:d4dda5c437f0	1214	*/
mbed_official	133:d4dda5c437f0	1215	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official	133:d4dda5c437f0	1216	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official	133:d4dda5c437f0	1217	/**
mbed_official	133:d4dda5c437f0	1218	* @brief Clear flag status of the NAND device.
mbed_official	133:d4dda5c437f0	1219	* @param __INSTANCE__: FMC_NAND handle
mbed_official	133:d4dda5c437f0	1220	* @param __BANK__: FMC_NAND Bank
mbed_official	133:d4dda5c437f0	1221	* @param __FLAG__: FMC_NAND flag
mbed_official	133:d4dda5c437f0	1222	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1223	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	133:d4dda5c437f0	1224	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	133:d4dda5c437f0	1225	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	133:d4dda5c437f0	1226	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	133:d4dda5c437f0	1227	* @retval None
mbed_official	133:d4dda5c437f0	1228	*/
mbed_official	133:d4dda5c437f0	1229	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official	133:d4dda5c437f0	1230	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	133:d4dda5c437f0	1231	/**
mbed_official	133:d4dda5c437f0	1232	* @brief Enable the PCCARD device interrupt.
mbed_official	133:d4dda5c437f0	1233	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	133:d4dda5c437f0	1234	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	133:d4dda5c437f0	1235	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1236	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	133:d4dda5c437f0	1237	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	133:d4dda5c437f0	1238	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	133:d4dda5c437f0	1239	* @retval None
mbed_official	133:d4dda5c437f0	1240	*/
mbed_official	133:d4dda5c437f0	1241	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1242
mbed_official	133:d4dda5c437f0	1243	/**
mbed_official	133:d4dda5c437f0	1244	* @brief Disable the PCCARD device interrupt.
mbed_official	133:d4dda5c437f0	1245	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	133:d4dda5c437f0	1246	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	133:d4dda5c437f0	1247	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1248	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	133:d4dda5c437f0	1249	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	133:d4dda5c437f0	1250	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	133:d4dda5c437f0	1251	* @retval None
mbed_official	133:d4dda5c437f0	1252	*/
mbed_official	133:d4dda5c437f0	1253	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1254
mbed_official	133:d4dda5c437f0	1255	/**
mbed_official	133:d4dda5c437f0	1256	* @brief Get flag status of the PCCARD device.
mbed_official	133:d4dda5c437f0	1257	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	133:d4dda5c437f0	1258	* @param __FLAG__: FMC_PCCARD flag
mbed_official	133:d4dda5c437f0	1259	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1260	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	133:d4dda5c437f0	1261	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	133:d4dda5c437f0	1262	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	133:d4dda5c437f0	1263	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	133:d4dda5c437f0	1264	* @retval The state of FLAG (SET or RESET).
mbed_official	133:d4dda5c437f0	1265	*/
mbed_official	133:d4dda5c437f0	1266	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official	133:d4dda5c437f0	1267
mbed_official	133:d4dda5c437f0	1268	/**
mbed_official	133:d4dda5c437f0	1269	* @brief Clear flag status of the PCCARD device.
mbed_official	133:d4dda5c437f0	1270	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	133:d4dda5c437f0	1271	* @param __FLAG__: FMC_PCCARD flag
mbed_official	133:d4dda5c437f0	1272	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1273	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	133:d4dda5c437f0	1274	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	133:d4dda5c437f0	1275	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	133:d4dda5c437f0	1276	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	133:d4dda5c437f0	1277	* @retval None
mbed_official	133:d4dda5c437f0	1278	*/
mbed_official	133:d4dda5c437f0	1279	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official	133:d4dda5c437f0	1280
mbed_official	133:d4dda5c437f0	1281	/**
mbed_official	133:d4dda5c437f0	1282	* @brief Enable the SDRAM device interrupt.
mbed_official	133:d4dda5c437f0	1283	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	133:d4dda5c437f0	1284	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	133:d4dda5c437f0	1285	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1286	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	133:d4dda5c437f0	1287	* @retval None
mbed_official	133:d4dda5c437f0	1288	*/
mbed_official	133:d4dda5c437f0	1289	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1290
mbed_official	133:d4dda5c437f0	1291	/**
mbed_official	133:d4dda5c437f0	1292	* @brief Disable the SDRAM device interrupt.
mbed_official	133:d4dda5c437f0	1293	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	133:d4dda5c437f0	1294	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	133:d4dda5c437f0	1295	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1296	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	133:d4dda5c437f0	1297	* @retval None
mbed_official	133:d4dda5c437f0	1298	*/
mbed_official	133:d4dda5c437f0	1299	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1300
mbed_official	133:d4dda5c437f0	1301	/**
mbed_official	133:d4dda5c437f0	1302	* @brief Get flag status of the SDRAM device.
mbed_official	133:d4dda5c437f0	1303	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	133:d4dda5c437f0	1304	* @param __FLAG__: FMC_SDRAM flag
mbed_official	133:d4dda5c437f0	1305	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1306	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
mbed_official	133:d4dda5c437f0	1307	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
mbed_official	133:d4dda5c437f0	1308	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
mbed_official	133:d4dda5c437f0	1309	* @retval The state of FLAG (SET or RESET).
mbed_official	133:d4dda5c437f0	1310	*/
mbed_official	133:d4dda5c437f0	1311	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
mbed_official	133:d4dda5c437f0	1312
mbed_official	133:d4dda5c437f0	1313	/**
mbed_official	133:d4dda5c437f0	1314	* @brief Clear flag status of the SDRAM device.
mbed_official	133:d4dda5c437f0	1315	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	133:d4dda5c437f0	1316	* @param __FLAG__: FMC_SDRAM flag
mbed_official	133:d4dda5c437f0	1317	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1318	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
mbed_official	133:d4dda5c437f0	1319	* @retval None
mbed_official	133:d4dda5c437f0	1320	*/
mbed_official	133:d4dda5c437f0	1321	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
mbed_official	133:d4dda5c437f0	1322	/**
mbed_official	133:d4dda5c437f0	1323	* @}
mbed_official	133:d4dda5c437f0	1324	*/
mbed_official	133:d4dda5c437f0	1325
mbed_official	133:d4dda5c437f0	1326	/* Exported functions --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	1327
mbed_official	133:d4dda5c437f0	1328	/* FMC_NORSRAM Controller functions *******************************************/
mbed_official	133:d4dda5c437f0	1329	/* Initialization/de-initialization functions */
mbed_official	133:d4dda5c437f0	1330	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
mbed_official	133:d4dda5c437f0	1331	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1332	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	133:d4dda5c437f0	1333	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1334
mbed_official	133:d4dda5c437f0	1335	/* FMC_NORSRAM Control functions */
mbed_official	133:d4dda5c437f0	1336	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1337	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1338
mbed_official	133:d4dda5c437f0	1339	/* FMC_NAND Controller functions **********************************************/
mbed_official	133:d4dda5c437f0	1340	/* Initialization/de-initialization functions */
mbed_official	133:d4dda5c437f0	1341	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
mbed_official	133:d4dda5c437f0	1342	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1343	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1344	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1345
mbed_official	133:d4dda5c437f0	1346	/* FMC_NAND Control functions */
mbed_official	133:d4dda5c437f0	1347	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1348	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1349	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	133:d4dda5c437f0	1350
mbed_official	133:d4dda5c437f0	1351	/* FMC_PCCARD Controller functions ********************************************/
mbed_official	133:d4dda5c437f0	1352	/* Initialization/de-initialization functions */
mbed_official	133:d4dda5c437f0	1353	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
mbed_official	133:d4dda5c437f0	1354	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	133:d4dda5c437f0	1355	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	133:d4dda5c437f0	1356	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	133:d4dda5c437f0	1357	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
mbed_official	133:d4dda5c437f0	1358
mbed_official	133:d4dda5c437f0	1359	/* FMC_SDRAM Controller functions *********************************************/
mbed_official	133:d4dda5c437f0	1360	/* Initialization/de-initialization functions */
mbed_official	133:d4dda5c437f0	1361	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
mbed_official	133:d4dda5c437f0	1362	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1363	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1364
mbed_official	133:d4dda5c437f0	1365	/* FMC_SDRAM Control functions */
mbed_official	133:d4dda5c437f0	1366	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1367	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1368	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
mbed_official	133:d4dda5c437f0	1369	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
mbed_official	133:d4dda5c437f0	1370	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
mbed_official	133:d4dda5c437f0	1371	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	133:d4dda5c437f0	1372
mbed_official	133:d4dda5c437f0	1373	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	1374	/**
mbed_official	133:d4dda5c437f0	1375	* @}
mbed_official	133:d4dda5c437f0	1376	*/
mbed_official	133:d4dda5c437f0	1377
mbed_official	133:d4dda5c437f0	1378	/**
mbed_official	133:d4dda5c437f0	1379	* @}
mbed_official	133:d4dda5c437f0	1380	*/
mbed_official	133:d4dda5c437f0	1381
mbed_official	133:d4dda5c437f0	1382	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	1383	}
mbed_official	133:d4dda5c437f0	1384	#endif
mbed_official	133:d4dda5c437f0	1385
mbed_official	133:d4dda5c437f0	1386	#endif /* __STM32F4xx_LL_FMC_H */
mbed_official	133:d4dda5c437f0	1387
mbed_official	133:d4dda5c437f0	1388	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	31 Aug 2014
Imports:	13
Forks:	0
Commits:	311
Dependents:	1
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.h@133:d4dda5c437f0, 2014-03-24 (annotated)

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