mbed-src-openwear - mbed library sources modified for open wear

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mbed library sources modified for open wear

Dependents: openwear-lifelogger-example

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.h@133:d4dda5c437f0, 2014-03-24 (annotated)

Committer:: mbed_official
Date:: Mon Mar 24 17:45:07 2014 +0000
Revision:: 133:d4dda5c437f0
Child:: 242:7074e42da0b2

Synchronized with git revision 47b961246bed973fe4cb8932781ffc8025b78a61



Full URL: https://github.com/mbedmicro/mbed/commit/47b961246bed973fe4cb8932781ffc8025b78a61/



[STM32F4-Discovery (STM32F407VG)] initial port

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_hal_tim.h
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	133:d4dda5c437f0	5	* @version V1.0.0
mbed_official	133:d4dda5c437f0	6	* @date 18-February-2014
mbed_official	133:d4dda5c437f0	7	* @brief Header file of TIM HAL module.
mbed_official	133:d4dda5c437f0	8	******************************************************************************
mbed_official	133:d4dda5c437f0	9	* @attention
mbed_official	133:d4dda5c437f0	10	*
mbed_official	133:d4dda5c437f0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	12	*
mbed_official	133:d4dda5c437f0	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	14	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	16	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	19	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	21	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	22	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	23	*
mbed_official	133:d4dda5c437f0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	34	*
mbed_official	133:d4dda5c437f0	35	******************************************************************************
mbed_official	133:d4dda5c437f0	36	*/
mbed_official	133:d4dda5c437f0	37
mbed_official	133:d4dda5c437f0	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	133:d4dda5c437f0	39	#ifndef __STM32F4xx_HAL_TIM_H
mbed_official	133:d4dda5c437f0	40	#define __STM32F4xx_HAL_TIM_H
mbed_official	133:d4dda5c437f0	41
mbed_official	133:d4dda5c437f0	42	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	43	extern "C" {
mbed_official	133:d4dda5c437f0	44	#endif
mbed_official	133:d4dda5c437f0	45
mbed_official	133:d4dda5c437f0	46	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	47	#include "stm32f4xx_hal_def.h"
mbed_official	133:d4dda5c437f0	48
mbed_official	133:d4dda5c437f0	49	/** @addtogroup STM32F4xx_HAL
mbed_official	133:d4dda5c437f0	50	* @{
mbed_official	133:d4dda5c437f0	51	*/
mbed_official	133:d4dda5c437f0	52
mbed_official	133:d4dda5c437f0	53	/** @addtogroup TIM
mbed_official	133:d4dda5c437f0	54	* @{
mbed_official	133:d4dda5c437f0	55	*/
mbed_official	133:d4dda5c437f0	56
mbed_official	133:d4dda5c437f0	57	/* Exported types ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	58
mbed_official	133:d4dda5c437f0	59	/**
mbed_official	133:d4dda5c437f0	60	* @brief TIM Time base Configuration Structure definition
mbed_official	133:d4dda5c437f0	61	*/
mbed_official	133:d4dda5c437f0	62	typedef struct
mbed_official	133:d4dda5c437f0	63	{
mbed_official	133:d4dda5c437f0	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	133:d4dda5c437f0	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	133:d4dda5c437f0	66
mbed_official	133:d4dda5c437f0	67	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	133:d4dda5c437f0	68	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	133:d4dda5c437f0	69
mbed_official	133:d4dda5c437f0	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	133:d4dda5c437f0	71	Auto-Reload Register at the next update event.
mbed_official	133:d4dda5c437f0	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	133:d4dda5c437f0	73
mbed_official	133:d4dda5c437f0	74	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	133:d4dda5c437f0	75	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	133:d4dda5c437f0	76
mbed_official	133:d4dda5c437f0	77	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	133:d4dda5c437f0	78	reaches zero, an update event is generated and counting restarts
mbed_official	133:d4dda5c437f0	79	from the RCR value (N).
mbed_official	133:d4dda5c437f0	80	This means in PWM mode that (N+1) corresponds to:
mbed_official	133:d4dda5c437f0	81	- the number of PWM periods in edge-aligned mode
mbed_official	133:d4dda5c437f0	82	- the number of half PWM period in center-aligned mode
mbed_official	133:d4dda5c437f0	83	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	133:d4dda5c437f0	84	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	85	} TIM_Base_InitTypeDef;
mbed_official	133:d4dda5c437f0	86
mbed_official	133:d4dda5c437f0	87	/**
mbed_official	133:d4dda5c437f0	88	* @brief TIM Output Compare Configuration Structure definition
mbed_official	133:d4dda5c437f0	89	*/
mbed_official	133:d4dda5c437f0	90
mbed_official	133:d4dda5c437f0	91	typedef struct
mbed_official	133:d4dda5c437f0	92	{
mbed_official	133:d4dda5c437f0	93	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	133:d4dda5c437f0	94	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	133:d4dda5c437f0	95
mbed_official	133:d4dda5c437f0	96	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	133:d4dda5c437f0	97	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	133:d4dda5c437f0	98
mbed_official	133:d4dda5c437f0	99	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	133:d4dda5c437f0	100	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	133:d4dda5c437f0	101
mbed_official	133:d4dda5c437f0	102	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	133:d4dda5c437f0	103	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	133:d4dda5c437f0	104	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	105
mbed_official	133:d4dda5c437f0	106	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	133:d4dda5c437f0	107	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	133:d4dda5c437f0	108	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	133:d4dda5c437f0	109
mbed_official	133:d4dda5c437f0	110
mbed_official	133:d4dda5c437f0	111	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	133:d4dda5c437f0	112	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	133:d4dda5c437f0	113	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	114
mbed_official	133:d4dda5c437f0	115	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	133:d4dda5c437f0	116	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	133:d4dda5c437f0	117	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	118	} TIM_OC_InitTypeDef;
mbed_official	133:d4dda5c437f0	119
mbed_official	133:d4dda5c437f0	120	/**
mbed_official	133:d4dda5c437f0	121	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	133:d4dda5c437f0	122	*/
mbed_official	133:d4dda5c437f0	123	typedef struct
mbed_official	133:d4dda5c437f0	124	{
mbed_official	133:d4dda5c437f0	125	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	133:d4dda5c437f0	126	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	133:d4dda5c437f0	127
mbed_official	133:d4dda5c437f0	128	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	133:d4dda5c437f0	129	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	133:d4dda5c437f0	130
mbed_official	133:d4dda5c437f0	131	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	133:d4dda5c437f0	132	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	133:d4dda5c437f0	133
mbed_official	133:d4dda5c437f0	134	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	133:d4dda5c437f0	135	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	133:d4dda5c437f0	136	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	137
mbed_official	133:d4dda5c437f0	138	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	133:d4dda5c437f0	139	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	133:d4dda5c437f0	140	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	141
mbed_official	133:d4dda5c437f0	142	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	133:d4dda5c437f0	143	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	133:d4dda5c437f0	144	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	133:d4dda5c437f0	145
mbed_official	133:d4dda5c437f0	146	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	133:d4dda5c437f0	147	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	133:d4dda5c437f0	148
mbed_official	133:d4dda5c437f0	149	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	133:d4dda5c437f0	150	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	133:d4dda5c437f0	151
mbed_official	133:d4dda5c437f0	152	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	133:d4dda5c437f0	153	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	133:d4dda5c437f0	154	} TIM_OnePulse_InitTypeDef;
mbed_official	133:d4dda5c437f0	155
mbed_official	133:d4dda5c437f0	156
mbed_official	133:d4dda5c437f0	157	/**
mbed_official	133:d4dda5c437f0	158	* @brief TIM Input Capture Configuration Structure definition
mbed_official	133:d4dda5c437f0	159	*/
mbed_official	133:d4dda5c437f0	160
mbed_official	133:d4dda5c437f0	161	typedef struct
mbed_official	133:d4dda5c437f0	162	{
mbed_official	133:d4dda5c437f0	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	133:d4dda5c437f0	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	133:d4dda5c437f0	165
mbed_official	133:d4dda5c437f0	166	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	133:d4dda5c437f0	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	133:d4dda5c437f0	168
mbed_official	133:d4dda5c437f0	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	133:d4dda5c437f0	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	133:d4dda5c437f0	171
mbed_official	133:d4dda5c437f0	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	133:d4dda5c437f0	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	133:d4dda5c437f0	174	} TIM_IC_InitTypeDef;
mbed_official	133:d4dda5c437f0	175
mbed_official	133:d4dda5c437f0	176	/**
mbed_official	133:d4dda5c437f0	177	* @brief TIM Encoder Configuration Structure definition
mbed_official	133:d4dda5c437f0	178	*/
mbed_official	133:d4dda5c437f0	179
mbed_official	133:d4dda5c437f0	180	typedef struct
mbed_official	133:d4dda5c437f0	181	{
mbed_official	133:d4dda5c437f0	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	133:d4dda5c437f0	183	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	133:d4dda5c437f0	184
mbed_official	133:d4dda5c437f0	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	133:d4dda5c437f0	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	133:d4dda5c437f0	187
mbed_official	133:d4dda5c437f0	188	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	133:d4dda5c437f0	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	133:d4dda5c437f0	190
mbed_official	133:d4dda5c437f0	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	133:d4dda5c437f0	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	133:d4dda5c437f0	193
mbed_official	133:d4dda5c437f0	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	133:d4dda5c437f0	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	133:d4dda5c437f0	196
mbed_official	133:d4dda5c437f0	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	133:d4dda5c437f0	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	133:d4dda5c437f0	199
mbed_official	133:d4dda5c437f0	200	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	133:d4dda5c437f0	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	133:d4dda5c437f0	202
mbed_official	133:d4dda5c437f0	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	133:d4dda5c437f0	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	133:d4dda5c437f0	205
mbed_official	133:d4dda5c437f0	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	133:d4dda5c437f0	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	133:d4dda5c437f0	208	} TIM_Encoder_InitTypeDef;
mbed_official	133:d4dda5c437f0	209
mbed_official	133:d4dda5c437f0	210	/**
mbed_official	133:d4dda5c437f0	211	* @brief Clock Configuration Handle Structure definition
mbed_official	133:d4dda5c437f0	212	*/
mbed_official	133:d4dda5c437f0	213	typedef struct
mbed_official	133:d4dda5c437f0	214	{
mbed_official	133:d4dda5c437f0	215	uint32_t ClockSource; /*!< TIM clock sources
mbed_official	133:d4dda5c437f0	216	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	133:d4dda5c437f0	217	uint32_t ClockPolarity; /*!< TIM clock polarity
mbed_official	133:d4dda5c437f0	218	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	133:d4dda5c437f0	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler
mbed_official	133:d4dda5c437f0	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	133:d4dda5c437f0	221	uint32_t ClockFilter; /*!< TIM clock filter
mbed_official	133:d4dda5c437f0	222	This parameter can be a value of @ref TIM_Clock_Filter */
mbed_official	133:d4dda5c437f0	223	}TIM_ClockConfigTypeDef;
mbed_official	133:d4dda5c437f0	224
mbed_official	133:d4dda5c437f0	225	/**
mbed_official	133:d4dda5c437f0	226	* @brief Clear Input Configuration Handle Structure definition
mbed_official	133:d4dda5c437f0	227	*/
mbed_official	133:d4dda5c437f0	228	typedef struct
mbed_official	133:d4dda5c437f0	229	{
mbed_official	133:d4dda5c437f0	230	uint32_t ClearInputState; /*!< TIM clear Input state
mbed_official	133:d4dda5c437f0	231	This parameter can be ENABLE or DISABLE */
mbed_official	133:d4dda5c437f0	232	uint32_t ClearInputSource; /*!< TIM clear Input sources
mbed_official	133:d4dda5c437f0	233	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	133:d4dda5c437f0	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
mbed_official	133:d4dda5c437f0	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	133:d4dda5c437f0	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
mbed_official	133:d4dda5c437f0	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	133:d4dda5c437f0	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
mbed_official	133:d4dda5c437f0	239	This parameter can be a value of @ref TIM_ClearInput_Filter */
mbed_official	133:d4dda5c437f0	240	}TIM_ClearInputConfigTypeDef;
mbed_official	133:d4dda5c437f0	241
mbed_official	133:d4dda5c437f0	242	/**
mbed_official	133:d4dda5c437f0	243	* @brief TIM Slave configuration Structure definition
mbed_official	133:d4dda5c437f0	244	*/
mbed_official	133:d4dda5c437f0	245	typedef struct {
mbed_official	133:d4dda5c437f0	246	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	133:d4dda5c437f0	247	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	133:d4dda5c437f0	248	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	133:d4dda5c437f0	249	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	133:d4dda5c437f0	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	133:d4dda5c437f0	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	133:d4dda5c437f0	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	133:d4dda5c437f0	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	133:d4dda5c437f0	254	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	133:d4dda5c437f0	255	This parameter can be a value of @ref TIM_Trigger_Filter */
mbed_official	133:d4dda5c437f0	256
mbed_official	133:d4dda5c437f0	257	}TIM_SlaveConfigTypeDef;
mbed_official	133:d4dda5c437f0	258
mbed_official	133:d4dda5c437f0	259	/**
mbed_official	133:d4dda5c437f0	260	* @brief HAL State structures definition
mbed_official	133:d4dda5c437f0	261	*/
mbed_official	133:d4dda5c437f0	262	typedef enum
mbed_official	133:d4dda5c437f0	263	{
mbed_official	133:d4dda5c437f0	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	133:d4dda5c437f0	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	133:d4dda5c437f0	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	133:d4dda5c437f0	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	133:d4dda5c437f0	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	133:d4dda5c437f0	269	}HAL_TIM_StateTypeDef;
mbed_official	133:d4dda5c437f0	270
mbed_official	133:d4dda5c437f0	271	/**
mbed_official	133:d4dda5c437f0	272	* @brief HAL Active channel structures definition
mbed_official	133:d4dda5c437f0	273	*/
mbed_official	133:d4dda5c437f0	274	typedef enum
mbed_official	133:d4dda5c437f0	275	{
mbed_official	133:d4dda5c437f0	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	133:d4dda5c437f0	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	133:d4dda5c437f0	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	133:d4dda5c437f0	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	133:d4dda5c437f0	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	133:d4dda5c437f0	281	}HAL_TIM_ActiveChannel;
mbed_official	133:d4dda5c437f0	282
mbed_official	133:d4dda5c437f0	283	/**
mbed_official	133:d4dda5c437f0	284	* @brief TIM Time Base Handle Structure definition
mbed_official	133:d4dda5c437f0	285	*/
mbed_official	133:d4dda5c437f0	286	typedef struct
mbed_official	133:d4dda5c437f0	287	{
mbed_official	133:d4dda5c437f0	288	TIM_TypeDef Instance; /!< Register base address */
mbed_official	133:d4dda5c437f0	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	133:d4dda5c437f0	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	133:d4dda5c437f0	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	133:d4dda5c437f0	292	This array is accessed by a @ref DMA_Handle_index */
mbed_official	133:d4dda5c437f0	293	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	133:d4dda5c437f0	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	133:d4dda5c437f0	295	}TIM_HandleTypeDef;
mbed_official	133:d4dda5c437f0	296
mbed_official	133:d4dda5c437f0	297	/* Exported constants --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	298	/** @defgroup TIM_Exported_Constants
mbed_official	133:d4dda5c437f0	299	* @{
mbed_official	133:d4dda5c437f0	300	*/
mbed_official	133:d4dda5c437f0	301
mbed_official	133:d4dda5c437f0	302	/** @defgroup TIM_Input_Channel_Polarity
mbed_official	133:d4dda5c437f0	303	* @{
mbed_official	133:d4dda5c437f0	304	*/
mbed_official	133:d4dda5c437f0	305	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	133:d4dda5c437f0	306	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	133:d4dda5c437f0	307	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	133:d4dda5c437f0	308	/**
mbed_official	133:d4dda5c437f0	309	* @}
mbed_official	133:d4dda5c437f0	310	*/
mbed_official	133:d4dda5c437f0	311
mbed_official	133:d4dda5c437f0	312	/** @defgroup TIM_ETR_Polarity
mbed_official	133:d4dda5c437f0	313	* @{
mbed_official	133:d4dda5c437f0	314	*/
mbed_official	133:d4dda5c437f0	315	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	133:d4dda5c437f0	316	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	133:d4dda5c437f0	317	/**
mbed_official	133:d4dda5c437f0	318	* @}
mbed_official	133:d4dda5c437f0	319	*/
mbed_official	133:d4dda5c437f0	320
mbed_official	133:d4dda5c437f0	321	/** @defgroup TIM_ETR_Prescaler
mbed_official	133:d4dda5c437f0	322	* @{
mbed_official	133:d4dda5c437f0	323	*/
mbed_official	133:d4dda5c437f0	324	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	133:d4dda5c437f0	325	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	133:d4dda5c437f0	326	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	133:d4dda5c437f0	327	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	133:d4dda5c437f0	328	/**
mbed_official	133:d4dda5c437f0	329	* @}
mbed_official	133:d4dda5c437f0	330	*/
mbed_official	133:d4dda5c437f0	331
mbed_official	133:d4dda5c437f0	332	/** @defgroup TIM_Counter_Mode
mbed_official	133:d4dda5c437f0	333	* @{
mbed_official	133:d4dda5c437f0	334	*/
mbed_official	133:d4dda5c437f0	335
mbed_official	133:d4dda5c437f0	336	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	337	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	133:d4dda5c437f0	338	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	133:d4dda5c437f0	339	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	133:d4dda5c437f0	340	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	133:d4dda5c437f0	341
mbed_official	133:d4dda5c437f0	342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	133:d4dda5c437f0	343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	133:d4dda5c437f0	344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	133:d4dda5c437f0	345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	133:d4dda5c437f0	346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	133:d4dda5c437f0	347	/**
mbed_official	133:d4dda5c437f0	348	* @}
mbed_official	133:d4dda5c437f0	349	*/
mbed_official	133:d4dda5c437f0	350
mbed_official	133:d4dda5c437f0	351	/** @defgroup TIM_ClockDivision
mbed_official	133:d4dda5c437f0	352	* @{
mbed_official	133:d4dda5c437f0	353	*/
mbed_official	133:d4dda5c437f0	354
mbed_official	133:d4dda5c437f0	355	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	356	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	133:d4dda5c437f0	357	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	133:d4dda5c437f0	358
mbed_official	133:d4dda5c437f0	359	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	133:d4dda5c437f0	360	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	361	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	133:d4dda5c437f0	362	/**
mbed_official	133:d4dda5c437f0	363	* @}
mbed_official	133:d4dda5c437f0	364	*/
mbed_official	133:d4dda5c437f0	365
mbed_official	133:d4dda5c437f0	366	/** @defgroup TIM_Output_Compare_and_PWM_modes
mbed_official	133:d4dda5c437f0	367	* @{
mbed_official	133:d4dda5c437f0	368	*/
mbed_official	133:d4dda5c437f0	369
mbed_official	133:d4dda5c437f0	370	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	371	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	133:d4dda5c437f0	372	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	133:d4dda5c437f0	373	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	133:d4dda5c437f0	374	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	133:d4dda5c437f0	375	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	133:d4dda5c437f0	376	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	133:d4dda5c437f0	377	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	133:d4dda5c437f0	378
mbed_official	133:d4dda5c437f0	379	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	133:d4dda5c437f0	380	((MODE) == TIM_OCMODE_PWM2))
mbed_official	133:d4dda5c437f0	381
mbed_official	133:d4dda5c437f0	382	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	133:d4dda5c437f0	383	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	133:d4dda5c437f0	384	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	133:d4dda5c437f0	385	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	133:d4dda5c437f0	386	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	133:d4dda5c437f0	387	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	133:d4dda5c437f0	388	/**
mbed_official	133:d4dda5c437f0	389	* @}
mbed_official	133:d4dda5c437f0	390	*/
mbed_official	133:d4dda5c437f0	391
mbed_official	133:d4dda5c437f0	392	/** @defgroup TIM_Output_Compare_State
mbed_official	133:d4dda5c437f0	393	* @{
mbed_official	133:d4dda5c437f0	394	*/
mbed_official	133:d4dda5c437f0	395
mbed_official	133:d4dda5c437f0	396	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	397	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	133:d4dda5c437f0	398
mbed_official	133:d4dda5c437f0	399	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	400	((STATE) == TIM_OUTPUTSTATE_ENABLE))
mbed_official	133:d4dda5c437f0	401	/**
mbed_official	133:d4dda5c437f0	402	* @}
mbed_official	133:d4dda5c437f0	403	*/
mbed_official	133:d4dda5c437f0	404	/** @defgroup TIM_Output_Fast_State
mbed_official	133:d4dda5c437f0	405	* @{
mbed_official	133:d4dda5c437f0	406	*/
mbed_official	133:d4dda5c437f0	407	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	408	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	133:d4dda5c437f0	409
mbed_official	133:d4dda5c437f0	410	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	411	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	133:d4dda5c437f0	412	/**
mbed_official	133:d4dda5c437f0	413	* @}
mbed_official	133:d4dda5c437f0	414	*/
mbed_official	133:d4dda5c437f0	415	/** @defgroup TIM_Output_Compare_N_State
mbed_official	133:d4dda5c437f0	416	* @{
mbed_official	133:d4dda5c437f0	417	*/
mbed_official	133:d4dda5c437f0	418
mbed_official	133:d4dda5c437f0	419	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	420	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	133:d4dda5c437f0	421
mbed_official	133:d4dda5c437f0	422	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	423	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
mbed_official	133:d4dda5c437f0	424	/**
mbed_official	133:d4dda5c437f0	425	* @}
mbed_official	133:d4dda5c437f0	426	*/
mbed_official	133:d4dda5c437f0	427
mbed_official	133:d4dda5c437f0	428	/** @defgroup TIM_Output_Compare_Polarity
mbed_official	133:d4dda5c437f0	429	* @{
mbed_official	133:d4dda5c437f0	430	*/
mbed_official	133:d4dda5c437f0	431
mbed_official	133:d4dda5c437f0	432	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	433	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	133:d4dda5c437f0	434
mbed_official	133:d4dda5c437f0	435	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	133:d4dda5c437f0	436	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	133:d4dda5c437f0	437	/**
mbed_official	133:d4dda5c437f0	438	* @}
mbed_official	133:d4dda5c437f0	439	*/
mbed_official	133:d4dda5c437f0	440
mbed_official	133:d4dda5c437f0	441	/** @defgroup TIM_Output_Compare_N_Polarity
mbed_official	133:d4dda5c437f0	442	* @{
mbed_official	133:d4dda5c437f0	443	*/
mbed_official	133:d4dda5c437f0	444
mbed_official	133:d4dda5c437f0	445	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	446	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	133:d4dda5c437f0	447
mbed_official	133:d4dda5c437f0	448	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	133:d4dda5c437f0	449	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	133:d4dda5c437f0	450	/**
mbed_official	133:d4dda5c437f0	451	* @}
mbed_official	133:d4dda5c437f0	452	*/
mbed_official	133:d4dda5c437f0	453
mbed_official	133:d4dda5c437f0	454	/** @defgroup TIM_Output_Compare_Idle_State
mbed_official	133:d4dda5c437f0	455	* @{
mbed_official	133:d4dda5c437f0	456	*/
mbed_official	133:d4dda5c437f0	457
mbed_official	133:d4dda5c437f0	458	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	133:d4dda5c437f0	459	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	460	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	133:d4dda5c437f0	461	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	133:d4dda5c437f0	462	/**
mbed_official	133:d4dda5c437f0	463	* @}
mbed_official	133:d4dda5c437f0	464	*/
mbed_official	133:d4dda5c437f0	465
mbed_official	133:d4dda5c437f0	466	/** @defgroup TIM_Output_Compare_N_Idle_State
mbed_official	133:d4dda5c437f0	467	* @{
mbed_official	133:d4dda5c437f0	468	*/
mbed_official	133:d4dda5c437f0	469
mbed_official	133:d4dda5c437f0	470	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	133:d4dda5c437f0	471	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	472	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	133:d4dda5c437f0	473	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	133:d4dda5c437f0	474	/**
mbed_official	133:d4dda5c437f0	475	* @}
mbed_official	133:d4dda5c437f0	476	*/
mbed_official	133:d4dda5c437f0	477
mbed_official	133:d4dda5c437f0	478	/** @defgroup TIM_Channel
mbed_official	133:d4dda5c437f0	479	* @{
mbed_official	133:d4dda5c437f0	480	*/
mbed_official	133:d4dda5c437f0	481
mbed_official	133:d4dda5c437f0	482	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	483	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	133:d4dda5c437f0	484	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	133:d4dda5c437f0	485	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	133:d4dda5c437f0	486	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	133:d4dda5c437f0	487
mbed_official	133:d4dda5c437f0	488	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	133:d4dda5c437f0	489	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	133:d4dda5c437f0	490	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	133:d4dda5c437f0	491	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	133:d4dda5c437f0	492	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	133:d4dda5c437f0	493
mbed_official	133:d4dda5c437f0	494	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	133:d4dda5c437f0	495	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	133:d4dda5c437f0	496
mbed_official	133:d4dda5c437f0	497	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	133:d4dda5c437f0	498	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	133:d4dda5c437f0	499
mbed_official	133:d4dda5c437f0	500	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	133:d4dda5c437f0	501	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	133:d4dda5c437f0	502	((CHANNEL) == TIM_CHANNEL_3))
mbed_official	133:d4dda5c437f0	503	/**
mbed_official	133:d4dda5c437f0	504	* @}
mbed_official	133:d4dda5c437f0	505	*/
mbed_official	133:d4dda5c437f0	506
mbed_official	133:d4dda5c437f0	507
mbed_official	133:d4dda5c437f0	508	/** @defgroup TIM_Input_Capture_Polarity
mbed_official	133:d4dda5c437f0	509	* @{
mbed_official	133:d4dda5c437f0	510	*/
mbed_official	133:d4dda5c437f0	511
mbed_official	133:d4dda5c437f0	512	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	133:d4dda5c437f0	513	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	133:d4dda5c437f0	514	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	133:d4dda5c437f0	515
mbed_official	133:d4dda5c437f0	516	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	133:d4dda5c437f0	517	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	133:d4dda5c437f0	518	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	133:d4dda5c437f0	519	/**
mbed_official	133:d4dda5c437f0	520	* @}
mbed_official	133:d4dda5c437f0	521	*/
mbed_official	133:d4dda5c437f0	522
mbed_official	133:d4dda5c437f0	523	/** @defgroup TIM_Input_Capture_Selection
mbed_official	133:d4dda5c437f0	524	* @{
mbed_official	133:d4dda5c437f0	525	*/
mbed_official	133:d4dda5c437f0	526
mbed_official	133:d4dda5c437f0	527	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	133:d4dda5c437f0	528	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	133:d4dda5c437f0	529	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	133:d4dda5c437f0	530	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	133:d4dda5c437f0	531	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	133:d4dda5c437f0	532
mbed_official	133:d4dda5c437f0	533	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	133:d4dda5c437f0	534	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	133:d4dda5c437f0	535	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	133:d4dda5c437f0	536	/**
mbed_official	133:d4dda5c437f0	537	* @}
mbed_official	133:d4dda5c437f0	538	*/
mbed_official	133:d4dda5c437f0	539
mbed_official	133:d4dda5c437f0	540	/** @defgroup TIM_Input_Capture_Prescaler
mbed_official	133:d4dda5c437f0	541	* @{
mbed_official	133:d4dda5c437f0	542	*/
mbed_official	133:d4dda5c437f0	543
mbed_official	133:d4dda5c437f0	544	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	133:d4dda5c437f0	545	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	133:d4dda5c437f0	546	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	133:d4dda5c437f0	547	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	133:d4dda5c437f0	548
mbed_official	133:d4dda5c437f0	549	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	133:d4dda5c437f0	550	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	551	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	133:d4dda5c437f0	552	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	133:d4dda5c437f0	553	/**
mbed_official	133:d4dda5c437f0	554	* @}
mbed_official	133:d4dda5c437f0	555	*/
mbed_official	133:d4dda5c437f0	556
mbed_official	133:d4dda5c437f0	557	/** @defgroup TIM_One_Pulse_Mode
mbed_official	133:d4dda5c437f0	558	* @{
mbed_official	133:d4dda5c437f0	559	*/
mbed_official	133:d4dda5c437f0	560
mbed_official	133:d4dda5c437f0	561	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	133:d4dda5c437f0	562	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	563	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	133:d4dda5c437f0	564	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	133:d4dda5c437f0	565	/**
mbed_official	133:d4dda5c437f0	566	* @}
mbed_official	133:d4dda5c437f0	567	*/
mbed_official	133:d4dda5c437f0	568	/** @defgroup TIM_Encoder_Mode
mbed_official	133:d4dda5c437f0	569	* @{
mbed_official	133:d4dda5c437f0	570	*/
mbed_official	133:d4dda5c437f0	571	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	133:d4dda5c437f0	572	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	133:d4dda5c437f0	573	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	133:d4dda5c437f0	574	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	133:d4dda5c437f0	575	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	133:d4dda5c437f0	576	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	133:d4dda5c437f0	577	/**
mbed_official	133:d4dda5c437f0	578	* @}
mbed_official	133:d4dda5c437f0	579	*/
mbed_official	133:d4dda5c437f0	580	/** @defgroup TIM_Interrupt_definition
mbed_official	133:d4dda5c437f0	581	* @{
mbed_official	133:d4dda5c437f0	582	*/
mbed_official	133:d4dda5c437f0	583	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	133:d4dda5c437f0	584	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	133:d4dda5c437f0	585	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	133:d4dda5c437f0	586	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	133:d4dda5c437f0	587	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	133:d4dda5c437f0	588	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	133:d4dda5c437f0	589	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	133:d4dda5c437f0	590	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	133:d4dda5c437f0	591
mbed_official	133:d4dda5c437f0	592	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	133:d4dda5c437f0	593
mbed_official	133:d4dda5c437f0	594	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
mbed_official	133:d4dda5c437f0	595	((IT) == TIM_IT_CC1) \|\| \
mbed_official	133:d4dda5c437f0	596	((IT) == TIM_IT_CC2) \|\| \
mbed_official	133:d4dda5c437f0	597	((IT) == TIM_IT_CC3) \|\| \
mbed_official	133:d4dda5c437f0	598	((IT) == TIM_IT_CC4) \|\| \
mbed_official	133:d4dda5c437f0	599	((IT) == TIM_IT_COM) \|\| \
mbed_official	133:d4dda5c437f0	600	((IT) == TIM_IT_TRIGGER) \|\| \
mbed_official	133:d4dda5c437f0	601	((IT) == TIM_IT_BREAK))
mbed_official	133:d4dda5c437f0	602	/**
mbed_official	133:d4dda5c437f0	603	* @}
mbed_official	133:d4dda5c437f0	604	*/
mbed_official	133:d4dda5c437f0	605	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	133:d4dda5c437f0	606	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	607
mbed_official	133:d4dda5c437f0	608	/** @defgroup TIM_DMA_sources
mbed_official	133:d4dda5c437f0	609	* @{
mbed_official	133:d4dda5c437f0	610	*/
mbed_official	133:d4dda5c437f0	611
mbed_official	133:d4dda5c437f0	612	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	133:d4dda5c437f0	613	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	133:d4dda5c437f0	614	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	133:d4dda5c437f0	615	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	133:d4dda5c437f0	616	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	133:d4dda5c437f0	617	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	133:d4dda5c437f0	618	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	133:d4dda5c437f0	619	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	133:d4dda5c437f0	620
mbed_official	133:d4dda5c437f0	621	/**
mbed_official	133:d4dda5c437f0	622	* @}
mbed_official	133:d4dda5c437f0	623	*/
mbed_official	133:d4dda5c437f0	624
mbed_official	133:d4dda5c437f0	625	/** @defgroup TIM_Event_Source
mbed_official	133:d4dda5c437f0	626	* @{
mbed_official	133:d4dda5c437f0	627	*/
mbed_official	133:d4dda5c437f0	628
mbed_official	133:d4dda5c437f0	629	#define TIM_EventSource_Update TIM_EGR_UG
mbed_official	133:d4dda5c437f0	630	#define TIM_EventSource_CC1 TIM_EGR_CC1G
mbed_official	133:d4dda5c437f0	631	#define TIM_EventSource_CC2 TIM_EGR_CC2G
mbed_official	133:d4dda5c437f0	632	#define TIM_EventSource_CC3 TIM_EGR_CC3G
mbed_official	133:d4dda5c437f0	633	#define TIM_EventSource_CC4 TIM_EGR_CC4G
mbed_official	133:d4dda5c437f0	634	#define TIM_EventSource_COM TIM_EGR_COMG
mbed_official	133:d4dda5c437f0	635	#define TIM_EventSource_Trigger TIM_EGR_TG
mbed_official	133:d4dda5c437f0	636	#define TIM_EventSource_Break TIM_EGR_BG
mbed_official	133:d4dda5c437f0	637	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	133:d4dda5c437f0	638
mbed_official	133:d4dda5c437f0	639	/**
mbed_official	133:d4dda5c437f0	640	* @}
mbed_official	133:d4dda5c437f0	641	*/
mbed_official	133:d4dda5c437f0	642
mbed_official	133:d4dda5c437f0	643	/** @defgroup TIM_Flag_definition
mbed_official	133:d4dda5c437f0	644	* @{
mbed_official	133:d4dda5c437f0	645	*/
mbed_official	133:d4dda5c437f0	646
mbed_official	133:d4dda5c437f0	647	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	133:d4dda5c437f0	648	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	133:d4dda5c437f0	649	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	133:d4dda5c437f0	650	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	133:d4dda5c437f0	651	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	133:d4dda5c437f0	652	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	133:d4dda5c437f0	653	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	133:d4dda5c437f0	654	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	133:d4dda5c437f0	655	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	133:d4dda5c437f0	656	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	133:d4dda5c437f0	657	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	133:d4dda5c437f0	658	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	133:d4dda5c437f0	659
mbed_official	133:d4dda5c437f0	660	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
mbed_official	133:d4dda5c437f0	661	((FLAG) == TIM_FLAG_CC1) \|\| \
mbed_official	133:d4dda5c437f0	662	((FLAG) == TIM_FLAG_CC2) \|\| \
mbed_official	133:d4dda5c437f0	663	((FLAG) == TIM_FLAG_CC3) \|\| \
mbed_official	133:d4dda5c437f0	664	((FLAG) == TIM_FLAG_CC4) \|\| \
mbed_official	133:d4dda5c437f0	665	((FLAG) == TIM_FLAG_COM) \|\| \
mbed_official	133:d4dda5c437f0	666	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	133:d4dda5c437f0	667	((FLAG) == TIM_FLAG_BREAK) \|\| \
mbed_official	133:d4dda5c437f0	668	((FLAG) == TIM_FLAG_CC1OF) \|\| \
mbed_official	133:d4dda5c437f0	669	((FLAG) == TIM_FLAG_CC2OF) \|\| \
mbed_official	133:d4dda5c437f0	670	((FLAG) == TIM_FLAG_CC3OF) \|\| \
mbed_official	133:d4dda5c437f0	671	((FLAG) == TIM_FLAG_CC4OF))
mbed_official	133:d4dda5c437f0	672	/**
mbed_official	133:d4dda5c437f0	673	* @}
mbed_official	133:d4dda5c437f0	674	*/
mbed_official	133:d4dda5c437f0	675
mbed_official	133:d4dda5c437f0	676	/** @defgroup TIM_Clock_Source
mbed_official	133:d4dda5c437f0	677	* @{
mbed_official	133:d4dda5c437f0	678	*/
mbed_official	133:d4dda5c437f0	679	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	133:d4dda5c437f0	680	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	133:d4dda5c437f0	681	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	682	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	133:d4dda5c437f0	683	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	133:d4dda5c437f0	684	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	133:d4dda5c437f0	685	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	133:d4dda5c437f0	686	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	133:d4dda5c437f0	687	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	133:d4dda5c437f0	688	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	133:d4dda5c437f0	689
mbed_official	133:d4dda5c437f0	690	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	133:d4dda5c437f0	691	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	133:d4dda5c437f0	692	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	133:d4dda5c437f0	693	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	133:d4dda5c437f0	694	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	133:d4dda5c437f0	695	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	133:d4dda5c437f0	696	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	133:d4dda5c437f0	697	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	133:d4dda5c437f0	698	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	133:d4dda5c437f0	699	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	133:d4dda5c437f0	700	/**
mbed_official	133:d4dda5c437f0	701	* @}
mbed_official	133:d4dda5c437f0	702	*/
mbed_official	133:d4dda5c437f0	703
mbed_official	133:d4dda5c437f0	704	/** @defgroup TIM_Clock_Polarity
mbed_official	133:d4dda5c437f0	705	* @{
mbed_official	133:d4dda5c437f0	706	*/
mbed_official	133:d4dda5c437f0	707	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	133:d4dda5c437f0	708	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	133:d4dda5c437f0	709	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	133:d4dda5c437f0	710	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	133:d4dda5c437f0	711	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	133:d4dda5c437f0	712
mbed_official	133:d4dda5c437f0	713	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	133:d4dda5c437f0	714	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	133:d4dda5c437f0	715	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	133:d4dda5c437f0	716	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	133:d4dda5c437f0	717	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	133:d4dda5c437f0	718	/**
mbed_official	133:d4dda5c437f0	719	* @}
mbed_official	133:d4dda5c437f0	720	*/
mbed_official	133:d4dda5c437f0	721	/** @defgroup TIM_Clock_Prescaler
mbed_official	133:d4dda5c437f0	722	* @{
mbed_official	133:d4dda5c437f0	723	*/
mbed_official	133:d4dda5c437f0	724	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	133:d4dda5c437f0	725	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	133:d4dda5c437f0	726	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	133:d4dda5c437f0	727	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	133:d4dda5c437f0	728
mbed_official	133:d4dda5c437f0	729	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	133:d4dda5c437f0	730	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	731	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	133:d4dda5c437f0	732	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	133:d4dda5c437f0	733	/**
mbed_official	133:d4dda5c437f0	734	* @}
mbed_official	133:d4dda5c437f0	735	*/
mbed_official	133:d4dda5c437f0	736	/** @defgroup TIM_Clock_Filter
mbed_official	133:d4dda5c437f0	737	* @{
mbed_official	133:d4dda5c437f0	738	*/
mbed_official	133:d4dda5c437f0	739
mbed_official	133:d4dda5c437f0	740	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	133:d4dda5c437f0	741	/**
mbed_official	133:d4dda5c437f0	742	* @}
mbed_official	133:d4dda5c437f0	743	*/
mbed_official	133:d4dda5c437f0	744
mbed_official	133:d4dda5c437f0	745	/** @defgroup TIM_ClearInput_Source
mbed_official	133:d4dda5c437f0	746	* @{
mbed_official	133:d4dda5c437f0	747	*/
mbed_official	133:d4dda5c437f0	748	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	133:d4dda5c437f0	749	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	750
mbed_official	133:d4dda5c437f0	751	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	133:d4dda5c437f0	752	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	133:d4dda5c437f0	753	/**
mbed_official	133:d4dda5c437f0	754	* @}
mbed_official	133:d4dda5c437f0	755	*/
mbed_official	133:d4dda5c437f0	756
mbed_official	133:d4dda5c437f0	757	/** @defgroup TIM_ClearInput_Polarity
mbed_official	133:d4dda5c437f0	758	* @{
mbed_official	133:d4dda5c437f0	759	*/
mbed_official	133:d4dda5c437f0	760	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	133:d4dda5c437f0	761	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	133:d4dda5c437f0	762	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	133:d4dda5c437f0	763	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	133:d4dda5c437f0	764	/**
mbed_official	133:d4dda5c437f0	765	* @}
mbed_official	133:d4dda5c437f0	766	*/
mbed_official	133:d4dda5c437f0	767
mbed_official	133:d4dda5c437f0	768	/** @defgroup TIM_ClearInput_Prescaler
mbed_official	133:d4dda5c437f0	769	* @{
mbed_official	133:d4dda5c437f0	770	*/
mbed_official	133:d4dda5c437f0	771	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	133:d4dda5c437f0	772	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	133:d4dda5c437f0	773	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	133:d4dda5c437f0	774	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	133:d4dda5c437f0	775	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	133:d4dda5c437f0	776	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	777	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	133:d4dda5c437f0	778	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	133:d4dda5c437f0	779	/**
mbed_official	133:d4dda5c437f0	780	* @}
mbed_official	133:d4dda5c437f0	781	*/
mbed_official	133:d4dda5c437f0	782
mbed_official	133:d4dda5c437f0	783	/** @defgroup TIM_ClearInput_Filter
mbed_official	133:d4dda5c437f0	784	* @{
mbed_official	133:d4dda5c437f0	785	*/
mbed_official	133:d4dda5c437f0	786
mbed_official	133:d4dda5c437f0	787	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	133:d4dda5c437f0	788	/**
mbed_official	133:d4dda5c437f0	789	* @}
mbed_official	133:d4dda5c437f0	790	*/
mbed_official	133:d4dda5c437f0	791
mbed_official	133:d4dda5c437f0	792	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
mbed_official	133:d4dda5c437f0	793	* @{
mbed_official	133:d4dda5c437f0	794	*/
mbed_official	133:d4dda5c437f0	795	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	133:d4dda5c437f0	796	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	797
mbed_official	133:d4dda5c437f0	798	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	799	((STATE) == TIM_OSSR_DISABLE))
mbed_official	133:d4dda5c437f0	800	/**
mbed_official	133:d4dda5c437f0	801	* @}
mbed_official	133:d4dda5c437f0	802	*/
mbed_official	133:d4dda5c437f0	803
mbed_official	133:d4dda5c437f0	804	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
mbed_official	133:d4dda5c437f0	805	* @{
mbed_official	133:d4dda5c437f0	806	*/
mbed_official	133:d4dda5c437f0	807	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	133:d4dda5c437f0	808	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	809
mbed_official	133:d4dda5c437f0	810	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	811	((STATE) == TIM_OSSI_DISABLE))
mbed_official	133:d4dda5c437f0	812	/**
mbed_official	133:d4dda5c437f0	813	* @}
mbed_official	133:d4dda5c437f0	814	*/
mbed_official	133:d4dda5c437f0	815	/** @defgroup TIM_Lock_level
mbed_official	133:d4dda5c437f0	816	* @{
mbed_official	133:d4dda5c437f0	817	*/
mbed_official	133:d4dda5c437f0	818	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	819	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	133:d4dda5c437f0	820	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	133:d4dda5c437f0	821	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	133:d4dda5c437f0	822
mbed_official	133:d4dda5c437f0	823	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	133:d4dda5c437f0	824	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	133:d4dda5c437f0	825	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	133:d4dda5c437f0	826	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	133:d4dda5c437f0	827	/**
mbed_official	133:d4dda5c437f0	828	* @}
mbed_official	133:d4dda5c437f0	829	*/
mbed_official	133:d4dda5c437f0	830	/** @defgroup TIM_Break_Input_enable_disable
mbed_official	133:d4dda5c437f0	831	* @{
mbed_official	133:d4dda5c437f0	832	*/
mbed_official	133:d4dda5c437f0	833	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	133:d4dda5c437f0	834	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	835
mbed_official	133:d4dda5c437f0	836	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	837	((STATE) == TIM_BREAK_DISABLE))
mbed_official	133:d4dda5c437f0	838	/**
mbed_official	133:d4dda5c437f0	839	* @}
mbed_official	133:d4dda5c437f0	840	*/
mbed_official	133:d4dda5c437f0	841	/** @defgroup TIM_Break_Polarity
mbed_official	133:d4dda5c437f0	842	* @{
mbed_official	133:d4dda5c437f0	843	*/
mbed_official	133:d4dda5c437f0	844	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	845	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	133:d4dda5c437f0	846
mbed_official	133:d4dda5c437f0	847	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	133:d4dda5c437f0	848	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	133:d4dda5c437f0	849	/**
mbed_official	133:d4dda5c437f0	850	* @}
mbed_official	133:d4dda5c437f0	851	*/
mbed_official	133:d4dda5c437f0	852	/** @defgroup TIM_AOE_Bit_Set_Reset
mbed_official	133:d4dda5c437f0	853	* @{
mbed_official	133:d4dda5c437f0	854	*/
mbed_official	133:d4dda5c437f0	855	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	133:d4dda5c437f0	856	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	857
mbed_official	133:d4dda5c437f0	858	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	859	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	133:d4dda5c437f0	860	/**
mbed_official	133:d4dda5c437f0	861	* @}
mbed_official	133:d4dda5c437f0	862	*/
mbed_official	133:d4dda5c437f0	863
mbed_official	133:d4dda5c437f0	864	/** @defgroup TIM_Master_Mode_Selection
mbed_official	133:d4dda5c437f0	865	* @{
mbed_official	133:d4dda5c437f0	866	*/
mbed_official	133:d4dda5c437f0	867	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	868	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	133:d4dda5c437f0	869	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	133:d4dda5c437f0	870	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	133:d4dda5c437f0	871	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	133:d4dda5c437f0	872	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	133:d4dda5c437f0	873	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	133:d4dda5c437f0	874	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	133:d4dda5c437f0	875
mbed_official	133:d4dda5c437f0	876	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	133:d4dda5c437f0	877	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	878	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	133:d4dda5c437f0	879	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	133:d4dda5c437f0	880	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	133:d4dda5c437f0	881	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	133:d4dda5c437f0	882	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	133:d4dda5c437f0	883	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	133:d4dda5c437f0	884
mbed_official	133:d4dda5c437f0	885
mbed_official	133:d4dda5c437f0	886	/**
mbed_official	133:d4dda5c437f0	887	* @}
mbed_official	133:d4dda5c437f0	888	*/
mbed_official	133:d4dda5c437f0	889	/** @defgroup TIM_Slave_Mode
mbed_official	133:d4dda5c437f0	890	* @{
mbed_official	133:d4dda5c437f0	891	*/
mbed_official	133:d4dda5c437f0	892	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	893	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	133:d4dda5c437f0	894	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	133:d4dda5c437f0	895	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	133:d4dda5c437f0	896	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	133:d4dda5c437f0	897
mbed_official	133:d4dda5c437f0	898	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	133:d4dda5c437f0	899	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	133:d4dda5c437f0	900	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	133:d4dda5c437f0	901	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	133:d4dda5c437f0	902	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	133:d4dda5c437f0	903	/**
mbed_official	133:d4dda5c437f0	904	* @}
mbed_official	133:d4dda5c437f0	905	*/
mbed_official	133:d4dda5c437f0	906
mbed_official	133:d4dda5c437f0	907	/** @defgroup TIM_Master_Slave_Mode
mbed_official	133:d4dda5c437f0	908	* @{
mbed_official	133:d4dda5c437f0	909	*/
mbed_official	133:d4dda5c437f0	910
mbed_official	133:d4dda5c437f0	911	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	133:d4dda5c437f0	912	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	913	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	133:d4dda5c437f0	914	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	133:d4dda5c437f0	915	/**
mbed_official	133:d4dda5c437f0	916	* @}
mbed_official	133:d4dda5c437f0	917	*/
mbed_official	133:d4dda5c437f0	918	/** @defgroup TIM_Trigger_Selection
mbed_official	133:d4dda5c437f0	919	* @{
mbed_official	133:d4dda5c437f0	920	*/
mbed_official	133:d4dda5c437f0	921
mbed_official	133:d4dda5c437f0	922	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	923	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	133:d4dda5c437f0	924	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	133:d4dda5c437f0	925	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	133:d4dda5c437f0	926	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	133:d4dda5c437f0	927	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	133:d4dda5c437f0	928	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	133:d4dda5c437f0	929	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	133:d4dda5c437f0	930	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	133:d4dda5c437f0	931	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	133:d4dda5c437f0	932	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	133:d4dda5c437f0	933	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	133:d4dda5c437f0	934	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	133:d4dda5c437f0	935	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	133:d4dda5c437f0	936	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	133:d4dda5c437f0	937	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	133:d4dda5c437f0	938	((SELECTION) == TIM_TS_ETRF))
mbed_official	133:d4dda5c437f0	939	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	133:d4dda5c437f0	940	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	133:d4dda5c437f0	941	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	133:d4dda5c437f0	942	((SELECTION) == TIM_TS_ITR3))
mbed_official	133:d4dda5c437f0	943	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	133:d4dda5c437f0	944	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	133:d4dda5c437f0	945	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	133:d4dda5c437f0	946	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	133:d4dda5c437f0	947	((SELECTION) == TIM_TS_NONE))
mbed_official	133:d4dda5c437f0	948	/**
mbed_official	133:d4dda5c437f0	949	* @}
mbed_official	133:d4dda5c437f0	950	*/
mbed_official	133:d4dda5c437f0	951
mbed_official	133:d4dda5c437f0	952	/** @defgroup TIM_Trigger_Polarity
mbed_official	133:d4dda5c437f0	953	* @{
mbed_official	133:d4dda5c437f0	954	*/
mbed_official	133:d4dda5c437f0	955	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	133:d4dda5c437f0	956	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	133:d4dda5c437f0	957	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	133:d4dda5c437f0	958	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	133:d4dda5c437f0	959	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	133:d4dda5c437f0	960
mbed_official	133:d4dda5c437f0	961	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	133:d4dda5c437f0	962	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	133:d4dda5c437f0	963	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	133:d4dda5c437f0	964	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	133:d4dda5c437f0	965	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	133:d4dda5c437f0	966	/**
mbed_official	133:d4dda5c437f0	967	* @}
mbed_official	133:d4dda5c437f0	968	*/
mbed_official	133:d4dda5c437f0	969
mbed_official	133:d4dda5c437f0	970	/** @defgroup TIM_Trigger_Prescaler
mbed_official	133:d4dda5c437f0	971	* @{
mbed_official	133:d4dda5c437f0	972	*/
mbed_official	133:d4dda5c437f0	973	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	133:d4dda5c437f0	974	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	133:d4dda5c437f0	975	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	133:d4dda5c437f0	976	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	133:d4dda5c437f0	977
mbed_official	133:d4dda5c437f0	978	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	133:d4dda5c437f0	979	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	980	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	133:d4dda5c437f0	981	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	133:d4dda5c437f0	982	/**
mbed_official	133:d4dda5c437f0	983	* @}
mbed_official	133:d4dda5c437f0	984	*/
mbed_official	133:d4dda5c437f0	985
mbed_official	133:d4dda5c437f0	986	/** @defgroup TIM_Trigger_Filter
mbed_official	133:d4dda5c437f0	987	* @{
mbed_official	133:d4dda5c437f0	988	*/
mbed_official	133:d4dda5c437f0	989
mbed_official	133:d4dda5c437f0	990	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	133:d4dda5c437f0	991	/**
mbed_official	133:d4dda5c437f0	992	* @}
mbed_official	133:d4dda5c437f0	993	*/
mbed_official	133:d4dda5c437f0	994
mbed_official	133:d4dda5c437f0	995	/** @defgroup TIM_TI1_Selection
mbed_official	133:d4dda5c437f0	996	* @{
mbed_official	133:d4dda5c437f0	997	*/
mbed_official	133:d4dda5c437f0	998
mbed_official	133:d4dda5c437f0	999	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	1000	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	133:d4dda5c437f0	1001
mbed_official	133:d4dda5c437f0	1002	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	133:d4dda5c437f0	1003	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	133:d4dda5c437f0	1004
mbed_official	133:d4dda5c437f0	1005	/**
mbed_official	133:d4dda5c437f0	1006	* @}
mbed_official	133:d4dda5c437f0	1007	*/
mbed_official	133:d4dda5c437f0	1008
mbed_official	133:d4dda5c437f0	1009	/** @defgroup TIM_DMA_Base_address
mbed_official	133:d4dda5c437f0	1010	* @{
mbed_official	133:d4dda5c437f0	1011	*/
mbed_official	133:d4dda5c437f0	1012
mbed_official	133:d4dda5c437f0	1013	#define TIM_DMABase_CR1 (0x00000000)
mbed_official	133:d4dda5c437f0	1014	#define TIM_DMABase_CR2 (0x00000001)
mbed_official	133:d4dda5c437f0	1015	#define TIM_DMABase_SMCR (0x00000002)
mbed_official	133:d4dda5c437f0	1016	#define TIM_DMABase_DIER (0x00000003)
mbed_official	133:d4dda5c437f0	1017	#define TIM_DMABase_SR (0x00000004)
mbed_official	133:d4dda5c437f0	1018	#define TIM_DMABase_EGR (0x00000005)
mbed_official	133:d4dda5c437f0	1019	#define TIM_DMABase_CCMR1 (0x00000006)
mbed_official	133:d4dda5c437f0	1020	#define TIM_DMABase_CCMR2 (0x00000007)
mbed_official	133:d4dda5c437f0	1021	#define TIM_DMABase_CCER (0x00000008)
mbed_official	133:d4dda5c437f0	1022	#define TIM_DMABase_CNT (0x00000009)
mbed_official	133:d4dda5c437f0	1023	#define TIM_DMABase_PSC (0x0000000A)
mbed_official	133:d4dda5c437f0	1024	#define TIM_DMABase_ARR (0x0000000B)
mbed_official	133:d4dda5c437f0	1025	#define TIM_DMABase_RCR (0x0000000C)
mbed_official	133:d4dda5c437f0	1026	#define TIM_DMABase_CCR1 (0x0000000D)
mbed_official	133:d4dda5c437f0	1027	#define TIM_DMABase_CCR2 (0x0000000E)
mbed_official	133:d4dda5c437f0	1028	#define TIM_DMABase_CCR3 (0x0000000F)
mbed_official	133:d4dda5c437f0	1029	#define TIM_DMABase_CCR4 (0x00000010)
mbed_official	133:d4dda5c437f0	1030	#define TIM_DMABase_BDTR (0x00000011)
mbed_official	133:d4dda5c437f0	1031	#define TIM_DMABase_DCR (0x00000012)
mbed_official	133:d4dda5c437f0	1032	#define TIM_DMABase_OR (0x00000013)
mbed_official	133:d4dda5c437f0	1033	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
mbed_official	133:d4dda5c437f0	1034	((BASE) == TIM_DMABase_CR2) \|\| \
mbed_official	133:d4dda5c437f0	1035	((BASE) == TIM_DMABase_SMCR) \|\| \
mbed_official	133:d4dda5c437f0	1036	((BASE) == TIM_DMABase_DIER) \|\| \
mbed_official	133:d4dda5c437f0	1037	((BASE) == TIM_DMABase_SR) \|\| \
mbed_official	133:d4dda5c437f0	1038	((BASE) == TIM_DMABase_EGR) \|\| \
mbed_official	133:d4dda5c437f0	1039	((BASE) == TIM_DMABase_CCMR1) \|\| \
mbed_official	133:d4dda5c437f0	1040	((BASE) == TIM_DMABase_CCMR2) \|\| \
mbed_official	133:d4dda5c437f0	1041	((BASE) == TIM_DMABase_CCER) \|\| \
mbed_official	133:d4dda5c437f0	1042	((BASE) == TIM_DMABase_CNT) \|\| \
mbed_official	133:d4dda5c437f0	1043	((BASE) == TIM_DMABase_PSC) \|\| \
mbed_official	133:d4dda5c437f0	1044	((BASE) == TIM_DMABase_ARR) \|\| \
mbed_official	133:d4dda5c437f0	1045	((BASE) == TIM_DMABase_RCR) \|\| \
mbed_official	133:d4dda5c437f0	1046	((BASE) == TIM_DMABase_CCR1) \|\| \
mbed_official	133:d4dda5c437f0	1047	((BASE) == TIM_DMABase_CCR2) \|\| \
mbed_official	133:d4dda5c437f0	1048	((BASE) == TIM_DMABase_CCR3) \|\| \
mbed_official	133:d4dda5c437f0	1049	((BASE) == TIM_DMABase_CCR4) \|\| \
mbed_official	133:d4dda5c437f0	1050	((BASE) == TIM_DMABase_BDTR) \|\| \
mbed_official	133:d4dda5c437f0	1051	((BASE) == TIM_DMABase_DCR) \|\| \
mbed_official	133:d4dda5c437f0	1052	((BASE) == TIM_DMABase_OR))
mbed_official	133:d4dda5c437f0	1053	/**
mbed_official	133:d4dda5c437f0	1054	* @}
mbed_official	133:d4dda5c437f0	1055	*/
mbed_official	133:d4dda5c437f0	1056
mbed_official	133:d4dda5c437f0	1057	/** @defgroup TIM_DMA_Burst_Length
mbed_official	133:d4dda5c437f0	1058	* @{
mbed_official	133:d4dda5c437f0	1059	*/
mbed_official	133:d4dda5c437f0	1060
mbed_official	133:d4dda5c437f0	1061	#define TIM_DMABurstLength_1Transfer (0x00000000)
mbed_official	133:d4dda5c437f0	1062	#define TIM_DMABurstLength_2Transfers (0x00000100)
mbed_official	133:d4dda5c437f0	1063	#define TIM_DMABurstLength_3Transfers (0x00000200)
mbed_official	133:d4dda5c437f0	1064	#define TIM_DMABurstLength_4Transfers (0x00000300)
mbed_official	133:d4dda5c437f0	1065	#define TIM_DMABurstLength_5Transfers (0x00000400)
mbed_official	133:d4dda5c437f0	1066	#define TIM_DMABurstLength_6Transfers (0x00000500)
mbed_official	133:d4dda5c437f0	1067	#define TIM_DMABurstLength_7Transfers (0x00000600)
mbed_official	133:d4dda5c437f0	1068	#define TIM_DMABurstLength_8Transfers (0x00000700)
mbed_official	133:d4dda5c437f0	1069	#define TIM_DMABurstLength_9Transfers (0x00000800)
mbed_official	133:d4dda5c437f0	1070	#define TIM_DMABurstLength_10Transfers (0x00000900)
mbed_official	133:d4dda5c437f0	1071	#define TIM_DMABurstLength_11Transfers (0x00000A00)
mbed_official	133:d4dda5c437f0	1072	#define TIM_DMABurstLength_12Transfers (0x00000B00)
mbed_official	133:d4dda5c437f0	1073	#define TIM_DMABurstLength_13Transfers (0x00000C00)
mbed_official	133:d4dda5c437f0	1074	#define TIM_DMABurstLength_14Transfers (0x00000D00)
mbed_official	133:d4dda5c437f0	1075	#define TIM_DMABurstLength_15Transfers (0x00000E00)
mbed_official	133:d4dda5c437f0	1076	#define TIM_DMABurstLength_16Transfers (0x00000F00)
mbed_official	133:d4dda5c437f0	1077	#define TIM_DMABurstLength_17Transfers (0x00001000)
mbed_official	133:d4dda5c437f0	1078	#define TIM_DMABurstLength_18Transfers (0x00001100)
mbed_official	133:d4dda5c437f0	1079	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
mbed_official	133:d4dda5c437f0	1080	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1081	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1082	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1083	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1084	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1085	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1086	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1087	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1088	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1089	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1090	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1091	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1092	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1093	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1094	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1095	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
mbed_official	133:d4dda5c437f0	1096	((LENGTH) == TIM_DMABurstLength_18Transfers))
mbed_official	133:d4dda5c437f0	1097	/**
mbed_official	133:d4dda5c437f0	1098	* @}
mbed_official	133:d4dda5c437f0	1099	*/
mbed_official	133:d4dda5c437f0	1100	/** @defgroup TIM_Input_Capture_Filer_Value
mbed_official	133:d4dda5c437f0	1101	* @{
mbed_official	133:d4dda5c437f0	1102	*/
mbed_official	133:d4dda5c437f0	1103
mbed_official	133:d4dda5c437f0	1104	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	133:d4dda5c437f0	1105	/**
mbed_official	133:d4dda5c437f0	1106	* @}
mbed_official	133:d4dda5c437f0	1107	*/
mbed_official	133:d4dda5c437f0	1108
mbed_official	133:d4dda5c437f0	1109	/** @defgroup DMA_Handle_index
mbed_official	133:d4dda5c437f0	1110	* @{
mbed_official	133:d4dda5c437f0	1111	*/
mbed_official	133:d4dda5c437f0	1112	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	133:d4dda5c437f0	1113	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	133:d4dda5c437f0	1114	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	133:d4dda5c437f0	1115	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	133:d4dda5c437f0	1116	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	133:d4dda5c437f0	1117	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	133:d4dda5c437f0	1118	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	133:d4dda5c437f0	1119	/**
mbed_official	133:d4dda5c437f0	1120	* @}
mbed_official	133:d4dda5c437f0	1121	*/
mbed_official	133:d4dda5c437f0	1122
mbed_official	133:d4dda5c437f0	1123	/** @defgroup Channel_CC_State
mbed_official	133:d4dda5c437f0	1124	* @{
mbed_official	133:d4dda5c437f0	1125	*/
mbed_official	133:d4dda5c437f0	1126	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	133:d4dda5c437f0	1127	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	1128	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	133:d4dda5c437f0	1129	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	133:d4dda5c437f0	1130	/**
mbed_official	133:d4dda5c437f0	1131	* @}
mbed_official	133:d4dda5c437f0	1132	*/
mbed_official	133:d4dda5c437f0	1133
mbed_official	133:d4dda5c437f0	1134	/**
mbed_official	133:d4dda5c437f0	1135	* @}
mbed_official	133:d4dda5c437f0	1136	*/
mbed_official	133:d4dda5c437f0	1137
mbed_official	133:d4dda5c437f0	1138	/* Exported macro ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	1139
mbed_official	133:d4dda5c437f0	1140	/**
mbed_official	133:d4dda5c437f0	1141	* @brief Enable the TIM peripheral.
mbed_official	133:d4dda5c437f0	1142	* @param __HANDLE__: TIM handle
mbed_official	133:d4dda5c437f0	1143	* @retval None
mbed_official	133:d4dda5c437f0	1144	*/
mbed_official	133:d4dda5c437f0	1145	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	133:d4dda5c437f0	1146
mbed_official	133:d4dda5c437f0	1147	/**
mbed_official	133:d4dda5c437f0	1148	* @brief Enable the TIM main Output.
mbed_official	133:d4dda5c437f0	1149	* @param __HANDLE__: TIM handle
mbed_official	133:d4dda5c437f0	1150	* @retval None
mbed_official	133:d4dda5c437f0	1151	*/
mbed_official	133:d4dda5c437f0	1152	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	133:d4dda5c437f0	1153
mbed_official	133:d4dda5c437f0	1154
mbed_official	133:d4dda5c437f0	1155	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	133:d4dda5c437f0	1156	channels have been disabled */
mbed_official	133:d4dda5c437f0	1157	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	133:d4dda5c437f0	1158	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	133:d4dda5c437f0	1159
mbed_official	133:d4dda5c437f0	1160	/**
mbed_official	133:d4dda5c437f0	1161	* @brief Disable the TIM peripheral.
mbed_official	133:d4dda5c437f0	1162	* @param __HANDLE__: TIM handle
mbed_official	133:d4dda5c437f0	1163	* @retval None
mbed_official	133:d4dda5c437f0	1164	*/
mbed_official	133:d4dda5c437f0	1165	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	133:d4dda5c437f0	1166	do { \
mbed_official	133:d4dda5c437f0	1167	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	133:d4dda5c437f0	1168	{ \
mbed_official	133:d4dda5c437f0	1169	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	133:d4dda5c437f0	1170	{ \
mbed_official	133:d4dda5c437f0	1171	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	133:d4dda5c437f0	1172	} \
mbed_official	133:d4dda5c437f0	1173	} \
mbed_official	133:d4dda5c437f0	1174	} while(0)
mbed_official	133:d4dda5c437f0	1175
mbed_official	133:d4dda5c437f0	1176	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
mbed_official	133:d4dda5c437f0	1177	channels have been disabled */
mbed_official	133:d4dda5c437f0	1178	/**
mbed_official	133:d4dda5c437f0	1179	* @brief Disable the TIM main Output.
mbed_official	133:d4dda5c437f0	1180	* @param __HANDLE__: TIM handle
mbed_official	133:d4dda5c437f0	1181	* @retval None
mbed_official	133:d4dda5c437f0	1182	*/
mbed_official	133:d4dda5c437f0	1183	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	133:d4dda5c437f0	1184	do { \
mbed_official	133:d4dda5c437f0	1185	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	133:d4dda5c437f0	1186	{ \
mbed_official	133:d4dda5c437f0	1187	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	133:d4dda5c437f0	1188	{ \
mbed_official	133:d4dda5c437f0	1189	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	133:d4dda5c437f0	1190	} \
mbed_official	133:d4dda5c437f0	1191	} \
mbed_official	133:d4dda5c437f0	1192	} while(0)
mbed_official	133:d4dda5c437f0	1193
mbed_official	133:d4dda5c437f0	1194	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1195	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	133:d4dda5c437f0	1196	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1197	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	133:d4dda5c437f0	1198	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	133:d4dda5c437f0	1199	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
mbed_official	133:d4dda5c437f0	1200
mbed_official	133:d4dda5c437f0	1201	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	133:d4dda5c437f0	1202	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1203
mbed_official	133:d4dda5c437f0	1204	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	133:d4dda5c437f0	1205	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC \|= (__PRESC__))
mbed_official	133:d4dda5c437f0	1206
mbed_official	133:d4dda5c437f0	1207	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	133:d4dda5c437f0	1208	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	133:d4dda5c437f0	1209	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	133:d4dda5c437f0	1210	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	133:d4dda5c437f0	1211	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	133:d4dda5c437f0	1212
mbed_official	133:d4dda5c437f0	1213	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
mbed_official	133:d4dda5c437f0	1214	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
mbed_official	133:d4dda5c437f0	1215	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
mbed_official	133:d4dda5c437f0	1216	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
mbed_official	133:d4dda5c437f0	1217	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
mbed_official	133:d4dda5c437f0	1218
mbed_official	133:d4dda5c437f0	1219	/**
mbed_official	133:d4dda5c437f0	1220	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	133:d4dda5c437f0	1221	* calling another time ConfigChannel function.
mbed_official	133:d4dda5c437f0	1222	* @param __HANDLE__: TIM handle.
mbed_official	133:d4dda5c437f0	1223	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	133:d4dda5c437f0	1224	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1225	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	133:d4dda5c437f0	1226	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	133:d4dda5c437f0	1227	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	133:d4dda5c437f0	1228	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	133:d4dda5c437f0	1229	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	133:d4dda5c437f0	1230	* @retval None
mbed_official	133:d4dda5c437f0	1231	*/
mbed_official	133:d4dda5c437f0	1232	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	133:d4dda5c437f0	1233	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	133:d4dda5c437f0	1234
mbed_official	133:d4dda5c437f0	1235	/**
mbed_official	133:d4dda5c437f0	1236	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	133:d4dda5c437f0	1237	* @param __HANDLE__: TIM handle.
mbed_official	133:d4dda5c437f0	1238	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	133:d4dda5c437f0	1239	* @retval None
mbed_official	133:d4dda5c437f0	1240	*/
mbed_official	133:d4dda5c437f0	1241	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	133:d4dda5c437f0	1242
mbed_official	133:d4dda5c437f0	1243	/**
mbed_official	133:d4dda5c437f0	1244	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	133:d4dda5c437f0	1245	* another time any Init function.
mbed_official	133:d4dda5c437f0	1246	* @param __HANDLE__: TIM handle.
mbed_official	133:d4dda5c437f0	1247	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	133:d4dda5c437f0	1248	* @retval None
mbed_official	133:d4dda5c437f0	1249	*/
mbed_official	133:d4dda5c437f0	1250	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
mbed_official	133:d4dda5c437f0	1251	do{ \
mbed_official	133:d4dda5c437f0	1252	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	133:d4dda5c437f0	1253	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	133:d4dda5c437f0	1254	} while(0)
mbed_official	133:d4dda5c437f0	1255
mbed_official	133:d4dda5c437f0	1256	/**
mbed_official	133:d4dda5c437f0	1257	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	133:d4dda5c437f0	1258	* another time any Init function.
mbed_official	133:d4dda5c437f0	1259	* @param __HANDLE__: TIM handle.
mbed_official	133:d4dda5c437f0	1260	* @param __CKD__: specifies the clock division value.
mbed_official	133:d4dda5c437f0	1261	* This parameter can be one of the following value:
mbed_official	133:d4dda5c437f0	1262	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	133:d4dda5c437f0	1263	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	133:d4dda5c437f0	1264	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	133:d4dda5c437f0	1265	* @retval None
mbed_official	133:d4dda5c437f0	1266	*/
mbed_official	133:d4dda5c437f0	1267	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
mbed_official	133:d4dda5c437f0	1268	do{ \
mbed_official	133:d4dda5c437f0	1269	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	133:d4dda5c437f0	1270	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	133:d4dda5c437f0	1271	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	133:d4dda5c437f0	1272	} while(0)
mbed_official	133:d4dda5c437f0	1273
mbed_official	133:d4dda5c437f0	1274	/**
mbed_official	133:d4dda5c437f0	1275	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	133:d4dda5c437f0	1276	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	133:d4dda5c437f0	1277	* @param __HANDLE__: TIM handle.
mbed_official	133:d4dda5c437f0	1278	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	133:d4dda5c437f0	1279	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1280	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	133:d4dda5c437f0	1281	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	133:d4dda5c437f0	1282	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	133:d4dda5c437f0	1283	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	133:d4dda5c437f0	1284	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	133:d4dda5c437f0	1285	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1286	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	133:d4dda5c437f0	1287	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	133:d4dda5c437f0	1288	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	133:d4dda5c437f0	1289	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	133:d4dda5c437f0	1290	* @retval None
mbed_official	133:d4dda5c437f0	1291	*/
mbed_official	133:d4dda5c437f0	1292	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	133:d4dda5c437f0	1293	do{ \
mbed_official	133:d4dda5c437f0	1294	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
mbed_official	133:d4dda5c437f0	1295	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	133:d4dda5c437f0	1296	} while(0)
mbed_official	133:d4dda5c437f0	1297
mbed_official	133:d4dda5c437f0	1298	/**
mbed_official	133:d4dda5c437f0	1299	* @}
mbed_official	133:d4dda5c437f0	1300	*/
mbed_official	133:d4dda5c437f0	1301
mbed_official	133:d4dda5c437f0	1302	/* Include TIM HAL Extension module */
mbed_official	133:d4dda5c437f0	1303	#include "stm32f4xx_hal_tim_ex.h"
mbed_official	133:d4dda5c437f0	1304
mbed_official	133:d4dda5c437f0	1305	/* Exported functions --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	1306
mbed_official	133:d4dda5c437f0	1307	/* Time Base functions ********************************************************/
mbed_official	133:d4dda5c437f0	1308	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1309	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1310	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1311	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1312	/* Blocking mode: Polling */
mbed_official	133:d4dda5c437f0	1313	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1314	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1315	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	1316	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1317	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1318	/* Non-Blocking mode: DMA */
mbed_official	133:d4dda5c437f0	1319	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	133:d4dda5c437f0	1320	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1321
mbed_official	133:d4dda5c437f0	1322	/* Timer Output Compare functions **********************************************/
mbed_official	133:d4dda5c437f0	1323	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1324	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1325	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1326	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1327	/* Blocking mode: Polling */
mbed_official	133:d4dda5c437f0	1328	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1329	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1330	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	1331	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1332	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1333	/* Non-Blocking mode: DMA */
mbed_official	133:d4dda5c437f0	1334	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	133:d4dda5c437f0	1335	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1336
mbed_official	133:d4dda5c437f0	1337	/* Timer PWM functions *********************************************************/
mbed_official	133:d4dda5c437f0	1338	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1339	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1340	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1341	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1342	/* Blocking mode: Polling */
mbed_official	133:d4dda5c437f0	1343	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1344	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1345	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	1346	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1347	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1348	/* Non-Blocking mode: DMA */
mbed_official	133:d4dda5c437f0	1349	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	133:d4dda5c437f0	1350	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1351
mbed_official	133:d4dda5c437f0	1352	/* Timer Input Capture functions ***********************************************/
mbed_official	133:d4dda5c437f0	1353	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1354	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1355	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1356	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1357	/* Blocking mode: Polling */
mbed_official	133:d4dda5c437f0	1358	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1359	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1360	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	1361	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1362	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1363	/* Non-Blocking mode: DMA */
mbed_official	133:d4dda5c437f0	1364	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	133:d4dda5c437f0	1365	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1366
mbed_official	133:d4dda5c437f0	1367	/* Timer One Pulse functions ***************************************************/
mbed_official	133:d4dda5c437f0	1368	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	133:d4dda5c437f0	1369	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1370	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1371	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1372	/* Blocking mode: Polling */
mbed_official	133:d4dda5c437f0	1373	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	133:d4dda5c437f0	1374	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	133:d4dda5c437f0	1375
mbed_official	133:d4dda5c437f0	1376	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	1377	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	133:d4dda5c437f0	1378	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	133:d4dda5c437f0	1379
mbed_official	133:d4dda5c437f0	1380	/* Timer Encoder functions *****************************************************/
mbed_official	133:d4dda5c437f0	1381	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	133:d4dda5c437f0	1382	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1383	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1384	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1385	/* Blocking mode: Polling */
mbed_official	133:d4dda5c437f0	1386	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1387	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1388	/* Non-Blocking mode: Interrupt */
mbed_official	133:d4dda5c437f0	1389	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1390	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1391	/* Non-Blocking mode: DMA */
mbed_official	133:d4dda5c437f0	1392	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	133:d4dda5c437f0	1393	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1394
mbed_official	133:d4dda5c437f0	1395	/* Interrupt Handler functions **********************************************/
mbed_official	133:d4dda5c437f0	1396	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1397
mbed_official	133:d4dda5c437f0	1398	/* Control functions *********************************************************/
mbed_official	133:d4dda5c437f0	1399	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1400	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1401	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1402	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	133:d4dda5c437f0	1403	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1404	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	133:d4dda5c437f0	1405	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	133:d4dda5c437f0	1406	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	133:d4dda5c437f0	1407	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	133:d4dda5c437f0	1408	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	133:d4dda5c437f0	1409	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	133:d4dda5c437f0	1410	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	133:d4dda5c437f0	1411	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	133:d4dda5c437f0	1412	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	133:d4dda5c437f0	1413	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	133:d4dda5c437f0	1414	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	133:d4dda5c437f0	1415
mbed_official	133:d4dda5c437f0	1416	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	133:d4dda5c437f0	1417	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1418	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1419	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1420	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1421	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1422	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1423
mbed_official	133:d4dda5c437f0	1424	/* Peripheral State functions **************************************************/
mbed_official	133:d4dda5c437f0	1425	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1426	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1427	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1428	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1429	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1430	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	133:d4dda5c437f0	1431
mbed_official	133:d4dda5c437f0	1432	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	133:d4dda5c437f0	1433	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	133:d4dda5c437f0	1434	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	133:d4dda5c437f0	1435	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	133:d4dda5c437f0	1436	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	133:d4dda5c437f0	1437	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	133:d4dda5c437f0	1438	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	133:d4dda5c437f0	1439
mbed_official	133:d4dda5c437f0	1440	/**
mbed_official	133:d4dda5c437f0	1441	* @}
mbed_official	133:d4dda5c437f0	1442	*/
mbed_official	133:d4dda5c437f0	1443
mbed_official	133:d4dda5c437f0	1444	/**
mbed_official	133:d4dda5c437f0	1445	* @}
mbed_official	133:d4dda5c437f0	1446	*/
mbed_official	133:d4dda5c437f0	1447
mbed_official	133:d4dda5c437f0	1448	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	1449	}
mbed_official	133:d4dda5c437f0	1450	#endif
mbed_official	133:d4dda5c437f0	1451
mbed_official	133:d4dda5c437f0	1452	#endif /* __STM32F4xx_HAL_TIM_H */
mbed_official	133:d4dda5c437f0	1453
mbed_official	133:d4dda5c437f0	1454	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	31 Aug 2014
Imports:	13
Forks:	0
Commits:	311
Dependents:	1
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.h@133:d4dda5c437f0, 2014-03-24 (annotated)

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