mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc.c@205:c41fc65bcfb4, 2014-05-22 (annotated)
- Committer:
- mbed_official
- Date:
- Thu May 22 20:00:09 2014 +0100
- Revision:
- 205:c41fc65bcfb4
- Child:
- 218:44081b78fdc2
Synchronized with git revision ea4b6f76efab17a3f7d7777b0cc1ef05fec6d1cb
Full URL: https://github.com/mbedmicro/mbed/commit/ea4b6f76efab17a3f7d7777b0cc1ef05fec6d1cb/
[NUCLEO_F072RB] cmsis files
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 205:c41fc65bcfb4 | 1 | /** |
mbed_official | 205:c41fc65bcfb4 | 2 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 3 | * @file stm32f0xx_hal_rcc.c |
mbed_official | 205:c41fc65bcfb4 | 4 | * @author MCD Application Team |
mbed_official | 205:c41fc65bcfb4 | 5 | * @version V1.0.0 |
mbed_official | 205:c41fc65bcfb4 | 6 | * @date 20-May-2014 |
mbed_official | 205:c41fc65bcfb4 | 7 | * @brief RCC HAL module driver. |
mbed_official | 205:c41fc65bcfb4 | 8 | * |
mbed_official | 205:c41fc65bcfb4 | 9 | * This file provides firmware functions to manage the following |
mbed_official | 205:c41fc65bcfb4 | 10 | * functionalities of the Reset and Clock Control (RCC) peripheral: |
mbed_official | 205:c41fc65bcfb4 | 11 | * + Initialization/de-initialization function |
mbed_official | 205:c41fc65bcfb4 | 12 | * + Peripheral Control function |
mbed_official | 205:c41fc65bcfb4 | 13 | * |
mbed_official | 205:c41fc65bcfb4 | 14 | @verbatim |
mbed_official | 205:c41fc65bcfb4 | 15 | ============================================================================== |
mbed_official | 205:c41fc65bcfb4 | 16 | ##### RCC specific features ##### |
mbed_official | 205:c41fc65bcfb4 | 17 | ============================================================================== |
mbed_official | 205:c41fc65bcfb4 | 18 | [..] |
mbed_official | 205:c41fc65bcfb4 | 19 | After reset the device is running from Internal High Speed oscillator |
mbed_official | 205:c41fc65bcfb4 | 20 | (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled, |
mbed_official | 205:c41fc65bcfb4 | 21 | and all peripherals are off except internal SRAM, Flash and JTAG. |
mbed_official | 205:c41fc65bcfb4 | 22 | (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; |
mbed_official | 205:c41fc65bcfb4 | 23 | all peripherals mapped on these busses are running at HSI speed. |
mbed_official | 205:c41fc65bcfb4 | 24 | (+) The clock for all peripherals is switched off, except the SRAM and FLASH. |
mbed_official | 205:c41fc65bcfb4 | 25 | (+) All GPIOs are in input floating state, except the JTAG pins which |
mbed_official | 205:c41fc65bcfb4 | 26 | are assigned to be used for debug purpose. |
mbed_official | 205:c41fc65bcfb4 | 27 | |
mbed_official | 205:c41fc65bcfb4 | 28 | [..] |
mbed_official | 205:c41fc65bcfb4 | 29 | Once the device started from reset, the user application has to: |
mbed_official | 205:c41fc65bcfb4 | 30 | (+) Configure the clock source to be used to drive the System clock |
mbed_official | 205:c41fc65bcfb4 | 31 | (if the application needs higher frequency/performance) |
mbed_official | 205:c41fc65bcfb4 | 32 | (+) Configure the System clock frequency and Flash settings |
mbed_official | 205:c41fc65bcfb4 | 33 | (+) Configure the AHB and APB busses prescalers |
mbed_official | 205:c41fc65bcfb4 | 34 | (+) Enable the clock for the peripheral(s) to be used |
mbed_official | 205:c41fc65bcfb4 | 35 | (+) Configure the clock source(s) for peripherals which clocks are not |
mbed_official | 205:c41fc65bcfb4 | 36 | derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) |
mbed_official | 205:c41fc65bcfb4 | 37 | @endverbatim |
mbed_official | 205:c41fc65bcfb4 | 38 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 39 | * @attention |
mbed_official | 205:c41fc65bcfb4 | 40 | * |
mbed_official | 205:c41fc65bcfb4 | 41 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 205:c41fc65bcfb4 | 42 | * |
mbed_official | 205:c41fc65bcfb4 | 43 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 205:c41fc65bcfb4 | 44 | * are permitted provided that the following conditions are met: |
mbed_official | 205:c41fc65bcfb4 | 45 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 46 | * this list of conditions and the following disclaimer. |
mbed_official | 205:c41fc65bcfb4 | 47 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 48 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 205:c41fc65bcfb4 | 49 | * and/or other materials provided with the distribution. |
mbed_official | 205:c41fc65bcfb4 | 50 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 205:c41fc65bcfb4 | 51 | * may be used to endorse or promote products derived from this software |
mbed_official | 205:c41fc65bcfb4 | 52 | * without specific prior written permission. |
mbed_official | 205:c41fc65bcfb4 | 53 | * |
mbed_official | 205:c41fc65bcfb4 | 54 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 205:c41fc65bcfb4 | 55 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 205:c41fc65bcfb4 | 56 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 205:c41fc65bcfb4 | 57 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 205:c41fc65bcfb4 | 58 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 205:c41fc65bcfb4 | 59 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 205:c41fc65bcfb4 | 60 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 205:c41fc65bcfb4 | 61 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 205:c41fc65bcfb4 | 62 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 205:c41fc65bcfb4 | 63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 205:c41fc65bcfb4 | 64 | * |
mbed_official | 205:c41fc65bcfb4 | 65 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 66 | */ |
mbed_official | 205:c41fc65bcfb4 | 67 | |
mbed_official | 205:c41fc65bcfb4 | 68 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 69 | #include "stm32f0xx_hal.h" |
mbed_official | 205:c41fc65bcfb4 | 70 | |
mbed_official | 205:c41fc65bcfb4 | 71 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 205:c41fc65bcfb4 | 72 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 73 | */ |
mbed_official | 205:c41fc65bcfb4 | 74 | |
mbed_official | 205:c41fc65bcfb4 | 75 | /** @defgroup RCC |
mbed_official | 205:c41fc65bcfb4 | 76 | * @brief RCC HAL module driver |
mbed_official | 205:c41fc65bcfb4 | 77 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 78 | */ |
mbed_official | 205:c41fc65bcfb4 | 79 | |
mbed_official | 205:c41fc65bcfb4 | 80 | #ifdef HAL_RCC_MODULE_ENABLED |
mbed_official | 205:c41fc65bcfb4 | 81 | |
mbed_official | 205:c41fc65bcfb4 | 82 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 83 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 84 | #define RCC_CFGR_HPRE_BITNUMBER 4 |
mbed_official | 205:c41fc65bcfb4 | 85 | #define RCC_CFGR_PPRE_BITNUMBER 8 |
mbed_official | 205:c41fc65bcfb4 | 86 | |
mbed_official | 205:c41fc65bcfb4 | 87 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 88 | #define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE() |
mbed_official | 205:c41fc65bcfb4 | 89 | #define MCO_GPIO_PORT GPIOA |
mbed_official | 205:c41fc65bcfb4 | 90 | #define MCO_PIN GPIO_PIN_8 |
mbed_official | 205:c41fc65bcfb4 | 91 | |
mbed_official | 205:c41fc65bcfb4 | 92 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 93 | const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 205:c41fc65bcfb4 | 94 | |
mbed_official | 205:c41fc65bcfb4 | 95 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 96 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 97 | |
mbed_official | 205:c41fc65bcfb4 | 98 | /** @defgroup RCC_Private_Functions |
mbed_official | 205:c41fc65bcfb4 | 99 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 100 | */ |
mbed_official | 205:c41fc65bcfb4 | 101 | |
mbed_official | 205:c41fc65bcfb4 | 102 | /** @defgroup HAL_RCC_Group1 Initialization/de-initialization function |
mbed_official | 205:c41fc65bcfb4 | 103 | * @brief Initialization and Configuration functions |
mbed_official | 205:c41fc65bcfb4 | 104 | * |
mbed_official | 205:c41fc65bcfb4 | 105 | @verbatim |
mbed_official | 205:c41fc65bcfb4 | 106 | =============================================================================== |
mbed_official | 205:c41fc65bcfb4 | 107 | ##### Initialization and de-initialization function ##### |
mbed_official | 205:c41fc65bcfb4 | 108 | =============================================================================== |
mbed_official | 205:c41fc65bcfb4 | 109 | [..] |
mbed_official | 205:c41fc65bcfb4 | 110 | This section provide functions allowing to configure the internal/external oscillators |
mbed_official | 205:c41fc65bcfb4 | 111 | (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, |
mbed_official | 205:c41fc65bcfb4 | 112 | AHB and APB1). |
mbed_official | 205:c41fc65bcfb4 | 113 | |
mbed_official | 205:c41fc65bcfb4 | 114 | [..] Internal/external clock and PLL configuration |
mbed_official | 205:c41fc65bcfb4 | 115 | (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through |
mbed_official | 205:c41fc65bcfb4 | 116 | the PLL as System clock source. |
mbed_official | 205:c41fc65bcfb4 | 117 | The HSI clock can be used also to clock the USART and I2C peripherals. |
mbed_official | 205:c41fc65bcfb4 | 118 | |
mbed_official | 205:c41fc65bcfb4 | 119 | (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock |
mbed_official | 205:c41fc65bcfb4 | 120 | the ADC peripheral. |
mbed_official | 205:c41fc65bcfb4 | 121 | |
mbed_official | 205:c41fc65bcfb4 | 122 | (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC |
mbed_official | 205:c41fc65bcfb4 | 123 | clock source. |
mbed_official | 205:c41fc65bcfb4 | 124 | |
mbed_official | 205:c41fc65bcfb4 | 125 | (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or |
mbed_official | 205:c41fc65bcfb4 | 126 | through the PLL as System clock source. Can be used also as RTC clock source. |
mbed_official | 205:c41fc65bcfb4 | 127 | |
mbed_official | 205:c41fc65bcfb4 | 128 | (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. |
mbed_official | 205:c41fc65bcfb4 | 129 | |
mbed_official | 205:c41fc65bcfb4 | 130 | (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: |
mbed_official | 205:c41fc65bcfb4 | 131 | (+@) The first output is used to generate the high speed system clock (up to 48 MHz) |
mbed_official | 205:c41fc65bcfb4 | 132 | (+@) The second output is used to generate the clock for the USB FS (48 MHz) |
mbed_official | 205:c41fc65bcfb4 | 133 | (+@) The third output may be used to generate the clock for the TIM, I2C and USART |
mbed_official | 205:c41fc65bcfb4 | 134 | peripherals (up to 48 MHz) |
mbed_official | 205:c41fc65bcfb4 | 135 | |
mbed_official | 205:c41fc65bcfb4 | 136 | (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() |
mbed_official | 205:c41fc65bcfb4 | 137 | and if a HSE clock failure occurs(HSE used directly or through PLL as System |
mbed_official | 205:c41fc65bcfb4 | 138 | clock source), the System clockis automatically switched to HSI and an interrupt |
mbed_official | 205:c41fc65bcfb4 | 139 | is generated if enabled. The interrupt is linked to the Cortex-M0 NMI |
mbed_official | 205:c41fc65bcfb4 | 140 | (Non-Maskable Interrupt) exception vector. |
mbed_official | 205:c41fc65bcfb4 | 141 | |
mbed_official | 205:c41fc65bcfb4 | 142 | (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL |
mbed_official | 205:c41fc65bcfb4 | 143 | clock (divided by 2) output on pin (such as PA8 pin). |
mbed_official | 205:c41fc65bcfb4 | 144 | |
mbed_official | 205:c41fc65bcfb4 | 145 | [..] System, AHB and APB busses clocks configuration |
mbed_official | 205:c41fc65bcfb4 | 146 | (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, |
mbed_official | 205:c41fc65bcfb4 | 147 | HSE and PLL. |
mbed_official | 205:c41fc65bcfb4 | 148 | The AHB clock (HCLK) is derived from System clock through configurable |
mbed_official | 205:c41fc65bcfb4 | 149 | prescaler and used to clock the CPU, memory and peripherals mapped |
mbed_official | 205:c41fc65bcfb4 | 150 | on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived |
mbed_official | 205:c41fc65bcfb4 | 151 | from AHB clock through configurable prescalers and used to clock |
mbed_official | 205:c41fc65bcfb4 | 152 | the peripherals mapped on these busses. You can use |
mbed_official | 205:c41fc65bcfb4 | 153 | "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. |
mbed_official | 205:c41fc65bcfb4 | 154 | |
mbed_official | 205:c41fc65bcfb4 | 155 | (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: |
mbed_official | 205:c41fc65bcfb4 | 156 | (+@) The FLASH program/erase clock which is always HSI 8MHz clock. |
mbed_official | 205:c41fc65bcfb4 | 157 | (+@) The USB 48 MHz clock which is derived from the PLL VCO clock. |
mbed_official | 205:c41fc65bcfb4 | 158 | (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. |
mbed_official | 205:c41fc65bcfb4 | 159 | (+@) The I2C clock which can be derived as well from HSI 8MHz clock. |
mbed_official | 205:c41fc65bcfb4 | 160 | (+@) The ADC clock which is derived from PLL output. |
mbed_official | 205:c41fc65bcfb4 | 161 | (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC |
mbed_official | 205:c41fc65bcfb4 | 162 | (HSE divided by a programmable prescaler). The System clock (SYSCLK) |
mbed_official | 205:c41fc65bcfb4 | 163 | frequency must be higher or equal to the RTC clock frequency. |
mbed_official | 205:c41fc65bcfb4 | 164 | (+@) IWDG clock which is always the LSI clock. |
mbed_official | 205:c41fc65bcfb4 | 165 | |
mbed_official | 205:c41fc65bcfb4 | 166 | (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, |
mbed_official | 205:c41fc65bcfb4 | 167 | Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: |
mbed_official | 205:c41fc65bcfb4 | 168 | +-----------------------------------------------+ |
mbed_official | 205:c41fc65bcfb4 | 169 | | Latency | SYSCLK clock frequency (MHz) | |
mbed_official | 205:c41fc65bcfb4 | 170 | |---------------|-------------------------------| |
mbed_official | 205:c41fc65bcfb4 | 171 | |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | |
mbed_official | 205:c41fc65bcfb4 | 172 | |---------------|-------------------------------| |
mbed_official | 205:c41fc65bcfb4 | 173 | |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | |
mbed_official | 205:c41fc65bcfb4 | 174 | +-----------------------------------------------+ |
mbed_official | 205:c41fc65bcfb4 | 175 | |
mbed_official | 205:c41fc65bcfb4 | 176 | (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and |
mbed_official | 205:c41fc65bcfb4 | 177 | prefetch is disabled. |
mbed_official | 205:c41fc65bcfb4 | 178 | |
mbed_official | 205:c41fc65bcfb4 | 179 | @endverbatim |
mbed_official | 205:c41fc65bcfb4 | 180 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 181 | */ |
mbed_official | 205:c41fc65bcfb4 | 182 | |
mbed_official | 205:c41fc65bcfb4 | 183 | /** |
mbed_official | 205:c41fc65bcfb4 | 184 | * @brief Resets the RCC clock configuration to the default reset state. |
mbed_official | 205:c41fc65bcfb4 | 185 | * @note The default reset state of the clock configuration is given below: |
mbed_official | 205:c41fc65bcfb4 | 186 | * - HSI ON and used as system clock source |
mbed_official | 205:c41fc65bcfb4 | 187 | * - HSE and PLL OFF |
mbed_official | 205:c41fc65bcfb4 | 188 | * - AHB, APB1 prescaler set to 1. |
mbed_official | 205:c41fc65bcfb4 | 189 | * - CSS, MCO OFF |
mbed_official | 205:c41fc65bcfb4 | 190 | * - All interrupts disabled |
mbed_official | 205:c41fc65bcfb4 | 191 | * @note This function doesn't modify the configuration of the |
mbed_official | 205:c41fc65bcfb4 | 192 | * - Peripheral clocks |
mbed_official | 205:c41fc65bcfb4 | 193 | * - LSI, LSE and RTC clocks |
mbed_official | 205:c41fc65bcfb4 | 194 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 195 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 196 | */ |
mbed_official | 205:c41fc65bcfb4 | 197 | void HAL_RCC_DeInit(void) |
mbed_official | 205:c41fc65bcfb4 | 198 | { |
mbed_official | 205:c41fc65bcfb4 | 199 | /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ |
mbed_official | 205:c41fc65bcfb4 | 200 | SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); |
mbed_official | 205:c41fc65bcfb4 | 201 | |
mbed_official | 205:c41fc65bcfb4 | 202 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ |
mbed_official | 205:c41fc65bcfb4 | 203 | CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); |
mbed_official | 205:c41fc65bcfb4 | 204 | |
mbed_official | 205:c41fc65bcfb4 | 205 | /* Reset HSEON, CSSON, PLLON bits */ |
mbed_official | 205:c41fc65bcfb4 | 206 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); |
mbed_official | 205:c41fc65bcfb4 | 207 | |
mbed_official | 205:c41fc65bcfb4 | 208 | /* Reset HSEBYP bit */ |
mbed_official | 205:c41fc65bcfb4 | 209 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
mbed_official | 205:c41fc65bcfb4 | 210 | |
mbed_official | 205:c41fc65bcfb4 | 211 | /* Reset CFGR register */ |
mbed_official | 205:c41fc65bcfb4 | 212 | CLEAR_REG(RCC->CFGR); |
mbed_official | 205:c41fc65bcfb4 | 213 | |
mbed_official | 205:c41fc65bcfb4 | 214 | /* Reset CFGR2 register */ |
mbed_official | 205:c41fc65bcfb4 | 215 | CLEAR_REG(RCC->CFGR2); |
mbed_official | 205:c41fc65bcfb4 | 216 | |
mbed_official | 205:c41fc65bcfb4 | 217 | /* Reset CFGR3 register */ |
mbed_official | 205:c41fc65bcfb4 | 218 | CLEAR_REG(RCC->CFGR3); |
mbed_official | 205:c41fc65bcfb4 | 219 | |
mbed_official | 205:c41fc65bcfb4 | 220 | /* Disable all interrupts */ |
mbed_official | 205:c41fc65bcfb4 | 221 | CLEAR_REG(RCC->CIR); |
mbed_official | 205:c41fc65bcfb4 | 222 | } |
mbed_official | 205:c41fc65bcfb4 | 223 | |
mbed_official | 205:c41fc65bcfb4 | 224 | /** |
mbed_official | 205:c41fc65bcfb4 | 225 | * @brief Initializes the RCC Oscillators according to the specified parameters in the |
mbed_official | 205:c41fc65bcfb4 | 226 | * RCC_OscInitTypeDef. |
mbed_official | 205:c41fc65bcfb4 | 227 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 205:c41fc65bcfb4 | 228 | * contains the configuration information for the RCC Oscillators. |
mbed_official | 205:c41fc65bcfb4 | 229 | * @note The PLL is not disabled when used as system clock. |
mbed_official | 205:c41fc65bcfb4 | 230 | * @retval HAL status |
mbed_official | 205:c41fc65bcfb4 | 231 | */ |
mbed_official | 205:c41fc65bcfb4 | 232 | __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
mbed_official | 205:c41fc65bcfb4 | 233 | { |
mbed_official | 205:c41fc65bcfb4 | 234 | /* Note : This function is defined into this file for library reference. */ |
mbed_official | 205:c41fc65bcfb4 | 235 | /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ |
mbed_official | 205:c41fc65bcfb4 | 236 | /* handle the possible oscillators present in STM32F0xx devices */ |
mbed_official | 205:c41fc65bcfb4 | 237 | |
mbed_official | 205:c41fc65bcfb4 | 238 | /* Return error status as not implemented here */ |
mbed_official | 205:c41fc65bcfb4 | 239 | return HAL_ERROR; |
mbed_official | 205:c41fc65bcfb4 | 240 | } |
mbed_official | 205:c41fc65bcfb4 | 241 | |
mbed_official | 205:c41fc65bcfb4 | 242 | /** |
mbed_official | 205:c41fc65bcfb4 | 243 | * @brief Initializes the CPU, AHB and APB busses clocks according to the specified |
mbed_official | 205:c41fc65bcfb4 | 244 | * parameters in the RCC_ClkInitStruct. |
mbed_official | 205:c41fc65bcfb4 | 245 | * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 205:c41fc65bcfb4 | 246 | * contains the configuration information for the RCC peripheral. |
mbed_official | 205:c41fc65bcfb4 | 247 | * @param FLatency: FLASH Latency |
mbed_official | 205:c41fc65bcfb4 | 248 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 249 | * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle |
mbed_official | 205:c41fc65bcfb4 | 250 | * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle |
mbed_official | 205:c41fc65bcfb4 | 251 | * |
mbed_official | 205:c41fc65bcfb4 | 252 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
mbed_official | 205:c41fc65bcfb4 | 253 | * and updated by HAL_RCC_GetHCLKFreq() function called within this function |
mbed_official | 205:c41fc65bcfb4 | 254 | * |
mbed_official | 205:c41fc65bcfb4 | 255 | * @note The HSI is used (enabled by hardware) as system clock source after |
mbed_official | 205:c41fc65bcfb4 | 256 | * startup from Reset, wake-up from STOP and STANDBY mode, or in case |
mbed_official | 205:c41fc65bcfb4 | 257 | * of failure of the HSE used directly or indirectly as system clock |
mbed_official | 205:c41fc65bcfb4 | 258 | * (if the Clock Security System CSS is enabled). |
mbed_official | 205:c41fc65bcfb4 | 259 | * |
mbed_official | 205:c41fc65bcfb4 | 260 | * @note A switch from one clock source to another occurs only if the target |
mbed_official | 205:c41fc65bcfb4 | 261 | * clock source is ready (clock stable after startup delay or PLL locked). |
mbed_official | 205:c41fc65bcfb4 | 262 | * If a clock source which is not yet ready is selected, the switch will |
mbed_official | 205:c41fc65bcfb4 | 263 | * occur when the clock source will be ready. |
mbed_official | 205:c41fc65bcfb4 | 264 | * @retval HAL status |
mbed_official | 205:c41fc65bcfb4 | 265 | */ |
mbed_official | 205:c41fc65bcfb4 | 266 | __weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) |
mbed_official | 205:c41fc65bcfb4 | 267 | { |
mbed_official | 205:c41fc65bcfb4 | 268 | /* Note : This function is defined into this file for library reference. */ |
mbed_official | 205:c41fc65bcfb4 | 269 | /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ |
mbed_official | 205:c41fc65bcfb4 | 270 | /* handle the possible oscillators present in STM32F0xx devices */ |
mbed_official | 205:c41fc65bcfb4 | 271 | |
mbed_official | 205:c41fc65bcfb4 | 272 | /* Return error status as not implemented here */ |
mbed_official | 205:c41fc65bcfb4 | 273 | return HAL_ERROR; |
mbed_official | 205:c41fc65bcfb4 | 274 | } |
mbed_official | 205:c41fc65bcfb4 | 275 | |
mbed_official | 205:c41fc65bcfb4 | 276 | /** |
mbed_official | 205:c41fc65bcfb4 | 277 | * @} |
mbed_official | 205:c41fc65bcfb4 | 278 | */ |
mbed_official | 205:c41fc65bcfb4 | 279 | |
mbed_official | 205:c41fc65bcfb4 | 280 | /** @defgroup HAL_RCC_Group2 Peripheral Control function |
mbed_official | 205:c41fc65bcfb4 | 281 | * @brief RCC clocks control functions |
mbed_official | 205:c41fc65bcfb4 | 282 | * |
mbed_official | 205:c41fc65bcfb4 | 283 | @verbatim |
mbed_official | 205:c41fc65bcfb4 | 284 | =============================================================================== |
mbed_official | 205:c41fc65bcfb4 | 285 | ##### Peripheral Control function ##### |
mbed_official | 205:c41fc65bcfb4 | 286 | =============================================================================== |
mbed_official | 205:c41fc65bcfb4 | 287 | [..] |
mbed_official | 205:c41fc65bcfb4 | 288 | This subsection provides a set of functions allowing to control the RCC Clocks |
mbed_official | 205:c41fc65bcfb4 | 289 | frequencies. |
mbed_official | 205:c41fc65bcfb4 | 290 | |
mbed_official | 205:c41fc65bcfb4 | 291 | @endverbatim |
mbed_official | 205:c41fc65bcfb4 | 292 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 293 | */ |
mbed_official | 205:c41fc65bcfb4 | 294 | |
mbed_official | 205:c41fc65bcfb4 | 295 | /** |
mbed_official | 205:c41fc65bcfb4 | 296 | * @brief Selects the clock source to output on MCO pin(such as PA8). |
mbed_official | 205:c41fc65bcfb4 | 297 | * @note MCO pin (such as PA8) should be configured in alternate function mode. |
mbed_official | 205:c41fc65bcfb4 | 298 | * @param RCC_MCOx: specifies the output direction for the clock source. |
mbed_official | 205:c41fc65bcfb4 | 299 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 300 | * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8). |
mbed_official | 205:c41fc65bcfb4 | 301 | * @param RCC_MCOSource: specifies the clock source to output. |
mbed_official | 205:c41fc65bcfb4 | 302 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 303 | * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source |
mbed_official | 205:c41fc65bcfb4 | 304 | * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source |
mbed_official | 205:c41fc65bcfb4 | 305 | * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source |
mbed_official | 205:c41fc65bcfb4 | 306 | * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source |
mbed_official | 205:c41fc65bcfb4 | 307 | * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices) |
mbed_official | 205:c41fc65bcfb4 | 308 | * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source |
mbed_official | 205:c41fc65bcfb4 | 309 | * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source |
mbed_official | 205:c41fc65bcfb4 | 310 | * @param RCC_MCODiv: specifies the MCOx prescaler. |
mbed_official | 205:c41fc65bcfb4 | 311 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 312 | * @arg RCC_MCO_NODIV: no division applied to MCO clock |
mbed_official | 205:c41fc65bcfb4 | 313 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 314 | */ |
mbed_official | 205:c41fc65bcfb4 | 315 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) |
mbed_official | 205:c41fc65bcfb4 | 316 | { |
mbed_official | 205:c41fc65bcfb4 | 317 | GPIO_InitTypeDef gpio; |
mbed_official | 205:c41fc65bcfb4 | 318 | /* Check the parameters */ |
mbed_official | 205:c41fc65bcfb4 | 319 | assert_param(IS_RCC_MCO(RCC_MCOx)); |
mbed_official | 205:c41fc65bcfb4 | 320 | assert_param(IS_RCC_MCODIV(RCC_MCODiv)); |
mbed_official | 205:c41fc65bcfb4 | 321 | /* RCC_MCO */ |
mbed_official | 205:c41fc65bcfb4 | 322 | assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource)); |
mbed_official | 205:c41fc65bcfb4 | 323 | |
mbed_official | 205:c41fc65bcfb4 | 324 | /* MCO Clock Enable */ |
mbed_official | 205:c41fc65bcfb4 | 325 | __MCO_CLK_ENABLE(); |
mbed_official | 205:c41fc65bcfb4 | 326 | |
mbed_official | 205:c41fc65bcfb4 | 327 | /* Configue the MCO pin in alternate function mode */ |
mbed_official | 205:c41fc65bcfb4 | 328 | gpio.Pin = MCO_PIN; |
mbed_official | 205:c41fc65bcfb4 | 329 | gpio.Mode = GPIO_MODE_AF_PP; |
mbed_official | 205:c41fc65bcfb4 | 330 | gpio.Speed = GPIO_SPEED_HIGH; |
mbed_official | 205:c41fc65bcfb4 | 331 | gpio.Pull = GPIO_NOPULL; |
mbed_official | 205:c41fc65bcfb4 | 332 | gpio.Alternate = GPIO_AF0_MCO; |
mbed_official | 205:c41fc65bcfb4 | 333 | HAL_GPIO_Init(MCO_GPIO_PORT, &gpio); |
mbed_official | 205:c41fc65bcfb4 | 334 | |
mbed_official | 205:c41fc65bcfb4 | 335 | /* Configure the MCO clock source */ |
mbed_official | 205:c41fc65bcfb4 | 336 | __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv); |
mbed_official | 205:c41fc65bcfb4 | 337 | } |
mbed_official | 205:c41fc65bcfb4 | 338 | |
mbed_official | 205:c41fc65bcfb4 | 339 | /** |
mbed_official | 205:c41fc65bcfb4 | 340 | * @brief Enables the Clock Security System. |
mbed_official | 205:c41fc65bcfb4 | 341 | * @note If a failure is detected on the HSE oscillator clock, this oscillator |
mbed_official | 205:c41fc65bcfb4 | 342 | * is automatically disabled and an interrupt is generated to inform the |
mbed_official | 205:c41fc65bcfb4 | 343 | * software about the failure (Clock Security System Interrupt, CSSI), |
mbed_official | 205:c41fc65bcfb4 | 344 | * allowing the MCU to perform rescue operations. The CSSI is linked to |
mbed_official | 205:c41fc65bcfb4 | 345 | * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. |
mbed_official | 205:c41fc65bcfb4 | 346 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 347 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 348 | */ |
mbed_official | 205:c41fc65bcfb4 | 349 | void HAL_RCC_EnableCSS(void) |
mbed_official | 205:c41fc65bcfb4 | 350 | { |
mbed_official | 205:c41fc65bcfb4 | 351 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
mbed_official | 205:c41fc65bcfb4 | 352 | } |
mbed_official | 205:c41fc65bcfb4 | 353 | |
mbed_official | 205:c41fc65bcfb4 | 354 | /** |
mbed_official | 205:c41fc65bcfb4 | 355 | * @brief Disables the Clock Security System. |
mbed_official | 205:c41fc65bcfb4 | 356 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 357 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 358 | */ |
mbed_official | 205:c41fc65bcfb4 | 359 | void HAL_RCC_DisableCSS(void) |
mbed_official | 205:c41fc65bcfb4 | 360 | { |
mbed_official | 205:c41fc65bcfb4 | 361 | CLEAR_BIT(RCC->CR, RCC_CR_CSSON); |
mbed_official | 205:c41fc65bcfb4 | 362 | } |
mbed_official | 205:c41fc65bcfb4 | 363 | |
mbed_official | 205:c41fc65bcfb4 | 364 | /** |
mbed_official | 205:c41fc65bcfb4 | 365 | * @brief Returns the SYSCLK frequency |
mbed_official | 205:c41fc65bcfb4 | 366 | * @note The system frequency computed by this function is not the real |
mbed_official | 205:c41fc65bcfb4 | 367 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 205:c41fc65bcfb4 | 368 | * constant and the selected clock source: |
mbed_official | 205:c41fc65bcfb4 | 369 | * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*) |
mbed_official | 205:c41fc65bcfb4 | 370 | * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*) |
mbed_official | 205:c41fc65bcfb4 | 371 | * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE |
mbed_official | 205:c41fc65bcfb4 | 372 | * divided by PREDIV factor(**) |
mbed_official | 205:c41fc65bcfb4 | 373 | * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE |
mbed_official | 205:c41fc65bcfb4 | 374 | * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based |
mbed_official | 205:c41fc65bcfb4 | 375 | * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the |
mbed_official | 205:c41fc65bcfb4 | 376 | * PLL factor . |
mbed_official | 205:c41fc65bcfb4 | 377 | * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file |
mbed_official | 205:c41fc65bcfb4 | 378 | * (default values 8 MHz and 48MHz). |
mbed_official | 205:c41fc65bcfb4 | 379 | * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value |
mbed_official | 205:c41fc65bcfb4 | 380 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 205:c41fc65bcfb4 | 381 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 205:c41fc65bcfb4 | 382 | * have wrong result. |
mbed_official | 205:c41fc65bcfb4 | 383 | * |
mbed_official | 205:c41fc65bcfb4 | 384 | * @note The result of this function could be not correct when using fractional |
mbed_official | 205:c41fc65bcfb4 | 385 | * value for HSE crystal. |
mbed_official | 205:c41fc65bcfb4 | 386 | * |
mbed_official | 205:c41fc65bcfb4 | 387 | * @note This function can be used by the user application to compute the |
mbed_official | 205:c41fc65bcfb4 | 388 | * baudrate for the communication peripherals or configure other parameters. |
mbed_official | 205:c41fc65bcfb4 | 389 | * |
mbed_official | 205:c41fc65bcfb4 | 390 | * @note Each time SYSCLK changes, this function must be called to update the |
mbed_official | 205:c41fc65bcfb4 | 391 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 205:c41fc65bcfb4 | 392 | * |
mbed_official | 205:c41fc65bcfb4 | 393 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 394 | * @retval SYSCLK frequency |
mbed_official | 205:c41fc65bcfb4 | 395 | */ |
mbed_official | 205:c41fc65bcfb4 | 396 | __weak uint32_t HAL_RCC_GetSysClockFreq(void) |
mbed_official | 205:c41fc65bcfb4 | 397 | { |
mbed_official | 205:c41fc65bcfb4 | 398 | /* Note : This function is defined into this file for library reference. */ |
mbed_official | 205:c41fc65bcfb4 | 399 | /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ |
mbed_official | 205:c41fc65bcfb4 | 400 | /* handle the possible oscillators present in STM32F0xx devices */ |
mbed_official | 205:c41fc65bcfb4 | 401 | |
mbed_official | 205:c41fc65bcfb4 | 402 | /* Return current SYSCLK frequency without computation */ |
mbed_official | 205:c41fc65bcfb4 | 403 | return SystemCoreClock; |
mbed_official | 205:c41fc65bcfb4 | 404 | } |
mbed_official | 205:c41fc65bcfb4 | 405 | |
mbed_official | 205:c41fc65bcfb4 | 406 | /** |
mbed_official | 205:c41fc65bcfb4 | 407 | * @brief Returns the HCLK frequency |
mbed_official | 205:c41fc65bcfb4 | 408 | * @note Each time HCLK changes, this function must be called to update the |
mbed_official | 205:c41fc65bcfb4 | 409 | * right HCLK value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 205:c41fc65bcfb4 | 410 | * |
mbed_official | 205:c41fc65bcfb4 | 411 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
mbed_official | 205:c41fc65bcfb4 | 412 | * and updated within this function |
mbed_official | 205:c41fc65bcfb4 | 413 | * |
mbed_official | 205:c41fc65bcfb4 | 414 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 415 | * @retval HCLK frequency |
mbed_official | 205:c41fc65bcfb4 | 416 | */ |
mbed_official | 205:c41fc65bcfb4 | 417 | uint32_t HAL_RCC_GetHCLKFreq(void) |
mbed_official | 205:c41fc65bcfb4 | 418 | { |
mbed_official | 205:c41fc65bcfb4 | 419 | SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; |
mbed_official | 205:c41fc65bcfb4 | 420 | return SystemCoreClock; |
mbed_official | 205:c41fc65bcfb4 | 421 | } |
mbed_official | 205:c41fc65bcfb4 | 422 | |
mbed_official | 205:c41fc65bcfb4 | 423 | /** |
mbed_official | 205:c41fc65bcfb4 | 424 | * @brief Returns the PCLK1 frequency |
mbed_official | 205:c41fc65bcfb4 | 425 | * @note Each time PCLK1 changes, this function must be called to update the |
mbed_official | 205:c41fc65bcfb4 | 426 | * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 205:c41fc65bcfb4 | 427 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 428 | * @retval PCLK1 frequency |
mbed_official | 205:c41fc65bcfb4 | 429 | */ |
mbed_official | 205:c41fc65bcfb4 | 430 | uint32_t HAL_RCC_GetPCLK1Freq(void) |
mbed_official | 205:c41fc65bcfb4 | 431 | { |
mbed_official | 205:c41fc65bcfb4 | 432 | /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 433 | return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]); |
mbed_official | 205:c41fc65bcfb4 | 434 | } |
mbed_official | 205:c41fc65bcfb4 | 435 | |
mbed_official | 205:c41fc65bcfb4 | 436 | /** |
mbed_official | 205:c41fc65bcfb4 | 437 | * @brief Configures the RCC_OscInitStruct according to the internal |
mbed_official | 205:c41fc65bcfb4 | 438 | * RCC configuration registers. |
mbed_official | 205:c41fc65bcfb4 | 439 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 205:c41fc65bcfb4 | 440 | * will be configured. |
mbed_official | 205:c41fc65bcfb4 | 441 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 442 | */ |
mbed_official | 205:c41fc65bcfb4 | 443 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
mbed_official | 205:c41fc65bcfb4 | 444 | { |
mbed_official | 205:c41fc65bcfb4 | 445 | /* Set all possible values for the Oscillator type parameter ---------------*/ |
mbed_official | 205:c41fc65bcfb4 | 446 | RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; |
mbed_official | 205:c41fc65bcfb4 | 447 | |
mbed_official | 205:c41fc65bcfb4 | 448 | /* Get the HSE configuration -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 449 | if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) |
mbed_official | 205:c41fc65bcfb4 | 450 | { |
mbed_official | 205:c41fc65bcfb4 | 451 | RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; |
mbed_official | 205:c41fc65bcfb4 | 452 | } |
mbed_official | 205:c41fc65bcfb4 | 453 | else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) |
mbed_official | 205:c41fc65bcfb4 | 454 | { |
mbed_official | 205:c41fc65bcfb4 | 455 | RCC_OscInitStruct->HSEState = RCC_HSE_ON; |
mbed_official | 205:c41fc65bcfb4 | 456 | } |
mbed_official | 205:c41fc65bcfb4 | 457 | else |
mbed_official | 205:c41fc65bcfb4 | 458 | { |
mbed_official | 205:c41fc65bcfb4 | 459 | RCC_OscInitStruct->HSEState = RCC_HSE_OFF; |
mbed_official | 205:c41fc65bcfb4 | 460 | } |
mbed_official | 205:c41fc65bcfb4 | 461 | |
mbed_official | 205:c41fc65bcfb4 | 462 | /* Get the HSI configuration -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 463 | if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) |
mbed_official | 205:c41fc65bcfb4 | 464 | { |
mbed_official | 205:c41fc65bcfb4 | 465 | RCC_OscInitStruct->HSIState = RCC_HSI_ON; |
mbed_official | 205:c41fc65bcfb4 | 466 | } |
mbed_official | 205:c41fc65bcfb4 | 467 | else |
mbed_official | 205:c41fc65bcfb4 | 468 | { |
mbed_official | 205:c41fc65bcfb4 | 469 | RCC_OscInitStruct->HSIState = RCC_HSI_OFF; |
mbed_official | 205:c41fc65bcfb4 | 470 | } |
mbed_official | 205:c41fc65bcfb4 | 471 | |
mbed_official | 205:c41fc65bcfb4 | 472 | RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); |
mbed_official | 205:c41fc65bcfb4 | 473 | |
mbed_official | 205:c41fc65bcfb4 | 474 | /* Get the LSE configuration -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 475 | if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) |
mbed_official | 205:c41fc65bcfb4 | 476 | { |
mbed_official | 205:c41fc65bcfb4 | 477 | RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; |
mbed_official | 205:c41fc65bcfb4 | 478 | } |
mbed_official | 205:c41fc65bcfb4 | 479 | else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) |
mbed_official | 205:c41fc65bcfb4 | 480 | { |
mbed_official | 205:c41fc65bcfb4 | 481 | RCC_OscInitStruct->LSEState = RCC_LSE_ON; |
mbed_official | 205:c41fc65bcfb4 | 482 | } |
mbed_official | 205:c41fc65bcfb4 | 483 | else |
mbed_official | 205:c41fc65bcfb4 | 484 | { |
mbed_official | 205:c41fc65bcfb4 | 485 | RCC_OscInitStruct->LSEState = RCC_LSE_OFF; |
mbed_official | 205:c41fc65bcfb4 | 486 | } |
mbed_official | 205:c41fc65bcfb4 | 487 | |
mbed_official | 205:c41fc65bcfb4 | 488 | /* Get the LSI configuration -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 489 | if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) |
mbed_official | 205:c41fc65bcfb4 | 490 | { |
mbed_official | 205:c41fc65bcfb4 | 491 | RCC_OscInitStruct->LSIState = RCC_LSI_ON; |
mbed_official | 205:c41fc65bcfb4 | 492 | } |
mbed_official | 205:c41fc65bcfb4 | 493 | else |
mbed_official | 205:c41fc65bcfb4 | 494 | { |
mbed_official | 205:c41fc65bcfb4 | 495 | RCC_OscInitStruct->LSIState = RCC_LSI_OFF; |
mbed_official | 205:c41fc65bcfb4 | 496 | } |
mbed_official | 205:c41fc65bcfb4 | 497 | |
mbed_official | 205:c41fc65bcfb4 | 498 | /* Get the PLL configuration -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 499 | if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) |
mbed_official | 205:c41fc65bcfb4 | 500 | { |
mbed_official | 205:c41fc65bcfb4 | 501 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; |
mbed_official | 205:c41fc65bcfb4 | 502 | } |
mbed_official | 205:c41fc65bcfb4 | 503 | else |
mbed_official | 205:c41fc65bcfb4 | 504 | { |
mbed_official | 205:c41fc65bcfb4 | 505 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; |
mbed_official | 205:c41fc65bcfb4 | 506 | } |
mbed_official | 205:c41fc65bcfb4 | 507 | RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); |
mbed_official | 205:c41fc65bcfb4 | 508 | RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); |
mbed_official | 205:c41fc65bcfb4 | 509 | RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); |
mbed_official | 205:c41fc65bcfb4 | 510 | |
mbed_official | 205:c41fc65bcfb4 | 511 | /* Get the HSI14 configuration -----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 512 | if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) |
mbed_official | 205:c41fc65bcfb4 | 513 | { |
mbed_official | 205:c41fc65bcfb4 | 514 | RCC_OscInitStruct->HSI14State = RCC_HSI_ON; |
mbed_official | 205:c41fc65bcfb4 | 515 | } |
mbed_official | 205:c41fc65bcfb4 | 516 | else |
mbed_official | 205:c41fc65bcfb4 | 517 | { |
mbed_official | 205:c41fc65bcfb4 | 518 | RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; |
mbed_official | 205:c41fc65bcfb4 | 519 | } |
mbed_official | 205:c41fc65bcfb4 | 520 | |
mbed_official | 205:c41fc65bcfb4 | 521 | RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber); |
mbed_official | 205:c41fc65bcfb4 | 522 | |
mbed_official | 205:c41fc65bcfb4 | 523 | /* Get the HSI48 configuration if any-----------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 524 | RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); |
mbed_official | 205:c41fc65bcfb4 | 525 | } |
mbed_official | 205:c41fc65bcfb4 | 526 | |
mbed_official | 205:c41fc65bcfb4 | 527 | /** |
mbed_official | 205:c41fc65bcfb4 | 528 | * @brief Get the RCC_ClkInitStruct according to the internal |
mbed_official | 205:c41fc65bcfb4 | 529 | * RCC configuration registers. |
mbed_official | 205:c41fc65bcfb4 | 530 | * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that |
mbed_official | 205:c41fc65bcfb4 | 531 | * contains the current clock configuration. |
mbed_official | 205:c41fc65bcfb4 | 532 | * @param pFLatency: Pointer on the Flash Latency. |
mbed_official | 205:c41fc65bcfb4 | 533 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 534 | */ |
mbed_official | 205:c41fc65bcfb4 | 535 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) |
mbed_official | 205:c41fc65bcfb4 | 536 | { |
mbed_official | 205:c41fc65bcfb4 | 537 | /* Set all possible values for the Clock type parameter --------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 538 | RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; |
mbed_official | 205:c41fc65bcfb4 | 539 | |
mbed_official | 205:c41fc65bcfb4 | 540 | /* Get the SYSCLK configuration --------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 541 | RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); |
mbed_official | 205:c41fc65bcfb4 | 542 | |
mbed_official | 205:c41fc65bcfb4 | 543 | /* Get the HCLK configuration ----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 544 | RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); |
mbed_official | 205:c41fc65bcfb4 | 545 | |
mbed_official | 205:c41fc65bcfb4 | 546 | /* Get the APB1 configuration ----------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 547 | RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); |
mbed_official | 205:c41fc65bcfb4 | 548 | |
mbed_official | 205:c41fc65bcfb4 | 549 | /* Get the Flash Wait State (Latency) configuration ------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 550 | *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); |
mbed_official | 205:c41fc65bcfb4 | 551 | } |
mbed_official | 205:c41fc65bcfb4 | 552 | |
mbed_official | 205:c41fc65bcfb4 | 553 | /** |
mbed_official | 205:c41fc65bcfb4 | 554 | * @brief This function handles the RCC CSS interrupt request. |
mbed_official | 205:c41fc65bcfb4 | 555 | * @note This API should be called under the NMI_Handler(). |
mbed_official | 205:c41fc65bcfb4 | 556 | * @param None |
mbed_official | 205:c41fc65bcfb4 | 557 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 558 | */ |
mbed_official | 205:c41fc65bcfb4 | 559 | void HAL_RCC_NMI_IRQHandler(void) |
mbed_official | 205:c41fc65bcfb4 | 560 | { |
mbed_official | 205:c41fc65bcfb4 | 561 | /* Check RCC CSSF flag */ |
mbed_official | 205:c41fc65bcfb4 | 562 | if(__HAL_RCC_GET_IT(RCC_IT_CSS)) |
mbed_official | 205:c41fc65bcfb4 | 563 | { |
mbed_official | 205:c41fc65bcfb4 | 564 | /* RCC Clock Security System interrupt user callback */ |
mbed_official | 205:c41fc65bcfb4 | 565 | HAL_RCC_CCSCallback(); |
mbed_official | 205:c41fc65bcfb4 | 566 | |
mbed_official | 205:c41fc65bcfb4 | 567 | /* Clear RCC CSS pending bit */ |
mbed_official | 205:c41fc65bcfb4 | 568 | __HAL_RCC_CLEAR_IT(RCC_IT_CSS); |
mbed_official | 205:c41fc65bcfb4 | 569 | } |
mbed_official | 205:c41fc65bcfb4 | 570 | } |
mbed_official | 205:c41fc65bcfb4 | 571 | |
mbed_official | 205:c41fc65bcfb4 | 572 | /** |
mbed_official | 205:c41fc65bcfb4 | 573 | * @brief RCC Clock Security System interrupt callback |
mbed_official | 205:c41fc65bcfb4 | 574 | * @param none |
mbed_official | 205:c41fc65bcfb4 | 575 | * @retval none |
mbed_official | 205:c41fc65bcfb4 | 576 | */ |
mbed_official | 205:c41fc65bcfb4 | 577 | __weak void HAL_RCC_CCSCallback(void) |
mbed_official | 205:c41fc65bcfb4 | 578 | { |
mbed_official | 205:c41fc65bcfb4 | 579 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 205:c41fc65bcfb4 | 580 | the HAL_RCC_CCSCallback could be implemented in the user file |
mbed_official | 205:c41fc65bcfb4 | 581 | */ |
mbed_official | 205:c41fc65bcfb4 | 582 | } |
mbed_official | 205:c41fc65bcfb4 | 583 | |
mbed_official | 205:c41fc65bcfb4 | 584 | /** |
mbed_official | 205:c41fc65bcfb4 | 585 | * @} |
mbed_official | 205:c41fc65bcfb4 | 586 | */ |
mbed_official | 205:c41fc65bcfb4 | 587 | |
mbed_official | 205:c41fc65bcfb4 | 588 | /** |
mbed_official | 205:c41fc65bcfb4 | 589 | * @} |
mbed_official | 205:c41fc65bcfb4 | 590 | */ |
mbed_official | 205:c41fc65bcfb4 | 591 | |
mbed_official | 205:c41fc65bcfb4 | 592 | #endif /* HAL_RCC_MODULE_ENABLED */ |
mbed_official | 205:c41fc65bcfb4 | 593 | /** |
mbed_official | 205:c41fc65bcfb4 | 594 | * @} |
mbed_official | 205:c41fc65bcfb4 | 595 | */ |
mbed_official | 205:c41fc65bcfb4 | 596 | |
mbed_official | 205:c41fc65bcfb4 | 597 | /** |
mbed_official | 205:c41fc65bcfb4 | 598 | * @} |
mbed_official | 205:c41fc65bcfb4 | 599 | */ |
mbed_official | 205:c41fc65bcfb4 | 600 | |
mbed_official | 205:c41fc65bcfb4 | 601 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |