Janek Mann / mbed-src-openwear

mbed library sources modified for open wear

Dependents:   openwear-lifelogger-example

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c@52:a51c77007319, 2013-12-02 (annotated)

Committer:
mbed_official
Date:
Mon Dec 02 11:30:05 2013 +0000
Revision:
52:a51c77007319
Child:
62:7731d679ae64
Synchronized with git revision 49df530ae72ce97ccc773d1f2c13b38e868e6abd



Full URL: https://github.com/mbedmicro/mbed/commit/49df530ae72ce97ccc773d1f2c13b38e868e6abd/



Add STMicroelectronics NUCLEO_F103RB target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 52:a51c77007319 1 /**
mbed_official 52:a51c77007319 2 ******************************************************************************
mbed_official 52:a51c77007319 3 * @file system_stm32f10x.c
mbed_official 52:a51c77007319 4 * @author MCD Application Team
mbed_official 52:a51c77007319 5 * @version V3.5.0
mbed_official 52:a51c77007319 6 * @date 11-March-2011
mbed_official 52:a51c77007319 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official 52:a51c77007319 8 *
mbed_official 52:a51c77007319 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 52:a51c77007319 10 * user application:
mbed_official 52:a51c77007319 11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 52:a51c77007319 12 * factors, AHB/APBx prescalers and Flash settings).
mbed_official 52:a51c77007319 13 * This function is called at startup just after reset and
mbed_official 52:a51c77007319 14 * before branch to main program. This call is made inside
mbed_official 52:a51c77007319 15 * the "startup_stm32f10x_xx.s" file.
mbed_official 52:a51c77007319 16 *
mbed_official 52:a51c77007319 17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 52:a51c77007319 18 * by the user application to setup the SysTick
mbed_official 52:a51c77007319 19 * timer or configure other parameters.
mbed_official 52:a51c77007319 20 *
mbed_official 52:a51c77007319 21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 52:a51c77007319 22 * be called whenever the core clock is changed
mbed_official 52:a51c77007319 23 * during program execution.
mbed_official 52:a51c77007319 24 *
mbed_official 52:a51c77007319 25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 52:a51c77007319 26 * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
mbed_official 52:a51c77007319 27 * configure the system clock before to branch to main program.
mbed_official 52:a51c77007319 28 *
mbed_official 52:a51c77007319 29 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 52:a51c77007319 30 * function will do nothing and HSI still used as system clock source. User can
mbed_official 52:a51c77007319 31 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 52:a51c77007319 32 *
mbed_official 52:a51c77007319 33 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
mbed_official 52:a51c77007319 34 * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
mbed_official 52:a51c77007319 35 * When HSE is used as system clock source, directly or through PLL, and you
mbed_official 52:a51c77007319 36 * are using different crystal you have to adapt the HSE value to your own
mbed_official 52:a51c77007319 37 * configuration.
mbed_official 52:a51c77007319 38 *
mbed_official 52:a51c77007319 39 ******************************************************************************
mbed_official 52:a51c77007319 40 * @attention
mbed_official 52:a51c77007319 41 *
mbed_official 52:a51c77007319 42 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
mbed_official 52:a51c77007319 43 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
mbed_official 52:a51c77007319 44 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
mbed_official 52:a51c77007319 45 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
mbed_official 52:a51c77007319 46 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
mbed_official 52:a51c77007319 47 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
mbed_official 52:a51c77007319 48 *
mbed_official 52:a51c77007319 49 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
mbed_official 52:a51c77007319 50 ******************************************************************************
mbed_official 52:a51c77007319 51 */
mbed_official 52:a51c77007319 52
mbed_official 52:a51c77007319 53 /** @addtogroup CMSIS
mbed_official 52:a51c77007319 54 * @{
mbed_official 52:a51c77007319 55 */
mbed_official 52:a51c77007319 56
mbed_official 52:a51c77007319 57 /** @addtogroup stm32f10x_system
mbed_official 52:a51c77007319 58 * @{
mbed_official 52:a51c77007319 59 */
mbed_official 52:a51c77007319 60
mbed_official 52:a51c77007319 61 /** @addtogroup STM32F10x_System_Private_Includes
mbed_official 52:a51c77007319 62 * @{
mbed_official 52:a51c77007319 63 */
mbed_official 52:a51c77007319 64
mbed_official 52:a51c77007319 65 #include "stm32f10x.h"
mbed_official 52:a51c77007319 66
mbed_official 52:a51c77007319 67 /**
mbed_official 52:a51c77007319 68 * @}
mbed_official 52:a51c77007319 69 */
mbed_official 52:a51c77007319 70
mbed_official 52:a51c77007319 71 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
mbed_official 52:a51c77007319 72 * @{
mbed_official 52:a51c77007319 73 */
mbed_official 52:a51c77007319 74
mbed_official 52:a51c77007319 75 /**
mbed_official 52:a51c77007319 76 * @}
mbed_official 52:a51c77007319 77 */
mbed_official 52:a51c77007319 78
mbed_official 52:a51c77007319 79 /** @addtogroup STM32F10x_System_Private_Defines
mbed_official 52:a51c77007319 80 * @{
mbed_official 52:a51c77007319 81 */
mbed_official 52:a51c77007319 82
mbed_official 52:a51c77007319 83 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
mbed_official 52:a51c77007319 84 frequency (after reset the HSI is used as SYSCLK source)
mbed_official 52:a51c77007319 85
mbed_official 52:a51c77007319 86 IMPORTANT NOTE:
mbed_official 52:a51c77007319 87 ==============
mbed_official 52:a51c77007319 88 1. After each device reset the HSI is used as System clock source.
mbed_official 52:a51c77007319 89
mbed_official 52:a51c77007319 90 2. Please make sure that the selected System clock doesn't exceed your device's
mbed_official 52:a51c77007319 91 maximum frequency.
mbed_official 52:a51c77007319 92
mbed_official 52:a51c77007319 93 3. If none of the define below is enabled, the HSI is used as System clock
mbed_official 52:a51c77007319 94 source.
mbed_official 52:a51c77007319 95
mbed_official 52:a51c77007319 96 4. The System clock configuration functions provided within this file assume that:
mbed_official 52:a51c77007319 97 - For Low, Medium and High density Value line devices an external 8MHz
mbed_official 52:a51c77007319 98 crystal is used to drive the System clock.
mbed_official 52:a51c77007319 99 - For Low, Medium and High density devices an external 8MHz crystal is
mbed_official 52:a51c77007319 100 used to drive the System clock.
mbed_official 52:a51c77007319 101 - For Connectivity line devices an external 25MHz crystal is used to drive
mbed_official 52:a51c77007319 102 the System clock.
mbed_official 52:a51c77007319 103 If you are using different crystal you have to adapt those functions accordingly.
mbed_official 52:a51c77007319 104 */
mbed_official 52:a51c77007319 105
mbed_official 52:a51c77007319 106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 52:a51c77007319 107 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
mbed_official 52:a51c77007319 108 #define SYSCLK_FREQ_24MHz 24000000
mbed_official 52:a51c77007319 109 #else
mbed_official 52:a51c77007319 110 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
mbed_official 52:a51c77007319 111 /* #define SYSCLK_FREQ_24MHz 24000000 */
mbed_official 52:a51c77007319 112 /* #define SYSCLK_FREQ_36MHz 36000000 */
mbed_official 52:a51c77007319 113 /* #define SYSCLK_FREQ_48MHz 48000000 */
mbed_official 52:a51c77007319 114 /* #define SYSCLK_FREQ_56MHz 56000000 */
mbed_official 52:a51c77007319 115 #define SYSCLK_FREQ_72MHz 72000000
mbed_official 52:a51c77007319 116 #endif
mbed_official 52:a51c77007319 117
mbed_official 52:a51c77007319 118 /*!< Uncomment the following line if you need to use external SRAM mounted
mbed_official 52:a51c77007319 119 on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
mbed_official 52:a51c77007319 120 STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
mbed_official 52:a51c77007319 121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
mbed_official 52:a51c77007319 122 /* #define DATA_IN_ExtSRAM */
mbed_official 52:a51c77007319 123 #endif
mbed_official 52:a51c77007319 124
mbed_official 52:a51c77007319 125 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 52:a51c77007319 126 Internal SRAM. */
mbed_official 52:a51c77007319 127 /* #define VECT_TAB_SRAM */
mbed_official 52:a51c77007319 128 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 52:a51c77007319 129 This value must be a multiple of 0x200. */
mbed_official 52:a51c77007319 130
mbed_official 52:a51c77007319 131
mbed_official 52:a51c77007319 132 /**
mbed_official 52:a51c77007319 133 * @}
mbed_official 52:a51c77007319 134 */
mbed_official 52:a51c77007319 135
mbed_official 52:a51c77007319 136 /** @addtogroup STM32F10x_System_Private_Macros
mbed_official 52:a51c77007319 137 * @{
mbed_official 52:a51c77007319 138 */
mbed_official 52:a51c77007319 139
mbed_official 52:a51c77007319 140 /**
mbed_official 52:a51c77007319 141 * @}
mbed_official 52:a51c77007319 142 */
mbed_official 52:a51c77007319 143
mbed_official 52:a51c77007319 144 /** @addtogroup STM32F10x_System_Private_Variables
mbed_official 52:a51c77007319 145 * @{
mbed_official 52:a51c77007319 146 */
mbed_official 52:a51c77007319 147
mbed_official 52:a51c77007319 148 /*******************************************************************************
mbed_official 52:a51c77007319 149 * Clock Definitions
mbed_official 52:a51c77007319 150 *******************************************************************************/
mbed_official 52:a51c77007319 151 #ifdef SYSCLK_FREQ_HSE
mbed_official 52:a51c77007319 152 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 153 #elif defined SYSCLK_FREQ_24MHz
mbed_official 52:a51c77007319 154 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 155 #elif defined SYSCLK_FREQ_36MHz
mbed_official 52:a51c77007319 156 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 157 #elif defined SYSCLK_FREQ_48MHz
mbed_official 52:a51c77007319 158 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 159 #elif defined SYSCLK_FREQ_56MHz
mbed_official 52:a51c77007319 160 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 161 #elif defined SYSCLK_FREQ_72MHz
mbed_official 52:a51c77007319 162 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 163 #else /*!< HSI Selected as System Clock source */
mbed_official 52:a51c77007319 164 uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
mbed_official 52:a51c77007319 165 #endif
mbed_official 52:a51c77007319 166
mbed_official 52:a51c77007319 167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 52:a51c77007319 168 /**
mbed_official 52:a51c77007319 169 * @}
mbed_official 52:a51c77007319 170 */
mbed_official 52:a51c77007319 171
mbed_official 52:a51c77007319 172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
mbed_official 52:a51c77007319 173 * @{
mbed_official 52:a51c77007319 174 */
mbed_official 52:a51c77007319 175
mbed_official 52:a51c77007319 176 static void SetSysClock(void);
mbed_official 52:a51c77007319 177
mbed_official 52:a51c77007319 178 #ifdef SYSCLK_FREQ_HSE
mbed_official 52:a51c77007319 179 static void SetSysClockToHSE(void);
mbed_official 52:a51c77007319 180 #elif defined SYSCLK_FREQ_24MHz
mbed_official 52:a51c77007319 181 static void SetSysClockTo24(void);
mbed_official 52:a51c77007319 182 #elif defined SYSCLK_FREQ_36MHz
mbed_official 52:a51c77007319 183 static void SetSysClockTo36(void);
mbed_official 52:a51c77007319 184 #elif defined SYSCLK_FREQ_48MHz
mbed_official 52:a51c77007319 185 static void SetSysClockTo48(void);
mbed_official 52:a51c77007319 186 #elif defined SYSCLK_FREQ_56MHz
mbed_official 52:a51c77007319 187 static void SetSysClockTo56(void);
mbed_official 52:a51c77007319 188 #elif defined SYSCLK_FREQ_72MHz
mbed_official 52:a51c77007319 189 static void SetSysClockTo72(void);
mbed_official 52:a51c77007319 190 #endif
mbed_official 52:a51c77007319 191
mbed_official 52:a51c77007319 192 #ifdef DATA_IN_ExtSRAM
mbed_official 52:a51c77007319 193 static void SystemInit_ExtMemCtl(void);
mbed_official 52:a51c77007319 194 #endif /* DATA_IN_ExtSRAM */
mbed_official 52:a51c77007319 195
mbed_official 52:a51c77007319 196 /**
mbed_official 52:a51c77007319 197 * @}
mbed_official 52:a51c77007319 198 */
mbed_official 52:a51c77007319 199
mbed_official 52:a51c77007319 200 /** @addtogroup STM32F10x_System_Private_Functions
mbed_official 52:a51c77007319 201 * @{
mbed_official 52:a51c77007319 202 */
mbed_official 52:a51c77007319 203
mbed_official 52:a51c77007319 204 /**
mbed_official 52:a51c77007319 205 * @brief Setup the microcontroller system
mbed_official 52:a51c77007319 206 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 52:a51c77007319 207 * SystemCoreClock variable.
mbed_official 52:a51c77007319 208 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 209 * @param None
mbed_official 52:a51c77007319 210 * @retval None
mbed_official 52:a51c77007319 211 */
mbed_official 52:a51c77007319 212 void SystemInit (void)
mbed_official 52:a51c77007319 213 {
mbed_official 52:a51c77007319 214 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
mbed_official 52:a51c77007319 215 /* Set HSION bit */
mbed_official 52:a51c77007319 216 RCC->CR |= (uint32_t)0x00000001;
mbed_official 52:a51c77007319 217
mbed_official 52:a51c77007319 218 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
mbed_official 52:a51c77007319 219 #ifndef STM32F10X_CL
mbed_official 52:a51c77007319 220 RCC->CFGR &= (uint32_t)0xF8FF0000;
mbed_official 52:a51c77007319 221 #else
mbed_official 52:a51c77007319 222 RCC->CFGR &= (uint32_t)0xF0FF0000;
mbed_official 52:a51c77007319 223 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 224
mbed_official 52:a51c77007319 225 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 52:a51c77007319 226 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 52:a51c77007319 227
mbed_official 52:a51c77007319 228 /* Reset HSEBYP bit */
mbed_official 52:a51c77007319 229 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 52:a51c77007319 230
mbed_official 52:a51c77007319 231 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
mbed_official 52:a51c77007319 232 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 52:a51c77007319 233
mbed_official 52:a51c77007319 234 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 235 /* Reset PLL2ON and PLL3ON bits */
mbed_official 52:a51c77007319 236 RCC->CR &= (uint32_t)0xEBFFFFFF;
mbed_official 52:a51c77007319 237
mbed_official 52:a51c77007319 238 /* Disable all interrupts and clear pending bits */
mbed_official 52:a51c77007319 239 RCC->CIR = 0x00FF0000;
mbed_official 52:a51c77007319 240
mbed_official 52:a51c77007319 241 /* Reset CFGR2 register */
mbed_official 52:a51c77007319 242 RCC->CFGR2 = 0x00000000;
mbed_official 52:a51c77007319 243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 52:a51c77007319 244 /* Disable all interrupts and clear pending bits */
mbed_official 52:a51c77007319 245 RCC->CIR = 0x009F0000;
mbed_official 52:a51c77007319 246
mbed_official 52:a51c77007319 247 /* Reset CFGR2 register */
mbed_official 52:a51c77007319 248 RCC->CFGR2 = 0x00000000;
mbed_official 52:a51c77007319 249 #else
mbed_official 52:a51c77007319 250 /* Disable all interrupts and clear pending bits */
mbed_official 52:a51c77007319 251 RCC->CIR = 0x009F0000;
mbed_official 52:a51c77007319 252 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 253
mbed_official 52:a51c77007319 254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
mbed_official 52:a51c77007319 255 #ifdef DATA_IN_ExtSRAM
mbed_official 52:a51c77007319 256 SystemInit_ExtMemCtl();
mbed_official 52:a51c77007319 257 #endif /* DATA_IN_ExtSRAM */
mbed_official 52:a51c77007319 258 #endif
mbed_official 52:a51c77007319 259
mbed_official 52:a51c77007319 260 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
mbed_official 52:a51c77007319 261 /* Configure the Flash Latency cycles and enable prefetch buffer */
mbed_official 52:a51c77007319 262 SetSysClock();
mbed_official 52:a51c77007319 263
mbed_official 52:a51c77007319 264 #ifdef VECT_TAB_SRAM
mbed_official 52:a51c77007319 265 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official 52:a51c77007319 266 #else
mbed_official 52:a51c77007319 267 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official 52:a51c77007319 268 #endif
mbed_official 52:a51c77007319 269 }
mbed_official 52:a51c77007319 270
mbed_official 52:a51c77007319 271 /**
mbed_official 52:a51c77007319 272 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 52:a51c77007319 273 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 52:a51c77007319 274 * be used by the user application to setup the SysTick timer or configure
mbed_official 52:a51c77007319 275 * other parameters.
mbed_official 52:a51c77007319 276 *
mbed_official 52:a51c77007319 277 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 52:a51c77007319 278 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 52:a51c77007319 279 * based on this variable will be incorrect.
mbed_official 52:a51c77007319 280 *
mbed_official 52:a51c77007319 281 * @note - The system frequency computed by this function is not the real
mbed_official 52:a51c77007319 282 * frequency in the chip. It is calculated based on the predefined
mbed_official 52:a51c77007319 283 * constant and the selected clock source:
mbed_official 52:a51c77007319 284 *
mbed_official 52:a51c77007319 285 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 52:a51c77007319 286 *
mbed_official 52:a51c77007319 287 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 52:a51c77007319 288 *
mbed_official 52:a51c77007319 289 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 52:a51c77007319 290 * or HSI_VALUE(*) multiplied by the PLL factors.
mbed_official 52:a51c77007319 291 *
mbed_official 52:a51c77007319 292 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official 52:a51c77007319 293 * 8 MHz) but the real value may vary depending on the variations
mbed_official 52:a51c77007319 294 * in voltage and temperature.
mbed_official 52:a51c77007319 295 *
mbed_official 52:a51c77007319 296 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official 52:a51c77007319 297 * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
mbed_official 52:a51c77007319 298 * that HSE_VALUE is same as the real frequency of the crystal used.
mbed_official 52:a51c77007319 299 * Otherwise, this function may have wrong result.
mbed_official 52:a51c77007319 300 *
mbed_official 52:a51c77007319 301 * - The result of this function could be not correct when using fractional
mbed_official 52:a51c77007319 302 * value for HSE crystal.
mbed_official 52:a51c77007319 303 * @param None
mbed_official 52:a51c77007319 304 * @retval None
mbed_official 52:a51c77007319 305 */
mbed_official 52:a51c77007319 306 void SystemCoreClockUpdate (void)
mbed_official 52:a51c77007319 307 {
mbed_official 52:a51c77007319 308 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
mbed_official 52:a51c77007319 309
mbed_official 52:a51c77007319 310 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 311 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
mbed_official 52:a51c77007319 312 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 313
mbed_official 52:a51c77007319 314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 52:a51c77007319 315 uint32_t prediv1factor = 0;
mbed_official 52:a51c77007319 316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
mbed_official 52:a51c77007319 317
mbed_official 52:a51c77007319 318 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 52:a51c77007319 319 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 52:a51c77007319 320
mbed_official 52:a51c77007319 321 switch (tmp)
mbed_official 52:a51c77007319 322 {
mbed_official 52:a51c77007319 323 case 0x00: /* HSI used as system clock */
mbed_official 52:a51c77007319 324 SystemCoreClock = HSI_VALUE;
mbed_official 52:a51c77007319 325 break;
mbed_official 52:a51c77007319 326 case 0x04: /* HSE used as system clock */
mbed_official 52:a51c77007319 327 SystemCoreClock = HSE_VALUE;
mbed_official 52:a51c77007319 328 break;
mbed_official 52:a51c77007319 329 case 0x08: /* PLL used as system clock */
mbed_official 52:a51c77007319 330
mbed_official 52:a51c77007319 331 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 52:a51c77007319 332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 52:a51c77007319 333 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 52:a51c77007319 334
mbed_official 52:a51c77007319 335 #ifndef STM32F10X_CL
mbed_official 52:a51c77007319 336 pllmull = ( pllmull >> 18) + 2;
mbed_official 52:a51c77007319 337
mbed_official 52:a51c77007319 338 if (pllsource == 0x00)
mbed_official 52:a51c77007319 339 {
mbed_official 52:a51c77007319 340 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 52:a51c77007319 341 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 52:a51c77007319 342 }
mbed_official 52:a51c77007319 343 else
mbed_official 52:a51c77007319 344 {
mbed_official 52:a51c77007319 345 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 52:a51c77007319 346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 52:a51c77007319 347 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 52:a51c77007319 348 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 52:a51c77007319 349 #else
mbed_official 52:a51c77007319 350 /* HSE selected as PLL clock entry */
mbed_official 52:a51c77007319 351 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
mbed_official 52:a51c77007319 352 {/* HSE oscillator clock divided by 2 */
mbed_official 52:a51c77007319 353 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
mbed_official 52:a51c77007319 354 }
mbed_official 52:a51c77007319 355 else
mbed_official 52:a51c77007319 356 {
mbed_official 52:a51c77007319 357 SystemCoreClock = HSE_VALUE * pllmull;
mbed_official 52:a51c77007319 358 }
mbed_official 52:a51c77007319 359 #endif
mbed_official 52:a51c77007319 360 }
mbed_official 52:a51c77007319 361 #else
mbed_official 52:a51c77007319 362 pllmull = pllmull >> 18;
mbed_official 52:a51c77007319 363
mbed_official 52:a51c77007319 364 if (pllmull != 0x0D)
mbed_official 52:a51c77007319 365 {
mbed_official 52:a51c77007319 366 pllmull += 2;
mbed_official 52:a51c77007319 367 }
mbed_official 52:a51c77007319 368 else
mbed_official 52:a51c77007319 369 { /* PLL multiplication factor = PLL input clock * 6.5 */
mbed_official 52:a51c77007319 370 pllmull = 13 / 2;
mbed_official 52:a51c77007319 371 }
mbed_official 52:a51c77007319 372
mbed_official 52:a51c77007319 373 if (pllsource == 0x00)
mbed_official 52:a51c77007319 374 {
mbed_official 52:a51c77007319 375 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 52:a51c77007319 376 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 52:a51c77007319 377 }
mbed_official 52:a51c77007319 378 else
mbed_official 52:a51c77007319 379 {/* PREDIV1 selected as PLL clock entry */
mbed_official 52:a51c77007319 380
mbed_official 52:a51c77007319 381 /* Get PREDIV1 clock source and division factor */
mbed_official 52:a51c77007319 382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
mbed_official 52:a51c77007319 383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 52:a51c77007319 384
mbed_official 52:a51c77007319 385 if (prediv1source == 0)
mbed_official 52:a51c77007319 386 {
mbed_official 52:a51c77007319 387 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 52:a51c77007319 388 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 52:a51c77007319 389 }
mbed_official 52:a51c77007319 390 else
mbed_official 52:a51c77007319 391 {/* PLL2 clock selected as PREDIV1 clock entry */
mbed_official 52:a51c77007319 392
mbed_official 52:a51c77007319 393 /* Get PREDIV2 division factor and PLL2 multiplication factor */
mbed_official 52:a51c77007319 394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
mbed_official 52:a51c77007319 395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
mbed_official 52:a51c77007319 396 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
mbed_official 52:a51c77007319 397 }
mbed_official 52:a51c77007319 398 }
mbed_official 52:a51c77007319 399 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 400 break;
mbed_official 52:a51c77007319 401
mbed_official 52:a51c77007319 402 default:
mbed_official 52:a51c77007319 403 SystemCoreClock = HSI_VALUE;
mbed_official 52:a51c77007319 404 break;
mbed_official 52:a51c77007319 405 }
mbed_official 52:a51c77007319 406
mbed_official 52:a51c77007319 407 /* Compute HCLK clock frequency ----------------*/
mbed_official 52:a51c77007319 408 /* Get HCLK prescaler */
mbed_official 52:a51c77007319 409 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 52:a51c77007319 410 /* HCLK clock frequency */
mbed_official 52:a51c77007319 411 SystemCoreClock >>= tmp;
mbed_official 52:a51c77007319 412 }
mbed_official 52:a51c77007319 413
mbed_official 52:a51c77007319 414 /**
mbed_official 52:a51c77007319 415 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
mbed_official 52:a51c77007319 416 * @param None
mbed_official 52:a51c77007319 417 * @retval None
mbed_official 52:a51c77007319 418 */
mbed_official 52:a51c77007319 419 static void SetSysClock(void)
mbed_official 52:a51c77007319 420 {
mbed_official 52:a51c77007319 421 #ifdef SYSCLK_FREQ_HSE
mbed_official 52:a51c77007319 422 SetSysClockToHSE();
mbed_official 52:a51c77007319 423 #elif defined SYSCLK_FREQ_24MHz
mbed_official 52:a51c77007319 424 SetSysClockTo24();
mbed_official 52:a51c77007319 425 #elif defined SYSCLK_FREQ_36MHz
mbed_official 52:a51c77007319 426 SetSysClockTo36();
mbed_official 52:a51c77007319 427 #elif defined SYSCLK_FREQ_48MHz
mbed_official 52:a51c77007319 428 SetSysClockTo48();
mbed_official 52:a51c77007319 429 #elif defined SYSCLK_FREQ_56MHz
mbed_official 52:a51c77007319 430 SetSysClockTo56();
mbed_official 52:a51c77007319 431 #elif defined SYSCLK_FREQ_72MHz
mbed_official 52:a51c77007319 432 SetSysClockTo72();
mbed_official 52:a51c77007319 433 #endif
mbed_official 52:a51c77007319 434
mbed_official 52:a51c77007319 435 /* If none of the define above is enabled, the HSI is used as System clock
mbed_official 52:a51c77007319 436 source (default after reset) */
mbed_official 52:a51c77007319 437 }
mbed_official 52:a51c77007319 438
mbed_official 52:a51c77007319 439 /**
mbed_official 52:a51c77007319 440 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
mbed_official 52:a51c77007319 441 * before jump to __main
mbed_official 52:a51c77007319 442 * @param None
mbed_official 52:a51c77007319 443 * @retval None
mbed_official 52:a51c77007319 444 */
mbed_official 52:a51c77007319 445 #ifdef DATA_IN_ExtSRAM
mbed_official 52:a51c77007319 446 /**
mbed_official 52:a51c77007319 447 * @brief Setup the external memory controller.
mbed_official 52:a51c77007319 448 * Called in startup_stm32f10x_xx.s/.c before jump to main.
mbed_official 52:a51c77007319 449 * This function configures the external SRAM mounted on STM3210E-EVAL
mbed_official 52:a51c77007319 450 * board (STM32 High density devices). This SRAM will be used as program
mbed_official 52:a51c77007319 451 * data memory (including heap and stack).
mbed_official 52:a51c77007319 452 * @param None
mbed_official 52:a51c77007319 453 * @retval None
mbed_official 52:a51c77007319 454 */
mbed_official 52:a51c77007319 455 void SystemInit_ExtMemCtl(void)
mbed_official 52:a51c77007319 456 {
mbed_official 52:a51c77007319 457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
mbed_official 52:a51c77007319 458 required, then adjust the Register Addresses */
mbed_official 52:a51c77007319 459
mbed_official 52:a51c77007319 460 /* Enable FSMC clock */
mbed_official 52:a51c77007319 461 RCC->AHBENR = 0x00000114;
mbed_official 52:a51c77007319 462
mbed_official 52:a51c77007319 463 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
mbed_official 52:a51c77007319 464 RCC->APB2ENR = 0x000001E0;
mbed_official 52:a51c77007319 465
mbed_official 52:a51c77007319 466 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
mbed_official 52:a51c77007319 467 /*---------------- SRAM Address lines configuration -------------------------*/
mbed_official 52:a51c77007319 468 /*---------------- NOE and NWE configuration --------------------------------*/
mbed_official 52:a51c77007319 469 /*---------------- NE3 configuration ----------------------------------------*/
mbed_official 52:a51c77007319 470 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
mbed_official 52:a51c77007319 471
mbed_official 52:a51c77007319 472 GPIOD->CRL = 0x44BB44BB;
mbed_official 52:a51c77007319 473 GPIOD->CRH = 0xBBBBBBBB;
mbed_official 52:a51c77007319 474
mbed_official 52:a51c77007319 475 GPIOE->CRL = 0xB44444BB;
mbed_official 52:a51c77007319 476 GPIOE->CRH = 0xBBBBBBBB;
mbed_official 52:a51c77007319 477
mbed_official 52:a51c77007319 478 GPIOF->CRL = 0x44BBBBBB;
mbed_official 52:a51c77007319 479 GPIOF->CRH = 0xBBBB4444;
mbed_official 52:a51c77007319 480
mbed_official 52:a51c77007319 481 GPIOG->CRL = 0x44BBBBBB;
mbed_official 52:a51c77007319 482 GPIOG->CRH = 0x44444B44;
mbed_official 52:a51c77007319 483
mbed_official 52:a51c77007319 484 /*---------------- FSMC Configuration ---------------------------------------*/
mbed_official 52:a51c77007319 485 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
mbed_official 52:a51c77007319 486
mbed_official 52:a51c77007319 487 FSMC_Bank1->BTCR[4] = 0x00001011;
mbed_official 52:a51c77007319 488 FSMC_Bank1->BTCR[5] = 0x00000200;
mbed_official 52:a51c77007319 489 }
mbed_official 52:a51c77007319 490 #endif /* DATA_IN_ExtSRAM */
mbed_official 52:a51c77007319 491
mbed_official 52:a51c77007319 492 #ifdef SYSCLK_FREQ_HSE
mbed_official 52:a51c77007319 493 /**
mbed_official 52:a51c77007319 494 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
mbed_official 52:a51c77007319 495 * and PCLK1 prescalers.
mbed_official 52:a51c77007319 496 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 497 * @param None
mbed_official 52:a51c77007319 498 * @retval None
mbed_official 52:a51c77007319 499 */
mbed_official 52:a51c77007319 500 static void SetSysClockToHSE(void)
mbed_official 52:a51c77007319 501 {
mbed_official 52:a51c77007319 502 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 52:a51c77007319 503
mbed_official 52:a51c77007319 504 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 52:a51c77007319 505 /* Enable HSE */
mbed_official 52:a51c77007319 506 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 52:a51c77007319 507
mbed_official 52:a51c77007319 508 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 52:a51c77007319 509 do
mbed_official 52:a51c77007319 510 {
mbed_official 52:a51c77007319 511 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 52:a51c77007319 512 StartUpCounter++;
mbed_official 52:a51c77007319 513 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 52:a51c77007319 514
mbed_official 52:a51c77007319 515 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 52:a51c77007319 516 {
mbed_official 52:a51c77007319 517 HSEStatus = (uint32_t)0x01;
mbed_official 52:a51c77007319 518 }
mbed_official 52:a51c77007319 519 else
mbed_official 52:a51c77007319 520 {
mbed_official 52:a51c77007319 521 HSEStatus = (uint32_t)0x00;
mbed_official 52:a51c77007319 522 }
mbed_official 52:a51c77007319 523
mbed_official 52:a51c77007319 524 if (HSEStatus == (uint32_t)0x01)
mbed_official 52:a51c77007319 525 {
mbed_official 52:a51c77007319 526
mbed_official 52:a51c77007319 527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
mbed_official 52:a51c77007319 528 /* Enable Prefetch Buffer */
mbed_official 52:a51c77007319 529 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 52:a51c77007319 530
mbed_official 52:a51c77007319 531 /* Flash 0 wait state */
mbed_official 52:a51c77007319 532 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 52:a51c77007319 533
mbed_official 52:a51c77007319 534 #ifndef STM32F10X_CL
mbed_official 52:a51c77007319 535 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official 52:a51c77007319 536 #else
mbed_official 52:a51c77007319 537 if (HSE_VALUE <= 24000000)
mbed_official 52:a51c77007319 538 {
mbed_official 52:a51c77007319 539 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official 52:a51c77007319 540 }
mbed_official 52:a51c77007319 541 else
mbed_official 52:a51c77007319 542 {
mbed_official 52:a51c77007319 543 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 52:a51c77007319 544 }
mbed_official 52:a51c77007319 545 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 546 #endif
mbed_official 52:a51c77007319 547
mbed_official 52:a51c77007319 548 /* HCLK = SYSCLK */
mbed_official 52:a51c77007319 549 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 52:a51c77007319 550
mbed_official 52:a51c77007319 551 /* PCLK2 = HCLK */
mbed_official 52:a51c77007319 552 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 52:a51c77007319 553
mbed_official 52:a51c77007319 554 /* PCLK1 = HCLK */
mbed_official 52:a51c77007319 555 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 52:a51c77007319 556
mbed_official 52:a51c77007319 557 /* Select HSE as system clock source */
mbed_official 52:a51c77007319 558 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 52:a51c77007319 559 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
mbed_official 52:a51c77007319 560
mbed_official 52:a51c77007319 561 /* Wait till HSE is used as system clock source */
mbed_official 52:a51c77007319 562 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
mbed_official 52:a51c77007319 563 {
mbed_official 52:a51c77007319 564 }
mbed_official 52:a51c77007319 565 }
mbed_official 52:a51c77007319 566 else
mbed_official 52:a51c77007319 567 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 52:a51c77007319 568 configuration. User can add here some code to deal with this error */
mbed_official 52:a51c77007319 569 }
mbed_official 52:a51c77007319 570 }
mbed_official 52:a51c77007319 571 #elif defined SYSCLK_FREQ_24MHz
mbed_official 52:a51c77007319 572 /**
mbed_official 52:a51c77007319 573 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
mbed_official 52:a51c77007319 574 * and PCLK1 prescalers.
mbed_official 52:a51c77007319 575 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 576 * @param None
mbed_official 52:a51c77007319 577 * @retval None
mbed_official 52:a51c77007319 578 */
mbed_official 52:a51c77007319 579 static void SetSysClockTo24(void)
mbed_official 52:a51c77007319 580 {
mbed_official 52:a51c77007319 581 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 52:a51c77007319 582
mbed_official 52:a51c77007319 583 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 52:a51c77007319 584 /* Enable HSE */
mbed_official 52:a51c77007319 585 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 52:a51c77007319 586
mbed_official 52:a51c77007319 587 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 52:a51c77007319 588 do
mbed_official 52:a51c77007319 589 {
mbed_official 52:a51c77007319 590 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 52:a51c77007319 591 StartUpCounter++;
mbed_official 52:a51c77007319 592 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 52:a51c77007319 593
mbed_official 52:a51c77007319 594 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 52:a51c77007319 595 {
mbed_official 52:a51c77007319 596 HSEStatus = (uint32_t)0x01;
mbed_official 52:a51c77007319 597 }
mbed_official 52:a51c77007319 598 else
mbed_official 52:a51c77007319 599 {
mbed_official 52:a51c77007319 600 HSEStatus = (uint32_t)0x00;
mbed_official 52:a51c77007319 601 }
mbed_official 52:a51c77007319 602
mbed_official 52:a51c77007319 603 if (HSEStatus == (uint32_t)0x01)
mbed_official 52:a51c77007319 604 {
mbed_official 52:a51c77007319 605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
mbed_official 52:a51c77007319 606 /* Enable Prefetch Buffer */
mbed_official 52:a51c77007319 607 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 52:a51c77007319 608
mbed_official 52:a51c77007319 609 /* Flash 0 wait state */
mbed_official 52:a51c77007319 610 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 52:a51c77007319 611 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official 52:a51c77007319 612 #endif
mbed_official 52:a51c77007319 613
mbed_official 52:a51c77007319 614 /* HCLK = SYSCLK */
mbed_official 52:a51c77007319 615 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 52:a51c77007319 616
mbed_official 52:a51c77007319 617 /* PCLK2 = HCLK */
mbed_official 52:a51c77007319 618 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 52:a51c77007319 619
mbed_official 52:a51c77007319 620 /* PCLK1 = HCLK */
mbed_official 52:a51c77007319 621 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 52:a51c77007319 622
mbed_official 52:a51c77007319 623 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 624 /* Configure PLLs ------------------------------------------------------*/
mbed_official 52:a51c77007319 625 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
mbed_official 52:a51c77007319 626 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 52:a51c77007319 627 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 52:a51c77007319 628 RCC_CFGR_PLLMULL6);
mbed_official 52:a51c77007319 629
mbed_official 52:a51c77007319 630 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 52:a51c77007319 631 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
mbed_official 52:a51c77007319 632 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 52:a51c77007319 633 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 52:a51c77007319 634 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 52:a51c77007319 635 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
mbed_official 52:a51c77007319 636
mbed_official 52:a51c77007319 637 /* Enable PLL2 */
mbed_official 52:a51c77007319 638 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 52:a51c77007319 639 /* Wait till PLL2 is ready */
mbed_official 52:a51c77007319 640 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 52:a51c77007319 641 {
mbed_official 52:a51c77007319 642 }
mbed_official 52:a51c77007319 643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
mbed_official 52:a51c77007319 644 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
mbed_official 52:a51c77007319 645 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 52:a51c77007319 646 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
mbed_official 52:a51c77007319 647 #else
mbed_official 52:a51c77007319 648 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
mbed_official 52:a51c77007319 649 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 52:a51c77007319 650 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
mbed_official 52:a51c77007319 651 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 652
mbed_official 52:a51c77007319 653 /* Enable PLL */
mbed_official 52:a51c77007319 654 RCC->CR |= RCC_CR_PLLON;
mbed_official 52:a51c77007319 655
mbed_official 52:a51c77007319 656 /* Wait till PLL is ready */
mbed_official 52:a51c77007319 657 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 52:a51c77007319 658 {
mbed_official 52:a51c77007319 659 }
mbed_official 52:a51c77007319 660
mbed_official 52:a51c77007319 661 /* Select PLL as system clock source */
mbed_official 52:a51c77007319 662 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 52:a51c77007319 663 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 52:a51c77007319 664
mbed_official 52:a51c77007319 665 /* Wait till PLL is used as system clock source */
mbed_official 52:a51c77007319 666 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 52:a51c77007319 667 {
mbed_official 52:a51c77007319 668 }
mbed_official 52:a51c77007319 669 }
mbed_official 52:a51c77007319 670 else
mbed_official 52:a51c77007319 671 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 52:a51c77007319 672 configuration. User can add here some code to deal with this error */
mbed_official 52:a51c77007319 673 }
mbed_official 52:a51c77007319 674 }
mbed_official 52:a51c77007319 675 #elif defined SYSCLK_FREQ_36MHz
mbed_official 52:a51c77007319 676 /**
mbed_official 52:a51c77007319 677 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
mbed_official 52:a51c77007319 678 * and PCLK1 prescalers.
mbed_official 52:a51c77007319 679 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 680 * @param None
mbed_official 52:a51c77007319 681 * @retval None
mbed_official 52:a51c77007319 682 */
mbed_official 52:a51c77007319 683 static void SetSysClockTo36(void)
mbed_official 52:a51c77007319 684 {
mbed_official 52:a51c77007319 685 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 52:a51c77007319 686
mbed_official 52:a51c77007319 687 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 52:a51c77007319 688 /* Enable HSE */
mbed_official 52:a51c77007319 689 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 52:a51c77007319 690
mbed_official 52:a51c77007319 691 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 52:a51c77007319 692 do
mbed_official 52:a51c77007319 693 {
mbed_official 52:a51c77007319 694 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 52:a51c77007319 695 StartUpCounter++;
mbed_official 52:a51c77007319 696 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 52:a51c77007319 697
mbed_official 52:a51c77007319 698 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 52:a51c77007319 699 {
mbed_official 52:a51c77007319 700 HSEStatus = (uint32_t)0x01;
mbed_official 52:a51c77007319 701 }
mbed_official 52:a51c77007319 702 else
mbed_official 52:a51c77007319 703 {
mbed_official 52:a51c77007319 704 HSEStatus = (uint32_t)0x00;
mbed_official 52:a51c77007319 705 }
mbed_official 52:a51c77007319 706
mbed_official 52:a51c77007319 707 if (HSEStatus == (uint32_t)0x01)
mbed_official 52:a51c77007319 708 {
mbed_official 52:a51c77007319 709 /* Enable Prefetch Buffer */
mbed_official 52:a51c77007319 710 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 52:a51c77007319 711
mbed_official 52:a51c77007319 712 /* Flash 1 wait state */
mbed_official 52:a51c77007319 713 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 52:a51c77007319 714 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 52:a51c77007319 715
mbed_official 52:a51c77007319 716 /* HCLK = SYSCLK */
mbed_official 52:a51c77007319 717 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 52:a51c77007319 718
mbed_official 52:a51c77007319 719 /* PCLK2 = HCLK */
mbed_official 52:a51c77007319 720 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 52:a51c77007319 721
mbed_official 52:a51c77007319 722 /* PCLK1 = HCLK */
mbed_official 52:a51c77007319 723 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 52:a51c77007319 724
mbed_official 52:a51c77007319 725 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 726 /* Configure PLLs ------------------------------------------------------*/
mbed_official 52:a51c77007319 727
mbed_official 52:a51c77007319 728 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
mbed_official 52:a51c77007319 729 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 52:a51c77007319 730 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 52:a51c77007319 731 RCC_CFGR_PLLMULL9);
mbed_official 52:a51c77007319 732
mbed_official 52:a51c77007319 733 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 52:a51c77007319 734 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
mbed_official 52:a51c77007319 735
mbed_official 52:a51c77007319 736 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 52:a51c77007319 737 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 52:a51c77007319 738 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 52:a51c77007319 739 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
mbed_official 52:a51c77007319 740
mbed_official 52:a51c77007319 741 /* Enable PLL2 */
mbed_official 52:a51c77007319 742 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 52:a51c77007319 743 /* Wait till PLL2 is ready */
mbed_official 52:a51c77007319 744 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 52:a51c77007319 745 {
mbed_official 52:a51c77007319 746 }
mbed_official 52:a51c77007319 747
mbed_official 52:a51c77007319 748 #else
mbed_official 52:a51c77007319 749 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
mbed_official 52:a51c77007319 750 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 52:a51c77007319 751 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
mbed_official 52:a51c77007319 752 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 753
mbed_official 52:a51c77007319 754 /* Enable PLL */
mbed_official 52:a51c77007319 755 RCC->CR |= RCC_CR_PLLON;
mbed_official 52:a51c77007319 756
mbed_official 52:a51c77007319 757 /* Wait till PLL is ready */
mbed_official 52:a51c77007319 758 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 52:a51c77007319 759 {
mbed_official 52:a51c77007319 760 }
mbed_official 52:a51c77007319 761
mbed_official 52:a51c77007319 762 /* Select PLL as system clock source */
mbed_official 52:a51c77007319 763 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 52:a51c77007319 764 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 52:a51c77007319 765
mbed_official 52:a51c77007319 766 /* Wait till PLL is used as system clock source */
mbed_official 52:a51c77007319 767 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 52:a51c77007319 768 {
mbed_official 52:a51c77007319 769 }
mbed_official 52:a51c77007319 770 }
mbed_official 52:a51c77007319 771 else
mbed_official 52:a51c77007319 772 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 52:a51c77007319 773 configuration. User can add here some code to deal with this error */
mbed_official 52:a51c77007319 774 }
mbed_official 52:a51c77007319 775 }
mbed_official 52:a51c77007319 776 #elif defined SYSCLK_FREQ_48MHz
mbed_official 52:a51c77007319 777 /**
mbed_official 52:a51c77007319 778 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
mbed_official 52:a51c77007319 779 * and PCLK1 prescalers.
mbed_official 52:a51c77007319 780 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 781 * @param None
mbed_official 52:a51c77007319 782 * @retval None
mbed_official 52:a51c77007319 783 */
mbed_official 52:a51c77007319 784 static void SetSysClockTo48(void)
mbed_official 52:a51c77007319 785 {
mbed_official 52:a51c77007319 786 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 52:a51c77007319 787
mbed_official 52:a51c77007319 788 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 52:a51c77007319 789 /* Enable HSE */
mbed_official 52:a51c77007319 790 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 52:a51c77007319 791
mbed_official 52:a51c77007319 792 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 52:a51c77007319 793 do
mbed_official 52:a51c77007319 794 {
mbed_official 52:a51c77007319 795 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 52:a51c77007319 796 StartUpCounter++;
mbed_official 52:a51c77007319 797 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 52:a51c77007319 798
mbed_official 52:a51c77007319 799 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 52:a51c77007319 800 {
mbed_official 52:a51c77007319 801 HSEStatus = (uint32_t)0x01;
mbed_official 52:a51c77007319 802 }
mbed_official 52:a51c77007319 803 else
mbed_official 52:a51c77007319 804 {
mbed_official 52:a51c77007319 805 HSEStatus = (uint32_t)0x00;
mbed_official 52:a51c77007319 806 }
mbed_official 52:a51c77007319 807
mbed_official 52:a51c77007319 808 if (HSEStatus == (uint32_t)0x01)
mbed_official 52:a51c77007319 809 {
mbed_official 52:a51c77007319 810 /* Enable Prefetch Buffer */
mbed_official 52:a51c77007319 811 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 52:a51c77007319 812
mbed_official 52:a51c77007319 813 /* Flash 1 wait state */
mbed_official 52:a51c77007319 814 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 52:a51c77007319 815 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 52:a51c77007319 816
mbed_official 52:a51c77007319 817 /* HCLK = SYSCLK */
mbed_official 52:a51c77007319 818 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 52:a51c77007319 819
mbed_official 52:a51c77007319 820 /* PCLK2 = HCLK */
mbed_official 52:a51c77007319 821 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 52:a51c77007319 822
mbed_official 52:a51c77007319 823 /* PCLK1 = HCLK */
mbed_official 52:a51c77007319 824 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 52:a51c77007319 825
mbed_official 52:a51c77007319 826 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 827 /* Configure PLLs ------------------------------------------------------*/
mbed_official 52:a51c77007319 828 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 52:a51c77007319 829 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official 52:a51c77007319 830
mbed_official 52:a51c77007319 831 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 52:a51c77007319 832 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 52:a51c77007319 833 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 52:a51c77007319 834 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
mbed_official 52:a51c77007319 835
mbed_official 52:a51c77007319 836 /* Enable PLL2 */
mbed_official 52:a51c77007319 837 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 52:a51c77007319 838 /* Wait till PLL2 is ready */
mbed_official 52:a51c77007319 839 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 52:a51c77007319 840 {
mbed_official 52:a51c77007319 841 }
mbed_official 52:a51c77007319 842
mbed_official 52:a51c77007319 843
mbed_official 52:a51c77007319 844 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
mbed_official 52:a51c77007319 845 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 52:a51c77007319 846 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 52:a51c77007319 847 RCC_CFGR_PLLMULL6);
mbed_official 52:a51c77007319 848 #else
mbed_official 52:a51c77007319 849 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
mbed_official 52:a51c77007319 850 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 52:a51c77007319 851 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
mbed_official 52:a51c77007319 852 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 853
mbed_official 52:a51c77007319 854 /* Enable PLL */
mbed_official 52:a51c77007319 855 RCC->CR |= RCC_CR_PLLON;
mbed_official 52:a51c77007319 856
mbed_official 52:a51c77007319 857 /* Wait till PLL is ready */
mbed_official 52:a51c77007319 858 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 52:a51c77007319 859 {
mbed_official 52:a51c77007319 860 }
mbed_official 52:a51c77007319 861
mbed_official 52:a51c77007319 862 /* Select PLL as system clock source */
mbed_official 52:a51c77007319 863 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 52:a51c77007319 864 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 52:a51c77007319 865
mbed_official 52:a51c77007319 866 /* Wait till PLL is used as system clock source */
mbed_official 52:a51c77007319 867 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 52:a51c77007319 868 {
mbed_official 52:a51c77007319 869 }
mbed_official 52:a51c77007319 870 }
mbed_official 52:a51c77007319 871 else
mbed_official 52:a51c77007319 872 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 52:a51c77007319 873 configuration. User can add here some code to deal with this error */
mbed_official 52:a51c77007319 874 }
mbed_official 52:a51c77007319 875 }
mbed_official 52:a51c77007319 876
mbed_official 52:a51c77007319 877 #elif defined SYSCLK_FREQ_56MHz
mbed_official 52:a51c77007319 878 /**
mbed_official 52:a51c77007319 879 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
mbed_official 52:a51c77007319 880 * and PCLK1 prescalers.
mbed_official 52:a51c77007319 881 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 882 * @param None
mbed_official 52:a51c77007319 883 * @retval None
mbed_official 52:a51c77007319 884 */
mbed_official 52:a51c77007319 885 static void SetSysClockTo56(void)
mbed_official 52:a51c77007319 886 {
mbed_official 52:a51c77007319 887 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 52:a51c77007319 888
mbed_official 52:a51c77007319 889 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 52:a51c77007319 890 /* Enable HSE */
mbed_official 52:a51c77007319 891 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 52:a51c77007319 892
mbed_official 52:a51c77007319 893 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 52:a51c77007319 894 do
mbed_official 52:a51c77007319 895 {
mbed_official 52:a51c77007319 896 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 52:a51c77007319 897 StartUpCounter++;
mbed_official 52:a51c77007319 898 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 52:a51c77007319 899
mbed_official 52:a51c77007319 900 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 52:a51c77007319 901 {
mbed_official 52:a51c77007319 902 HSEStatus = (uint32_t)0x01;
mbed_official 52:a51c77007319 903 }
mbed_official 52:a51c77007319 904 else
mbed_official 52:a51c77007319 905 {
mbed_official 52:a51c77007319 906 HSEStatus = (uint32_t)0x00;
mbed_official 52:a51c77007319 907 }
mbed_official 52:a51c77007319 908
mbed_official 52:a51c77007319 909 if (HSEStatus == (uint32_t)0x01)
mbed_official 52:a51c77007319 910 {
mbed_official 52:a51c77007319 911 /* Enable Prefetch Buffer */
mbed_official 52:a51c77007319 912 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 52:a51c77007319 913
mbed_official 52:a51c77007319 914 /* Flash 2 wait state */
mbed_official 52:a51c77007319 915 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 52:a51c77007319 916 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
mbed_official 52:a51c77007319 917
mbed_official 52:a51c77007319 918 /* HCLK = SYSCLK */
mbed_official 52:a51c77007319 919 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 52:a51c77007319 920
mbed_official 52:a51c77007319 921 /* PCLK2 = HCLK */
mbed_official 52:a51c77007319 922 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 52:a51c77007319 923
mbed_official 52:a51c77007319 924 /* PCLK1 = HCLK */
mbed_official 52:a51c77007319 925 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 52:a51c77007319 926
mbed_official 52:a51c77007319 927 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 928 /* Configure PLLs ------------------------------------------------------*/
mbed_official 52:a51c77007319 929 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 52:a51c77007319 930 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official 52:a51c77007319 931
mbed_official 52:a51c77007319 932 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 52:a51c77007319 933 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 52:a51c77007319 934 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 52:a51c77007319 935 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
mbed_official 52:a51c77007319 936
mbed_official 52:a51c77007319 937 /* Enable PLL2 */
mbed_official 52:a51c77007319 938 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 52:a51c77007319 939 /* Wait till PLL2 is ready */
mbed_official 52:a51c77007319 940 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 52:a51c77007319 941 {
mbed_official 52:a51c77007319 942 }
mbed_official 52:a51c77007319 943
mbed_official 52:a51c77007319 944
mbed_official 52:a51c77007319 945 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
mbed_official 52:a51c77007319 946 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 52:a51c77007319 947 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 52:a51c77007319 948 RCC_CFGR_PLLMULL7);
mbed_official 52:a51c77007319 949 #else
mbed_official 52:a51c77007319 950 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
mbed_official 52:a51c77007319 951 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 52:a51c77007319 952 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
mbed_official 52:a51c77007319 953
mbed_official 52:a51c77007319 954 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 955
mbed_official 52:a51c77007319 956 /* Enable PLL */
mbed_official 52:a51c77007319 957 RCC->CR |= RCC_CR_PLLON;
mbed_official 52:a51c77007319 958
mbed_official 52:a51c77007319 959 /* Wait till PLL is ready */
mbed_official 52:a51c77007319 960 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 52:a51c77007319 961 {
mbed_official 52:a51c77007319 962 }
mbed_official 52:a51c77007319 963
mbed_official 52:a51c77007319 964 /* Select PLL as system clock source */
mbed_official 52:a51c77007319 965 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 52:a51c77007319 966 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 52:a51c77007319 967
mbed_official 52:a51c77007319 968 /* Wait till PLL is used as system clock source */
mbed_official 52:a51c77007319 969 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 52:a51c77007319 970 {
mbed_official 52:a51c77007319 971 }
mbed_official 52:a51c77007319 972 }
mbed_official 52:a51c77007319 973 else
mbed_official 52:a51c77007319 974 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 52:a51c77007319 975 configuration. User can add here some code to deal with this error */
mbed_official 52:a51c77007319 976 }
mbed_official 52:a51c77007319 977 }
mbed_official 52:a51c77007319 978
mbed_official 52:a51c77007319 979 #elif defined SYSCLK_FREQ_72MHz
mbed_official 52:a51c77007319 980 /**
mbed_official 52:a51c77007319 981 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
mbed_official 52:a51c77007319 982 * and PCLK1 prescalers.
mbed_official 52:a51c77007319 983 * @note This function should be used only after reset.
mbed_official 52:a51c77007319 984 * @param None
mbed_official 52:a51c77007319 985 * @retval None
mbed_official 52:a51c77007319 986 */
mbed_official 52:a51c77007319 987 static void SetSysClockTo72(void)
mbed_official 52:a51c77007319 988 {
mbed_official 52:a51c77007319 989 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 52:a51c77007319 990
mbed_official 52:a51c77007319 991 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 52:a51c77007319 992 /* Enable HSE */
mbed_official 52:a51c77007319 993 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 52:a51c77007319 994
mbed_official 52:a51c77007319 995 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 52:a51c77007319 996 do
mbed_official 52:a51c77007319 997 {
mbed_official 52:a51c77007319 998 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 52:a51c77007319 999 StartUpCounter++;
mbed_official 52:a51c77007319 1000 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 52:a51c77007319 1001
mbed_official 52:a51c77007319 1002 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 52:a51c77007319 1003 {
mbed_official 52:a51c77007319 1004 HSEStatus = (uint32_t)0x01;
mbed_official 52:a51c77007319 1005 }
mbed_official 52:a51c77007319 1006 else
mbed_official 52:a51c77007319 1007 {
mbed_official 52:a51c77007319 1008 HSEStatus = (uint32_t)0x00;
mbed_official 52:a51c77007319 1009 }
mbed_official 52:a51c77007319 1010
mbed_official 52:a51c77007319 1011 if (HSEStatus == (uint32_t)0x01)
mbed_official 52:a51c77007319 1012 {
mbed_official 52:a51c77007319 1013 /* Enable Prefetch Buffer */
mbed_official 52:a51c77007319 1014 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 52:a51c77007319 1015
mbed_official 52:a51c77007319 1016 /* Flash 2 wait state */
mbed_official 52:a51c77007319 1017 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 52:a51c77007319 1018 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
mbed_official 52:a51c77007319 1019
mbed_official 52:a51c77007319 1020
mbed_official 52:a51c77007319 1021 /* HCLK = SYSCLK */
mbed_official 52:a51c77007319 1022 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 52:a51c77007319 1023
mbed_official 52:a51c77007319 1024 /* PCLK2 = HCLK */
mbed_official 52:a51c77007319 1025 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 52:a51c77007319 1026
mbed_official 52:a51c77007319 1027 /* PCLK1 = HCLK */
mbed_official 52:a51c77007319 1028 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 52:a51c77007319 1029
mbed_official 52:a51c77007319 1030 #ifdef STM32F10X_CL
mbed_official 52:a51c77007319 1031 /* Configure PLLs ------------------------------------------------------*/
mbed_official 52:a51c77007319 1032 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 52:a51c77007319 1033 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official 52:a51c77007319 1034
mbed_official 52:a51c77007319 1035 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 52:a51c77007319 1036 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 52:a51c77007319 1037 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 52:a51c77007319 1038 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
mbed_official 52:a51c77007319 1039
mbed_official 52:a51c77007319 1040 /* Enable PLL2 */
mbed_official 52:a51c77007319 1041 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 52:a51c77007319 1042 /* Wait till PLL2 is ready */
mbed_official 52:a51c77007319 1043 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 52:a51c77007319 1044 {
mbed_official 52:a51c77007319 1045 }
mbed_official 52:a51c77007319 1046
mbed_official 52:a51c77007319 1047
mbed_official 52:a51c77007319 1048 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
mbed_official 52:a51c77007319 1049 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 52:a51c77007319 1050 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 52:a51c77007319 1051 RCC_CFGR_PLLMULL9);
mbed_official 52:a51c77007319 1052 #else
mbed_official 52:a51c77007319 1053 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
mbed_official 52:a51c77007319 1054 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
mbed_official 52:a51c77007319 1055 RCC_CFGR_PLLMULL));
mbed_official 52:a51c77007319 1056 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
mbed_official 52:a51c77007319 1057 #endif /* STM32F10X_CL */
mbed_official 52:a51c77007319 1058
mbed_official 52:a51c77007319 1059 /* Enable PLL */
mbed_official 52:a51c77007319 1060 RCC->CR |= RCC_CR_PLLON;
mbed_official 52:a51c77007319 1061
mbed_official 52:a51c77007319 1062 /* Wait till PLL is ready */
mbed_official 52:a51c77007319 1063 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 52:a51c77007319 1064 {
mbed_official 52:a51c77007319 1065 }
mbed_official 52:a51c77007319 1066
mbed_official 52:a51c77007319 1067 /* Select PLL as system clock source */
mbed_official 52:a51c77007319 1068 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 52:a51c77007319 1069 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 52:a51c77007319 1070
mbed_official 52:a51c77007319 1071 /* Wait till PLL is used as system clock source */
mbed_official 52:a51c77007319 1072 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 52:a51c77007319 1073 {
mbed_official 52:a51c77007319 1074 }
mbed_official 52:a51c77007319 1075 }
mbed_official 52:a51c77007319 1076 else
mbed_official 52:a51c77007319 1077 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 52:a51c77007319 1078 configuration. User can add here some code to deal with this error */
mbed_official 52:a51c77007319 1079 }
mbed_official 52:a51c77007319 1080 }
mbed_official 52:a51c77007319 1081 #endif
mbed_official 52:a51c77007319 1082
mbed_official 52:a51c77007319 1083 /**
mbed_official 52:a51c77007319 1084 * @}
mbed_official 52:a51c77007319 1085 */
mbed_official 52:a51c77007319 1086
mbed_official 52:a51c77007319 1087 /**
mbed_official 52:a51c77007319 1088 * @}
mbed_official 52:a51c77007319 1089 */
mbed_official 52:a51c77007319 1090
mbed_official 52:a51c77007319 1091 /**
mbed_official 52:a51c77007319 1092 * @}
mbed_official 52:a51c77007319 1093 */
mbed_official 52:a51c77007319 1094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/