Janek Mann / mbed-src-openwear

mbed library sources modified for open wear

Dependents:   openwear-lifelogger-example

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_ll_sdmmc.h@310:6188e0254baa, 2014-09-16 (annotated)

Committer:
janekm
Date:
Tue Sep 16 22:42:01 2014 +0000
Revision:
310:6188e0254baa
Parent:
297:ec1b66a3d094 
N/A

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_ll_sdmmc.h
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief Header file of SDMMC HAL module.
mbed_official 133:d4dda5c437f0 8 ******************************************************************************
mbed_official 133:d4dda5c437f0 9 * @attention
mbed_official 133:d4dda5c437f0 10 *
mbed_official 133:d4dda5c437f0 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 12 *
mbed_official 133:d4dda5c437f0 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 14 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 16 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 19 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 21 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 22 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 23 *
mbed_official 133:d4dda5c437f0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 34 *
mbed_official 133:d4dda5c437f0 35 ******************************************************************************
mbed_official 133:d4dda5c437f0 36 */
mbed_official 133:d4dda5c437f0 37
mbed_official 133:d4dda5c437f0 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 133:d4dda5c437f0 39 #ifndef __STM32F4xx_LL_SDMMC_H
mbed_official 133:d4dda5c437f0 40 #define __STM32F4xx_LL_SDMMC_H
mbed_official 133:d4dda5c437f0 41
mbed_official 133:d4dda5c437f0 42 #ifdef __cplusplus
mbed_official 133:d4dda5c437f0 43 extern "C" {
mbed_official 133:d4dda5c437f0 44 #endif
mbed_official 133:d4dda5c437f0 45
mbed_official 133:d4dda5c437f0 46 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 47 #include "stm32f4xx_hal_def.h"
mbed_official 133:d4dda5c437f0 48
mbed_official 133:d4dda5c437f0 49 /** @addtogroup STM32F4xx_Driver
mbed_official 133:d4dda5c437f0 50 * @{
mbed_official 133:d4dda5c437f0 51 */
mbed_official 133:d4dda5c437f0 52
mbed_official 133:d4dda5c437f0 53 /** @addtogroup SDMMC
mbed_official 133:d4dda5c437f0 54 * @{
mbed_official 133:d4dda5c437f0 55 */
mbed_official 133:d4dda5c437f0 56
mbed_official 133:d4dda5c437f0 57 /* Exported types ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 58
mbed_official 133:d4dda5c437f0 59 /**
mbed_official 133:d4dda5c437f0 60 * @brief SDMMC Configuration Structure definition
mbed_official 133:d4dda5c437f0 61 */
mbed_official 133:d4dda5c437f0 62 typedef struct
mbed_official 133:d4dda5c437f0 63 {
mbed_official 133:d4dda5c437f0 64 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
mbed_official 133:d4dda5c437f0 65 This parameter can be a value of @ref SDIO_Clock_Edge */
mbed_official 133:d4dda5c437f0 66
mbed_official 133:d4dda5c437f0 67 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
mbed_official 133:d4dda5c437f0 68 enabled or disabled.
mbed_official 133:d4dda5c437f0 69 This parameter can be a value of @ref SDIO_Clock_Bypass */
mbed_official 133:d4dda5c437f0 70
mbed_official 133:d4dda5c437f0 71 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
mbed_official 133:d4dda5c437f0 72 disabled when the bus is idle.
mbed_official 133:d4dda5c437f0 73 This parameter can be a value of @ref SDIO_Clock_Power_Save */
mbed_official 133:d4dda5c437f0 74
mbed_official 133:d4dda5c437f0 75 uint32_t BusWide; /*!< Specifies the SDIO bus width.
mbed_official 133:d4dda5c437f0 76 This parameter can be a value of @ref SDIO_Bus_Wide */
mbed_official 133:d4dda5c437f0 77
mbed_official 133:d4dda5c437f0 78 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
mbed_official 133:d4dda5c437f0 79 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
mbed_official 133:d4dda5c437f0 80
mbed_official 133:d4dda5c437f0 81 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
mbed_official 133:d4dda5c437f0 82 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 133:d4dda5c437f0 83
mbed_official 133:d4dda5c437f0 84 }SDIO_InitTypeDef;
mbed_official 133:d4dda5c437f0 85
mbed_official 133:d4dda5c437f0 86
mbed_official 133:d4dda5c437f0 87 /**
mbed_official 133:d4dda5c437f0 88 * @brief SDIO Command Control structure
mbed_official 133:d4dda5c437f0 89 */
mbed_official 133:d4dda5c437f0 90 typedef struct
mbed_official 133:d4dda5c437f0 91 {
mbed_official 133:d4dda5c437f0 92 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
mbed_official 133:d4dda5c437f0 93 to a card as part of a command message. If a command
mbed_official 133:d4dda5c437f0 94 contains an argument, it must be loaded into this register
mbed_official 133:d4dda5c437f0 95 before writing the command to the command register. */
mbed_official 133:d4dda5c437f0 96
mbed_official 133:d4dda5c437f0 97 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
mbed_official 133:d4dda5c437f0 98 Max_Data = 64 */
mbed_official 133:d4dda5c437f0 99
mbed_official 133:d4dda5c437f0 100 uint32_t Response; /*!< Specifies the SDIO response type.
mbed_official 133:d4dda5c437f0 101 This parameter can be a value of @ref SDIO_Response_Type */
mbed_official 133:d4dda5c437f0 102
mbed_official 133:d4dda5c437f0 103 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
mbed_official 133:d4dda5c437f0 104 enabled or disabled.
mbed_official 133:d4dda5c437f0 105 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
mbed_official 133:d4dda5c437f0 106
mbed_official 133:d4dda5c437f0 107 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
mbed_official 133:d4dda5c437f0 108 is enabled or disabled.
mbed_official 133:d4dda5c437f0 109 This parameter can be a value of @ref SDIO_CPSM_State */
mbed_official 133:d4dda5c437f0 110 }SDIO_CmdInitTypeDef;
mbed_official 133:d4dda5c437f0 111
mbed_official 133:d4dda5c437f0 112
mbed_official 133:d4dda5c437f0 113 /**
mbed_official 133:d4dda5c437f0 114 * @brief SDIO Data Control structure
mbed_official 133:d4dda5c437f0 115 */
mbed_official 133:d4dda5c437f0 116 typedef struct
mbed_official 133:d4dda5c437f0 117 {
mbed_official 133:d4dda5c437f0 118 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
mbed_official 133:d4dda5c437f0 119
mbed_official 133:d4dda5c437f0 120 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
mbed_official 133:d4dda5c437f0 121
mbed_official 133:d4dda5c437f0 122 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
mbed_official 133:d4dda5c437f0 123 This parameter can be a value of @ref SDIO_Data_Block_Size */
mbed_official 133:d4dda5c437f0 124
mbed_official 133:d4dda5c437f0 125 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
mbed_official 133:d4dda5c437f0 126 is a read or write.
mbed_official 133:d4dda5c437f0 127 This parameter can be a value of @ref SDIO_Transfer_Direction */
mbed_official 133:d4dda5c437f0 128
mbed_official 133:d4dda5c437f0 129 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
mbed_official 133:d4dda5c437f0 130 This parameter can be a value of @ref SDIO_Transfer_Type */
mbed_official 133:d4dda5c437f0 131
mbed_official 133:d4dda5c437f0 132 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
mbed_official 133:d4dda5c437f0 133 is enabled or disabled.
mbed_official 133:d4dda5c437f0 134 This parameter can be a value of @ref SDIO_DPSM_State */
mbed_official 133:d4dda5c437f0 135 }SDIO_DataInitTypeDef;
mbed_official 133:d4dda5c437f0 136
mbed_official 133:d4dda5c437f0 137 /* Exported constants --------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 138
mbed_official 133:d4dda5c437f0 139 /** @defgroup SDIO_Exported_Constants
mbed_official 133:d4dda5c437f0 140 * @{
mbed_official 133:d4dda5c437f0 141 */
mbed_official 133:d4dda5c437f0 142
mbed_official 133:d4dda5c437f0 143 /** @defgroup SDIO_Clock_Edge
mbed_official 133:d4dda5c437f0 144 * @{
mbed_official 133:d4dda5c437f0 145 */
mbed_official 133:d4dda5c437f0 146 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 147 #define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 148
mbed_official 133:d4dda5c437f0 149 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
mbed_official 133:d4dda5c437f0 150 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
mbed_official 133:d4dda5c437f0 151 /**
mbed_official 133:d4dda5c437f0 152 * @}
mbed_official 133:d4dda5c437f0 153 */
mbed_official 133:d4dda5c437f0 154
mbed_official 133:d4dda5c437f0 155 /** @defgroup SDIO_Clock_Bypass
mbed_official 133:d4dda5c437f0 156 * @{
mbed_official 133:d4dda5c437f0 157 */
mbed_official 133:d4dda5c437f0 158 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 159 #define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 160
mbed_official 133:d4dda5c437f0 161 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
mbed_official 133:d4dda5c437f0 162 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
mbed_official 133:d4dda5c437f0 163 /**
mbed_official 133:d4dda5c437f0 164 * @}
mbed_official 133:d4dda5c437f0 165 */
mbed_official 133:d4dda5c437f0 166
mbed_official 133:d4dda5c437f0 167 /** @defgroup SDIO_Clock_Power_Save
mbed_official 133:d4dda5c437f0 168 * @{
mbed_official 133:d4dda5c437f0 169 */
mbed_official 133:d4dda5c437f0 170 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 171 #define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 172
mbed_official 133:d4dda5c437f0 173 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
mbed_official 133:d4dda5c437f0 174 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
mbed_official 133:d4dda5c437f0 175 /**
mbed_official 133:d4dda5c437f0 176 * @}
mbed_official 133:d4dda5c437f0 177 */
mbed_official 133:d4dda5c437f0 178
mbed_official 133:d4dda5c437f0 179 /** @defgroup SDIO_Bus_Wide
mbed_official 133:d4dda5c437f0 180 * @{
mbed_official 133:d4dda5c437f0 181 */
mbed_official 133:d4dda5c437f0 182 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 183 #define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 184 #define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 185
mbed_official 133:d4dda5c437f0 186 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
mbed_official 133:d4dda5c437f0 187 ((WIDE) == SDIO_BUS_WIDE_4B) || \
mbed_official 133:d4dda5c437f0 188 ((WIDE) == SDIO_BUS_WIDE_8B))
mbed_official 133:d4dda5c437f0 189 /**
mbed_official 133:d4dda5c437f0 190 * @}
mbed_official 133:d4dda5c437f0 191 */
mbed_official 133:d4dda5c437f0 192
mbed_official 133:d4dda5c437f0 193 /** @defgroup SDIO_Hardware_Flow_Control
mbed_official 133:d4dda5c437f0 194 * @{
mbed_official 133:d4dda5c437f0 195 */
mbed_official 133:d4dda5c437f0 196 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 197 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 198
mbed_official 133:d4dda5c437f0 199 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
mbed_official 133:d4dda5c437f0 200 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
mbed_official 133:d4dda5c437f0 201 /**
mbed_official 133:d4dda5c437f0 202 * @}
mbed_official 133:d4dda5c437f0 203 */
mbed_official 133:d4dda5c437f0 204
mbed_official 133:d4dda5c437f0 205 /** @defgroup SDIO_Clock_Division
mbed_official 133:d4dda5c437f0 206 * @{
mbed_official 133:d4dda5c437f0 207 */
mbed_official 133:d4dda5c437f0 208 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
mbed_official 133:d4dda5c437f0 209 /**
mbed_official 133:d4dda5c437f0 210 * @}
mbed_official 133:d4dda5c437f0 211 */
mbed_official 133:d4dda5c437f0 212
mbed_official 133:d4dda5c437f0 213 /**
mbed_official 133:d4dda5c437f0 214 * @}
mbed_official 133:d4dda5c437f0 215 */
mbed_official 133:d4dda5c437f0 216
mbed_official 133:d4dda5c437f0 217 /** @defgroup SDIO_Command_Index
mbed_official 133:d4dda5c437f0 218 * @{
mbed_official 133:d4dda5c437f0 219 */
mbed_official 133:d4dda5c437f0 220 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
mbed_official 133:d4dda5c437f0 221 /**
mbed_official 133:d4dda5c437f0 222 * @}
mbed_official 133:d4dda5c437f0 223 */
mbed_official 133:d4dda5c437f0 224
mbed_official 133:d4dda5c437f0 225 /** @defgroup SDIO_Response_Type
mbed_official 133:d4dda5c437f0 226 * @{
mbed_official 133:d4dda5c437f0 227 */
mbed_official 133:d4dda5c437f0 228 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 229 #define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 230 #define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 231
mbed_official 133:d4dda5c437f0 232 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
mbed_official 133:d4dda5c437f0 233 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
mbed_official 133:d4dda5c437f0 234 ((RESPONSE) == SDIO_RESPONSE_LONG))
mbed_official 133:d4dda5c437f0 235 /**
mbed_official 133:d4dda5c437f0 236 * @}
mbed_official 133:d4dda5c437f0 237 */
mbed_official 133:d4dda5c437f0 238
mbed_official 133:d4dda5c437f0 239 /** @defgroup SDIO_Wait_Interrupt_State
mbed_official 133:d4dda5c437f0 240 * @{
mbed_official 133:d4dda5c437f0 241 */
mbed_official 133:d4dda5c437f0 242 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 243 #define SDIO_WAIT_IT ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 244 #define SDIO_WAIT_PEND ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 245
mbed_official 133:d4dda5c437f0 246 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
mbed_official 133:d4dda5c437f0 247 ((WAIT) == SDIO_WAIT_IT) || \
mbed_official 133:d4dda5c437f0 248 ((WAIT) == SDIO_WAIT_PEND))
mbed_official 133:d4dda5c437f0 249 /**
mbed_official 133:d4dda5c437f0 250 * @}
mbed_official 133:d4dda5c437f0 251 */
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 /** @defgroup SDIO_CPSM_State
mbed_official 133:d4dda5c437f0 254 * @{
mbed_official 133:d4dda5c437f0 255 */
mbed_official 133:d4dda5c437f0 256 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 257 #define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 258
mbed_official 133:d4dda5c437f0 259 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
mbed_official 133:d4dda5c437f0 260 ((CPSM) == SDIO_CPSM_ENABLE))
mbed_official 133:d4dda5c437f0 261 /**
mbed_official 133:d4dda5c437f0 262 * @}
mbed_official 133:d4dda5c437f0 263 */
mbed_official 133:d4dda5c437f0 264
mbed_official 133:d4dda5c437f0 265 /** @defgroup SDIO_Response_Registers
mbed_official 133:d4dda5c437f0 266 * @{
mbed_official 133:d4dda5c437f0 267 */
mbed_official 133:d4dda5c437f0 268 #define SDIO_RESP1 ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 269 #define SDIO_RESP2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 270 #define SDIO_RESP3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 271 #define SDIO_RESP4 ((uint32_t)0x0000000C)
mbed_official 133:d4dda5c437f0 272
mbed_official 133:d4dda5c437f0 273 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
mbed_official 133:d4dda5c437f0 274 ((RESP) == SDIO_RESP2) || \
mbed_official 133:d4dda5c437f0 275 ((RESP) == SDIO_RESP3) || \
mbed_official 133:d4dda5c437f0 276 ((RESP) == SDIO_RESP4))
mbed_official 133:d4dda5c437f0 277 /**
mbed_official 133:d4dda5c437f0 278 * @}
mbed_official 133:d4dda5c437f0 279 */
mbed_official 133:d4dda5c437f0 280
mbed_official 133:d4dda5c437f0 281 /** @defgroup SDIO_Data_Length
mbed_official 133:d4dda5c437f0 282 * @{
mbed_official 133:d4dda5c437f0 283 */
mbed_official 133:d4dda5c437f0 284 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
mbed_official 133:d4dda5c437f0 285 /**
mbed_official 133:d4dda5c437f0 286 * @}
mbed_official 133:d4dda5c437f0 287 */
mbed_official 133:d4dda5c437f0 288
mbed_official 133:d4dda5c437f0 289 /** @defgroup SDIO_Data_Block_Size
mbed_official 133:d4dda5c437f0 290 * @{
mbed_official 133:d4dda5c437f0 291 */
mbed_official 133:d4dda5c437f0 292 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 293 #define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 294 #define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 295 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
mbed_official 133:d4dda5c437f0 296 #define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 297 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
mbed_official 133:d4dda5c437f0 298 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
mbed_official 133:d4dda5c437f0 299 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
mbed_official 133:d4dda5c437f0 300 #define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 301 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
mbed_official 133:d4dda5c437f0 302 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
mbed_official 133:d4dda5c437f0 303 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
mbed_official 133:d4dda5c437f0 304 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 305 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
mbed_official 133:d4dda5c437f0 306 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
mbed_official 133:d4dda5c437f0 307
mbed_official 133:d4dda5c437f0 308 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
mbed_official 133:d4dda5c437f0 309 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
mbed_official 133:d4dda5c437f0 310 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
mbed_official 133:d4dda5c437f0 311 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
mbed_official 133:d4dda5c437f0 312 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
mbed_official 133:d4dda5c437f0 313 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
mbed_official 133:d4dda5c437f0 314 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
mbed_official 133:d4dda5c437f0 315 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
mbed_official 133:d4dda5c437f0 316 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
mbed_official 133:d4dda5c437f0 317 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
mbed_official 133:d4dda5c437f0 318 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
mbed_official 133:d4dda5c437f0 319 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
mbed_official 133:d4dda5c437f0 320 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
mbed_official 133:d4dda5c437f0 321 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
mbed_official 133:d4dda5c437f0 322 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
mbed_official 133:d4dda5c437f0 323 /**
mbed_official 133:d4dda5c437f0 324 * @}
mbed_official 133:d4dda5c437f0 325 */
mbed_official 133:d4dda5c437f0 326
mbed_official 133:d4dda5c437f0 327 /** @defgroup SDIO_Transfer_Direction
mbed_official 133:d4dda5c437f0 328 * @{
mbed_official 133:d4dda5c437f0 329 */
mbed_official 133:d4dda5c437f0 330 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 331 #define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
mbed_official 133:d4dda5c437f0 334 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
mbed_official 133:d4dda5c437f0 335 /**
mbed_official 133:d4dda5c437f0 336 * @}
mbed_official 133:d4dda5c437f0 337 */
mbed_official 133:d4dda5c437f0 338
mbed_official 133:d4dda5c437f0 339 /** @defgroup SDIO_Transfer_Type
mbed_official 133:d4dda5c437f0 340 * @{
mbed_official 133:d4dda5c437f0 341 */
mbed_official 133:d4dda5c437f0 342 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 343 #define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 344
mbed_official 133:d4dda5c437f0 345 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
mbed_official 133:d4dda5c437f0 346 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
mbed_official 133:d4dda5c437f0 347 /**
mbed_official 133:d4dda5c437f0 348 * @}
mbed_official 133:d4dda5c437f0 349 */
mbed_official 133:d4dda5c437f0 350
mbed_official 133:d4dda5c437f0 351 /** @defgroup SDIO_DPSM_State
mbed_official 133:d4dda5c437f0 352 * @{
mbed_official 133:d4dda5c437f0 353 */
mbed_official 133:d4dda5c437f0 354 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 355 #define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 356
mbed_official 133:d4dda5c437f0 357 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
mbed_official 133:d4dda5c437f0 358 ((DPSM) == SDIO_DPSM_ENABLE))
mbed_official 133:d4dda5c437f0 359 /**
mbed_official 133:d4dda5c437f0 360 * @}
mbed_official 133:d4dda5c437f0 361 */
mbed_official 133:d4dda5c437f0 362
mbed_official 133:d4dda5c437f0 363 /** @defgroup SDIO_Read_Wait_Mode
mbed_official 133:d4dda5c437f0 364 * @{
mbed_official 133:d4dda5c437f0 365 */
mbed_official 133:d4dda5c437f0 366 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 367 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 368
mbed_official 133:d4dda5c437f0 369 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
mbed_official 133:d4dda5c437f0 370 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
mbed_official 133:d4dda5c437f0 371 /**
mbed_official 133:d4dda5c437f0 372 * @}
mbed_official 133:d4dda5c437f0 373 */
mbed_official 133:d4dda5c437f0 374
mbed_official 133:d4dda5c437f0 375 /** @defgroup SDIO_Interrupt_sources
mbed_official 133:d4dda5c437f0 376 * @{
mbed_official 133:d4dda5c437f0 377 */
mbed_official 133:d4dda5c437f0 378 #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 379 #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 380 #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 381 #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 382 #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 383 #define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 384 #define SDIO_IT_CMDREND ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 385 #define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 386 #define SDIO_IT_DATAEND ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 387 #define SDIO_IT_STBITERR ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 388 #define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 389 #define SDIO_IT_CMDACT ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 390 #define SDIO_IT_TXACT ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 391 #define SDIO_IT_RXACT ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 392 #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 393 #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 394 #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 395 #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 396 #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 397 #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 398 #define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 399 #define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 400 #define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 401 #define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 402
mbed_official 133:d4dda5c437f0 403 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
mbed_official 133:d4dda5c437f0 404 /**
mbed_official 133:d4dda5c437f0 405 * @}
mbed_official 133:d4dda5c437f0 406 */
mbed_official 133:d4dda5c437f0 407
mbed_official 133:d4dda5c437f0 408 /** @defgroup SDIO_Flags
mbed_official 133:d4dda5c437f0 409 * @{
mbed_official 133:d4dda5c437f0 410 */
mbed_official 133:d4dda5c437f0 411 #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 412 #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 413 #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 414 #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 415 #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 416 #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 417 #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 418 #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 419 #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 420 #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 421 #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 422 #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 423 #define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 424 #define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 425 #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 426 #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 427 #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 428 #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 429 #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 430 #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 431 #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 432 #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 433 #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 434 #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 435
mbed_official 133:d4dda5c437f0 436 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
mbed_official 133:d4dda5c437f0 437 ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
mbed_official 133:d4dda5c437f0 438 ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
mbed_official 133:d4dda5c437f0 439 ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
mbed_official 133:d4dda5c437f0 440 ((FLAG) == SDIO_FLAG_TXUNDERR) || \
mbed_official 133:d4dda5c437f0 441 ((FLAG) == SDIO_FLAG_RXOVERR) || \
mbed_official 133:d4dda5c437f0 442 ((FLAG) == SDIO_FLAG_CMDREND) || \
mbed_official 133:d4dda5c437f0 443 ((FLAG) == SDIO_FLAG_CMDSENT) || \
mbed_official 133:d4dda5c437f0 444 ((FLAG) == SDIO_FLAG_DATAEND) || \
mbed_official 133:d4dda5c437f0 445 ((FLAG) == SDIO_FLAG_STBITERR) || \
mbed_official 133:d4dda5c437f0 446 ((FLAG) == SDIO_FLAG_DBCKEND) || \
mbed_official 133:d4dda5c437f0 447 ((FLAG) == SDIO_FLAG_CMDACT) || \
mbed_official 133:d4dda5c437f0 448 ((FLAG) == SDIO_FLAG_TXACT) || \
mbed_official 133:d4dda5c437f0 449 ((FLAG) == SDIO_FLAG_RXACT) || \
mbed_official 133:d4dda5c437f0 450 ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
mbed_official 133:d4dda5c437f0 451 ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
mbed_official 133:d4dda5c437f0 452 ((FLAG) == SDIO_FLAG_TXFIFOF) || \
mbed_official 133:d4dda5c437f0 453 ((FLAG) == SDIO_FLAG_RXFIFOF) || \
mbed_official 133:d4dda5c437f0 454 ((FLAG) == SDIO_FLAG_TXFIFOE) || \
mbed_official 133:d4dda5c437f0 455 ((FLAG) == SDIO_FLAG_RXFIFOE) || \
mbed_official 133:d4dda5c437f0 456 ((FLAG) == SDIO_FLAG_TXDAVL) || \
mbed_official 133:d4dda5c437f0 457 ((FLAG) == SDIO_FLAG_RXDAVL) || \
mbed_official 133:d4dda5c437f0 458 ((FLAG) == SDIO_FLAG_SDIOIT) || \
mbed_official 133:d4dda5c437f0 459 ((FLAG) == SDIO_FLAG_CEATAEND))
mbed_official 133:d4dda5c437f0 460
mbed_official 133:d4dda5c437f0 461 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
mbed_official 133:d4dda5c437f0 462
mbed_official 133:d4dda5c437f0 463 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
mbed_official 133:d4dda5c437f0 464 ((IT) == SDIO_IT_DCRCFAIL) || \
mbed_official 133:d4dda5c437f0 465 ((IT) == SDIO_IT_CTIMEOUT) || \
mbed_official 133:d4dda5c437f0 466 ((IT) == SDIO_IT_DTIMEOUT) || \
mbed_official 133:d4dda5c437f0 467 ((IT) == SDIO_IT_TXUNDERR) || \
mbed_official 133:d4dda5c437f0 468 ((IT) == SDIO_IT_RXOVERR) || \
mbed_official 133:d4dda5c437f0 469 ((IT) == SDIO_IT_CMDREND) || \
mbed_official 133:d4dda5c437f0 470 ((IT) == SDIO_IT_CMDSENT) || \
mbed_official 133:d4dda5c437f0 471 ((IT) == SDIO_IT_DATAEND) || \
mbed_official 133:d4dda5c437f0 472 ((IT) == SDIO_IT_STBITERR) || \
mbed_official 133:d4dda5c437f0 473 ((IT) == SDIO_IT_DBCKEND) || \
mbed_official 133:d4dda5c437f0 474 ((IT) == SDIO_IT_CMDACT) || \
mbed_official 133:d4dda5c437f0 475 ((IT) == SDIO_IT_TXACT) || \
mbed_official 133:d4dda5c437f0 476 ((IT) == SDIO_IT_RXACT) || \
mbed_official 133:d4dda5c437f0 477 ((IT) == SDIO_IT_TXFIFOHE) || \
mbed_official 133:d4dda5c437f0 478 ((IT) == SDIO_IT_RXFIFOHF) || \
mbed_official 133:d4dda5c437f0 479 ((IT) == SDIO_IT_TXFIFOF) || \
mbed_official 133:d4dda5c437f0 480 ((IT) == SDIO_IT_RXFIFOF) || \
mbed_official 133:d4dda5c437f0 481 ((IT) == SDIO_IT_TXFIFOE) || \
mbed_official 133:d4dda5c437f0 482 ((IT) == SDIO_IT_RXFIFOE) || \
mbed_official 133:d4dda5c437f0 483 ((IT) == SDIO_IT_TXDAVL) || \
mbed_official 133:d4dda5c437f0 484 ((IT) == SDIO_IT_RXDAVL) || \
mbed_official 133:d4dda5c437f0 485 ((IT) == SDIO_IT_SDIOIT) || \
mbed_official 133:d4dda5c437f0 486 ((IT) == SDIO_IT_CEATAEND))
mbed_official 133:d4dda5c437f0 487
mbed_official 133:d4dda5c437f0 488 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
mbed_official 133:d4dda5c437f0 489
mbed_official 133:d4dda5c437f0 490 /**
mbed_official 133:d4dda5c437f0 491 * @}
mbed_official 133:d4dda5c437f0 492 */
mbed_official 133:d4dda5c437f0 493
mbed_official 133:d4dda5c437f0 494
mbed_official 133:d4dda5c437f0 495 /** @defgroup SDIO_Instance_definition
mbed_official 133:d4dda5c437f0 496 * @{
mbed_official 133:d4dda5c437f0 497 */
mbed_official 133:d4dda5c437f0 498 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
mbed_official 133:d4dda5c437f0 499
mbed_official 133:d4dda5c437f0 500 /**
mbed_official 133:d4dda5c437f0 501 * @}
mbed_official 133:d4dda5c437f0 502 */
mbed_official 133:d4dda5c437f0 503
mbed_official 133:d4dda5c437f0 504 /* Exported macro ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 505 /* ------------ SDIO registers bit address in the alias region -------------- */
mbed_official 133:d4dda5c437f0 506 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
mbed_official 133:d4dda5c437f0 507
mbed_official 133:d4dda5c437f0 508 /* --- CLKCR Register ---*/
mbed_official 133:d4dda5c437f0 509 /* Alias word address of CLKEN bit */
mbed_official 133:d4dda5c437f0 510 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
mbed_official 133:d4dda5c437f0 511 #define CLKEN_BitNumber 0x08
mbed_official 133:d4dda5c437f0 512 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
mbed_official 133:d4dda5c437f0 513
mbed_official 133:d4dda5c437f0 514 /* --- CMD Register ---*/
mbed_official 133:d4dda5c437f0 515 /* Alias word address of SDIOSUSPEND bit */
mbed_official 133:d4dda5c437f0 516 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
mbed_official 133:d4dda5c437f0 517 #define SDIOSUSPEND_BitNumber 0x0B
mbed_official 133:d4dda5c437f0 518 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
mbed_official 133:d4dda5c437f0 519
mbed_official 133:d4dda5c437f0 520 /* Alias word address of ENCMDCOMPL bit */
mbed_official 133:d4dda5c437f0 521 #define ENCMDCOMPL_BitNumber 0x0C
mbed_official 133:d4dda5c437f0 522 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
mbed_official 133:d4dda5c437f0 523
mbed_official 133:d4dda5c437f0 524 /* Alias word address of NIEN bit */
mbed_official 133:d4dda5c437f0 525 #define NIEN_BitNumber 0x0D
mbed_official 133:d4dda5c437f0 526 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
mbed_official 133:d4dda5c437f0 527
mbed_official 133:d4dda5c437f0 528 /* Alias word address of ATACMD bit */
mbed_official 133:d4dda5c437f0 529 #define ATACMD_BitNumber 0x0E
mbed_official 133:d4dda5c437f0 530 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
mbed_official 133:d4dda5c437f0 531
mbed_official 133:d4dda5c437f0 532 /* --- DCTRL Register ---*/
mbed_official 133:d4dda5c437f0 533 /* Alias word address of DMAEN bit */
mbed_official 133:d4dda5c437f0 534 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
mbed_official 133:d4dda5c437f0 535 #define DMAEN_BitNumber 0x03
mbed_official 133:d4dda5c437f0 536 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
mbed_official 133:d4dda5c437f0 537
mbed_official 133:d4dda5c437f0 538 /* Alias word address of RWSTART bit */
mbed_official 133:d4dda5c437f0 539 #define RWSTART_BitNumber 0x08
mbed_official 133:d4dda5c437f0 540 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
mbed_official 133:d4dda5c437f0 541
mbed_official 133:d4dda5c437f0 542 /* Alias word address of RWSTOP bit */
mbed_official 133:d4dda5c437f0 543 #define RWSTOP_BitNumber 0x09
mbed_official 133:d4dda5c437f0 544 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
mbed_official 133:d4dda5c437f0 545
mbed_official 133:d4dda5c437f0 546 /* Alias word address of RWMOD bit */
mbed_official 133:d4dda5c437f0 547 #define RWMOD_BitNumber 0x0A
mbed_official 133:d4dda5c437f0 548 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
mbed_official 133:d4dda5c437f0 549
mbed_official 133:d4dda5c437f0 550 /* Alias word address of SDIOEN bit */
mbed_official 133:d4dda5c437f0 551 #define SDIOEN_BitNumber 0x0B
mbed_official 133:d4dda5c437f0 552 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
mbed_official 133:d4dda5c437f0 553
mbed_official 133:d4dda5c437f0 554 /* ---------------------- SDIO registers bit mask --------------------------- */
mbed_official 133:d4dda5c437f0 555 /* --- CLKCR Register ---*/
mbed_official 133:d4dda5c437f0 556 /* CLKCR register clear mask */
mbed_official 133:d4dda5c437f0 557 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
mbed_official 133:d4dda5c437f0 558
mbed_official 133:d4dda5c437f0 559 /* --- PWRCTRL Register ---*/
mbed_official 133:d4dda5c437f0 560 /* SDIO PWRCTRL Mask */
mbed_official 133:d4dda5c437f0 561 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
mbed_official 133:d4dda5c437f0 562
mbed_official 133:d4dda5c437f0 563 /* --- DCTRL Register ---*/
mbed_official 133:d4dda5c437f0 564 /* SDIO DCTRL Clear Mask */
mbed_official 133:d4dda5c437f0 565 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
mbed_official 133:d4dda5c437f0 566
mbed_official 133:d4dda5c437f0 567 /* --- CMD Register ---*/
mbed_official 133:d4dda5c437f0 568 /* CMD Register clear mask */
mbed_official 133:d4dda5c437f0 569 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
mbed_official 133:d4dda5c437f0 570
mbed_official 133:d4dda5c437f0 571 /* SDIO RESP Registers Address */
mbed_official 133:d4dda5c437f0 572 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
mbed_official 133:d4dda5c437f0 573
mbed_official 133:d4dda5c437f0 574 /* SD FLASH SDIO Interface */
mbed_official 133:d4dda5c437f0 575 #define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
mbed_official 133:d4dda5c437f0 576
mbed_official 133:d4dda5c437f0 577 /* SDIO Intialization Frequency (400KHz max) */
mbed_official 133:d4dda5c437f0 578 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
mbed_official 133:d4dda5c437f0 579
mbed_official 133:d4dda5c437f0 580 /* SDIO Data Transfer Frequency (25MHz max) */
mbed_official 133:d4dda5c437f0 581 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
mbed_official 133:d4dda5c437f0 582
mbed_official 133:d4dda5c437f0 583 /** @defgroup SDIO_Interrupt_Clock
mbed_official 133:d4dda5c437f0 584 * @brief macros to handle interrupts and specific clock configurations
mbed_official 133:d4dda5c437f0 585 * @{
mbed_official 133:d4dda5c437f0 586 */
mbed_official 133:d4dda5c437f0 587
mbed_official 133:d4dda5c437f0 588 /**
mbed_official 133:d4dda5c437f0 589 * @brief Enable the SDIO device.
mbed_official 133:d4dda5c437f0 590 * @param None
mbed_official 133:d4dda5c437f0 591 * @retval None
mbed_official 133:d4dda5c437f0 592 */
mbed_official 133:d4dda5c437f0 593 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
mbed_official 133:d4dda5c437f0 594
mbed_official 133:d4dda5c437f0 595 /**
mbed_official 133:d4dda5c437f0 596 * @brief Disable the SDIO device.
mbed_official 133:d4dda5c437f0 597 * @param None
mbed_official 133:d4dda5c437f0 598 * @retval None
mbed_official 133:d4dda5c437f0 599 */
mbed_official 133:d4dda5c437f0 600 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
mbed_official 133:d4dda5c437f0 601
mbed_official 133:d4dda5c437f0 602 /**
mbed_official 133:d4dda5c437f0 603 * @brief Enable the SDIO DMA transfer.
mbed_official 133:d4dda5c437f0 604 * @param None
mbed_official 133:d4dda5c437f0 605 * @retval None
mbed_official 133:d4dda5c437f0 606 */
mbed_official 133:d4dda5c437f0 607 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
mbed_official 133:d4dda5c437f0 608
mbed_official 133:d4dda5c437f0 609 /**
mbed_official 133:d4dda5c437f0 610 * @brief Disable the SDIO DMA transfer.
mbed_official 133:d4dda5c437f0 611 * @param None
mbed_official 133:d4dda5c437f0 612 * @retval None
mbed_official 133:d4dda5c437f0 613 */
mbed_official 133:d4dda5c437f0 614 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
mbed_official 133:d4dda5c437f0 615
mbed_official 133:d4dda5c437f0 616 /**
mbed_official 133:d4dda5c437f0 617 * @brief Enable the SDIO device interrupt.
mbed_official 133:d4dda5c437f0 618 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 133:d4dda5c437f0 619 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
mbed_official 133:d4dda5c437f0 620 * This parameter can be one or a combination of the following values:
mbed_official 133:d4dda5c437f0 621 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 622 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 623 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 133:d4dda5c437f0 624 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 133:d4dda5c437f0 625 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 133:d4dda5c437f0 626 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 133:d4dda5c437f0 627 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 628 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 133:d4dda5c437f0 629 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 133:d4dda5c437f0 630 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 133:d4dda5c437f0 631 * bus mode interrupt
mbed_official 133:d4dda5c437f0 632 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 633 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 133:d4dda5c437f0 634 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 133:d4dda5c437f0 635 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 133:d4dda5c437f0 636 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 133:d4dda5c437f0 637 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 133:d4dda5c437f0 638 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 133:d4dda5c437f0 639 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 133:d4dda5c437f0 640 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 133:d4dda5c437f0 641 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 133:d4dda5c437f0 642 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 133:d4dda5c437f0 643 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 133:d4dda5c437f0 644 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 133:d4dda5c437f0 645 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 133:d4dda5c437f0 646 * @retval None
mbed_official 133:d4dda5c437f0 647 */
mbed_official 133:d4dda5c437f0 648 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
mbed_official 133:d4dda5c437f0 649
mbed_official 133:d4dda5c437f0 650 /**
mbed_official 133:d4dda5c437f0 651 * @brief Disable the SDIO device interrupt.
mbed_official 133:d4dda5c437f0 652 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 133:d4dda5c437f0 653 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
mbed_official 133:d4dda5c437f0 654 * This parameter can be one or a combination of the following values:
mbed_official 133:d4dda5c437f0 655 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 656 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 657 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 133:d4dda5c437f0 658 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 133:d4dda5c437f0 659 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 133:d4dda5c437f0 660 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 133:d4dda5c437f0 661 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 662 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 133:d4dda5c437f0 663 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 133:d4dda5c437f0 664 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 133:d4dda5c437f0 665 * bus mode interrupt
mbed_official 133:d4dda5c437f0 666 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 667 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 133:d4dda5c437f0 668 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 133:d4dda5c437f0 669 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 133:d4dda5c437f0 670 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 133:d4dda5c437f0 671 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 133:d4dda5c437f0 672 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 133:d4dda5c437f0 673 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 133:d4dda5c437f0 674 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 133:d4dda5c437f0 675 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 133:d4dda5c437f0 676 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 133:d4dda5c437f0 677 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 133:d4dda5c437f0 678 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 133:d4dda5c437f0 679 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 133:d4dda5c437f0 680 * @retval None
mbed_official 133:d4dda5c437f0 681 */
mbed_official 133:d4dda5c437f0 682 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
mbed_official 133:d4dda5c437f0 683
mbed_official 133:d4dda5c437f0 684 /**
mbed_official 133:d4dda5c437f0 685 * @brief Checks whether the specified SDIO flag is set or not.
mbed_official 133:d4dda5c437f0 686 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 133:d4dda5c437f0 687 * @param __FLAG__: specifies the flag to check.
mbed_official 133:d4dda5c437f0 688 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 689 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 133:d4dda5c437f0 690 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 133:d4dda5c437f0 691 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
mbed_official 133:d4dda5c437f0 692 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
mbed_official 133:d4dda5c437f0 693 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 133:d4dda5c437f0 694 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 133:d4dda5c437f0 695 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 133:d4dda5c437f0 696 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
mbed_official 133:d4dda5c437f0 697 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 133:d4dda5c437f0 698 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
mbed_official 133:d4dda5c437f0 699 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 133:d4dda5c437f0 700 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
mbed_official 133:d4dda5c437f0 701 * @arg SDIO_FLAG_TXACT: Data transmit in progress
mbed_official 133:d4dda5c437f0 702 * @arg SDIO_FLAG_RXACT: Data receive in progress
mbed_official 133:d4dda5c437f0 703 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
mbed_official 133:d4dda5c437f0 704 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
mbed_official 133:d4dda5c437f0 705 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
mbed_official 133:d4dda5c437f0 706 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
mbed_official 133:d4dda5c437f0 707 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
mbed_official 133:d4dda5c437f0 708 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
mbed_official 133:d4dda5c437f0 709 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
mbed_official 133:d4dda5c437f0 710 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
mbed_official 133:d4dda5c437f0 711 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
mbed_official 133:d4dda5c437f0 712 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 133:d4dda5c437f0 713 * @retval The new state of SDIO_FLAG (SET or RESET).
mbed_official 133:d4dda5c437f0 714 */
mbed_official 133:d4dda5c437f0 715 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
mbed_official 133:d4dda5c437f0 716
mbed_official 133:d4dda5c437f0 717
mbed_official 133:d4dda5c437f0 718 /**
mbed_official 133:d4dda5c437f0 719 * @brief Clears the SDIO's pending flags.
mbed_official 133:d4dda5c437f0 720 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 133:d4dda5c437f0 721 * @param __FLAG__: specifies the flag to clear.
mbed_official 133:d4dda5c437f0 722 * This parameter can be one or a combination of the following values:
mbed_official 133:d4dda5c437f0 723 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 133:d4dda5c437f0 724 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 133:d4dda5c437f0 725 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
mbed_official 133:d4dda5c437f0 726 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
mbed_official 133:d4dda5c437f0 727 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 133:d4dda5c437f0 728 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 133:d4dda5c437f0 729 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 133:d4dda5c437f0 730 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
mbed_official 133:d4dda5c437f0 731 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 133:d4dda5c437f0 732 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
mbed_official 133:d4dda5c437f0 733 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 133:d4dda5c437f0 734 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
mbed_official 133:d4dda5c437f0 735 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 133:d4dda5c437f0 736 * @retval None
mbed_official 133:d4dda5c437f0 737 */
mbed_official 133:d4dda5c437f0 738 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
mbed_official 133:d4dda5c437f0 739
mbed_official 133:d4dda5c437f0 740 /**
mbed_official 133:d4dda5c437f0 741 * @brief Checks whether the specified SDIO interrupt has occurred or not.
mbed_official 133:d4dda5c437f0 742 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 133:d4dda5c437f0 743 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
mbed_official 133:d4dda5c437f0 744 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 745 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 746 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 747 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 133:d4dda5c437f0 748 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 133:d4dda5c437f0 749 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 133:d4dda5c437f0 750 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 133:d4dda5c437f0 751 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 752 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 133:d4dda5c437f0 753 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 133:d4dda5c437f0 754 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 133:d4dda5c437f0 755 * bus mode interrupt
mbed_official 133:d4dda5c437f0 756 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 757 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 133:d4dda5c437f0 758 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 133:d4dda5c437f0 759 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 133:d4dda5c437f0 760 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 133:d4dda5c437f0 761 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 133:d4dda5c437f0 762 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 133:d4dda5c437f0 763 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 133:d4dda5c437f0 764 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 133:d4dda5c437f0 765 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 133:d4dda5c437f0 766 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 133:d4dda5c437f0 767 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 133:d4dda5c437f0 768 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 133:d4dda5c437f0 769 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 133:d4dda5c437f0 770 * @retval The new state of SDIO_IT (SET or RESET).
mbed_official 133:d4dda5c437f0 771 */
mbed_official 133:d4dda5c437f0 772 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
mbed_official 133:d4dda5c437f0 773
mbed_official 133:d4dda5c437f0 774 /**
mbed_official 133:d4dda5c437f0 775 * @brief Clears the SDIO's interrupt pending bits.
mbed_official 133:d4dda5c437f0 776 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 133:d4dda5c437f0 777 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official 133:d4dda5c437f0 778 * This parameter can be one or a combination of the following values:
mbed_official 133:d4dda5c437f0 779 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 780 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 133:d4dda5c437f0 781 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 133:d4dda5c437f0 782 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 133:d4dda5c437f0 783 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 133:d4dda5c437f0 784 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 133:d4dda5c437f0 785 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 133:d4dda5c437f0 786 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 133:d4dda5c437f0 787 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
mbed_official 133:d4dda5c437f0 788 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 133:d4dda5c437f0 789 * bus mode interrupt
mbed_official 133:d4dda5c437f0 790 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 133:d4dda5c437f0 791 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 133:d4dda5c437f0 792 * @retval None
mbed_official 133:d4dda5c437f0 793 */
mbed_official 133:d4dda5c437f0 794 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
mbed_official 133:d4dda5c437f0 795
mbed_official 133:d4dda5c437f0 796 /**
mbed_official 133:d4dda5c437f0 797 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 133:d4dda5c437f0 798 * @param None
mbed_official 133:d4dda5c437f0 799 * @retval None
mbed_official 133:d4dda5c437f0 800 */
mbed_official 133:d4dda5c437f0 801 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
mbed_official 133:d4dda5c437f0 802
mbed_official 133:d4dda5c437f0 803 /**
mbed_official 133:d4dda5c437f0 804 * @brief Disable Start the SD I/O Read Wait operations.
mbed_official 133:d4dda5c437f0 805 * @param None
mbed_official 133:d4dda5c437f0 806 * @retval None
mbed_official 133:d4dda5c437f0 807 */
mbed_official 133:d4dda5c437f0 808 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
mbed_official 133:d4dda5c437f0 809
mbed_official 133:d4dda5c437f0 810 /**
mbed_official 133:d4dda5c437f0 811 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 133:d4dda5c437f0 812 * @param None
mbed_official 133:d4dda5c437f0 813 * @retval None
mbed_official 133:d4dda5c437f0 814 */
mbed_official 133:d4dda5c437f0 815 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
mbed_official 133:d4dda5c437f0 816
mbed_official 133:d4dda5c437f0 817 /**
mbed_official 133:d4dda5c437f0 818 * @brief Disable Stop the SD I/O Read Wait operations.
mbed_official 133:d4dda5c437f0 819 * @param None
mbed_official 133:d4dda5c437f0 820 * @retval None
mbed_official 133:d4dda5c437f0 821 */
mbed_official 133:d4dda5c437f0 822 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
mbed_official 133:d4dda5c437f0 823
mbed_official 133:d4dda5c437f0 824 /**
mbed_official 133:d4dda5c437f0 825 * @brief Enable the SD I/O Mode Operation.
mbed_official 133:d4dda5c437f0 826 * @param None
mbed_official 133:d4dda5c437f0 827 * @retval None
mbed_official 133:d4dda5c437f0 828 */
mbed_official 133:d4dda5c437f0 829 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
mbed_official 133:d4dda5c437f0 830
mbed_official 133:d4dda5c437f0 831 /**
mbed_official 133:d4dda5c437f0 832 * @brief Disable the SD I/O Mode Operation.
mbed_official 133:d4dda5c437f0 833 * @param None
mbed_official 133:d4dda5c437f0 834 * @retval None
mbed_official 133:d4dda5c437f0 835 */
mbed_official 133:d4dda5c437f0 836 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
mbed_official 133:d4dda5c437f0 837
mbed_official 133:d4dda5c437f0 838 /**
mbed_official 133:d4dda5c437f0 839 * @brief Enable the SD I/O Suspend command sending.
mbed_official 133:d4dda5c437f0 840 * @param None
mbed_official 133:d4dda5c437f0 841 * @retval None
mbed_official 133:d4dda5c437f0 842 */
mbed_official 133:d4dda5c437f0 843 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
mbed_official 133:d4dda5c437f0 844
mbed_official 133:d4dda5c437f0 845 /**
mbed_official 133:d4dda5c437f0 846 * @brief Disable the SD I/O Suspend command sending.
mbed_official 133:d4dda5c437f0 847 * @param None
mbed_official 133:d4dda5c437f0 848 * @retval None
mbed_official 133:d4dda5c437f0 849 */
mbed_official 133:d4dda5c437f0 850 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
mbed_official 133:d4dda5c437f0 851
mbed_official 133:d4dda5c437f0 852 /**
mbed_official 133:d4dda5c437f0 853 * @brief Enable the command completion signal.
mbed_official 133:d4dda5c437f0 854 * @param None
mbed_official 133:d4dda5c437f0 855 * @retval None
mbed_official 133:d4dda5c437f0 856 */
mbed_official 133:d4dda5c437f0 857 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
mbed_official 133:d4dda5c437f0 858
mbed_official 133:d4dda5c437f0 859 /**
mbed_official 133:d4dda5c437f0 860 * @brief Disable the command completion signal.
mbed_official 133:d4dda5c437f0 861 * @param None
mbed_official 133:d4dda5c437f0 862 * @retval None
mbed_official 133:d4dda5c437f0 863 */
mbed_official 133:d4dda5c437f0 864 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
mbed_official 133:d4dda5c437f0 865
mbed_official 133:d4dda5c437f0 866 /**
mbed_official 133:d4dda5c437f0 867 * @brief Enable the CE-ATA interrupt.
mbed_official 133:d4dda5c437f0 868 * @param None
mbed_official 133:d4dda5c437f0 869 * @retval None
mbed_official 133:d4dda5c437f0 870 */
mbed_official 133:d4dda5c437f0 871 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
mbed_official 133:d4dda5c437f0 872
mbed_official 133:d4dda5c437f0 873 /**
mbed_official 133:d4dda5c437f0 874 * @brief Disable the CE-ATA interrupt.
mbed_official 133:d4dda5c437f0 875 * @param None
mbed_official 133:d4dda5c437f0 876 * @retval None
mbed_official 133:d4dda5c437f0 877 */
mbed_official 133:d4dda5c437f0 878 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
mbed_official 133:d4dda5c437f0 879
mbed_official 133:d4dda5c437f0 880 /**
mbed_official 133:d4dda5c437f0 881 * @brief Enable send CE-ATA command (CMD61).
mbed_official 133:d4dda5c437f0 882 * @param None
mbed_official 133:d4dda5c437f0 883 * @retval None
mbed_official 133:d4dda5c437f0 884 */
mbed_official 133:d4dda5c437f0 885 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
mbed_official 133:d4dda5c437f0 886
mbed_official 133:d4dda5c437f0 887 /**
mbed_official 133:d4dda5c437f0 888 * @brief Disable send CE-ATA command (CMD61).
mbed_official 133:d4dda5c437f0 889 * @param None
mbed_official 133:d4dda5c437f0 890 * @retval None
mbed_official 133:d4dda5c437f0 891 */
mbed_official 133:d4dda5c437f0 892 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
mbed_official 133:d4dda5c437f0 893
mbed_official 133:d4dda5c437f0 894 /**
mbed_official 133:d4dda5c437f0 895 * @}
mbed_official 133:d4dda5c437f0 896 */
mbed_official 133:d4dda5c437f0 897
mbed_official 133:d4dda5c437f0 898 /* Exported functions --------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 899
mbed_official 133:d4dda5c437f0 900 /* Initialization/de-initialization functions **********************************/
mbed_official 133:d4dda5c437f0 901 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
mbed_official 133:d4dda5c437f0 902
mbed_official 133:d4dda5c437f0 903 /* I/O operation functions *****************************************************/
mbed_official 133:d4dda5c437f0 904 /* Blocking mode: Polling */
mbed_official 133:d4dda5c437f0 905 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 906 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
mbed_official 133:d4dda5c437f0 907
mbed_official 133:d4dda5c437f0 908 /* Peripheral Control functions ************************************************/
mbed_official 133:d4dda5c437f0 909 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 910 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 911 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 912
mbed_official 133:d4dda5c437f0 913 /* Command path state machine (CPSM) management functions */
mbed_official 133:d4dda5c437f0 914 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
mbed_official 133:d4dda5c437f0 915 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 916 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
mbed_official 133:d4dda5c437f0 917
mbed_official 133:d4dda5c437f0 918 /* Data path state machine (DPSM) management functions */
mbed_official 133:d4dda5c437f0 919 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
mbed_official 133:d4dda5c437f0 920 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 921 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
mbed_official 133:d4dda5c437f0 922
mbed_official 133:d4dda5c437f0 923 /* SDIO IO Cards mode management functions */
mbed_official 133:d4dda5c437f0 924 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
mbed_official 133:d4dda5c437f0 925
mbed_official 133:d4dda5c437f0 926 #ifdef __cplusplus
mbed_official 133:d4dda5c437f0 927 }
mbed_official 133:d4dda5c437f0 928 #endif
mbed_official 133:d4dda5c437f0 929
mbed_official 133:d4dda5c437f0 930 #endif /* __STM32F4xx_LL_SDMMC_H */
mbed_official 133:d4dda5c437f0 931
mbed_official 133:d4dda5c437f0 932 /**
mbed_official 133:d4dda5c437f0 933 * @}
mbed_official 133:d4dda5c437f0 934 */
mbed_official 133:d4dda5c437f0 935
mbed_official 133:d4dda5c437f0 936 /**
mbed_official 133:d4dda5c437f0 937 * @}
mbed_official 133:d4dda5c437f0 938 */
mbed_official 133:d4dda5c437f0 939
mbed_official 133:d4dda5c437f0 940 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/