mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_ll_fsmc.c@310:6188e0254baa, 2014-09-16 (annotated)
- Committer:
- janekm
- Date:
- Tue Sep 16 22:42:01 2014 +0000
- Revision:
- 310:6188e0254baa
- Parent:
- 297:ec1b66a3d094
N/A
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 133:d4dda5c437f0 | 1 | /** |
mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_ll_fsmc.c |
mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
mbed_official | 133:d4dda5c437f0 | 7 | * @brief FSMC Low Layer HAL module driver. |
mbed_official | 133:d4dda5c437f0 | 8 | * |
mbed_official | 133:d4dda5c437f0 | 9 | * This file provides firmware functions to manage the following |
mbed_official | 133:d4dda5c437f0 | 10 | * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: |
mbed_official | 133:d4dda5c437f0 | 11 | * + Initialization/de-initialization functions |
mbed_official | 133:d4dda5c437f0 | 12 | * + Peripheral Control functions |
mbed_official | 133:d4dda5c437f0 | 13 | * + Peripheral State functions |
mbed_official | 133:d4dda5c437f0 | 14 | * |
mbed_official | 133:d4dda5c437f0 | 15 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 16 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 17 | ##### FSMC peripheral features ##### |
mbed_official | 133:d4dda5c437f0 | 18 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 19 | [..] The Flexible static memory controller (FSMC) includes two memory controllers: |
mbed_official | 133:d4dda5c437f0 | 20 | (+) The NOR/PSRAM memory controller |
mbed_official | 133:d4dda5c437f0 | 21 | (+) The NAND/PC Card memory controller |
mbed_official | 133:d4dda5c437f0 | 22 | |
mbed_official | 133:d4dda5c437f0 | 23 | [..] The FSMC functional block makes the interface with synchronous and asynchronous static |
mbed_official | 133:d4dda5c437f0 | 24 | memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: |
mbed_official | 133:d4dda5c437f0 | 25 | (+) to translate AHB transactions into the appropriate external device protocol. |
mbed_official | 133:d4dda5c437f0 | 26 | (+) to meet the access time requirements of the external memory devices. |
mbed_official | 133:d4dda5c437f0 | 27 | |
mbed_official | 133:d4dda5c437f0 | 28 | [..] All external memories share the addresses, data and control signals with the controller. |
mbed_official | 133:d4dda5c437f0 | 29 | Each external device is accessed by means of a unique Chip Select. The FSMC performs |
mbed_official | 133:d4dda5c437f0 | 30 | only one access at a time to an external device. |
mbed_official | 133:d4dda5c437f0 | 31 | The main features of the FSMC controller are the following: |
mbed_official | 133:d4dda5c437f0 | 32 | (+) Interface with static-memory mapped devices including: |
mbed_official | 133:d4dda5c437f0 | 33 | (++) Static random access memory (SRAM). |
mbed_official | 133:d4dda5c437f0 | 34 | (++) Read-only memory (ROM). |
mbed_official | 133:d4dda5c437f0 | 35 | (++) NOR Flash memory/OneNAND Flash memory. |
mbed_official | 133:d4dda5c437f0 | 36 | (++) PSRAM (4 memory banks). |
mbed_official | 133:d4dda5c437f0 | 37 | (++) 16-bit PC Card compatible devices. |
mbed_official | 133:d4dda5c437f0 | 38 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
mbed_official | 133:d4dda5c437f0 | 39 | data. |
mbed_official | 133:d4dda5c437f0 | 40 | (+) Independent Chip Select control for each memory bank. |
mbed_official | 133:d4dda5c437f0 | 41 | (+) Independent configuration for each memory bank. |
mbed_official | 133:d4dda5c437f0 | 42 | |
mbed_official | 133:d4dda5c437f0 | 43 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 44 | ****************************************************************************** |
mbed_official | 133:d4dda5c437f0 | 45 | * @attention |
mbed_official | 133:d4dda5c437f0 | 46 | * |
mbed_official | 133:d4dda5c437f0 | 47 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 133:d4dda5c437f0 | 48 | * |
mbed_official | 133:d4dda5c437f0 | 49 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 133:d4dda5c437f0 | 50 | * are permitted provided that the following conditions are met: |
mbed_official | 133:d4dda5c437f0 | 51 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 133:d4dda5c437f0 | 52 | * this list of conditions and the following disclaimer. |
mbed_official | 133:d4dda5c437f0 | 53 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 133:d4dda5c437f0 | 54 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 133:d4dda5c437f0 | 55 | * and/or other materials provided with the distribution. |
mbed_official | 133:d4dda5c437f0 | 56 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 133:d4dda5c437f0 | 57 | * may be used to endorse or promote products derived from this software |
mbed_official | 133:d4dda5c437f0 | 58 | * without specific prior written permission. |
mbed_official | 133:d4dda5c437f0 | 59 | * |
mbed_official | 133:d4dda5c437f0 | 60 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 133:d4dda5c437f0 | 61 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 133:d4dda5c437f0 | 62 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 133:d4dda5c437f0 | 63 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 133:d4dda5c437f0 | 64 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 133:d4dda5c437f0 | 65 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 133:d4dda5c437f0 | 66 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 133:d4dda5c437f0 | 67 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 133:d4dda5c437f0 | 68 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 133:d4dda5c437f0 | 69 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 133:d4dda5c437f0 | 70 | * |
mbed_official | 133:d4dda5c437f0 | 71 | ****************************************************************************** |
mbed_official | 133:d4dda5c437f0 | 72 | */ |
mbed_official | 133:d4dda5c437f0 | 73 | |
mbed_official | 133:d4dda5c437f0 | 74 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 75 | #include "stm32f4xx_hal.h" |
mbed_official | 133:d4dda5c437f0 | 76 | |
mbed_official | 133:d4dda5c437f0 | 77 | /** @addtogroup STM32F4xx_HAL_Driver |
mbed_official | 133:d4dda5c437f0 | 78 | * @{ |
mbed_official | 133:d4dda5c437f0 | 79 | */ |
mbed_official | 133:d4dda5c437f0 | 80 | |
mbed_official | 133:d4dda5c437f0 | 81 | /** @defgroup FSMC |
mbed_official | 133:d4dda5c437f0 | 82 | * @brief FSMC driver modules |
mbed_official | 133:d4dda5c437f0 | 83 | * @{ |
mbed_official | 133:d4dda5c437f0 | 84 | */ |
mbed_official | 133:d4dda5c437f0 | 85 | |
mbed_official | 133:d4dda5c437f0 | 86 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) |
mbed_official | 133:d4dda5c437f0 | 87 | |
mbed_official | 133:d4dda5c437f0 | 88 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
mbed_official | 133:d4dda5c437f0 | 89 | |
mbed_official | 133:d4dda5c437f0 | 90 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 91 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 92 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 93 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 94 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 95 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 96 | |
mbed_official | 133:d4dda5c437f0 | 97 | /** @defgroup FSMC_Private_Functions |
mbed_official | 133:d4dda5c437f0 | 98 | * @{ |
mbed_official | 133:d4dda5c437f0 | 99 | */ |
mbed_official | 133:d4dda5c437f0 | 100 | |
mbed_official | 133:d4dda5c437f0 | 101 | /** @defgroup FSMC_NORSRAM Controller functions |
mbed_official | 133:d4dda5c437f0 | 102 | * @brief NORSRAM Controller functions |
mbed_official | 133:d4dda5c437f0 | 103 | * |
mbed_official | 133:d4dda5c437f0 | 104 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 105 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 106 | ##### How to use NORSRAM device driver ##### |
mbed_official | 133:d4dda5c437f0 | 107 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 108 | |
mbed_official | 133:d4dda5c437f0 | 109 | [..] |
mbed_official | 133:d4dda5c437f0 | 110 | This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order |
mbed_official | 133:d4dda5c437f0 | 111 | to run the NORSRAM external devices. |
mbed_official | 133:d4dda5c437f0 | 112 | |
mbed_official | 133:d4dda5c437f0 | 113 | (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() |
mbed_official | 133:d4dda5c437f0 | 114 | (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() |
mbed_official | 133:d4dda5c437f0 | 115 | (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 116 | (+) FSMC NORSRAM bank extended timing configuration using the function |
mbed_official | 133:d4dda5c437f0 | 117 | FSMC_NORSRAM_Extended_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 118 | (+) FSMC NORSRAM bank enable/disable write operation using the functions |
mbed_official | 133:d4dda5c437f0 | 119 | FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() |
mbed_official | 133:d4dda5c437f0 | 120 | |
mbed_official | 133:d4dda5c437f0 | 121 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 122 | * @{ |
mbed_official | 133:d4dda5c437f0 | 123 | */ |
mbed_official | 133:d4dda5c437f0 | 124 | |
mbed_official | 133:d4dda5c437f0 | 125 | /** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions |
mbed_official | 133:d4dda5c437f0 | 126 | * @brief Initialization and Configuration functions |
mbed_official | 133:d4dda5c437f0 | 127 | * |
mbed_official | 133:d4dda5c437f0 | 128 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 129 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 130 | ##### Initialization and de_initialization functions ##### |
mbed_official | 133:d4dda5c437f0 | 131 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 132 | [..] |
mbed_official | 133:d4dda5c437f0 | 133 | This section provides functions allowing to: |
mbed_official | 133:d4dda5c437f0 | 134 | (+) Initialize and configure the FSMC NORSRAM interface |
mbed_official | 133:d4dda5c437f0 | 135 | (+) De-initialize the FSMC NORSRAM interface |
mbed_official | 133:d4dda5c437f0 | 136 | (+) Configure the FSMC clock and associated GPIOs |
mbed_official | 133:d4dda5c437f0 | 137 | |
mbed_official | 133:d4dda5c437f0 | 138 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 139 | * @{ |
mbed_official | 133:d4dda5c437f0 | 140 | */ |
mbed_official | 133:d4dda5c437f0 | 141 | |
mbed_official | 133:d4dda5c437f0 | 142 | /** |
mbed_official | 133:d4dda5c437f0 | 143 | * @brief Initialize the FSMC_NORSRAM device according to the specified |
mbed_official | 133:d4dda5c437f0 | 144 | * control parameters in the FSMC_NORSRAM_InitTypeDef |
mbed_official | 133:d4dda5c437f0 | 145 | * @param Device: Pointer to NORSRAM device instance |
mbed_official | 133:d4dda5c437f0 | 146 | * @param Init: Pointer to NORSRAM Initialization structure |
mbed_official | 133:d4dda5c437f0 | 147 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 148 | */ |
mbed_official | 133:d4dda5c437f0 | 149 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) |
mbed_official | 133:d4dda5c437f0 | 150 | { |
mbed_official | 133:d4dda5c437f0 | 151 | uint32_t tmpr = 0; |
mbed_official | 133:d4dda5c437f0 | 152 | |
mbed_official | 133:d4dda5c437f0 | 153 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 154 | assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); |
mbed_official | 133:d4dda5c437f0 | 155 | assert_param(IS_FSMC_MUX(Init->DataAddressMux)); |
mbed_official | 133:d4dda5c437f0 | 156 | assert_param(IS_FSMC_MEMORY(Init->MemoryType)); |
mbed_official | 133:d4dda5c437f0 | 157 | assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
mbed_official | 133:d4dda5c437f0 | 158 | assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); |
mbed_official | 133:d4dda5c437f0 | 159 | assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
mbed_official | 133:d4dda5c437f0 | 160 | assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); |
mbed_official | 133:d4dda5c437f0 | 161 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
mbed_official | 133:d4dda5c437f0 | 162 | assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); |
mbed_official | 133:d4dda5c437f0 | 163 | assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); |
mbed_official | 133:d4dda5c437f0 | 164 | assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); |
mbed_official | 133:d4dda5c437f0 | 165 | assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); |
mbed_official | 133:d4dda5c437f0 | 166 | assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); |
mbed_official | 133:d4dda5c437f0 | 167 | |
mbed_official | 133:d4dda5c437f0 | 168 | /* Set NORSRAM device control parameters */ |
mbed_official | 133:d4dda5c437f0 | 169 | tmpr = (uint32_t)(Init->DataAddressMux |\ |
mbed_official | 133:d4dda5c437f0 | 170 | Init->MemoryType |\ |
mbed_official | 133:d4dda5c437f0 | 171 | Init->MemoryDataWidth |\ |
mbed_official | 133:d4dda5c437f0 | 172 | Init->BurstAccessMode |\ |
mbed_official | 133:d4dda5c437f0 | 173 | Init->WaitSignalPolarity |\ |
mbed_official | 133:d4dda5c437f0 | 174 | Init->WrapMode |\ |
mbed_official | 133:d4dda5c437f0 | 175 | Init->WaitSignalActive |\ |
mbed_official | 133:d4dda5c437f0 | 176 | Init->WriteOperation |\ |
mbed_official | 133:d4dda5c437f0 | 177 | Init->WaitSignal |\ |
mbed_official | 133:d4dda5c437f0 | 178 | Init->ExtendedMode |\ |
mbed_official | 133:d4dda5c437f0 | 179 | Init->AsynchronousWait |\ |
mbed_official | 133:d4dda5c437f0 | 180 | Init->WriteBurst |
mbed_official | 133:d4dda5c437f0 | 181 | ); |
mbed_official | 133:d4dda5c437f0 | 182 | |
mbed_official | 133:d4dda5c437f0 | 183 | if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) |
mbed_official | 133:d4dda5c437f0 | 184 | { |
mbed_official | 133:d4dda5c437f0 | 185 | tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; |
mbed_official | 133:d4dda5c437f0 | 186 | } |
mbed_official | 133:d4dda5c437f0 | 187 | |
mbed_official | 133:d4dda5c437f0 | 188 | Device->BTCR[Init->NSBank] = tmpr; |
mbed_official | 133:d4dda5c437f0 | 189 | |
mbed_official | 133:d4dda5c437f0 | 190 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 191 | } |
mbed_official | 133:d4dda5c437f0 | 192 | |
mbed_official | 133:d4dda5c437f0 | 193 | |
mbed_official | 133:d4dda5c437f0 | 194 | /** |
mbed_official | 133:d4dda5c437f0 | 195 | * @brief DeInitialize the FSMC_NORSRAM peripheral |
mbed_official | 133:d4dda5c437f0 | 196 | * @param Device: Pointer to NORSRAM device instance |
mbed_official | 133:d4dda5c437f0 | 197 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
mbed_official | 133:d4dda5c437f0 | 198 | * @param Bank: NORSRAM bank number |
mbed_official | 133:d4dda5c437f0 | 199 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 200 | */ |
mbed_official | 133:d4dda5c437f0 | 201 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 202 | { |
mbed_official | 133:d4dda5c437f0 | 203 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 204 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
mbed_official | 133:d4dda5c437f0 | 205 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
mbed_official | 133:d4dda5c437f0 | 206 | |
mbed_official | 133:d4dda5c437f0 | 207 | /* Disable the FSMC_NORSRAM device */ |
mbed_official | 133:d4dda5c437f0 | 208 | __FSMC_NORSRAM_DISABLE(Device, Bank); |
mbed_official | 133:d4dda5c437f0 | 209 | |
mbed_official | 133:d4dda5c437f0 | 210 | /* De-initialize the FSMC_NORSRAM device */ |
mbed_official | 133:d4dda5c437f0 | 211 | /* FSMC_NORSRAM_BANK1 */ |
mbed_official | 133:d4dda5c437f0 | 212 | if(Bank == FSMC_NORSRAM_BANK1) |
mbed_official | 133:d4dda5c437f0 | 213 | { |
mbed_official | 133:d4dda5c437f0 | 214 | Device->BTCR[Bank] = 0x000030DB; |
mbed_official | 133:d4dda5c437f0 | 215 | } |
mbed_official | 133:d4dda5c437f0 | 216 | /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ |
mbed_official | 133:d4dda5c437f0 | 217 | else |
mbed_official | 133:d4dda5c437f0 | 218 | { |
mbed_official | 133:d4dda5c437f0 | 219 | Device->BTCR[Bank] = 0x000030D2; |
mbed_official | 133:d4dda5c437f0 | 220 | } |
mbed_official | 133:d4dda5c437f0 | 221 | |
mbed_official | 133:d4dda5c437f0 | 222 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
mbed_official | 133:d4dda5c437f0 | 223 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
mbed_official | 133:d4dda5c437f0 | 224 | |
mbed_official | 133:d4dda5c437f0 | 225 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 226 | } |
mbed_official | 133:d4dda5c437f0 | 227 | |
mbed_official | 133:d4dda5c437f0 | 228 | |
mbed_official | 133:d4dda5c437f0 | 229 | /** |
mbed_official | 133:d4dda5c437f0 | 230 | * @brief Initialize the FSMC_NORSRAM Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 231 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 232 | * @param Device: Pointer to NORSRAM device instance |
mbed_official | 133:d4dda5c437f0 | 233 | * @param Timing: Pointer to NORSRAM Timing structure |
mbed_official | 133:d4dda5c437f0 | 234 | * @param Bank: NORSRAM bank number |
mbed_official | 133:d4dda5c437f0 | 235 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 236 | */ |
mbed_official | 133:d4dda5c437f0 | 237 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 238 | { |
mbed_official | 133:d4dda5c437f0 | 239 | uint32_t tmpr = 0; |
mbed_official | 133:d4dda5c437f0 | 240 | |
mbed_official | 133:d4dda5c437f0 | 241 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 242 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 243 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
mbed_official | 133:d4dda5c437f0 | 244 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 245 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
mbed_official | 133:d4dda5c437f0 | 246 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
mbed_official | 133:d4dda5c437f0 | 247 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
mbed_official | 133:d4dda5c437f0 | 248 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
mbed_official | 133:d4dda5c437f0 | 249 | |
mbed_official | 133:d4dda5c437f0 | 250 | /* Set FSMC_NORSRAM device timing parameters */ |
mbed_official | 133:d4dda5c437f0 | 251 | tmpr = (uint32_t)(Timing->AddressSetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 252 | ((Timing->AddressHoldTime) << 4) |\ |
mbed_official | 133:d4dda5c437f0 | 253 | ((Timing->DataSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 254 | ((Timing->BusTurnAroundDuration) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 255 | (((Timing->CLKDivision)-1) << 20) |\ |
mbed_official | 133:d4dda5c437f0 | 256 | (((Timing->DataLatency)-2) << 24) |\ |
mbed_official | 133:d4dda5c437f0 | 257 | (Timing->AccessMode) |
mbed_official | 133:d4dda5c437f0 | 258 | ); |
mbed_official | 133:d4dda5c437f0 | 259 | |
mbed_official | 133:d4dda5c437f0 | 260 | Device->BTCR[Bank + 1] = tmpr; |
mbed_official | 133:d4dda5c437f0 | 261 | |
mbed_official | 133:d4dda5c437f0 | 262 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 263 | } |
mbed_official | 133:d4dda5c437f0 | 264 | |
mbed_official | 133:d4dda5c437f0 | 265 | /** |
mbed_official | 133:d4dda5c437f0 | 266 | * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 267 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 268 | * @param Device: Pointer to NORSRAM device instance |
mbed_official | 133:d4dda5c437f0 | 269 | * @param Timing: Pointer to NORSRAM Timing structure |
mbed_official | 133:d4dda5c437f0 | 270 | * @param Bank: NORSRAM bank number |
mbed_official | 133:d4dda5c437f0 | 271 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 272 | */ |
mbed_official | 133:d4dda5c437f0 | 273 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
mbed_official | 133:d4dda5c437f0 | 274 | { |
mbed_official | 133:d4dda5c437f0 | 275 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
mbed_official | 133:d4dda5c437f0 | 276 | if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) |
mbed_official | 133:d4dda5c437f0 | 277 | { |
mbed_official | 133:d4dda5c437f0 | 278 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 279 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 280 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
mbed_official | 133:d4dda5c437f0 | 281 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 282 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
mbed_official | 133:d4dda5c437f0 | 283 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
mbed_official | 133:d4dda5c437f0 | 284 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
mbed_official | 133:d4dda5c437f0 | 285 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
mbed_official | 133:d4dda5c437f0 | 286 | |
mbed_official | 133:d4dda5c437f0 | 287 | Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 288 | ((Timing->AddressHoldTime) << 4) |\ |
mbed_official | 133:d4dda5c437f0 | 289 | ((Timing->DataSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 290 | ((Timing->BusTurnAroundDuration) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 291 | (((Timing->CLKDivision)-1) << 20) |\ |
mbed_official | 133:d4dda5c437f0 | 292 | (((Timing->DataLatency)-2) << 24) |\ |
mbed_official | 133:d4dda5c437f0 | 293 | (Timing->AccessMode)); |
mbed_official | 133:d4dda5c437f0 | 294 | } |
mbed_official | 133:d4dda5c437f0 | 295 | else |
mbed_official | 133:d4dda5c437f0 | 296 | { |
mbed_official | 133:d4dda5c437f0 | 297 | Device->BWTR[Bank] = 0x0FFFFFFF; |
mbed_official | 133:d4dda5c437f0 | 298 | } |
mbed_official | 133:d4dda5c437f0 | 299 | |
mbed_official | 133:d4dda5c437f0 | 300 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 301 | } |
mbed_official | 133:d4dda5c437f0 | 302 | |
mbed_official | 133:d4dda5c437f0 | 303 | |
mbed_official | 133:d4dda5c437f0 | 304 | /** |
mbed_official | 133:d4dda5c437f0 | 305 | * @} |
mbed_official | 133:d4dda5c437f0 | 306 | */ |
mbed_official | 133:d4dda5c437f0 | 307 | |
mbed_official | 133:d4dda5c437f0 | 308 | |
mbed_official | 133:d4dda5c437f0 | 309 | /** @defgroup HAL_FSMC_NORSRAM_Group3 Control functions |
mbed_official | 133:d4dda5c437f0 | 310 | * @brief management functions |
mbed_official | 133:d4dda5c437f0 | 311 | * |
mbed_official | 133:d4dda5c437f0 | 312 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 313 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 314 | ##### FSMC_NORSRAM Control functions ##### |
mbed_official | 133:d4dda5c437f0 | 315 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 316 | [..] |
mbed_official | 133:d4dda5c437f0 | 317 | This subsection provides a set of functions allowing to control dynamically |
mbed_official | 133:d4dda5c437f0 | 318 | the FSMC NORSRAM interface. |
mbed_official | 133:d4dda5c437f0 | 319 | |
mbed_official | 133:d4dda5c437f0 | 320 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 321 | * @{ |
mbed_official | 133:d4dda5c437f0 | 322 | */ |
mbed_official | 133:d4dda5c437f0 | 323 | |
mbed_official | 133:d4dda5c437f0 | 324 | /** |
mbed_official | 133:d4dda5c437f0 | 325 | * @brief Enables dynamically FSMC_NORSRAM write operation. |
mbed_official | 133:d4dda5c437f0 | 326 | * @param Device: Pointer to NORSRAM device instance |
mbed_official | 133:d4dda5c437f0 | 327 | * @param Bank: NORSRAM bank number |
mbed_official | 133:d4dda5c437f0 | 328 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 329 | */ |
mbed_official | 133:d4dda5c437f0 | 330 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 331 | { |
mbed_official | 133:d4dda5c437f0 | 332 | /* Enable write operation */ |
mbed_official | 133:d4dda5c437f0 | 333 | Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; |
mbed_official | 133:d4dda5c437f0 | 334 | |
mbed_official | 133:d4dda5c437f0 | 335 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 336 | } |
mbed_official | 133:d4dda5c437f0 | 337 | |
mbed_official | 133:d4dda5c437f0 | 338 | /** |
mbed_official | 133:d4dda5c437f0 | 339 | * @brief Disables dynamically FSMC_NORSRAM write operation. |
mbed_official | 133:d4dda5c437f0 | 340 | * @param Device: Pointer to NORSRAM device instance |
mbed_official | 133:d4dda5c437f0 | 341 | * @param Bank: NORSRAM bank number |
mbed_official | 133:d4dda5c437f0 | 342 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 343 | */ |
mbed_official | 133:d4dda5c437f0 | 344 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 345 | { |
mbed_official | 133:d4dda5c437f0 | 346 | /* Disable write operation */ |
mbed_official | 133:d4dda5c437f0 | 347 | Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; |
mbed_official | 133:d4dda5c437f0 | 348 | |
mbed_official | 133:d4dda5c437f0 | 349 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 350 | } |
mbed_official | 133:d4dda5c437f0 | 351 | |
mbed_official | 133:d4dda5c437f0 | 352 | /** |
mbed_official | 133:d4dda5c437f0 | 353 | * @} |
mbed_official | 133:d4dda5c437f0 | 354 | */ |
mbed_official | 133:d4dda5c437f0 | 355 | |
mbed_official | 133:d4dda5c437f0 | 356 | /** |
mbed_official | 133:d4dda5c437f0 | 357 | * @} |
mbed_official | 133:d4dda5c437f0 | 358 | */ |
mbed_official | 133:d4dda5c437f0 | 359 | |
mbed_official | 133:d4dda5c437f0 | 360 | /** @defgroup FSMC_PCCARD Controller functions |
mbed_official | 133:d4dda5c437f0 | 361 | * @brief PCCARD Controller functions |
mbed_official | 133:d4dda5c437f0 | 362 | * |
mbed_official | 133:d4dda5c437f0 | 363 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 364 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 365 | ##### How to use NAND device driver ##### |
mbed_official | 133:d4dda5c437f0 | 366 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 367 | [..] |
mbed_official | 133:d4dda5c437f0 | 368 | This driver contains a set of APIs to interface with the FSMC NAND banks in order |
mbed_official | 133:d4dda5c437f0 | 369 | to run the NAND external devices. |
mbed_official | 133:d4dda5c437f0 | 370 | |
mbed_official | 133:d4dda5c437f0 | 371 | (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() |
mbed_official | 133:d4dda5c437f0 | 372 | (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() |
mbed_official | 133:d4dda5c437f0 | 373 | (+) FSMC NAND bank common space timing configuration using the function |
mbed_official | 133:d4dda5c437f0 | 374 | FSMC_NAND_CommonSpace_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 375 | (+) FSMC NAND bank attribute space timing configuration using the function |
mbed_official | 133:d4dda5c437f0 | 376 | FSMC_NAND_AttributeSpace_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 377 | (+) FSMC NAND bank enable/disable ECC correction feature using the functions |
mbed_official | 133:d4dda5c437f0 | 378 | FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() |
mbed_official | 133:d4dda5c437f0 | 379 | (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() |
mbed_official | 133:d4dda5c437f0 | 380 | |
mbed_official | 133:d4dda5c437f0 | 381 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 382 | * @{ |
mbed_official | 133:d4dda5c437f0 | 383 | */ |
mbed_official | 133:d4dda5c437f0 | 384 | |
mbed_official | 133:d4dda5c437f0 | 385 | /** @defgroup HAL_FSMC_NAND_Group1 Initialization/de-initialization functions |
mbed_official | 133:d4dda5c437f0 | 386 | * @brief Initialization and Configuration functions |
mbed_official | 133:d4dda5c437f0 | 387 | * |
mbed_official | 133:d4dda5c437f0 | 388 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 389 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 390 | ##### Initialization and de_initialization functions ##### |
mbed_official | 133:d4dda5c437f0 | 391 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 392 | [..] |
mbed_official | 133:d4dda5c437f0 | 393 | This section provides functions allowing to: |
mbed_official | 133:d4dda5c437f0 | 394 | (+) Initialize and configure the FSMC NAND interface |
mbed_official | 133:d4dda5c437f0 | 395 | (+) De-initialize the FSMC NAND interface |
mbed_official | 133:d4dda5c437f0 | 396 | (+) Configure the FSMC clock and associated GPIOs |
mbed_official | 133:d4dda5c437f0 | 397 | |
mbed_official | 133:d4dda5c437f0 | 398 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 399 | * @{ |
mbed_official | 133:d4dda5c437f0 | 400 | */ |
mbed_official | 133:d4dda5c437f0 | 401 | |
mbed_official | 133:d4dda5c437f0 | 402 | /** |
mbed_official | 133:d4dda5c437f0 | 403 | * @brief Initializes the FSMC_NAND device according to the specified |
mbed_official | 133:d4dda5c437f0 | 404 | * control parameters in the FSMC_NAND_HandleTypeDef |
mbed_official | 133:d4dda5c437f0 | 405 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 406 | * @param Init: Pointer to NAND Initialization structure |
mbed_official | 133:d4dda5c437f0 | 407 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 408 | */ |
mbed_official | 133:d4dda5c437f0 | 409 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) |
mbed_official | 133:d4dda5c437f0 | 410 | { |
mbed_official | 133:d4dda5c437f0 | 411 | uint32_t tmppcr = 0; |
mbed_official | 133:d4dda5c437f0 | 412 | |
mbed_official | 133:d4dda5c437f0 | 413 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 414 | assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); |
mbed_official | 133:d4dda5c437f0 | 415 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
mbed_official | 133:d4dda5c437f0 | 416 | assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
mbed_official | 133:d4dda5c437f0 | 417 | assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); |
mbed_official | 133:d4dda5c437f0 | 418 | assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
mbed_official | 133:d4dda5c437f0 | 419 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 420 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 421 | |
mbed_official | 133:d4dda5c437f0 | 422 | /* Set NAND device control parameters */ |
mbed_official | 133:d4dda5c437f0 | 423 | tmppcr = (uint32_t)(Init->Waitfeature |\ |
mbed_official | 133:d4dda5c437f0 | 424 | FSMC_PCR_MEMORY_TYPE_NAND |\ |
mbed_official | 133:d4dda5c437f0 | 425 | Init->MemoryDataWidth |\ |
mbed_official | 133:d4dda5c437f0 | 426 | Init->EccComputation |\ |
mbed_official | 133:d4dda5c437f0 | 427 | Init->ECCPageSize |\ |
mbed_official | 133:d4dda5c437f0 | 428 | ((Init->TCLRSetupTime) << 9) |\ |
mbed_official | 133:d4dda5c437f0 | 429 | ((Init->TARSetupTime) << 13) |
mbed_official | 133:d4dda5c437f0 | 430 | ); |
mbed_official | 133:d4dda5c437f0 | 431 | |
mbed_official | 133:d4dda5c437f0 | 432 | if(Init->NandBank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 433 | { |
mbed_official | 133:d4dda5c437f0 | 434 | /* NAND bank 2 registers configuration */ |
mbed_official | 133:d4dda5c437f0 | 435 | Device->PCR2 = tmppcr; |
mbed_official | 133:d4dda5c437f0 | 436 | } |
mbed_official | 133:d4dda5c437f0 | 437 | else |
mbed_official | 133:d4dda5c437f0 | 438 | { |
mbed_official | 133:d4dda5c437f0 | 439 | /* NAND bank 3 registers configuration */ |
mbed_official | 133:d4dda5c437f0 | 440 | Device->PCR3 = tmppcr; |
mbed_official | 133:d4dda5c437f0 | 441 | } |
mbed_official | 133:d4dda5c437f0 | 442 | |
mbed_official | 133:d4dda5c437f0 | 443 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 444 | |
mbed_official | 133:d4dda5c437f0 | 445 | } |
mbed_official | 133:d4dda5c437f0 | 446 | |
mbed_official | 133:d4dda5c437f0 | 447 | /** |
mbed_official | 133:d4dda5c437f0 | 448 | * @brief Initializes the FSMC_NAND Common space Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 449 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 450 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 451 | * @param Timing: Pointer to NAND timing structure |
mbed_official | 133:d4dda5c437f0 | 452 | * @param Bank: NAND bank number |
mbed_official | 133:d4dda5c437f0 | 453 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 454 | */ |
mbed_official | 133:d4dda5c437f0 | 455 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 456 | { |
mbed_official | 133:d4dda5c437f0 | 457 | uint32_t tmppmem = 0; |
mbed_official | 133:d4dda5c437f0 | 458 | |
mbed_official | 133:d4dda5c437f0 | 459 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 460 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
mbed_official | 133:d4dda5c437f0 | 461 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 462 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 463 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 464 | |
mbed_official | 133:d4dda5c437f0 | 465 | /* Set FSMC_NAND device timing parameters */ |
mbed_official | 133:d4dda5c437f0 | 466 | tmppmem = (uint32_t)(Timing->SetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 467 | ((Timing->WaitSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 468 | ((Timing->HoldSetupTime) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 469 | ((Timing->HiZSetupTime) << 24) |
mbed_official | 133:d4dda5c437f0 | 470 | ); |
mbed_official | 133:d4dda5c437f0 | 471 | |
mbed_official | 133:d4dda5c437f0 | 472 | if(Bank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 473 | { |
mbed_official | 133:d4dda5c437f0 | 474 | /* NAND bank 2 registers configuration */ |
mbed_official | 133:d4dda5c437f0 | 475 | Device->PMEM2 = tmppmem; |
mbed_official | 133:d4dda5c437f0 | 476 | } |
mbed_official | 133:d4dda5c437f0 | 477 | else |
mbed_official | 133:d4dda5c437f0 | 478 | { |
mbed_official | 133:d4dda5c437f0 | 479 | /* NAND bank 3 registers configuration */ |
mbed_official | 133:d4dda5c437f0 | 480 | Device->PMEM3 = tmppmem; |
mbed_official | 133:d4dda5c437f0 | 481 | } |
mbed_official | 133:d4dda5c437f0 | 482 | |
mbed_official | 133:d4dda5c437f0 | 483 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 484 | } |
mbed_official | 133:d4dda5c437f0 | 485 | |
mbed_official | 133:d4dda5c437f0 | 486 | /** |
mbed_official | 133:d4dda5c437f0 | 487 | * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 488 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 489 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 490 | * @param Timing: Pointer to NAND timing structure |
mbed_official | 133:d4dda5c437f0 | 491 | * @param Bank: NAND bank number |
mbed_official | 133:d4dda5c437f0 | 492 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 493 | */ |
mbed_official | 133:d4dda5c437f0 | 494 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 495 | { |
mbed_official | 133:d4dda5c437f0 | 496 | uint32_t tmppatt = 0; |
mbed_official | 133:d4dda5c437f0 | 497 | |
mbed_official | 133:d4dda5c437f0 | 498 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 499 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
mbed_official | 133:d4dda5c437f0 | 500 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 501 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 502 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 503 | |
mbed_official | 133:d4dda5c437f0 | 504 | /* Set FSMC_NAND device timing parameters */ |
mbed_official | 133:d4dda5c437f0 | 505 | tmppatt = (uint32_t)(Timing->SetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 506 | ((Timing->WaitSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 507 | ((Timing->HoldSetupTime) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 508 | ((Timing->HiZSetupTime) << 24) |
mbed_official | 133:d4dda5c437f0 | 509 | ); |
mbed_official | 133:d4dda5c437f0 | 510 | |
mbed_official | 133:d4dda5c437f0 | 511 | if(Bank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 512 | { |
mbed_official | 133:d4dda5c437f0 | 513 | /* NAND bank 2 registers configuration */ |
mbed_official | 133:d4dda5c437f0 | 514 | Device->PATT2 = tmppatt; |
mbed_official | 133:d4dda5c437f0 | 515 | } |
mbed_official | 133:d4dda5c437f0 | 516 | else |
mbed_official | 133:d4dda5c437f0 | 517 | { |
mbed_official | 133:d4dda5c437f0 | 518 | /* NAND bank 3 registers configuration */ |
mbed_official | 133:d4dda5c437f0 | 519 | Device->PATT3 = tmppatt; |
mbed_official | 133:d4dda5c437f0 | 520 | } |
mbed_official | 133:d4dda5c437f0 | 521 | |
mbed_official | 133:d4dda5c437f0 | 522 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 523 | } |
mbed_official | 133:d4dda5c437f0 | 524 | |
mbed_official | 133:d4dda5c437f0 | 525 | |
mbed_official | 133:d4dda5c437f0 | 526 | /** |
mbed_official | 133:d4dda5c437f0 | 527 | * @brief DeInitializes the FSMC_NAND device |
mbed_official | 133:d4dda5c437f0 | 528 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 529 | * @param Bank: NAND bank number |
mbed_official | 133:d4dda5c437f0 | 530 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 531 | */ |
mbed_official | 133:d4dda5c437f0 | 532 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 533 | { |
mbed_official | 133:d4dda5c437f0 | 534 | /* Disable the NAND Bank */ |
mbed_official | 133:d4dda5c437f0 | 535 | __FSMC_NAND_DISABLE(Device, Bank); |
mbed_official | 133:d4dda5c437f0 | 536 | |
mbed_official | 133:d4dda5c437f0 | 537 | /* De-initialize the NAND Bank */ |
mbed_official | 133:d4dda5c437f0 | 538 | if(Bank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 539 | { |
mbed_official | 133:d4dda5c437f0 | 540 | /* Set the FSMC_NAND_BANK2 registers to their reset values */ |
mbed_official | 133:d4dda5c437f0 | 541 | Device->PCR2 = 0x00000018; |
mbed_official | 133:d4dda5c437f0 | 542 | Device->SR2 = 0x00000040; |
mbed_official | 133:d4dda5c437f0 | 543 | Device->PMEM2 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 544 | Device->PATT2 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 545 | } |
mbed_official | 133:d4dda5c437f0 | 546 | /* FSMC_Bank3_NAND */ |
mbed_official | 133:d4dda5c437f0 | 547 | else |
mbed_official | 133:d4dda5c437f0 | 548 | { |
mbed_official | 133:d4dda5c437f0 | 549 | /* Set the FSMC_NAND_BANK3 registers to their reset values */ |
mbed_official | 133:d4dda5c437f0 | 550 | Device->PCR3 = 0x00000018; |
mbed_official | 133:d4dda5c437f0 | 551 | Device->SR3 = 0x00000040; |
mbed_official | 133:d4dda5c437f0 | 552 | Device->PMEM3 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 553 | Device->PATT3 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 554 | } |
mbed_official | 133:d4dda5c437f0 | 555 | |
mbed_official | 133:d4dda5c437f0 | 556 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 557 | } |
mbed_official | 133:d4dda5c437f0 | 558 | |
mbed_official | 133:d4dda5c437f0 | 559 | /** |
mbed_official | 133:d4dda5c437f0 | 560 | * @} |
mbed_official | 133:d4dda5c437f0 | 561 | */ |
mbed_official | 133:d4dda5c437f0 | 562 | |
mbed_official | 133:d4dda5c437f0 | 563 | |
mbed_official | 133:d4dda5c437f0 | 564 | /** @defgroup HAL_FSMC_NAND_Group3 Control functions |
mbed_official | 133:d4dda5c437f0 | 565 | * @brief management functions |
mbed_official | 133:d4dda5c437f0 | 566 | * |
mbed_official | 133:d4dda5c437f0 | 567 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 568 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 569 | ##### FSMC_NAND Control functions ##### |
mbed_official | 133:d4dda5c437f0 | 570 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 571 | [..] |
mbed_official | 133:d4dda5c437f0 | 572 | This subsection provides a set of functions allowing to control dynamically |
mbed_official | 133:d4dda5c437f0 | 573 | the FSMC NAND interface. |
mbed_official | 133:d4dda5c437f0 | 574 | |
mbed_official | 133:d4dda5c437f0 | 575 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 576 | * @{ |
mbed_official | 133:d4dda5c437f0 | 577 | */ |
mbed_official | 133:d4dda5c437f0 | 578 | |
mbed_official | 133:d4dda5c437f0 | 579 | |
mbed_official | 133:d4dda5c437f0 | 580 | /** |
mbed_official | 133:d4dda5c437f0 | 581 | * @brief Enables dynamically FSMC_NAND ECC feature. |
mbed_official | 133:d4dda5c437f0 | 582 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 583 | * @param Bank: NAND bank number |
mbed_official | 133:d4dda5c437f0 | 584 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 585 | */ |
mbed_official | 133:d4dda5c437f0 | 586 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 587 | { |
mbed_official | 133:d4dda5c437f0 | 588 | /* Enable ECC feature */ |
mbed_official | 133:d4dda5c437f0 | 589 | if(Bank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 590 | { |
mbed_official | 133:d4dda5c437f0 | 591 | Device->PCR2 |= FSMC_PCR2_ECCEN; |
mbed_official | 133:d4dda5c437f0 | 592 | } |
mbed_official | 133:d4dda5c437f0 | 593 | else |
mbed_official | 133:d4dda5c437f0 | 594 | { |
mbed_official | 133:d4dda5c437f0 | 595 | Device->PCR3 |= FSMC_PCR3_ECCEN; |
mbed_official | 133:d4dda5c437f0 | 596 | } |
mbed_official | 133:d4dda5c437f0 | 597 | |
mbed_official | 133:d4dda5c437f0 | 598 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 599 | } |
mbed_official | 133:d4dda5c437f0 | 600 | |
mbed_official | 133:d4dda5c437f0 | 601 | |
mbed_official | 133:d4dda5c437f0 | 602 | /** |
mbed_official | 133:d4dda5c437f0 | 603 | * @brief Disables dynamically FSMC_NAND ECC feature. |
mbed_official | 133:d4dda5c437f0 | 604 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 605 | * @param Bank: NAND bank number |
mbed_official | 133:d4dda5c437f0 | 606 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 607 | */ |
mbed_official | 133:d4dda5c437f0 | 608 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
mbed_official | 133:d4dda5c437f0 | 609 | { |
mbed_official | 133:d4dda5c437f0 | 610 | /* Disable ECC feature */ |
mbed_official | 133:d4dda5c437f0 | 611 | if(Bank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 612 | { |
mbed_official | 133:d4dda5c437f0 | 613 | Device->PCR2 &= ~FSMC_PCR2_ECCEN; |
mbed_official | 133:d4dda5c437f0 | 614 | } |
mbed_official | 133:d4dda5c437f0 | 615 | else |
mbed_official | 133:d4dda5c437f0 | 616 | { |
mbed_official | 133:d4dda5c437f0 | 617 | Device->PCR3 &= ~FSMC_PCR3_ECCEN; |
mbed_official | 133:d4dda5c437f0 | 618 | } |
mbed_official | 133:d4dda5c437f0 | 619 | |
mbed_official | 133:d4dda5c437f0 | 620 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 621 | } |
mbed_official | 133:d4dda5c437f0 | 622 | |
mbed_official | 133:d4dda5c437f0 | 623 | /** |
mbed_official | 133:d4dda5c437f0 | 624 | * @brief Disables dynamically FSMC_NAND ECC feature. |
mbed_official | 133:d4dda5c437f0 | 625 | * @param Device: Pointer to NAND device instance |
mbed_official | 133:d4dda5c437f0 | 626 | * @param ECCval: Pointer to ECC value |
mbed_official | 133:d4dda5c437f0 | 627 | * @param Bank: NAND bank number |
mbed_official | 133:d4dda5c437f0 | 628 | * @param Timeout: Timeout wait value |
mbed_official | 133:d4dda5c437f0 | 629 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 630 | */ |
mbed_official | 133:d4dda5c437f0 | 631 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
mbed_official | 133:d4dda5c437f0 | 632 | { |
mbed_official | 133:d4dda5c437f0 | 633 | uint32_t timeout = 0; |
mbed_official | 133:d4dda5c437f0 | 634 | |
mbed_official | 133:d4dda5c437f0 | 635 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 636 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
mbed_official | 133:d4dda5c437f0 | 637 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
mbed_official | 133:d4dda5c437f0 | 638 | |
mbed_official | 133:d4dda5c437f0 | 639 | timeout = HAL_GetTick() + Timeout; |
mbed_official | 133:d4dda5c437f0 | 640 | |
mbed_official | 133:d4dda5c437f0 | 641 | /* Wait untill FIFO is empty */ |
mbed_official | 133:d4dda5c437f0 | 642 | while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT)) |
mbed_official | 133:d4dda5c437f0 | 643 | { |
mbed_official | 133:d4dda5c437f0 | 644 | /* Check for the Timeout */ |
mbed_official | 133:d4dda5c437f0 | 645 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 133:d4dda5c437f0 | 646 | { |
mbed_official | 133:d4dda5c437f0 | 647 | if(HAL_GetTick() >= timeout) |
mbed_official | 133:d4dda5c437f0 | 648 | { |
mbed_official | 133:d4dda5c437f0 | 649 | return HAL_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 650 | } |
mbed_official | 133:d4dda5c437f0 | 651 | } |
mbed_official | 133:d4dda5c437f0 | 652 | } |
mbed_official | 133:d4dda5c437f0 | 653 | |
mbed_official | 133:d4dda5c437f0 | 654 | if(Bank == FSMC_NAND_BANK2) |
mbed_official | 133:d4dda5c437f0 | 655 | { |
mbed_official | 133:d4dda5c437f0 | 656 | /* Get the ECCR2 register value */ |
mbed_official | 133:d4dda5c437f0 | 657 | *ECCval = (uint32_t)Device->ECCR2; |
mbed_official | 133:d4dda5c437f0 | 658 | } |
mbed_official | 133:d4dda5c437f0 | 659 | else |
mbed_official | 133:d4dda5c437f0 | 660 | { |
mbed_official | 133:d4dda5c437f0 | 661 | /* Get the ECCR3 register value */ |
mbed_official | 133:d4dda5c437f0 | 662 | *ECCval = (uint32_t)Device->ECCR3; |
mbed_official | 133:d4dda5c437f0 | 663 | } |
mbed_official | 133:d4dda5c437f0 | 664 | |
mbed_official | 133:d4dda5c437f0 | 665 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 666 | } |
mbed_official | 133:d4dda5c437f0 | 667 | |
mbed_official | 133:d4dda5c437f0 | 668 | /** |
mbed_official | 133:d4dda5c437f0 | 669 | * @} |
mbed_official | 133:d4dda5c437f0 | 670 | */ |
mbed_official | 133:d4dda5c437f0 | 671 | |
mbed_official | 133:d4dda5c437f0 | 672 | /** |
mbed_official | 133:d4dda5c437f0 | 673 | * @} |
mbed_official | 133:d4dda5c437f0 | 674 | */ |
mbed_official | 133:d4dda5c437f0 | 675 | |
mbed_official | 133:d4dda5c437f0 | 676 | /** @defgroup FSMC_PCCARD Controller functions |
mbed_official | 133:d4dda5c437f0 | 677 | * @brief PCCARD Controller functions |
mbed_official | 133:d4dda5c437f0 | 678 | * |
mbed_official | 133:d4dda5c437f0 | 679 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 680 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 681 | ##### How to use PCCARD device driver ##### |
mbed_official | 133:d4dda5c437f0 | 682 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 683 | [..] |
mbed_official | 133:d4dda5c437f0 | 684 | This driver contains a set of APIs to interface with the FSMC PCCARD bank in order |
mbed_official | 133:d4dda5c437f0 | 685 | to run the PCCARD/compact flash external devices. |
mbed_official | 133:d4dda5c437f0 | 686 | |
mbed_official | 133:d4dda5c437f0 | 687 | (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() |
mbed_official | 133:d4dda5c437f0 | 688 | (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() |
mbed_official | 133:d4dda5c437f0 | 689 | (+) FSMC PCCARD bank common space timing configuration using the function |
mbed_official | 133:d4dda5c437f0 | 690 | FSMC_PCCARD_CommonSpace_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 691 | (+) FSMC PCCARD bank attribute space timing configuration using the function |
mbed_official | 133:d4dda5c437f0 | 692 | FSMC_PCCARD_AttributeSpace_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 693 | (+) FSMC PCCARD bank IO space timing configuration using the function |
mbed_official | 133:d4dda5c437f0 | 694 | FSMC_PCCARD_IOSpace_Timing_Init() |
mbed_official | 133:d4dda5c437f0 | 695 | |
mbed_official | 133:d4dda5c437f0 | 696 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 697 | * @{ |
mbed_official | 133:d4dda5c437f0 | 698 | */ |
mbed_official | 133:d4dda5c437f0 | 699 | |
mbed_official | 133:d4dda5c437f0 | 700 | /** @defgroup HAL_FSMC_PCCARD_Group1 Initialization/de-initialization functions |
mbed_official | 133:d4dda5c437f0 | 701 | * @brief Initialization and Configuration functions |
mbed_official | 133:d4dda5c437f0 | 702 | * |
mbed_official | 133:d4dda5c437f0 | 703 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 704 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 705 | ##### Initialization and de_initialization functions ##### |
mbed_official | 133:d4dda5c437f0 | 706 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 707 | [..] |
mbed_official | 133:d4dda5c437f0 | 708 | This section provides functions allowing to: |
mbed_official | 133:d4dda5c437f0 | 709 | (+) Initialize and configure the FSMC PCCARD interface |
mbed_official | 133:d4dda5c437f0 | 710 | (+) De-initialize the FSMC PCCARD interface |
mbed_official | 133:d4dda5c437f0 | 711 | (+) Configure the FSMC clock and associated GPIOs |
mbed_official | 133:d4dda5c437f0 | 712 | |
mbed_official | 133:d4dda5c437f0 | 713 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 714 | * @{ |
mbed_official | 133:d4dda5c437f0 | 715 | */ |
mbed_official | 133:d4dda5c437f0 | 716 | |
mbed_official | 133:d4dda5c437f0 | 717 | /** |
mbed_official | 133:d4dda5c437f0 | 718 | * @brief Initializes the FSMC_PCCARD device according to the specified |
mbed_official | 133:d4dda5c437f0 | 719 | * control parameters in the FSMC_PCCARD_HandleTypeDef |
mbed_official | 133:d4dda5c437f0 | 720 | * @param Device: Pointer to PCCARD device instance |
mbed_official | 133:d4dda5c437f0 | 721 | * @param Init: Pointer to PCCARD Initialization structure |
mbed_official | 133:d4dda5c437f0 | 722 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 723 | */ |
mbed_official | 133:d4dda5c437f0 | 724 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) |
mbed_official | 133:d4dda5c437f0 | 725 | { |
mbed_official | 133:d4dda5c437f0 | 726 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 727 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
mbed_official | 133:d4dda5c437f0 | 728 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 729 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 730 | |
mbed_official | 133:d4dda5c437f0 | 731 | /* Set FSMC_PCCARD device control parameters */ |
mbed_official | 133:d4dda5c437f0 | 732 | Device->PCR4 = (uint32_t)(Init->Waitfeature |\ |
mbed_official | 133:d4dda5c437f0 | 733 | FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ |
mbed_official | 133:d4dda5c437f0 | 734 | (Init->TCLRSetupTime << 9) |\ |
mbed_official | 133:d4dda5c437f0 | 735 | (Init->TARSetupTime << 13)); |
mbed_official | 133:d4dda5c437f0 | 736 | |
mbed_official | 133:d4dda5c437f0 | 737 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 738 | |
mbed_official | 133:d4dda5c437f0 | 739 | } |
mbed_official | 133:d4dda5c437f0 | 740 | |
mbed_official | 133:d4dda5c437f0 | 741 | /** |
mbed_official | 133:d4dda5c437f0 | 742 | * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 743 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 744 | * @param Device: Pointer to PCCARD device instance |
mbed_official | 133:d4dda5c437f0 | 745 | * @param Timing: Pointer to PCCARD timing structure |
mbed_official | 133:d4dda5c437f0 | 746 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 747 | */ |
mbed_official | 133:d4dda5c437f0 | 748 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
mbed_official | 133:d4dda5c437f0 | 749 | { |
mbed_official | 133:d4dda5c437f0 | 750 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 751 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
mbed_official | 133:d4dda5c437f0 | 752 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 753 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 754 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 755 | |
mbed_official | 133:d4dda5c437f0 | 756 | /* Set PCCARD timing parameters */ |
mbed_official | 133:d4dda5c437f0 | 757 | Device->PMEM4 = (uint32_t)((Timing->SetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 758 | ((Timing->WaitSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 759 | (Timing->HoldSetupTime) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 760 | ((Timing->HiZSetupTime) << 24) |
mbed_official | 133:d4dda5c437f0 | 761 | ); |
mbed_official | 133:d4dda5c437f0 | 762 | |
mbed_official | 133:d4dda5c437f0 | 763 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 764 | } |
mbed_official | 133:d4dda5c437f0 | 765 | |
mbed_official | 133:d4dda5c437f0 | 766 | /** |
mbed_official | 133:d4dda5c437f0 | 767 | * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 768 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 769 | * @param Device: Pointer to PCCARD device instance |
mbed_official | 133:d4dda5c437f0 | 770 | * @param Timing: Pointer to PCCARD timing structure |
mbed_official | 133:d4dda5c437f0 | 771 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 772 | */ |
mbed_official | 133:d4dda5c437f0 | 773 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
mbed_official | 133:d4dda5c437f0 | 774 | { |
mbed_official | 133:d4dda5c437f0 | 775 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 776 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
mbed_official | 133:d4dda5c437f0 | 777 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 778 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 779 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 780 | |
mbed_official | 133:d4dda5c437f0 | 781 | /* Set PCCARD timing parameters */ |
mbed_official | 133:d4dda5c437f0 | 782 | Device->PATT4 = (uint32_t)((Timing->SetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 783 | ((Timing->WaitSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 784 | (Timing->HoldSetupTime) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 785 | ((Timing->HiZSetupTime) << 24) |
mbed_official | 133:d4dda5c437f0 | 786 | ); |
mbed_official | 133:d4dda5c437f0 | 787 | |
mbed_official | 133:d4dda5c437f0 | 788 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 789 | } |
mbed_official | 133:d4dda5c437f0 | 790 | |
mbed_official | 133:d4dda5c437f0 | 791 | /** |
mbed_official | 133:d4dda5c437f0 | 792 | * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified |
mbed_official | 133:d4dda5c437f0 | 793 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
mbed_official | 133:d4dda5c437f0 | 794 | * @param Device: Pointer to PCCARD device instance |
mbed_official | 133:d4dda5c437f0 | 795 | * @param Timing: Pointer to PCCARD timing structure |
mbed_official | 133:d4dda5c437f0 | 796 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 797 | */ |
mbed_official | 133:d4dda5c437f0 | 798 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
mbed_official | 133:d4dda5c437f0 | 799 | { |
mbed_official | 133:d4dda5c437f0 | 800 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 801 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
mbed_official | 133:d4dda5c437f0 | 802 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 803 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 804 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
mbed_official | 133:d4dda5c437f0 | 805 | |
mbed_official | 133:d4dda5c437f0 | 806 | /* Set FSMC_PCCARD device timing parameters */ |
mbed_official | 133:d4dda5c437f0 | 807 | Device->PIO4 = (uint32_t)((Timing->SetupTime |\ |
mbed_official | 133:d4dda5c437f0 | 808 | ((Timing->WaitSetupTime) << 8) |\ |
mbed_official | 133:d4dda5c437f0 | 809 | (Timing->HoldSetupTime) << 16) |\ |
mbed_official | 133:d4dda5c437f0 | 810 | ((Timing->HiZSetupTime) << 24) |
mbed_official | 133:d4dda5c437f0 | 811 | ); |
mbed_official | 133:d4dda5c437f0 | 812 | |
mbed_official | 133:d4dda5c437f0 | 813 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 814 | } |
mbed_official | 133:d4dda5c437f0 | 815 | |
mbed_official | 133:d4dda5c437f0 | 816 | /** |
mbed_official | 133:d4dda5c437f0 | 817 | * @brief DeInitializes the FSMC_PCCARD device |
mbed_official | 133:d4dda5c437f0 | 818 | * @param Device: Pointer to PCCARD device instance |
mbed_official | 133:d4dda5c437f0 | 819 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 820 | */ |
mbed_official | 133:d4dda5c437f0 | 821 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) |
mbed_official | 133:d4dda5c437f0 | 822 | { |
mbed_official | 133:d4dda5c437f0 | 823 | /* Disable the FSMC_PCCARD device */ |
mbed_official | 133:d4dda5c437f0 | 824 | __FSMC_PCCARD_DISABLE(Device); |
mbed_official | 133:d4dda5c437f0 | 825 | |
mbed_official | 133:d4dda5c437f0 | 826 | /* De-initialize the FSMC_PCCARD device */ |
mbed_official | 133:d4dda5c437f0 | 827 | Device->PCR4 = 0x00000018; |
mbed_official | 133:d4dda5c437f0 | 828 | Device->SR4 = 0x00000000; |
mbed_official | 133:d4dda5c437f0 | 829 | Device->PMEM4 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 830 | Device->PATT4 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 831 | Device->PIO4 = 0xFCFCFCFC; |
mbed_official | 133:d4dda5c437f0 | 832 | |
mbed_official | 133:d4dda5c437f0 | 833 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 834 | } |
mbed_official | 133:d4dda5c437f0 | 835 | |
mbed_official | 133:d4dda5c437f0 | 836 | /** |
mbed_official | 133:d4dda5c437f0 | 837 | * @} |
mbed_official | 133:d4dda5c437f0 | 838 | */ |
mbed_official | 133:d4dda5c437f0 | 839 | |
mbed_official | 133:d4dda5c437f0 | 840 | /** |
mbed_official | 133:d4dda5c437f0 | 841 | * @} |
mbed_official | 133:d4dda5c437f0 | 842 | */ |
mbed_official | 133:d4dda5c437f0 | 843 | |
mbed_official | 133:d4dda5c437f0 | 844 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
mbed_official | 133:d4dda5c437f0 | 845 | |
mbed_official | 133:d4dda5c437f0 | 846 | #endif /* HAL_FSMC_MODULE_ENABLED */ |
mbed_official | 133:d4dda5c437f0 | 847 | |
mbed_official | 133:d4dda5c437f0 | 848 | /** |
mbed_official | 133:d4dda5c437f0 | 849 | * @} |
mbed_official | 133:d4dda5c437f0 | 850 | */ |
mbed_official | 133:d4dda5c437f0 | 851 | |
mbed_official | 133:d4dda5c437f0 | 852 | /** |
mbed_official | 133:d4dda5c437f0 | 853 | * @} |
mbed_official | 133:d4dda5c437f0 | 854 | */ |
mbed_official | 133:d4dda5c437f0 | 855 | |
mbed_official | 133:d4dda5c437f0 | 856 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |