Janek Mann / mbed-src-openwear

mbed library sources modified for open wear

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_tim.c@310:6188e0254baa, 2014-09-16 (annotated)

Committer:
janekm
Date:
Tue Sep 16 22:42:01 2014 +0000
Revision:
310:6188e0254baa
Parent:
181:a4cbdfbbd2f4 
N/A

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 181:a4cbdfbbd2f4 1 /**
mbed_official 181:a4cbdfbbd2f4 2 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 3 * @file stm32l0xx_hal_tim.c
mbed_official 181:a4cbdfbbd2f4 4 * @author MCD Application Team
mbed_official 181:a4cbdfbbd2f4 5 * @version V1.0.0
mbed_official 181:a4cbdfbbd2f4 6 * @date 22-April-2014
mbed_official 181:a4cbdfbbd2f4 7 * @brief TIM HAL module driver.
mbed_official 181:a4cbdfbbd2f4 8 * @brief This file provides firmware functions to manage the following
mbed_official 181:a4cbdfbbd2f4 9 * functionalities of the Timer (TIM) peripheral:
mbed_official 181:a4cbdfbbd2f4 10 * + Time Base Initialization
mbed_official 181:a4cbdfbbd2f4 11 * + Time Base Start
mbed_official 181:a4cbdfbbd2f4 12 * + Time Base Start Interruption
mbed_official 181:a4cbdfbbd2f4 13 * + Time Base Start DMA
mbed_official 181:a4cbdfbbd2f4 14 * + Time Output Compare/PWM Initialization
mbed_official 181:a4cbdfbbd2f4 15 * + Time Output Compare/PWM Channel Configuration
mbed_official 181:a4cbdfbbd2f4 16 * + Time Output Compare/PWM Start
mbed_official 181:a4cbdfbbd2f4 17 * + Time Output Compare/PWM Start Interruption
mbed_official 181:a4cbdfbbd2f4 18 * + Time Output Compare/PWM Start DMA
mbed_official 181:a4cbdfbbd2f4 19 * + Time Input Capture Initialization
mbed_official 181:a4cbdfbbd2f4 20 * + Time Input Capture Channel Configuration
mbed_official 181:a4cbdfbbd2f4 21 * + Time Input Capture Start
mbed_official 181:a4cbdfbbd2f4 22 * + Time Input Capture Start Interruption
mbed_official 181:a4cbdfbbd2f4 23 * + Time Input Capture Start DMA
mbed_official 181:a4cbdfbbd2f4 24 * + Time One Pulse Initialization
mbed_official 181:a4cbdfbbd2f4 25 * + Time One Pulse Channel Configuration
mbed_official 181:a4cbdfbbd2f4 26 * + Time One Pulse Start
mbed_official 181:a4cbdfbbd2f4 27 * + Time Encoder Interface Initialization
mbed_official 181:a4cbdfbbd2f4 28 * + Time Encoder Interface Start
mbed_official 181:a4cbdfbbd2f4 29 * + Time Encoder Interface Start Interruption
mbed_official 181:a4cbdfbbd2f4 30 * + Time Encoder Interface Start DMA
mbed_official 181:a4cbdfbbd2f4 31 * + Time OCRef clear configuration
mbed_official 181:a4cbdfbbd2f4 32 * + Time External Clock configuration
mbed_official 181:a4cbdfbbd2f4 33 * + Time Complementary signal bread and dead time configuration
mbed_official 181:a4cbdfbbd2f4 34 * + Time Master and Slave synchronization configuration
mbed_official 181:a4cbdfbbd2f4 35 @verbatim
mbed_official 181:a4cbdfbbd2f4 36 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 37 ##### TIMER Generic features #####
mbed_official 181:a4cbdfbbd2f4 38 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 39 [..] The Timer features include:
mbed_official 181:a4cbdfbbd2f4 40 (#) 16-bit up, down, up/down auto-reload counter.
mbed_official 181:a4cbdfbbd2f4 41 (#) 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
mbed_official 181:a4cbdfbbd2f4 42 frequency either by any factor between 1 and 65536.
mbed_official 181:a4cbdfbbd2f4 43 (#) Up to 4 independent channels for:
mbed_official 181:a4cbdfbbd2f4 44 Input Capture
mbed_official 181:a4cbdfbbd2f4 45 Output Compare
mbed_official 181:a4cbdfbbd2f4 46 PWM generation (Edge and Center-aligned Mode)
mbed_official 181:a4cbdfbbd2f4 47 One-pulse mode output
mbed_official 181:a4cbdfbbd2f4 48 (#) Synchronization circuit to control the timer with external signals and to interconnect
mbed_official 181:a4cbdfbbd2f4 49 several timers together.
mbed_official 181:a4cbdfbbd2f4 50 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
mbed_official 181:a4cbdfbbd2f4 51 purposes
mbed_official 181:a4cbdfbbd2f4 52
mbed_official 181:a4cbdfbbd2f4 53 ##### How to use this driver #####
mbed_official 181:a4cbdfbbd2f4 54 ================================================================================
mbed_official 181:a4cbdfbbd2f4 55 [..]
mbed_official 181:a4cbdfbbd2f4 56 (#) Enable the TIM interface clock using
mbed_official 181:a4cbdfbbd2f4 57 __TIMx_CLK_ENABLE();
mbed_official 181:a4cbdfbbd2f4 58
mbed_official 181:a4cbdfbbd2f4 59 (#) TIM pins configuration
mbed_official 181:a4cbdfbbd2f4 60 (++) Enable the clock for the TIM GPIOs using the following function:
mbed_official 181:a4cbdfbbd2f4 61 __GPIOx_CLK_ENABLE();
mbed_official 181:a4cbdfbbd2f4 62 (++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official 181:a4cbdfbbd2f4 63
mbed_official 181:a4cbdfbbd2f4 64 (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
mbed_official 181:a4cbdfbbd2f4 65 using the following function:
mbed_official 181:a4cbdfbbd2f4 66 HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
mbed_official 181:a4cbdfbbd2f4 67
mbed_official 181:a4cbdfbbd2f4 68 (#) Configure the TIM in the desired functioning mode using one of the
mbed_official 181:a4cbdfbbd2f4 69 initialization function of this driver:
mbed_official 181:a4cbdfbbd2f4 70 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official 181:a4cbdfbbd2f4 71 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official 181:a4cbdfbbd2f4 72 Output Compare signal.
mbed_official 181:a4cbdfbbd2f4 73 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official 181:a4cbdfbbd2f4 74 PWM signal.
mbed_official 181:a4cbdfbbd2f4 75 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official 181:a4cbdfbbd2f4 76 external signal.
mbed_official 181:a4cbdfbbd2f4 77 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
mbed_official 181:a4cbdfbbd2f4 78 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official 181:a4cbdfbbd2f4 79
mbed_official 181:a4cbdfbbd2f4 80 (#) Activate the TIM peripheral using one of the start functions:
mbed_official 181:a4cbdfbbd2f4 81 HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
mbed_official 181:a4cbdfbbd2f4 82 HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
mbed_official 181:a4cbdfbbd2f4 83 HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
mbed_official 181:a4cbdfbbd2f4 84 HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
mbed_official 181:a4cbdfbbd2f4 85 HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
mbed_official 181:a4cbdfbbd2f4 86 HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
mbed_official 181:a4cbdfbbd2f4 87
mbed_official 181:a4cbdfbbd2f4 88 (#) The DMA Burst is managed with the two following functions:
mbed_official 181:a4cbdfbbd2f4 89 HAL_TIM_DMABurst_WriteStart
mbed_official 181:a4cbdfbbd2f4 90 HAL_TIM_DMABurst_ReadStart
mbed_official 181:a4cbdfbbd2f4 91
mbed_official 181:a4cbdfbbd2f4 92 @endverbatim
mbed_official 181:a4cbdfbbd2f4 93 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 94 * @attention
mbed_official 181:a4cbdfbbd2f4 95 *
mbed_official 181:a4cbdfbbd2f4 96 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 181:a4cbdfbbd2f4 97 *
mbed_official 181:a4cbdfbbd2f4 98 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 181:a4cbdfbbd2f4 99 * are permitted provided that the following conditions are met:
mbed_official 181:a4cbdfbbd2f4 100 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 101 * this list of conditions and the following disclaimer.
mbed_official 181:a4cbdfbbd2f4 102 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 181:a4cbdfbbd2f4 103 * this list of conditions and the following disclaimer in the documentation
mbed_official 181:a4cbdfbbd2f4 104 * and/or other materials provided with the distribution.
mbed_official 181:a4cbdfbbd2f4 105 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 181:a4cbdfbbd2f4 106 * may be used to endorse or promote products derived from this software
mbed_official 181:a4cbdfbbd2f4 107 * without specific prior written permission.
mbed_official 181:a4cbdfbbd2f4 108 *
mbed_official 181:a4cbdfbbd2f4 109 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 181:a4cbdfbbd2f4 110 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 181:a4cbdfbbd2f4 111 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 181:a4cbdfbbd2f4 112 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 181:a4cbdfbbd2f4 113 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 181:a4cbdfbbd2f4 114 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 181:a4cbdfbbd2f4 115 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 181:a4cbdfbbd2f4 116 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 181:a4cbdfbbd2f4 117 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 181:a4cbdfbbd2f4 118 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 181:a4cbdfbbd2f4 119 *
mbed_official 181:a4cbdfbbd2f4 120 ******************************************************************************
mbed_official 181:a4cbdfbbd2f4 121 */
mbed_official 181:a4cbdfbbd2f4 122
mbed_official 181:a4cbdfbbd2f4 123 /* Includes ------------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 124 #include "stm32l0xx_hal.h"
mbed_official 181:a4cbdfbbd2f4 125
mbed_official 181:a4cbdfbbd2f4 126 /** @addtogroup STM32L0xx_HAL_Driver
mbed_official 181:a4cbdfbbd2f4 127 * @{
mbed_official 181:a4cbdfbbd2f4 128 */
mbed_official 181:a4cbdfbbd2f4 129
mbed_official 181:a4cbdfbbd2f4 130 /** @defgroup TIM
mbed_official 181:a4cbdfbbd2f4 131 * @brief TIM HAL module driver
mbed_official 181:a4cbdfbbd2f4 132 * @{
mbed_official 181:a4cbdfbbd2f4 133 */
mbed_official 181:a4cbdfbbd2f4 134
mbed_official 181:a4cbdfbbd2f4 135 #ifdef HAL_TIM_MODULE_ENABLED
mbed_official 181:a4cbdfbbd2f4 136
mbed_official 181:a4cbdfbbd2f4 137 /* Private typedef -----------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 138 /* Private define ------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 139 /* Private macro -------------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 140 /* Private variables ---------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 141 /* Private function prototypes -----------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 142 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
mbed_official 181:a4cbdfbbd2f4 143 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 181:a4cbdfbbd2f4 144 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 181:a4cbdfbbd2f4 145 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 181:a4cbdfbbd2f4 146 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 181:a4cbdfbbd2f4 147 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 148 uint32_t TIM_ICFilter);
mbed_official 181:a4cbdfbbd2f4 149 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 181:a4cbdfbbd2f4 150 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 151 uint32_t TIM_ICFilter);
mbed_official 181:a4cbdfbbd2f4 152 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 181:a4cbdfbbd2f4 153 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 154 uint32_t TIM_ICFilter);
mbed_official 181:a4cbdfbbd2f4 155 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 156 uint32_t TIM_ICFilter);
mbed_official 181:a4cbdfbbd2f4 157
mbed_official 181:a4cbdfbbd2f4 158 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 181:a4cbdfbbd2f4 159 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official 181:a4cbdfbbd2f4 160
mbed_official 181:a4cbdfbbd2f4 161 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
mbed_official 181:a4cbdfbbd2f4 162 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official 181:a4cbdfbbd2f4 163 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official 181:a4cbdfbbd2f4 164 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official 181:a4cbdfbbd2f4 165 /* Private functions ---------------------------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 166
mbed_official 181:a4cbdfbbd2f4 167 /** @defgroup TIM_Private_Functions
mbed_official 181:a4cbdfbbd2f4 168 * @{
mbed_official 181:a4cbdfbbd2f4 169 */
mbed_official 181:a4cbdfbbd2f4 170
mbed_official 181:a4cbdfbbd2f4 171 /** @defgroup HAL_TIM_Group1 Initialization/de-initialization functions
mbed_official 181:a4cbdfbbd2f4 172 * @brief Initialization and Configuration functions
mbed_official 181:a4cbdfbbd2f4 173 *
mbed_official 181:a4cbdfbbd2f4 174 @verbatim
mbed_official 181:a4cbdfbbd2f4 175 ===============================================================================
mbed_official 181:a4cbdfbbd2f4 176 ##### Initialization/de-initialization functions #####
mbed_official 181:a4cbdfbbd2f4 177 ===============================================================================
mbed_official 181:a4cbdfbbd2f4 178 [..] This section provides functions allowing to:
mbed_official 181:a4cbdfbbd2f4 179 (+) Initialize and configure the TIM.
mbed_official 181:a4cbdfbbd2f4 180 (+) De-initialize the TIM.
mbed_official 181:a4cbdfbbd2f4 181
mbed_official 181:a4cbdfbbd2f4 182 @endverbatim
mbed_official 181:a4cbdfbbd2f4 183 * @{
mbed_official 181:a4cbdfbbd2f4 184 */
mbed_official 181:a4cbdfbbd2f4 185 /**
mbed_official 181:a4cbdfbbd2f4 186 * @brief Initializes the TIM Time base Unit according to the specified
mbed_official 181:a4cbdfbbd2f4 187 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 181:a4cbdfbbd2f4 188 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 189 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 190 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 191 */
mbed_official 181:a4cbdfbbd2f4 192 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 193 {
mbed_official 181:a4cbdfbbd2f4 194 /* Check the TIM handle allocation */
mbed_official 181:a4cbdfbbd2f4 195 if(htim == NULL)
mbed_official 181:a4cbdfbbd2f4 196 {
mbed_official 181:a4cbdfbbd2f4 197 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 198 }
mbed_official 181:a4cbdfbbd2f4 199
mbed_official 181:a4cbdfbbd2f4 200 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 201 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 202 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 181:a4cbdfbbd2f4 203 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 181:a4cbdfbbd2f4 204
mbed_official 181:a4cbdfbbd2f4 205 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 206 {
mbed_official 181:a4cbdfbbd2f4 207 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 181:a4cbdfbbd2f4 208 HAL_TIM_Base_MspInit(htim);
mbed_official 181:a4cbdfbbd2f4 209 }
mbed_official 181:a4cbdfbbd2f4 210
mbed_official 181:a4cbdfbbd2f4 211 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 212 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 213
mbed_official 181:a4cbdfbbd2f4 214 /* Set the Time Base configuration */
mbed_official 181:a4cbdfbbd2f4 215 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 181:a4cbdfbbd2f4 216
mbed_official 181:a4cbdfbbd2f4 217 /* Initialize the TIM state*/
mbed_official 181:a4cbdfbbd2f4 218 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 219
mbed_official 181:a4cbdfbbd2f4 220 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 221 }
mbed_official 181:a4cbdfbbd2f4 222
mbed_official 181:a4cbdfbbd2f4 223 /**
mbed_official 181:a4cbdfbbd2f4 224 * @brief Initializes the TIM Output Compare according to the specified
mbed_official 181:a4cbdfbbd2f4 225 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 181:a4cbdfbbd2f4 226 * @param htim: TIM Output Compare handle
mbed_official 181:a4cbdfbbd2f4 227 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 228 */
mbed_official 181:a4cbdfbbd2f4 229 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official 181:a4cbdfbbd2f4 230 {
mbed_official 181:a4cbdfbbd2f4 231 /* Check the TIM handle allocation */
mbed_official 181:a4cbdfbbd2f4 232 if(htim == NULL)
mbed_official 181:a4cbdfbbd2f4 233 {
mbed_official 181:a4cbdfbbd2f4 234 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 235 }
mbed_official 181:a4cbdfbbd2f4 236
mbed_official 181:a4cbdfbbd2f4 237 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 238 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 239 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 181:a4cbdfbbd2f4 240 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 181:a4cbdfbbd2f4 241
mbed_official 181:a4cbdfbbd2f4 242 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 243 {
mbed_official 181:a4cbdfbbd2f4 244 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 181:a4cbdfbbd2f4 245 HAL_TIM_OC_MspInit(htim);
mbed_official 181:a4cbdfbbd2f4 246 }
mbed_official 181:a4cbdfbbd2f4 247 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 248 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 249
mbed_official 181:a4cbdfbbd2f4 250 /* Init the base time for the Output Compare */
mbed_official 181:a4cbdfbbd2f4 251 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 181:a4cbdfbbd2f4 252
mbed_official 181:a4cbdfbbd2f4 253 /* Initialize the TIM state*/
mbed_official 181:a4cbdfbbd2f4 254 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 255
mbed_official 181:a4cbdfbbd2f4 256 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 257 }
mbed_official 181:a4cbdfbbd2f4 258
mbed_official 181:a4cbdfbbd2f4 259 /**
mbed_official 181:a4cbdfbbd2f4 260 * @brief Initializes the TIM PWM Time Base according to the specified
mbed_official 181:a4cbdfbbd2f4 261 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 181:a4cbdfbbd2f4 262 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 263 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 264 */
mbed_official 181:a4cbdfbbd2f4 265 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 266 {
mbed_official 181:a4cbdfbbd2f4 267 /* Check the TIM handle allocation */
mbed_official 181:a4cbdfbbd2f4 268 if(htim == NULL)
mbed_official 181:a4cbdfbbd2f4 269 {
mbed_official 181:a4cbdfbbd2f4 270 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 271 }
mbed_official 181:a4cbdfbbd2f4 272
mbed_official 181:a4cbdfbbd2f4 273 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 274 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 275 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 181:a4cbdfbbd2f4 276 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 181:a4cbdfbbd2f4 277
mbed_official 181:a4cbdfbbd2f4 278 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 279 {
mbed_official 181:a4cbdfbbd2f4 280 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 281 HAL_TIM_PWM_MspInit(htim);
mbed_official 181:a4cbdfbbd2f4 282 }
mbed_official 181:a4cbdfbbd2f4 283
mbed_official 181:a4cbdfbbd2f4 284 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 285 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 286
mbed_official 181:a4cbdfbbd2f4 287 /* Init the base time for the PWM */
mbed_official 181:a4cbdfbbd2f4 288 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 181:a4cbdfbbd2f4 289
mbed_official 181:a4cbdfbbd2f4 290 /* Initialize the TIM state*/
mbed_official 181:a4cbdfbbd2f4 291 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 292
mbed_official 181:a4cbdfbbd2f4 293 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 294 }
mbed_official 181:a4cbdfbbd2f4 295
mbed_official 181:a4cbdfbbd2f4 296 /**
mbed_official 181:a4cbdfbbd2f4 297 * @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official 181:a4cbdfbbd2f4 298 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 181:a4cbdfbbd2f4 299 * @param htim: TIM Input Capture handle
mbed_official 181:a4cbdfbbd2f4 300 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 301 */
mbed_official 181:a4cbdfbbd2f4 302 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 303 {
mbed_official 181:a4cbdfbbd2f4 304 /* Check the TIM handle allocation */
mbed_official 181:a4cbdfbbd2f4 305 if(htim == NULL)
mbed_official 181:a4cbdfbbd2f4 306 {
mbed_official 181:a4cbdfbbd2f4 307 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 308 }
mbed_official 181:a4cbdfbbd2f4 309
mbed_official 181:a4cbdfbbd2f4 310 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 311 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 312 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 181:a4cbdfbbd2f4 313 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 181:a4cbdfbbd2f4 314
mbed_official 181:a4cbdfbbd2f4 315 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 316 {
mbed_official 181:a4cbdfbbd2f4 317 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 318 HAL_TIM_IC_MspInit(htim);
mbed_official 181:a4cbdfbbd2f4 319 }
mbed_official 181:a4cbdfbbd2f4 320
mbed_official 181:a4cbdfbbd2f4 321 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 322 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 323
mbed_official 181:a4cbdfbbd2f4 324 /* Init the base time for the input capture */
mbed_official 181:a4cbdfbbd2f4 325 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 181:a4cbdfbbd2f4 326
mbed_official 181:a4cbdfbbd2f4 327 /* Initialize the TIM state*/
mbed_official 181:a4cbdfbbd2f4 328 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 329
mbed_official 181:a4cbdfbbd2f4 330 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 331 }
mbed_official 181:a4cbdfbbd2f4 332
mbed_official 181:a4cbdfbbd2f4 333 /**
mbed_official 181:a4cbdfbbd2f4 334 * @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official 181:a4cbdfbbd2f4 335 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 181:a4cbdfbbd2f4 336 * @param htim: TIM OnePulse handle
mbed_official 181:a4cbdfbbd2f4 337 * @param OnePulseMode: Select the One pulse mode.
mbed_official 181:a4cbdfbbd2f4 338 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 339 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official 181:a4cbdfbbd2f4 340 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official 181:a4cbdfbbd2f4 341 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 342 */
mbed_official 181:a4cbdfbbd2f4 343 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official 181:a4cbdfbbd2f4 344 {
mbed_official 181:a4cbdfbbd2f4 345 /* Check the TIM handle allocation */
mbed_official 181:a4cbdfbbd2f4 346 if(htim == NULL)
mbed_official 181:a4cbdfbbd2f4 347 {
mbed_official 181:a4cbdfbbd2f4 348 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 349 }
mbed_official 181:a4cbdfbbd2f4 350
mbed_official 181:a4cbdfbbd2f4 351 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 352 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 353 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 181:a4cbdfbbd2f4 354 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 181:a4cbdfbbd2f4 355 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official 181:a4cbdfbbd2f4 356
mbed_official 181:a4cbdfbbd2f4 357 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 358 {
mbed_official 181:a4cbdfbbd2f4 359 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 360 HAL_TIM_OnePulse_MspInit(htim);
mbed_official 181:a4cbdfbbd2f4 361 }
mbed_official 181:a4cbdfbbd2f4 362
mbed_official 181:a4cbdfbbd2f4 363 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 364 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 365
mbed_official 181:a4cbdfbbd2f4 366 /* Configure the Time base in the One Pulse Mode */
mbed_official 181:a4cbdfbbd2f4 367 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 181:a4cbdfbbd2f4 368
mbed_official 181:a4cbdfbbd2f4 369 /* Reset the OPM Bit */
mbed_official 181:a4cbdfbbd2f4 370 htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official 181:a4cbdfbbd2f4 371
mbed_official 181:a4cbdfbbd2f4 372 /* Configure the OPM Mode */
mbed_official 181:a4cbdfbbd2f4 373 htim->Instance->CR1 |= OnePulseMode;
mbed_official 181:a4cbdfbbd2f4 374
mbed_official 181:a4cbdfbbd2f4 375 /* Initialize the TIM state*/
mbed_official 181:a4cbdfbbd2f4 376 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 377
mbed_official 181:a4cbdfbbd2f4 378 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 379 }
mbed_official 181:a4cbdfbbd2f4 380
mbed_official 181:a4cbdfbbd2f4 381 /**
mbed_official 181:a4cbdfbbd2f4 382 * @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official 181:a4cbdfbbd2f4 383 * @param htim: TIM Encoder Interface handle
mbed_official 181:a4cbdfbbd2f4 384 * @param sConfig: TIM Encoder Interface configuration structure
mbed_official 181:a4cbdfbbd2f4 385 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 386 */
mbed_official 181:a4cbdfbbd2f4 387 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
mbed_official 181:a4cbdfbbd2f4 388 {
mbed_official 181:a4cbdfbbd2f4 389 uint32_t tmpsmcr = 0;
mbed_official 181:a4cbdfbbd2f4 390 uint32_t tmpccmr1 = 0;
mbed_official 181:a4cbdfbbd2f4 391 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 392
mbed_official 181:a4cbdfbbd2f4 393 /* Check the TIM handle allocation */
mbed_official 181:a4cbdfbbd2f4 394 if(htim == NULL)
mbed_official 181:a4cbdfbbd2f4 395 {
mbed_official 181:a4cbdfbbd2f4 396 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 397 }
mbed_official 181:a4cbdfbbd2f4 398
mbed_official 181:a4cbdfbbd2f4 399 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 400 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 401 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official 181:a4cbdfbbd2f4 402 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official 181:a4cbdfbbd2f4 403 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official 181:a4cbdfbbd2f4 404 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official 181:a4cbdfbbd2f4 405 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official 181:a4cbdfbbd2f4 406 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official 181:a4cbdfbbd2f4 407 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official 181:a4cbdfbbd2f4 408 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official 181:a4cbdfbbd2f4 409 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official 181:a4cbdfbbd2f4 410
mbed_official 181:a4cbdfbbd2f4 411 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 181:a4cbdfbbd2f4 412 {
mbed_official 181:a4cbdfbbd2f4 413 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 414 HAL_TIM_Encoder_MspInit(htim);
mbed_official 181:a4cbdfbbd2f4 415 }
mbed_official 181:a4cbdfbbd2f4 416
mbed_official 181:a4cbdfbbd2f4 417 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 418 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 419
mbed_official 181:a4cbdfbbd2f4 420 /* Reset the SMS bits */
mbed_official 181:a4cbdfbbd2f4 421 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 181:a4cbdfbbd2f4 422
mbed_official 181:a4cbdfbbd2f4 423 /* Configure the Time base in the Encoder Mode */
mbed_official 181:a4cbdfbbd2f4 424 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 181:a4cbdfbbd2f4 425
mbed_official 181:a4cbdfbbd2f4 426 /* Get the TIMx SMCR register value */
mbed_official 181:a4cbdfbbd2f4 427 tmpsmcr = htim->Instance->SMCR;
mbed_official 181:a4cbdfbbd2f4 428
mbed_official 181:a4cbdfbbd2f4 429 /* Get the TIMx CCMR1 register value */
mbed_official 181:a4cbdfbbd2f4 430 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 181:a4cbdfbbd2f4 431
mbed_official 181:a4cbdfbbd2f4 432 /* Get the TIMx CCER register value */
mbed_official 181:a4cbdfbbd2f4 433 tmpccer = htim->Instance->CCER;
mbed_official 181:a4cbdfbbd2f4 434
mbed_official 181:a4cbdfbbd2f4 435 /* Set the encoder Mode */
mbed_official 181:a4cbdfbbd2f4 436 tmpsmcr |= sConfig->EncoderMode;
mbed_official 181:a4cbdfbbd2f4 437
mbed_official 181:a4cbdfbbd2f4 438 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official 181:a4cbdfbbd2f4 439 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
mbed_official 181:a4cbdfbbd2f4 440 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
mbed_official 181:a4cbdfbbd2f4 441
mbed_official 181:a4cbdfbbd2f4 442 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official 181:a4cbdfbbd2f4 443 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
mbed_official 181:a4cbdfbbd2f4 444 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
mbed_official 181:a4cbdfbbd2f4 445 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
mbed_official 181:a4cbdfbbd2f4 446 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
mbed_official 181:a4cbdfbbd2f4 447
mbed_official 181:a4cbdfbbd2f4 448 /* Set the TI1 and the TI2 Polarities */
mbed_official 181:a4cbdfbbd2f4 449 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
mbed_official 181:a4cbdfbbd2f4 450 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
mbed_official 181:a4cbdfbbd2f4 451 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
mbed_official 181:a4cbdfbbd2f4 452
mbed_official 181:a4cbdfbbd2f4 453 /* Write to TIMx SMCR */
mbed_official 181:a4cbdfbbd2f4 454 htim->Instance->SMCR = tmpsmcr;
mbed_official 181:a4cbdfbbd2f4 455
mbed_official 181:a4cbdfbbd2f4 456 /* Write to TIMx CCMR1 */
mbed_official 181:a4cbdfbbd2f4 457 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 181:a4cbdfbbd2f4 458
mbed_official 181:a4cbdfbbd2f4 459 /* Write to TIMx CCER */
mbed_official 181:a4cbdfbbd2f4 460 htim->Instance->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 461
mbed_official 181:a4cbdfbbd2f4 462 /* Initialize the TIM state*/
mbed_official 181:a4cbdfbbd2f4 463 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 464
mbed_official 181:a4cbdfbbd2f4 465 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 466 }
mbed_official 181:a4cbdfbbd2f4 467
mbed_official 181:a4cbdfbbd2f4 468 /**
mbed_official 181:a4cbdfbbd2f4 469 * @brief DeInitializes the TIM Base peripheral
mbed_official 181:a4cbdfbbd2f4 470 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 471 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 472 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 473 */
mbed_official 181:a4cbdfbbd2f4 474 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 475 {
mbed_official 181:a4cbdfbbd2f4 476 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 477 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 478
mbed_official 181:a4cbdfbbd2f4 479 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 480
mbed_official 181:a4cbdfbbd2f4 481 /* Disable the TIM Peripheral Clock */
mbed_official 181:a4cbdfbbd2f4 482 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 483
mbed_official 181:a4cbdfbbd2f4 484 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 181:a4cbdfbbd2f4 485 HAL_TIM_Base_MspDeInit(htim);
mbed_official 181:a4cbdfbbd2f4 486
mbed_official 181:a4cbdfbbd2f4 487 /* Change TIM state */
mbed_official 181:a4cbdfbbd2f4 488 htim->State = HAL_TIM_STATE_RESET;
mbed_official 181:a4cbdfbbd2f4 489
mbed_official 181:a4cbdfbbd2f4 490 /* Release Lock */
mbed_official 181:a4cbdfbbd2f4 491 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 492
mbed_official 181:a4cbdfbbd2f4 493 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 494 }
mbed_official 181:a4cbdfbbd2f4 495
mbed_official 181:a4cbdfbbd2f4 496 /**
mbed_official 181:a4cbdfbbd2f4 497 * @brief DeInitializes the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 498 * @param htim: TIM Output Compare handle
mbed_official 181:a4cbdfbbd2f4 499 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 500 */
mbed_official 181:a4cbdfbbd2f4 501 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 502 {
mbed_official 181:a4cbdfbbd2f4 503 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 504 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 505
mbed_official 181:a4cbdfbbd2f4 506 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 507
mbed_official 181:a4cbdfbbd2f4 508 /* Disable the TIM Peripheral Clock */
mbed_official 181:a4cbdfbbd2f4 509 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 510
mbed_official 181:a4cbdfbbd2f4 511 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 512 HAL_TIM_OC_MspDeInit(htim);
mbed_official 181:a4cbdfbbd2f4 513
mbed_official 181:a4cbdfbbd2f4 514 /* Change TIM state */
mbed_official 181:a4cbdfbbd2f4 515 htim->State = HAL_TIM_STATE_RESET;
mbed_official 181:a4cbdfbbd2f4 516
mbed_official 181:a4cbdfbbd2f4 517 /* Release Lock */
mbed_official 181:a4cbdfbbd2f4 518 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 519
mbed_official 181:a4cbdfbbd2f4 520 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 521 }
mbed_official 181:a4cbdfbbd2f4 522
mbed_official 181:a4cbdfbbd2f4 523 /**
mbed_official 181:a4cbdfbbd2f4 524 * @brief DeInitializes the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 525 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 526 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 527 */
mbed_official 181:a4cbdfbbd2f4 528 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 529 {
mbed_official 181:a4cbdfbbd2f4 530 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 531 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 532
mbed_official 181:a4cbdfbbd2f4 533 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 534
mbed_official 181:a4cbdfbbd2f4 535 /* Disable the TIM Peripheral Clock */
mbed_official 181:a4cbdfbbd2f4 536 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 537
mbed_official 181:a4cbdfbbd2f4 538 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 539 HAL_TIM_PWM_MspDeInit(htim);
mbed_official 181:a4cbdfbbd2f4 540
mbed_official 181:a4cbdfbbd2f4 541 /* Change TIM state */
mbed_official 181:a4cbdfbbd2f4 542 htim->State = HAL_TIM_STATE_RESET;
mbed_official 181:a4cbdfbbd2f4 543
mbed_official 181:a4cbdfbbd2f4 544 /* Release Lock */
mbed_official 181:a4cbdfbbd2f4 545 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 546
mbed_official 181:a4cbdfbbd2f4 547 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 548 }
mbed_official 181:a4cbdfbbd2f4 549
mbed_official 181:a4cbdfbbd2f4 550 /**
mbed_official 181:a4cbdfbbd2f4 551 * @brief DeInitializes the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 552 * @param htim: TIM Input Capture handle
mbed_official 181:a4cbdfbbd2f4 553 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 554 */
mbed_official 181:a4cbdfbbd2f4 555 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 556 {
mbed_official 181:a4cbdfbbd2f4 557 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 558 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 559
mbed_official 181:a4cbdfbbd2f4 560 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 561
mbed_official 181:a4cbdfbbd2f4 562 /* Disable the TIM Peripheral Clock */
mbed_official 181:a4cbdfbbd2f4 563 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 564
mbed_official 181:a4cbdfbbd2f4 565 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 181:a4cbdfbbd2f4 566 HAL_TIM_IC_MspDeInit(htim);
mbed_official 181:a4cbdfbbd2f4 567
mbed_official 181:a4cbdfbbd2f4 568 /* Change TIM state */
mbed_official 181:a4cbdfbbd2f4 569 htim->State = HAL_TIM_STATE_RESET;
mbed_official 181:a4cbdfbbd2f4 570
mbed_official 181:a4cbdfbbd2f4 571 /* Release Lock */
mbed_official 181:a4cbdfbbd2f4 572 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 573
mbed_official 181:a4cbdfbbd2f4 574 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 575 }
mbed_official 181:a4cbdfbbd2f4 576
mbed_official 181:a4cbdfbbd2f4 577 /**
mbed_official 181:a4cbdfbbd2f4 578 * @brief DeInitializes the TIM One Pulse
mbed_official 181:a4cbdfbbd2f4 579 * @param htim: TIM One Pulse handle
mbed_official 181:a4cbdfbbd2f4 580 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 581 */
mbed_official 181:a4cbdfbbd2f4 582 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 583 {
mbed_official 181:a4cbdfbbd2f4 584 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 585 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 586
mbed_official 181:a4cbdfbbd2f4 587 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 588
mbed_official 181:a4cbdfbbd2f4 589 /* Disable the TIM Peripheral Clock */
mbed_official 181:a4cbdfbbd2f4 590 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 591
mbed_official 181:a4cbdfbbd2f4 592 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 181:a4cbdfbbd2f4 593 HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official 181:a4cbdfbbd2f4 594
mbed_official 181:a4cbdfbbd2f4 595 /* Change TIM state */
mbed_official 181:a4cbdfbbd2f4 596 htim->State = HAL_TIM_STATE_RESET;
mbed_official 181:a4cbdfbbd2f4 597
mbed_official 181:a4cbdfbbd2f4 598 /* Release Lock */
mbed_official 181:a4cbdfbbd2f4 599 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 600
mbed_official 181:a4cbdfbbd2f4 601 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 602 }
mbed_official 181:a4cbdfbbd2f4 603
mbed_official 181:a4cbdfbbd2f4 604 /**
mbed_official 181:a4cbdfbbd2f4 605 * @brief DeInitializes the TIM Encoder interface
mbed_official 181:a4cbdfbbd2f4 606 * @param htim: TIM Encoder handle
mbed_official 181:a4cbdfbbd2f4 607 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 608 */
mbed_official 181:a4cbdfbbd2f4 609 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 610 {
mbed_official 181:a4cbdfbbd2f4 611 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 612 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 613
mbed_official 181:a4cbdfbbd2f4 614 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 615
mbed_official 181:a4cbdfbbd2f4 616 /* Disable the TIM Peripheral Clock */
mbed_official 181:a4cbdfbbd2f4 617 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 618
mbed_official 181:a4cbdfbbd2f4 619 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 181:a4cbdfbbd2f4 620 HAL_TIM_Encoder_MspDeInit(htim);
mbed_official 181:a4cbdfbbd2f4 621
mbed_official 181:a4cbdfbbd2f4 622 /* Change TIM state */
mbed_official 181:a4cbdfbbd2f4 623 htim->State = HAL_TIM_STATE_RESET;
mbed_official 181:a4cbdfbbd2f4 624
mbed_official 181:a4cbdfbbd2f4 625 /* Release Lock */
mbed_official 181:a4cbdfbbd2f4 626 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 627
mbed_official 181:a4cbdfbbd2f4 628 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 629 }
mbed_official 181:a4cbdfbbd2f4 630
mbed_official 181:a4cbdfbbd2f4 631 /**
mbed_official 181:a4cbdfbbd2f4 632 * @brief Initializes the TIM Base MSP.
mbed_official 181:a4cbdfbbd2f4 633 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 634 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 635 * @retval None
mbed_official 181:a4cbdfbbd2f4 636 */
mbed_official 181:a4cbdfbbd2f4 637 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 638 {
mbed_official 181:a4cbdfbbd2f4 639 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 640 the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 641 */
mbed_official 181:a4cbdfbbd2f4 642 }
mbed_official 181:a4cbdfbbd2f4 643
mbed_official 181:a4cbdfbbd2f4 644 /**
mbed_official 181:a4cbdfbbd2f4 645 * @brief Initializes the TIM Output Compare MSP.
mbed_official 181:a4cbdfbbd2f4 646 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 647 * @retval None
mbed_official 181:a4cbdfbbd2f4 648 */
mbed_official 181:a4cbdfbbd2f4 649 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 650 {
mbed_official 181:a4cbdfbbd2f4 651 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 652 the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 653 */
mbed_official 181:a4cbdfbbd2f4 654 }
mbed_official 181:a4cbdfbbd2f4 655
mbed_official 181:a4cbdfbbd2f4 656 /**
mbed_official 181:a4cbdfbbd2f4 657 * @brief Initializes the TIM PWM MSP.
mbed_official 181:a4cbdfbbd2f4 658 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 659 * @retval None
mbed_official 181:a4cbdfbbd2f4 660 */
mbed_official 181:a4cbdfbbd2f4 661 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 662 {
mbed_official 181:a4cbdfbbd2f4 663 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 664 the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 665 */
mbed_official 181:a4cbdfbbd2f4 666 }
mbed_official 181:a4cbdfbbd2f4 667
mbed_official 181:a4cbdfbbd2f4 668 /**
mbed_official 181:a4cbdfbbd2f4 669 * @brief Initializes the TIM INput Capture MSP.
mbed_official 181:a4cbdfbbd2f4 670 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 671 * @retval None
mbed_official 181:a4cbdfbbd2f4 672 */
mbed_official 181:a4cbdfbbd2f4 673 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 674 {
mbed_official 181:a4cbdfbbd2f4 675 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 676 the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 677 */
mbed_official 181:a4cbdfbbd2f4 678 }
mbed_official 181:a4cbdfbbd2f4 679
mbed_official 181:a4cbdfbbd2f4 680 /**
mbed_official 181:a4cbdfbbd2f4 681 * @brief Initializes the TIM One Pulse MSP.
mbed_official 181:a4cbdfbbd2f4 682 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 683 * @retval None
mbed_official 181:a4cbdfbbd2f4 684 */
mbed_official 181:a4cbdfbbd2f4 685 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 686 {
mbed_official 181:a4cbdfbbd2f4 687 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 688 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 689 */
mbed_official 181:a4cbdfbbd2f4 690 }
mbed_official 181:a4cbdfbbd2f4 691
mbed_official 181:a4cbdfbbd2f4 692 /**
mbed_official 181:a4cbdfbbd2f4 693 * @brief Initializes the TIM Encoder Interface MSP.
mbed_official 181:a4cbdfbbd2f4 694 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 695 * @retval None
mbed_official 181:a4cbdfbbd2f4 696 */
mbed_official 181:a4cbdfbbd2f4 697 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 698 {
mbed_official 181:a4cbdfbbd2f4 699 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 700 the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 701 */
mbed_official 181:a4cbdfbbd2f4 702 }
mbed_official 181:a4cbdfbbd2f4 703
mbed_official 181:a4cbdfbbd2f4 704 /**
mbed_official 181:a4cbdfbbd2f4 705 * @brief DeInitializes TIM Base MSP.
mbed_official 181:a4cbdfbbd2f4 706 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 707 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 708 * @retval None
mbed_official 181:a4cbdfbbd2f4 709 */
mbed_official 181:a4cbdfbbd2f4 710 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 711 {
mbed_official 181:a4cbdfbbd2f4 712 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 713 the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 714 */
mbed_official 181:a4cbdfbbd2f4 715 }
mbed_official 181:a4cbdfbbd2f4 716
mbed_official 181:a4cbdfbbd2f4 717 /**
mbed_official 181:a4cbdfbbd2f4 718 * @brief DeInitializes TIM Output Compare MSP.
mbed_official 181:a4cbdfbbd2f4 719 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 720 * @retval None
mbed_official 181:a4cbdfbbd2f4 721 */
mbed_official 181:a4cbdfbbd2f4 722 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 723 {
mbed_official 181:a4cbdfbbd2f4 724 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 725 the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 726 */
mbed_official 181:a4cbdfbbd2f4 727 }
mbed_official 181:a4cbdfbbd2f4 728
mbed_official 181:a4cbdfbbd2f4 729 /**
mbed_official 181:a4cbdfbbd2f4 730 * @brief DeInitializes TIM PWM MSP.
mbed_official 181:a4cbdfbbd2f4 731 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 732 * @retval None
mbed_official 181:a4cbdfbbd2f4 733 */
mbed_official 181:a4cbdfbbd2f4 734 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 735 {
mbed_official 181:a4cbdfbbd2f4 736 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 737 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 738 */
mbed_official 181:a4cbdfbbd2f4 739 }
mbed_official 181:a4cbdfbbd2f4 740
mbed_official 181:a4cbdfbbd2f4 741 /**
mbed_official 181:a4cbdfbbd2f4 742 * @brief DeInitializes TIM Input Capture MSP.
mbed_official 181:a4cbdfbbd2f4 743 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 744 * @retval None
mbed_official 181:a4cbdfbbd2f4 745 */
mbed_official 181:a4cbdfbbd2f4 746 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 747 {
mbed_official 181:a4cbdfbbd2f4 748 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 749 the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 750 */
mbed_official 181:a4cbdfbbd2f4 751 }
mbed_official 181:a4cbdfbbd2f4 752
mbed_official 181:a4cbdfbbd2f4 753 /**
mbed_official 181:a4cbdfbbd2f4 754 * @brief DeInitializes TIM One Pulse MSP.
mbed_official 181:a4cbdfbbd2f4 755 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 756 * @retval None
mbed_official 181:a4cbdfbbd2f4 757 */
mbed_official 181:a4cbdfbbd2f4 758 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 759 {
mbed_official 181:a4cbdfbbd2f4 760 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 761 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 762 */
mbed_official 181:a4cbdfbbd2f4 763 }
mbed_official 181:a4cbdfbbd2f4 764
mbed_official 181:a4cbdfbbd2f4 765 /**
mbed_official 181:a4cbdfbbd2f4 766 * @brief DeInitializes TIM Encoder Interface MSP.
mbed_official 181:a4cbdfbbd2f4 767 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 768 * @retval None
mbed_official 181:a4cbdfbbd2f4 769 */
mbed_official 181:a4cbdfbbd2f4 770 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 771 {
mbed_official 181:a4cbdfbbd2f4 772 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 773 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 774 */
mbed_official 181:a4cbdfbbd2f4 775 }
mbed_official 181:a4cbdfbbd2f4 776
mbed_official 181:a4cbdfbbd2f4 777 /**
mbed_official 181:a4cbdfbbd2f4 778 * @}
mbed_official 181:a4cbdfbbd2f4 779 */
mbed_official 181:a4cbdfbbd2f4 780 /** @defgroup TIM_Group2 I/O operation functions
mbed_official 181:a4cbdfbbd2f4 781 * @brief I/O operation functions
mbed_official 181:a4cbdfbbd2f4 782 *
mbed_official 181:a4cbdfbbd2f4 783 @verbatim
mbed_official 181:a4cbdfbbd2f4 784 ===============================================================================
mbed_official 181:a4cbdfbbd2f4 785 ##### IO operation functions #####
mbed_official 181:a4cbdfbbd2f4 786 ===============================================================================
mbed_official 181:a4cbdfbbd2f4 787 [..] This section provides functions allowing to:
mbed_official 181:a4cbdfbbd2f4 788 (+) Start the Time Base.
mbed_official 181:a4cbdfbbd2f4 789 (+) Stop the Time Base.
mbed_official 181:a4cbdfbbd2f4 790 (+) Start the Time Base and enable interrupt.
mbed_official 181:a4cbdfbbd2f4 791 (+) Stop the Time Base and disable interrupt.
mbed_official 181:a4cbdfbbd2f4 792 (+) Start the Time Base and enable DMA transfer.
mbed_official 181:a4cbdfbbd2f4 793 (+) Stop the Time Base and disable DMA transfer.
mbed_official 181:a4cbdfbbd2f4 794 (+) Start the Output Compare/PWM.
mbed_official 181:a4cbdfbbd2f4 795 (+) Stop the Output Compare/PWM.
mbed_official 181:a4cbdfbbd2f4 796 (+) Start the Output Compare/PWM and enable interrupts.
mbed_official 181:a4cbdfbbd2f4 797 (+) Stop the Output Compare/PWM and disable interrupts.
mbed_official 181:a4cbdfbbd2f4 798 (+) Start the Output Compare/PWM and enable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 799 (+) Stop the Output Compare/PWM and disable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 800 (+) Start the Input Capture measurement.
mbed_official 181:a4cbdfbbd2f4 801 (+) Stop the Input Capture.
mbed_official 181:a4cbdfbbd2f4 802 (+) Start the Input Capture and enable interrupts.
mbed_official 181:a4cbdfbbd2f4 803 (+) Stop the Input Capture and disable interrupts.
mbed_official 181:a4cbdfbbd2f4 804 (+) Start the Input Capture and enable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 805 (+) Stop the Input Capture and disable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 806 (+) Start the One Pulse generation.
mbed_official 181:a4cbdfbbd2f4 807 (+) Stop the One Pulse.
mbed_official 181:a4cbdfbbd2f4 808 (+) Start the One Pulse and enable interrupts.
mbed_official 181:a4cbdfbbd2f4 809 (+) Stop the One Pulse and disable interrupts.
mbed_official 181:a4cbdfbbd2f4 810 (+) Start the Encoder Interface.
mbed_official 181:a4cbdfbbd2f4 811 (+) Stop the Encoder Interface.
mbed_official 181:a4cbdfbbd2f4 812 (+) Start the Encoder Interface and enable interrupts.
mbed_official 181:a4cbdfbbd2f4 813 (+) Stop the Encoder Interface and disable interrupts.
mbed_official 181:a4cbdfbbd2f4 814 (+) Start the Encoder Interface and enable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 815 (+) Stop the Encoder Interface and disable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 816 (+) Start the Hall Sensor Interface.
mbed_official 181:a4cbdfbbd2f4 817 (+) Stop the Hall Sensor Interface.
mbed_official 181:a4cbdfbbd2f4 818 (+) Start the Hall Sensor Interface and enable interrupts.
mbed_official 181:a4cbdfbbd2f4 819 (+) Stop the Hall Sensor Interface and disable interrupts.
mbed_official 181:a4cbdfbbd2f4 820 (+) Start the Hall Sensor Interface and enable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 821 (+) Stop the Hall Sensor Interface and disable DMA transfers.
mbed_official 181:a4cbdfbbd2f4 822 (+) Handle TIM interrupt request.
mbed_official 181:a4cbdfbbd2f4 823
mbed_official 181:a4cbdfbbd2f4 824 @endverbatim
mbed_official 181:a4cbdfbbd2f4 825 * @{
mbed_official 181:a4cbdfbbd2f4 826 */
mbed_official 181:a4cbdfbbd2f4 827 /**
mbed_official 181:a4cbdfbbd2f4 828 * @brief Starts the TIM Base generation.
mbed_official 181:a4cbdfbbd2f4 829 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 830 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 831 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 832 */
mbed_official 181:a4cbdfbbd2f4 833 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 834 {
mbed_official 181:a4cbdfbbd2f4 835 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 836 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 837
mbed_official 181:a4cbdfbbd2f4 838 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 839 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 840
mbed_official 181:a4cbdfbbd2f4 841 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 842 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 843
mbed_official 181:a4cbdfbbd2f4 844 /* Change the TIM state*/
mbed_official 181:a4cbdfbbd2f4 845 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 846
mbed_official 181:a4cbdfbbd2f4 847 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 848 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 849 }
mbed_official 181:a4cbdfbbd2f4 850
mbed_official 181:a4cbdfbbd2f4 851 /**
mbed_official 181:a4cbdfbbd2f4 852 * @brief Stops the TIM Base generation.
mbed_official 181:a4cbdfbbd2f4 853 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 854 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 855 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 856 */
mbed_official 181:a4cbdfbbd2f4 857 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 858 {
mbed_official 181:a4cbdfbbd2f4 859 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 860 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 861
mbed_official 181:a4cbdfbbd2f4 862 /* Set the TIM state */
mbed_official 181:a4cbdfbbd2f4 863 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 864
mbed_official 181:a4cbdfbbd2f4 865 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 866 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 867
mbed_official 181:a4cbdfbbd2f4 868 /* Change the TIM state*/
mbed_official 181:a4cbdfbbd2f4 869 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 870
mbed_official 181:a4cbdfbbd2f4 871 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 872 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 873 }
mbed_official 181:a4cbdfbbd2f4 874
mbed_official 181:a4cbdfbbd2f4 875 /**
mbed_official 181:a4cbdfbbd2f4 876 * @brief Starts the TIM Base generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 877 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 878 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 879 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 880 */
mbed_official 181:a4cbdfbbd2f4 881 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 882 {
mbed_official 181:a4cbdfbbd2f4 883 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 884 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 885
mbed_official 181:a4cbdfbbd2f4 886 /* Enable the TIM Update interrupt */
mbed_official 181:a4cbdfbbd2f4 887 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 181:a4cbdfbbd2f4 888
mbed_official 181:a4cbdfbbd2f4 889 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 890 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 891
mbed_official 181:a4cbdfbbd2f4 892 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 893 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 894 }
mbed_official 181:a4cbdfbbd2f4 895
mbed_official 181:a4cbdfbbd2f4 896 /**
mbed_official 181:a4cbdfbbd2f4 897 * @brief Stops the TIM Base generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 898 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 899 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 900 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 901 */
mbed_official 181:a4cbdfbbd2f4 902 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 903 {
mbed_official 181:a4cbdfbbd2f4 904 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 905 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 906 /* Disable the TIM Update interrupt */
mbed_official 181:a4cbdfbbd2f4 907 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 181:a4cbdfbbd2f4 908
mbed_official 181:a4cbdfbbd2f4 909 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 910 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 911
mbed_official 181:a4cbdfbbd2f4 912 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 913 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 914 }
mbed_official 181:a4cbdfbbd2f4 915
mbed_official 181:a4cbdfbbd2f4 916 /**
mbed_official 181:a4cbdfbbd2f4 917 * @brief Starts the TIM Base generation in DMA mode.
mbed_official 181:a4cbdfbbd2f4 918 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 919 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 920 * @param pData: The source Buffer address.
mbed_official 181:a4cbdfbbd2f4 921 * @param Length: The length of data to be transferred from memory to peripheral.
mbed_official 181:a4cbdfbbd2f4 922 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 923 */
mbed_official 181:a4cbdfbbd2f4 924 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
mbed_official 181:a4cbdfbbd2f4 925 {
mbed_official 181:a4cbdfbbd2f4 926 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 927 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 928
mbed_official 181:a4cbdfbbd2f4 929 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 930 {
mbed_official 181:a4cbdfbbd2f4 931 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 932 }
mbed_official 181:a4cbdfbbd2f4 933 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 934 {
mbed_official 181:a4cbdfbbd2f4 935 if((pData == 0 ) && (Length > 0))
mbed_official 181:a4cbdfbbd2f4 936 {
mbed_official 181:a4cbdfbbd2f4 937 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 938 }
mbed_official 181:a4cbdfbbd2f4 939 else
mbed_official 181:a4cbdfbbd2f4 940 {
mbed_official 181:a4cbdfbbd2f4 941 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 942 }
mbed_official 181:a4cbdfbbd2f4 943 }
mbed_official 181:a4cbdfbbd2f4 944 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 945 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 181:a4cbdfbbd2f4 946
mbed_official 181:a4cbdfbbd2f4 947 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 948 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 949
mbed_official 181:a4cbdfbbd2f4 950 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 951 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official 181:a4cbdfbbd2f4 952
mbed_official 181:a4cbdfbbd2f4 953 /* Enable the TIM Update DMA request */
mbed_official 181:a4cbdfbbd2f4 954 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 181:a4cbdfbbd2f4 955
mbed_official 181:a4cbdfbbd2f4 956 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 957 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 958
mbed_official 181:a4cbdfbbd2f4 959 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 960 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 961 }
mbed_official 181:a4cbdfbbd2f4 962
mbed_official 181:a4cbdfbbd2f4 963 /**
mbed_official 181:a4cbdfbbd2f4 964 * @brief Stops the TIM Base generation in DMA mode.
mbed_official 181:a4cbdfbbd2f4 965 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 966 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 967 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 968 */
mbed_official 181:a4cbdfbbd2f4 969 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 970 {
mbed_official 181:a4cbdfbbd2f4 971 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 972 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 973
mbed_official 181:a4cbdfbbd2f4 974 /* Disable the TIM Update DMA request */
mbed_official 181:a4cbdfbbd2f4 975 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 181:a4cbdfbbd2f4 976
mbed_official 181:a4cbdfbbd2f4 977 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 978 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 979
mbed_official 181:a4cbdfbbd2f4 980 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 981 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 982
mbed_official 181:a4cbdfbbd2f4 983 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 984 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 985 }
mbed_official 181:a4cbdfbbd2f4 986
mbed_official 181:a4cbdfbbd2f4 987 /**
mbed_official 181:a4cbdfbbd2f4 988 * @brief Starts the TIM Output Compare signal generation.
mbed_official 181:a4cbdfbbd2f4 989 * @param htim : pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 990 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 991 * @param Channel: TIM Channel to be enabled.
mbed_official 181:a4cbdfbbd2f4 992 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 993 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 994 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 995 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 996 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 997 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 998 */
mbed_official 181:a4cbdfbbd2f4 999 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1000 {
mbed_official 181:a4cbdfbbd2f4 1001 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1002 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1003
mbed_official 181:a4cbdfbbd2f4 1004 /* Enable the Output compare channel */
mbed_official 181:a4cbdfbbd2f4 1005 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1006
mbed_official 181:a4cbdfbbd2f4 1007 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1008 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1009
mbed_official 181:a4cbdfbbd2f4 1010 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1011 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1012 }
mbed_official 181:a4cbdfbbd2f4 1013
mbed_official 181:a4cbdfbbd2f4 1014 /**
mbed_official 181:a4cbdfbbd2f4 1015 * @brief Stops the TIM Output Compare signal generation.
mbed_official 181:a4cbdfbbd2f4 1016 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1017 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1018 * @param Channel: TIM Channel to be disabled.
mbed_official 181:a4cbdfbbd2f4 1019 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1020 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1021 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1022 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1023 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1024 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1025 */
mbed_official 181:a4cbdfbbd2f4 1026 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1027 {
mbed_official 181:a4cbdfbbd2f4 1028 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1029 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1030
mbed_official 181:a4cbdfbbd2f4 1031 /* Disable the Output compare channel */
mbed_official 181:a4cbdfbbd2f4 1032 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1033
mbed_official 181:a4cbdfbbd2f4 1034 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1035 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1036
mbed_official 181:a4cbdfbbd2f4 1037 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1038 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1039 }
mbed_official 181:a4cbdfbbd2f4 1040
mbed_official 181:a4cbdfbbd2f4 1041 /**
mbed_official 181:a4cbdfbbd2f4 1042 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 1043 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1044 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1045 * @param Channel: TIM Channel to be enabled.
mbed_official 181:a4cbdfbbd2f4 1046 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1049 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1050 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1051 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1052 */
mbed_official 181:a4cbdfbbd2f4 1053 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1054 {
mbed_official 181:a4cbdfbbd2f4 1055 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1056 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1057
mbed_official 181:a4cbdfbbd2f4 1058 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1059 {
mbed_official 181:a4cbdfbbd2f4 1060 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1061 {
mbed_official 181:a4cbdfbbd2f4 1062 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 1063 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 1064 }
mbed_official 181:a4cbdfbbd2f4 1065 break;
mbed_official 181:a4cbdfbbd2f4 1066
mbed_official 181:a4cbdfbbd2f4 1067 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1068 {
mbed_official 181:a4cbdfbbd2f4 1069 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 1070 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 1071 }
mbed_official 181:a4cbdfbbd2f4 1072 break;
mbed_official 181:a4cbdfbbd2f4 1073
mbed_official 181:a4cbdfbbd2f4 1074 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1075 {
mbed_official 181:a4cbdfbbd2f4 1076 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 181:a4cbdfbbd2f4 1077 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 1078 }
mbed_official 181:a4cbdfbbd2f4 1079 break;
mbed_official 181:a4cbdfbbd2f4 1080
mbed_official 181:a4cbdfbbd2f4 1081 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1082 {
mbed_official 181:a4cbdfbbd2f4 1083 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1084 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 1085 }
mbed_official 181:a4cbdfbbd2f4 1086 break;
mbed_official 181:a4cbdfbbd2f4 1087
mbed_official 181:a4cbdfbbd2f4 1088 default:
mbed_official 181:a4cbdfbbd2f4 1089 break;
mbed_official 181:a4cbdfbbd2f4 1090 }
mbed_official 181:a4cbdfbbd2f4 1091
mbed_official 181:a4cbdfbbd2f4 1092 /* Enable the Output compare channel */
mbed_official 181:a4cbdfbbd2f4 1093 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1094
mbed_official 181:a4cbdfbbd2f4 1095 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1096 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1097
mbed_official 181:a4cbdfbbd2f4 1098 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1099 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1100 }
mbed_official 181:a4cbdfbbd2f4 1101
mbed_official 181:a4cbdfbbd2f4 1102 /**
mbed_official 181:a4cbdfbbd2f4 1103 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 1104 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1105 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1106 * @param Channel: TIM Channel to be disabled.
mbed_official 181:a4cbdfbbd2f4 1107 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1108 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1109 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1110 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1111 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1112 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1113 */
mbed_official 181:a4cbdfbbd2f4 1114 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1115 {
mbed_official 181:a4cbdfbbd2f4 1116 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1117 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1118
mbed_official 181:a4cbdfbbd2f4 1119 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1120 {
mbed_official 181:a4cbdfbbd2f4 1121 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1122 {
mbed_official 181:a4cbdfbbd2f4 1123 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 1124 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 1125 }
mbed_official 181:a4cbdfbbd2f4 1126 break;
mbed_official 181:a4cbdfbbd2f4 1127
mbed_official 181:a4cbdfbbd2f4 1128 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1129 {
mbed_official 181:a4cbdfbbd2f4 1130 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 1131 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 1132 }
mbed_official 181:a4cbdfbbd2f4 1133 break;
mbed_official 181:a4cbdfbbd2f4 1134
mbed_official 181:a4cbdfbbd2f4 1135 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1136 {
mbed_official 181:a4cbdfbbd2f4 1137 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 181:a4cbdfbbd2f4 1138 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 1139 }
mbed_official 181:a4cbdfbbd2f4 1140 break;
mbed_official 181:a4cbdfbbd2f4 1141
mbed_official 181:a4cbdfbbd2f4 1142 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1143 {
mbed_official 181:a4cbdfbbd2f4 1144 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1145 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 1146 }
mbed_official 181:a4cbdfbbd2f4 1147 break;
mbed_official 181:a4cbdfbbd2f4 1148
mbed_official 181:a4cbdfbbd2f4 1149 default:
mbed_official 181:a4cbdfbbd2f4 1150 break;
mbed_official 181:a4cbdfbbd2f4 1151 }
mbed_official 181:a4cbdfbbd2f4 1152
mbed_official 181:a4cbdfbbd2f4 1153 /* Disable the Output compare channel */
mbed_official 181:a4cbdfbbd2f4 1154 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1155
mbed_official 181:a4cbdfbbd2f4 1156 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1157 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1158
mbed_official 181:a4cbdfbbd2f4 1159 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1160 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1161 }
mbed_official 181:a4cbdfbbd2f4 1162
mbed_official 181:a4cbdfbbd2f4 1163 /**
mbed_official 181:a4cbdfbbd2f4 1164 * @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official 181:a4cbdfbbd2f4 1165 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1166 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1167 * @param Channel: TIM Channel to be enabled.
mbed_official 181:a4cbdfbbd2f4 1168 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1169 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1170 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1171 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1172 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1173 * @param pData: The source Buffer address.
mbed_official 181:a4cbdfbbd2f4 1174 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 181:a4cbdfbbd2f4 1175 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1176 */
mbed_official 181:a4cbdfbbd2f4 1177 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 181:a4cbdfbbd2f4 1178 {
mbed_official 181:a4cbdfbbd2f4 1179 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1180 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1181
mbed_official 181:a4cbdfbbd2f4 1182 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 1183 {
mbed_official 181:a4cbdfbbd2f4 1184 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 1185 }
mbed_official 181:a4cbdfbbd2f4 1186 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 1187 {
mbed_official 181:a4cbdfbbd2f4 1188 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 181:a4cbdfbbd2f4 1189 {
mbed_official 181:a4cbdfbbd2f4 1190 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 1191 }
mbed_official 181:a4cbdfbbd2f4 1192 else
mbed_official 181:a4cbdfbbd2f4 1193 {
mbed_official 181:a4cbdfbbd2f4 1194 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 1195 }
mbed_official 181:a4cbdfbbd2f4 1196 }
mbed_official 181:a4cbdfbbd2f4 1197 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1198 {
mbed_official 181:a4cbdfbbd2f4 1199 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1200 {
mbed_official 181:a4cbdfbbd2f4 1201 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1202 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1203
mbed_official 181:a4cbdfbbd2f4 1204 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1205 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1206
mbed_official 181:a4cbdfbbd2f4 1207 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1208 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 181:a4cbdfbbd2f4 1209
mbed_official 181:a4cbdfbbd2f4 1210 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 181:a4cbdfbbd2f4 1211 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 1212 }
mbed_official 181:a4cbdfbbd2f4 1213 break;
mbed_official 181:a4cbdfbbd2f4 1214
mbed_official 181:a4cbdfbbd2f4 1215 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1216 {
mbed_official 181:a4cbdfbbd2f4 1217 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1218 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1219
mbed_official 181:a4cbdfbbd2f4 1220 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1221 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1222
mbed_official 181:a4cbdfbbd2f4 1223 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1224 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 181:a4cbdfbbd2f4 1225
mbed_official 181:a4cbdfbbd2f4 1226 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 181:a4cbdfbbd2f4 1227 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 1228 }
mbed_official 181:a4cbdfbbd2f4 1229 break;
mbed_official 181:a4cbdfbbd2f4 1230
mbed_official 181:a4cbdfbbd2f4 1231 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1232 {
mbed_official 181:a4cbdfbbd2f4 1233 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1234 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1235
mbed_official 181:a4cbdfbbd2f4 1236 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1237 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1238
mbed_official 181:a4cbdfbbd2f4 1239 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1240 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 181:a4cbdfbbd2f4 1241
mbed_official 181:a4cbdfbbd2f4 1242 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 181:a4cbdfbbd2f4 1243 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 181:a4cbdfbbd2f4 1244 }
mbed_official 181:a4cbdfbbd2f4 1245 break;
mbed_official 181:a4cbdfbbd2f4 1246
mbed_official 181:a4cbdfbbd2f4 1247 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1248 {
mbed_official 181:a4cbdfbbd2f4 1249 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1250 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1251
mbed_official 181:a4cbdfbbd2f4 1252 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1253 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1254
mbed_official 181:a4cbdfbbd2f4 1255 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1256 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 181:a4cbdfbbd2f4 1257
mbed_official 181:a4cbdfbbd2f4 1258 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 181:a4cbdfbbd2f4 1259 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 181:a4cbdfbbd2f4 1260 }
mbed_official 181:a4cbdfbbd2f4 1261 break;
mbed_official 181:a4cbdfbbd2f4 1262
mbed_official 181:a4cbdfbbd2f4 1263 default:
mbed_official 181:a4cbdfbbd2f4 1264 break;
mbed_official 181:a4cbdfbbd2f4 1265 }
mbed_official 181:a4cbdfbbd2f4 1266
mbed_official 181:a4cbdfbbd2f4 1267 /* Enable the Output compare channel */
mbed_official 181:a4cbdfbbd2f4 1268 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1269
mbed_official 181:a4cbdfbbd2f4 1270 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1271 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1272
mbed_official 181:a4cbdfbbd2f4 1273 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1274 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1275 }
mbed_official 181:a4cbdfbbd2f4 1276
mbed_official 181:a4cbdfbbd2f4 1277 /**
mbed_official 181:a4cbdfbbd2f4 1278 * @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official 181:a4cbdfbbd2f4 1279 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1280 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1281 * @param Channel: TIM Channel to be disabled.
mbed_official 181:a4cbdfbbd2f4 1282 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1283 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1284 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1285 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1286 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1287 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1288 */
mbed_official 181:a4cbdfbbd2f4 1289 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1290 {
mbed_official 181:a4cbdfbbd2f4 1291 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1292 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1293
mbed_official 181:a4cbdfbbd2f4 1294 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1295 {
mbed_official 181:a4cbdfbbd2f4 1296 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1297 {
mbed_official 181:a4cbdfbbd2f4 1298 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 181:a4cbdfbbd2f4 1299 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 1300 }
mbed_official 181:a4cbdfbbd2f4 1301 break;
mbed_official 181:a4cbdfbbd2f4 1302
mbed_official 181:a4cbdfbbd2f4 1303 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1304 {
mbed_official 181:a4cbdfbbd2f4 1305 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 181:a4cbdfbbd2f4 1306 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 1307 }
mbed_official 181:a4cbdfbbd2f4 1308 break;
mbed_official 181:a4cbdfbbd2f4 1309
mbed_official 181:a4cbdfbbd2f4 1310 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1311 {
mbed_official 181:a4cbdfbbd2f4 1312 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 181:a4cbdfbbd2f4 1313 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 181:a4cbdfbbd2f4 1314 }
mbed_official 181:a4cbdfbbd2f4 1315 break;
mbed_official 181:a4cbdfbbd2f4 1316
mbed_official 181:a4cbdfbbd2f4 1317 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1318 {
mbed_official 181:a4cbdfbbd2f4 1319 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1320 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 181:a4cbdfbbd2f4 1321 }
mbed_official 181:a4cbdfbbd2f4 1322 break;
mbed_official 181:a4cbdfbbd2f4 1323
mbed_official 181:a4cbdfbbd2f4 1324 default:
mbed_official 181:a4cbdfbbd2f4 1325 break;
mbed_official 181:a4cbdfbbd2f4 1326 }
mbed_official 181:a4cbdfbbd2f4 1327
mbed_official 181:a4cbdfbbd2f4 1328 /* Disable the Output compare channel */
mbed_official 181:a4cbdfbbd2f4 1329 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1330
mbed_official 181:a4cbdfbbd2f4 1331 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1332 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1333
mbed_official 181:a4cbdfbbd2f4 1334 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 1335 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 1336
mbed_official 181:a4cbdfbbd2f4 1337 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1338 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1339 }
mbed_official 181:a4cbdfbbd2f4 1340
mbed_official 181:a4cbdfbbd2f4 1341 /**
mbed_official 181:a4cbdfbbd2f4 1342 * @brief Starts the PWM signal generation.
mbed_official 181:a4cbdfbbd2f4 1343 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1344 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1345 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 1346 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1347 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1348 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1349 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1350 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1351 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1352 */
mbed_official 181:a4cbdfbbd2f4 1353 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1354 {
mbed_official 181:a4cbdfbbd2f4 1355 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1356 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1357
mbed_official 181:a4cbdfbbd2f4 1358 /* Enable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 1359 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1360
mbed_official 181:a4cbdfbbd2f4 1361 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1362 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1363
mbed_official 181:a4cbdfbbd2f4 1364 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1365 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1366 }
mbed_official 181:a4cbdfbbd2f4 1367
mbed_official 181:a4cbdfbbd2f4 1368 /**
mbed_official 181:a4cbdfbbd2f4 1369 * @brief Stops the PWM signal generation.
mbed_official 181:a4cbdfbbd2f4 1370 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1371 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1372 * @param Channel: TIM Channels to be disabled.
mbed_official 181:a4cbdfbbd2f4 1373 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1374 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1375 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1376 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1377 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1378 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1379 */
mbed_official 181:a4cbdfbbd2f4 1380 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1381 {
mbed_official 181:a4cbdfbbd2f4 1382 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1383 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1384
mbed_official 181:a4cbdfbbd2f4 1385 /* Disable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 1386 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1387
mbed_official 181:a4cbdfbbd2f4 1388 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1389 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1390
mbed_official 181:a4cbdfbbd2f4 1391 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 1392 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 1393
mbed_official 181:a4cbdfbbd2f4 1394 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1395 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1396 }
mbed_official 181:a4cbdfbbd2f4 1397
mbed_official 181:a4cbdfbbd2f4 1398 /**
mbed_official 181:a4cbdfbbd2f4 1399 * @brief Starts the PWM signal generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 1400 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1401 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1402 * @param Channel: TIM Channel to be disabled.
mbed_official 181:a4cbdfbbd2f4 1403 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1404 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1405 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1406 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1407 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1408 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1409 */
mbed_official 181:a4cbdfbbd2f4 1410 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1411 {
mbed_official 181:a4cbdfbbd2f4 1412 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1413 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1414
mbed_official 181:a4cbdfbbd2f4 1415 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1416 {
mbed_official 181:a4cbdfbbd2f4 1417 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1418 {
mbed_official 181:a4cbdfbbd2f4 1419 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 1420 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 1421 }
mbed_official 181:a4cbdfbbd2f4 1422 break;
mbed_official 181:a4cbdfbbd2f4 1423
mbed_official 181:a4cbdfbbd2f4 1424 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1425 {
mbed_official 181:a4cbdfbbd2f4 1426 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 1427 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 1428 }
mbed_official 181:a4cbdfbbd2f4 1429 break;
mbed_official 181:a4cbdfbbd2f4 1430
mbed_official 181:a4cbdfbbd2f4 1431 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1432 {
mbed_official 181:a4cbdfbbd2f4 1433 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 181:a4cbdfbbd2f4 1434 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 1435 }
mbed_official 181:a4cbdfbbd2f4 1436 break;
mbed_official 181:a4cbdfbbd2f4 1437
mbed_official 181:a4cbdfbbd2f4 1438 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1439 {
mbed_official 181:a4cbdfbbd2f4 1440 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1441 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 1442 }
mbed_official 181:a4cbdfbbd2f4 1443 break;
mbed_official 181:a4cbdfbbd2f4 1444
mbed_official 181:a4cbdfbbd2f4 1445 default:
mbed_official 181:a4cbdfbbd2f4 1446 break;
mbed_official 181:a4cbdfbbd2f4 1447 }
mbed_official 181:a4cbdfbbd2f4 1448
mbed_official 181:a4cbdfbbd2f4 1449 /* Enable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 1450 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1451
mbed_official 181:a4cbdfbbd2f4 1452 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1453 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1454
mbed_official 181:a4cbdfbbd2f4 1455 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1456 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1457 }
mbed_official 181:a4cbdfbbd2f4 1458
mbed_official 181:a4cbdfbbd2f4 1459 /**
mbed_official 181:a4cbdfbbd2f4 1460 * @brief Stops the PWM signal generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 1461 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1462 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1463 * @param Channel: TIM Channels to be disabled.
mbed_official 181:a4cbdfbbd2f4 1464 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1465 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1466 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1467 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1468 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1469 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1470 */
mbed_official 181:a4cbdfbbd2f4 1471 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1472 {
mbed_official 181:a4cbdfbbd2f4 1473 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1474 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1475
mbed_official 181:a4cbdfbbd2f4 1476 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1477 {
mbed_official 181:a4cbdfbbd2f4 1478 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1479 {
mbed_official 181:a4cbdfbbd2f4 1480 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 1481 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 1482 }
mbed_official 181:a4cbdfbbd2f4 1483 break;
mbed_official 181:a4cbdfbbd2f4 1484
mbed_official 181:a4cbdfbbd2f4 1485 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1486 {
mbed_official 181:a4cbdfbbd2f4 1487 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 1488 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 1489 }
mbed_official 181:a4cbdfbbd2f4 1490 break;
mbed_official 181:a4cbdfbbd2f4 1491
mbed_official 181:a4cbdfbbd2f4 1492 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1493 {
mbed_official 181:a4cbdfbbd2f4 1494 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 181:a4cbdfbbd2f4 1495 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 1496 }
mbed_official 181:a4cbdfbbd2f4 1497 break;
mbed_official 181:a4cbdfbbd2f4 1498
mbed_official 181:a4cbdfbbd2f4 1499 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1500 {
mbed_official 181:a4cbdfbbd2f4 1501 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1502 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 1503 }
mbed_official 181:a4cbdfbbd2f4 1504 break;
mbed_official 181:a4cbdfbbd2f4 1505
mbed_official 181:a4cbdfbbd2f4 1506 default:
mbed_official 181:a4cbdfbbd2f4 1507 break;
mbed_official 181:a4cbdfbbd2f4 1508 }
mbed_official 181:a4cbdfbbd2f4 1509
mbed_official 181:a4cbdfbbd2f4 1510 /* Disable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 1511 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1512
mbed_official 181:a4cbdfbbd2f4 1513 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1514 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1515
mbed_official 181:a4cbdfbbd2f4 1516 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1517 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1518 }
mbed_official 181:a4cbdfbbd2f4 1519
mbed_official 181:a4cbdfbbd2f4 1520 /**
mbed_official 181:a4cbdfbbd2f4 1521 * @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official 181:a4cbdfbbd2f4 1522 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1523 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1524 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 1525 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1526 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1527 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1528 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1529 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1530 * @param pData: The source Buffer address.
mbed_official 181:a4cbdfbbd2f4 1531 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 181:a4cbdfbbd2f4 1532 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1533 */
mbed_official 181:a4cbdfbbd2f4 1534 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 181:a4cbdfbbd2f4 1535 {
mbed_official 181:a4cbdfbbd2f4 1536 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1537 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1538
mbed_official 181:a4cbdfbbd2f4 1539 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 1540 {
mbed_official 181:a4cbdfbbd2f4 1541 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 1542 }
mbed_official 181:a4cbdfbbd2f4 1543 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 1544 {
mbed_official 181:a4cbdfbbd2f4 1545 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 181:a4cbdfbbd2f4 1546 {
mbed_official 181:a4cbdfbbd2f4 1547 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 1548 }
mbed_official 181:a4cbdfbbd2f4 1549 else
mbed_official 181:a4cbdfbbd2f4 1550 {
mbed_official 181:a4cbdfbbd2f4 1551 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 1552 }
mbed_official 181:a4cbdfbbd2f4 1553 }
mbed_official 181:a4cbdfbbd2f4 1554 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1555 {
mbed_official 181:a4cbdfbbd2f4 1556 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1557 {
mbed_official 181:a4cbdfbbd2f4 1558 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1559 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1560
mbed_official 181:a4cbdfbbd2f4 1561 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1562 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1563
mbed_official 181:a4cbdfbbd2f4 1564 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1565 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 181:a4cbdfbbd2f4 1566
mbed_official 181:a4cbdfbbd2f4 1567 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 181:a4cbdfbbd2f4 1568 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 1569 }
mbed_official 181:a4cbdfbbd2f4 1570 break;
mbed_official 181:a4cbdfbbd2f4 1571
mbed_official 181:a4cbdfbbd2f4 1572 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1573 {
mbed_official 181:a4cbdfbbd2f4 1574 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1575 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1576
mbed_official 181:a4cbdfbbd2f4 1577 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1578 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1579
mbed_official 181:a4cbdfbbd2f4 1580 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1581 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 181:a4cbdfbbd2f4 1582
mbed_official 181:a4cbdfbbd2f4 1583 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 181:a4cbdfbbd2f4 1584 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 1585 }
mbed_official 181:a4cbdfbbd2f4 1586 break;
mbed_official 181:a4cbdfbbd2f4 1587
mbed_official 181:a4cbdfbbd2f4 1588 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1589 {
mbed_official 181:a4cbdfbbd2f4 1590 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1591 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1592
mbed_official 181:a4cbdfbbd2f4 1593 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1594 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1595
mbed_official 181:a4cbdfbbd2f4 1596 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1597 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 181:a4cbdfbbd2f4 1598
mbed_official 181:a4cbdfbbd2f4 1599 /* Enable the TIM Output Capture/Compare 3 request */
mbed_official 181:a4cbdfbbd2f4 1600 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 181:a4cbdfbbd2f4 1601 }
mbed_official 181:a4cbdfbbd2f4 1602 break;
mbed_official 181:a4cbdfbbd2f4 1603
mbed_official 181:a4cbdfbbd2f4 1604 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1605 {
mbed_official 181:a4cbdfbbd2f4 1606 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1607 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 1608
mbed_official 181:a4cbdfbbd2f4 1609 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1610 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1611
mbed_official 181:a4cbdfbbd2f4 1612 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1613 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 181:a4cbdfbbd2f4 1614
mbed_official 181:a4cbdfbbd2f4 1615 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 181:a4cbdfbbd2f4 1616 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 181:a4cbdfbbd2f4 1617 }
mbed_official 181:a4cbdfbbd2f4 1618 break;
mbed_official 181:a4cbdfbbd2f4 1619
mbed_official 181:a4cbdfbbd2f4 1620 default:
mbed_official 181:a4cbdfbbd2f4 1621 break;
mbed_official 181:a4cbdfbbd2f4 1622 }
mbed_official 181:a4cbdfbbd2f4 1623
mbed_official 181:a4cbdfbbd2f4 1624 /* Enable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 1625 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1626
mbed_official 181:a4cbdfbbd2f4 1627 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1628 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1629
mbed_official 181:a4cbdfbbd2f4 1630 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1631 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1632 }
mbed_official 181:a4cbdfbbd2f4 1633
mbed_official 181:a4cbdfbbd2f4 1634 /**
mbed_official 181:a4cbdfbbd2f4 1635 * @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official 181:a4cbdfbbd2f4 1636 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1637 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1638 * @param Channel: TIM Channels to be disabled.
mbed_official 181:a4cbdfbbd2f4 1639 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1640 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1641 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1642 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1643 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1644 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1645 */
mbed_official 181:a4cbdfbbd2f4 1646 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1647 {
mbed_official 181:a4cbdfbbd2f4 1648 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1649 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1650
mbed_official 181:a4cbdfbbd2f4 1651 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1652 {
mbed_official 181:a4cbdfbbd2f4 1653 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1654 {
mbed_official 181:a4cbdfbbd2f4 1655 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 181:a4cbdfbbd2f4 1656 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 1657 }
mbed_official 181:a4cbdfbbd2f4 1658 break;
mbed_official 181:a4cbdfbbd2f4 1659
mbed_official 181:a4cbdfbbd2f4 1660 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1661 {
mbed_official 181:a4cbdfbbd2f4 1662 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 181:a4cbdfbbd2f4 1663 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 1664 }
mbed_official 181:a4cbdfbbd2f4 1665 break;
mbed_official 181:a4cbdfbbd2f4 1666
mbed_official 181:a4cbdfbbd2f4 1667 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1668 {
mbed_official 181:a4cbdfbbd2f4 1669 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 181:a4cbdfbbd2f4 1670 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 181:a4cbdfbbd2f4 1671 }
mbed_official 181:a4cbdfbbd2f4 1672 break;
mbed_official 181:a4cbdfbbd2f4 1673
mbed_official 181:a4cbdfbbd2f4 1674 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1675 {
mbed_official 181:a4cbdfbbd2f4 1676 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1677 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 181:a4cbdfbbd2f4 1678 }
mbed_official 181:a4cbdfbbd2f4 1679 break;
mbed_official 181:a4cbdfbbd2f4 1680
mbed_official 181:a4cbdfbbd2f4 1681 default:
mbed_official 181:a4cbdfbbd2f4 1682 break;
mbed_official 181:a4cbdfbbd2f4 1683 }
mbed_official 181:a4cbdfbbd2f4 1684
mbed_official 181:a4cbdfbbd2f4 1685 /* Disable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 1686 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1687
mbed_official 181:a4cbdfbbd2f4 1688 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1689 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1690
mbed_official 181:a4cbdfbbd2f4 1691 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 1692 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 1693
mbed_official 181:a4cbdfbbd2f4 1694 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1695 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1696 }
mbed_official 181:a4cbdfbbd2f4 1697
mbed_official 181:a4cbdfbbd2f4 1698 /**
mbed_official 181:a4cbdfbbd2f4 1699 * @brief Starts the TIM Input Capture measurement.
mbed_official 181:a4cbdfbbd2f4 1700 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1701 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1702 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 1703 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1704 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1705 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1706 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1707 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1708 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1709 */
mbed_official 181:a4cbdfbbd2f4 1710 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1711 {
mbed_official 181:a4cbdfbbd2f4 1712 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1713 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1714
mbed_official 181:a4cbdfbbd2f4 1715 /* Enable the Input Capture channel */
mbed_official 181:a4cbdfbbd2f4 1716 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1717
mbed_official 181:a4cbdfbbd2f4 1718 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1719 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1720
mbed_official 181:a4cbdfbbd2f4 1721 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1722 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1723 }
mbed_official 181:a4cbdfbbd2f4 1724
mbed_official 181:a4cbdfbbd2f4 1725 /**
mbed_official 181:a4cbdfbbd2f4 1726 * @brief Stops the TIM Input Capture measurement.
mbed_official 181:a4cbdfbbd2f4 1727 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1728 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1729 * @param Channel: TIM Channels to be disabled.
mbed_official 181:a4cbdfbbd2f4 1730 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1731 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1732 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1733 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1734 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1735 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1736 */
mbed_official 181:a4cbdfbbd2f4 1737 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1738 {
mbed_official 181:a4cbdfbbd2f4 1739 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1740 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1741
mbed_official 181:a4cbdfbbd2f4 1742 /* Disable the Input Capture channel */
mbed_official 181:a4cbdfbbd2f4 1743 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1744
mbed_official 181:a4cbdfbbd2f4 1745 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1746 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1747
mbed_official 181:a4cbdfbbd2f4 1748 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1749 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1750 }
mbed_official 181:a4cbdfbbd2f4 1751
mbed_official 181:a4cbdfbbd2f4 1752 /**
mbed_official 181:a4cbdfbbd2f4 1753 * @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 1754 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1755 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1756 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 1757 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1758 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1759 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1760 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1761 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1762 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1763 */
mbed_official 181:a4cbdfbbd2f4 1764 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1765 {
mbed_official 181:a4cbdfbbd2f4 1766 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1767 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1768
mbed_official 181:a4cbdfbbd2f4 1769 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1770 {
mbed_official 181:a4cbdfbbd2f4 1771 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1772 {
mbed_official 181:a4cbdfbbd2f4 1773 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 1774 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 1775 }
mbed_official 181:a4cbdfbbd2f4 1776 break;
mbed_official 181:a4cbdfbbd2f4 1777
mbed_official 181:a4cbdfbbd2f4 1778 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1779 {
mbed_official 181:a4cbdfbbd2f4 1780 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 1781 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 1782 }
mbed_official 181:a4cbdfbbd2f4 1783 break;
mbed_official 181:a4cbdfbbd2f4 1784
mbed_official 181:a4cbdfbbd2f4 1785 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1786 {
mbed_official 181:a4cbdfbbd2f4 1787 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 181:a4cbdfbbd2f4 1788 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 1789 }
mbed_official 181:a4cbdfbbd2f4 1790 break;
mbed_official 181:a4cbdfbbd2f4 1791
mbed_official 181:a4cbdfbbd2f4 1792 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1793 {
mbed_official 181:a4cbdfbbd2f4 1794 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1795 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 1796 }
mbed_official 181:a4cbdfbbd2f4 1797 break;
mbed_official 181:a4cbdfbbd2f4 1798
mbed_official 181:a4cbdfbbd2f4 1799 default:
mbed_official 181:a4cbdfbbd2f4 1800 break;
mbed_official 181:a4cbdfbbd2f4 1801 }
mbed_official 181:a4cbdfbbd2f4 1802 /* Enable the Input Capture channel */
mbed_official 181:a4cbdfbbd2f4 1803 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1804
mbed_official 181:a4cbdfbbd2f4 1805 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1806 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1807
mbed_official 181:a4cbdfbbd2f4 1808 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1809 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1810 }
mbed_official 181:a4cbdfbbd2f4 1811
mbed_official 181:a4cbdfbbd2f4 1812 /**
mbed_official 181:a4cbdfbbd2f4 1813 * @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 1814 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1815 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1816 * @param Channel : TIM Channels to be disabled
mbed_official 181:a4cbdfbbd2f4 1817 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1818 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1819 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1820 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1821 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1822 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1823 */
mbed_official 181:a4cbdfbbd2f4 1824 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 1825 {
mbed_official 181:a4cbdfbbd2f4 1826 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1827 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1828
mbed_official 181:a4cbdfbbd2f4 1829 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1830 {
mbed_official 181:a4cbdfbbd2f4 1831 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1832 {
mbed_official 181:a4cbdfbbd2f4 1833 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 1834 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 1835 }
mbed_official 181:a4cbdfbbd2f4 1836 break;
mbed_official 181:a4cbdfbbd2f4 1837
mbed_official 181:a4cbdfbbd2f4 1838 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1839 {
mbed_official 181:a4cbdfbbd2f4 1840 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 1841 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 1842 }
mbed_official 181:a4cbdfbbd2f4 1843 break;
mbed_official 181:a4cbdfbbd2f4 1844
mbed_official 181:a4cbdfbbd2f4 1845 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1846 {
mbed_official 181:a4cbdfbbd2f4 1847 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 181:a4cbdfbbd2f4 1848 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 1849 }
mbed_official 181:a4cbdfbbd2f4 1850 break;
mbed_official 181:a4cbdfbbd2f4 1851
mbed_official 181:a4cbdfbbd2f4 1852 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1853 {
mbed_official 181:a4cbdfbbd2f4 1854 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 181:a4cbdfbbd2f4 1855 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 1856 }
mbed_official 181:a4cbdfbbd2f4 1857 break;
mbed_official 181:a4cbdfbbd2f4 1858
mbed_official 181:a4cbdfbbd2f4 1859 default:
mbed_official 181:a4cbdfbbd2f4 1860 break;
mbed_official 181:a4cbdfbbd2f4 1861 }
mbed_official 181:a4cbdfbbd2f4 1862
mbed_official 181:a4cbdfbbd2f4 1863 /* Disable the Input Capture channel */
mbed_official 181:a4cbdfbbd2f4 1864 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 1865
mbed_official 181:a4cbdfbbd2f4 1866 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1867 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1868
mbed_official 181:a4cbdfbbd2f4 1869 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1870 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1871 }
mbed_official 181:a4cbdfbbd2f4 1872
mbed_official 181:a4cbdfbbd2f4 1873 /**
mbed_official 181:a4cbdfbbd2f4 1874 * @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official 181:a4cbdfbbd2f4 1875 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1876 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1877 * @param Channel : TIM Channels to be enabled
mbed_official 181:a4cbdfbbd2f4 1878 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1879 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1880 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1881 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1882 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1883 * @param pData: The destination Buffer address.
mbed_official 181:a4cbdfbbd2f4 1884 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 181:a4cbdfbbd2f4 1885 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 1886 */
mbed_official 181:a4cbdfbbd2f4 1887 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 181:a4cbdfbbd2f4 1888 {
mbed_official 181:a4cbdfbbd2f4 1889 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 1890 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 1891 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 1892
mbed_official 181:a4cbdfbbd2f4 1893 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 1894 {
mbed_official 181:a4cbdfbbd2f4 1895 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 1896 }
mbed_official 181:a4cbdfbbd2f4 1897 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 1898 {
mbed_official 181:a4cbdfbbd2f4 1899 if((pData == 0 ) && (Length > 0))
mbed_official 181:a4cbdfbbd2f4 1900 {
mbed_official 181:a4cbdfbbd2f4 1901 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 1902 }
mbed_official 181:a4cbdfbbd2f4 1903 else
mbed_official 181:a4cbdfbbd2f4 1904 {
mbed_official 181:a4cbdfbbd2f4 1905 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 1906 }
mbed_official 181:a4cbdfbbd2f4 1907 }
mbed_official 181:a4cbdfbbd2f4 1908
mbed_official 181:a4cbdfbbd2f4 1909 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 1910 {
mbed_official 181:a4cbdfbbd2f4 1911 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 1912 {
mbed_official 181:a4cbdfbbd2f4 1913 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1914 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 1915
mbed_official 181:a4cbdfbbd2f4 1916 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1917 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1918
mbed_official 181:a4cbdfbbd2f4 1919 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1920 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official 181:a4cbdfbbd2f4 1921
mbed_official 181:a4cbdfbbd2f4 1922 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 181:a4cbdfbbd2f4 1923 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 1924 }
mbed_official 181:a4cbdfbbd2f4 1925 break;
mbed_official 181:a4cbdfbbd2f4 1926
mbed_official 181:a4cbdfbbd2f4 1927 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 1928 {
mbed_official 181:a4cbdfbbd2f4 1929 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1930 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 1931
mbed_official 181:a4cbdfbbd2f4 1932 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1933 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1934
mbed_official 181:a4cbdfbbd2f4 1935 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1936 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official 181:a4cbdfbbd2f4 1937
mbed_official 181:a4cbdfbbd2f4 1938 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 181:a4cbdfbbd2f4 1939 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 1940 }
mbed_official 181:a4cbdfbbd2f4 1941 break;
mbed_official 181:a4cbdfbbd2f4 1942
mbed_official 181:a4cbdfbbd2f4 1943 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 1944 {
mbed_official 181:a4cbdfbbd2f4 1945 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1946 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 1947
mbed_official 181:a4cbdfbbd2f4 1948 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1949 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1950
mbed_official 181:a4cbdfbbd2f4 1951 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1952 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official 181:a4cbdfbbd2f4 1953
mbed_official 181:a4cbdfbbd2f4 1954 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 181:a4cbdfbbd2f4 1955 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 181:a4cbdfbbd2f4 1956 }
mbed_official 181:a4cbdfbbd2f4 1957 break;
mbed_official 181:a4cbdfbbd2f4 1958
mbed_official 181:a4cbdfbbd2f4 1959 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 1960 {
mbed_official 181:a4cbdfbbd2f4 1961 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 1962 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 1963
mbed_official 181:a4cbdfbbd2f4 1964 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 1965 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 1966
mbed_official 181:a4cbdfbbd2f4 1967 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 1968 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official 181:a4cbdfbbd2f4 1969
mbed_official 181:a4cbdfbbd2f4 1970 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 181:a4cbdfbbd2f4 1971 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 181:a4cbdfbbd2f4 1972 }
mbed_official 181:a4cbdfbbd2f4 1973 break;
mbed_official 181:a4cbdfbbd2f4 1974
mbed_official 181:a4cbdfbbd2f4 1975 default:
mbed_official 181:a4cbdfbbd2f4 1976 break;
mbed_official 181:a4cbdfbbd2f4 1977 }
mbed_official 181:a4cbdfbbd2f4 1978
mbed_official 181:a4cbdfbbd2f4 1979 /* Enable the Input Capture channel */
mbed_official 181:a4cbdfbbd2f4 1980 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 1981
mbed_official 181:a4cbdfbbd2f4 1982 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 1983 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 1984
mbed_official 181:a4cbdfbbd2f4 1985 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 1986 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 1987 }
mbed_official 181:a4cbdfbbd2f4 1988
mbed_official 181:a4cbdfbbd2f4 1989 /**
mbed_official 181:a4cbdfbbd2f4 1990 * @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official 181:a4cbdfbbd2f4 1991 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 1992 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 1993 * @param Channel : TIM Channels to be disabled
mbed_official 181:a4cbdfbbd2f4 1994 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 1995 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 1996 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 1997 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 1998 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 1999 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2000 */
mbed_official 181:a4cbdfbbd2f4 2001 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2002 {
mbed_official 181:a4cbdfbbd2f4 2003 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2004 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 181:a4cbdfbbd2f4 2005 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2006
mbed_official 181:a4cbdfbbd2f4 2007 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2008 {
mbed_official 181:a4cbdfbbd2f4 2009 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2010 {
mbed_official 181:a4cbdfbbd2f4 2011 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 181:a4cbdfbbd2f4 2012 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 2013 }
mbed_official 181:a4cbdfbbd2f4 2014 break;
mbed_official 181:a4cbdfbbd2f4 2015
mbed_official 181:a4cbdfbbd2f4 2016 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2017 {
mbed_official 181:a4cbdfbbd2f4 2018 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 181:a4cbdfbbd2f4 2019 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 2020 }
mbed_official 181:a4cbdfbbd2f4 2021 break;
mbed_official 181:a4cbdfbbd2f4 2022
mbed_official 181:a4cbdfbbd2f4 2023 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 2024 {
mbed_official 181:a4cbdfbbd2f4 2025 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 181:a4cbdfbbd2f4 2026 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 181:a4cbdfbbd2f4 2027 }
mbed_official 181:a4cbdfbbd2f4 2028 break;
mbed_official 181:a4cbdfbbd2f4 2029
mbed_official 181:a4cbdfbbd2f4 2030 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 2031 {
mbed_official 181:a4cbdfbbd2f4 2032 /* Disable the TIM Capture/Compare 4 DMA request */
mbed_official 181:a4cbdfbbd2f4 2033 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 181:a4cbdfbbd2f4 2034 }
mbed_official 181:a4cbdfbbd2f4 2035 break;
mbed_official 181:a4cbdfbbd2f4 2036
mbed_official 181:a4cbdfbbd2f4 2037 default:
mbed_official 181:a4cbdfbbd2f4 2038 break;
mbed_official 181:a4cbdfbbd2f4 2039 }
mbed_official 181:a4cbdfbbd2f4 2040
mbed_official 181:a4cbdfbbd2f4 2041 /* Disable the Input Capture channel */
mbed_official 181:a4cbdfbbd2f4 2042 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2043
mbed_official 181:a4cbdfbbd2f4 2044 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2045 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2046
mbed_official 181:a4cbdfbbd2f4 2047 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 2048 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 2049
mbed_official 181:a4cbdfbbd2f4 2050 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2051 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2052 }
mbed_official 181:a4cbdfbbd2f4 2053
mbed_official 181:a4cbdfbbd2f4 2054 /**
mbed_official 181:a4cbdfbbd2f4 2055 * @brief Starts the TIM One Pulse signal generation.
mbed_official 181:a4cbdfbbd2f4 2056 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2057 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2058 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2059 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2060 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2061 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2062 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2063 */
mbed_official 181:a4cbdfbbd2f4 2064 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 181:a4cbdfbbd2f4 2065 {
mbed_official 181:a4cbdfbbd2f4 2066 /* Enable the Capture compare and the Input Capture channels
mbed_official 181:a4cbdfbbd2f4 2067 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2068 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 181:a4cbdfbbd2f4 2069 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 181:a4cbdfbbd2f4 2070 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 181:a4cbdfbbd2f4 2071
mbed_official 181:a4cbdfbbd2f4 2072 No need to enable the counter, it's enabled automatically by hardware
mbed_official 181:a4cbdfbbd2f4 2073 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 181:a4cbdfbbd2f4 2074
mbed_official 181:a4cbdfbbd2f4 2075 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2076 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2077
mbed_official 181:a4cbdfbbd2f4 2078 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2079 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2080 }
mbed_official 181:a4cbdfbbd2f4 2081
mbed_official 181:a4cbdfbbd2f4 2082 /**
mbed_official 181:a4cbdfbbd2f4 2083 * @brief Stops the TIM One Pulse signal generation.
mbed_official 181:a4cbdfbbd2f4 2084 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2085 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2086 * @param OutputChannel : TIM Channels to be disable.
mbed_official 181:a4cbdfbbd2f4 2087 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2088 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2089 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2090 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2091 */
mbed_official 181:a4cbdfbbd2f4 2092 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 181:a4cbdfbbd2f4 2093 {
mbed_official 181:a4cbdfbbd2f4 2094 /* Disable the Capture compare and the Input Capture channels
mbed_official 181:a4cbdfbbd2f4 2095 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2096 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 181:a4cbdfbbd2f4 2097 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 181:a4cbdfbbd2f4 2098 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 181:a4cbdfbbd2f4 2099
mbed_official 181:a4cbdfbbd2f4 2100 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2101 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2102
mbed_official 181:a4cbdfbbd2f4 2103 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2104 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2105
mbed_official 181:a4cbdfbbd2f4 2106 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2107 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2108 }
mbed_official 181:a4cbdfbbd2f4 2109
mbed_official 181:a4cbdfbbd2f4 2110 /**
mbed_official 181:a4cbdfbbd2f4 2111 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 2112 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2113 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2114 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2115 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2116 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2117 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2118 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2119 */
mbed_official 181:a4cbdfbbd2f4 2120 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 181:a4cbdfbbd2f4 2121 {
mbed_official 181:a4cbdfbbd2f4 2122 /* Enable the Capture compare and the Input Capture channels
mbed_official 181:a4cbdfbbd2f4 2123 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2124 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 181:a4cbdfbbd2f4 2125 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 181:a4cbdfbbd2f4 2126 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 181:a4cbdfbbd2f4 2127
mbed_official 181:a4cbdfbbd2f4 2128 No need to enable the counter, it's enabled automatically by hardware
mbed_official 181:a4cbdfbbd2f4 2129 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 181:a4cbdfbbd2f4 2130
mbed_official 181:a4cbdfbbd2f4 2131 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 2132 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2133
mbed_official 181:a4cbdfbbd2f4 2134 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 2135 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2136
mbed_official 181:a4cbdfbbd2f4 2137 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2138 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2139
mbed_official 181:a4cbdfbbd2f4 2140 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2141 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2142 }
mbed_official 181:a4cbdfbbd2f4 2143
mbed_official 181:a4cbdfbbd2f4 2144 /**
mbed_official 181:a4cbdfbbd2f4 2145 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 2146 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2147 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2148 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2149 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2150 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2151 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2152 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2153 */
mbed_official 181:a4cbdfbbd2f4 2154 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 181:a4cbdfbbd2f4 2155 {
mbed_official 181:a4cbdfbbd2f4 2156 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 181:a4cbdfbbd2f4 2157 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2158
mbed_official 181:a4cbdfbbd2f4 2159 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 181:a4cbdfbbd2f4 2160 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2161
mbed_official 181:a4cbdfbbd2f4 2162 /* Disable the Capture compare and the Input Capture channels
mbed_official 181:a4cbdfbbd2f4 2163 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2164 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 181:a4cbdfbbd2f4 2165 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 181:a4cbdfbbd2f4 2166 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 181:a4cbdfbbd2f4 2167 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2168 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2169
mbed_official 181:a4cbdfbbd2f4 2170 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2171 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2172
mbed_official 181:a4cbdfbbd2f4 2173 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2174 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2175 }
mbed_official 181:a4cbdfbbd2f4 2176
mbed_official 181:a4cbdfbbd2f4 2177 /**
mbed_official 181:a4cbdfbbd2f4 2178 * @brief Starts the TIM Encoder Interface.
mbed_official 181:a4cbdfbbd2f4 2179 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2180 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2181 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2182 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2185 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2186 */
mbed_official 181:a4cbdfbbd2f4 2187 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2188 {
mbed_official 181:a4cbdfbbd2f4 2189 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2190 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2191
mbed_official 181:a4cbdfbbd2f4 2192 /* Enable the encoder interface channels */
mbed_official 181:a4cbdfbbd2f4 2193 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2194 {
mbed_official 181:a4cbdfbbd2f4 2195 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2196 {
mbed_official 181:a4cbdfbbd2f4 2197 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2198 break;
mbed_official 181:a4cbdfbbd2f4 2199 }
mbed_official 181:a4cbdfbbd2f4 2200 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2201 {
mbed_official 181:a4cbdfbbd2f4 2202 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2203 break;
mbed_official 181:a4cbdfbbd2f4 2204 }
mbed_official 181:a4cbdfbbd2f4 2205 default :
mbed_official 181:a4cbdfbbd2f4 2206 {
mbed_official 181:a4cbdfbbd2f4 2207 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2208 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2209 break;
mbed_official 181:a4cbdfbbd2f4 2210 }
mbed_official 181:a4cbdfbbd2f4 2211 }
mbed_official 181:a4cbdfbbd2f4 2212 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2213 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2214
mbed_official 181:a4cbdfbbd2f4 2215 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2216 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2217 }
mbed_official 181:a4cbdfbbd2f4 2218
mbed_official 181:a4cbdfbbd2f4 2219 /**
mbed_official 181:a4cbdfbbd2f4 2220 * @brief Stops the TIM Encoder Interface.
mbed_official 181:a4cbdfbbd2f4 2221 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2222 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2223 * @param Channel: TIM Channels to be disabled.
mbed_official 181:a4cbdfbbd2f4 2224 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2225 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2226 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2227 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2228 */
mbed_official 181:a4cbdfbbd2f4 2229 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2230 {
mbed_official 181:a4cbdfbbd2f4 2231 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2232 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2233
mbed_official 181:a4cbdfbbd2f4 2234 /* Disable the Input Capture channels 1 and 2
mbed_official 181:a4cbdfbbd2f4 2235 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 181:a4cbdfbbd2f4 2236 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2237 {
mbed_official 181:a4cbdfbbd2f4 2238 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2239 {
mbed_official 181:a4cbdfbbd2f4 2240 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2241 break;
mbed_official 181:a4cbdfbbd2f4 2242 }
mbed_official 181:a4cbdfbbd2f4 2243 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2244 {
mbed_official 181:a4cbdfbbd2f4 2245 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2246 break;
mbed_official 181:a4cbdfbbd2f4 2247 }
mbed_official 181:a4cbdfbbd2f4 2248 default :
mbed_official 181:a4cbdfbbd2f4 2249 {
mbed_official 181:a4cbdfbbd2f4 2250 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2251 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2252 break;
mbed_official 181:a4cbdfbbd2f4 2253 }
mbed_official 181:a4cbdfbbd2f4 2254 }
mbed_official 181:a4cbdfbbd2f4 2255 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2256 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2257
mbed_official 181:a4cbdfbbd2f4 2258 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2259 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2260 }
mbed_official 181:a4cbdfbbd2f4 2261
mbed_official 181:a4cbdfbbd2f4 2262 /**
mbed_official 181:a4cbdfbbd2f4 2263 * @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 2264 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2265 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2266 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2267 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2268 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2269 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2270 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2271 */
mbed_official 181:a4cbdfbbd2f4 2272 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2273 {
mbed_official 181:a4cbdfbbd2f4 2274 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2275 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2276
mbed_official 181:a4cbdfbbd2f4 2277 /* Enable the encoder interface channels */
mbed_official 181:a4cbdfbbd2f4 2278 /* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official 181:a4cbdfbbd2f4 2279 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2280 {
mbed_official 181:a4cbdfbbd2f4 2281 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2282 {
mbed_official 181:a4cbdfbbd2f4 2283 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2284 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2285 break;
mbed_official 181:a4cbdfbbd2f4 2286 }
mbed_official 181:a4cbdfbbd2f4 2287 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2288 {
mbed_official 181:a4cbdfbbd2f4 2289 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2290 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2291 break;
mbed_official 181:a4cbdfbbd2f4 2292 }
mbed_official 181:a4cbdfbbd2f4 2293 default :
mbed_official 181:a4cbdfbbd2f4 2294 {
mbed_official 181:a4cbdfbbd2f4 2295 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2296 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2297 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2298 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2299 break;
mbed_official 181:a4cbdfbbd2f4 2300 }
mbed_official 181:a4cbdfbbd2f4 2301 }
mbed_official 181:a4cbdfbbd2f4 2302
mbed_official 181:a4cbdfbbd2f4 2303 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2304 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2305
mbed_official 181:a4cbdfbbd2f4 2306 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2307 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2308 }
mbed_official 181:a4cbdfbbd2f4 2309
mbed_official 181:a4cbdfbbd2f4 2310 /**
mbed_official 181:a4cbdfbbd2f4 2311 * @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official 181:a4cbdfbbd2f4 2312 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2313 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2314 * @param Channel: TIM Channels to be disabled.
mbed_official 181:a4cbdfbbd2f4 2315 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2316 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2317 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2318 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2319 */
mbed_official 181:a4cbdfbbd2f4 2320 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2321 {
mbed_official 181:a4cbdfbbd2f4 2322 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2323 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2324
mbed_official 181:a4cbdfbbd2f4 2325 /* Disable the Input Capture channels 1 and 2
mbed_official 181:a4cbdfbbd2f4 2326 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 181:a4cbdfbbd2f4 2327 if(Channel == TIM_CHANNEL_1)
mbed_official 181:a4cbdfbbd2f4 2328 {
mbed_official 181:a4cbdfbbd2f4 2329 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2330
mbed_official 181:a4cbdfbbd2f4 2331 /* Disable the capture compare Interrupts 1 */
mbed_official 181:a4cbdfbbd2f4 2332 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2333 }
mbed_official 181:a4cbdfbbd2f4 2334 else if(Channel == TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2335 {
mbed_official 181:a4cbdfbbd2f4 2336 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2337
mbed_official 181:a4cbdfbbd2f4 2338 /* Disable the capture compare Interrupts 2 */
mbed_official 181:a4cbdfbbd2f4 2339 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2340 }
mbed_official 181:a4cbdfbbd2f4 2341 else
mbed_official 181:a4cbdfbbd2f4 2342 {
mbed_official 181:a4cbdfbbd2f4 2343 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2345
mbed_official 181:a4cbdfbbd2f4 2346 /* Disable the capture compare Interrupts 1 and 2 */
mbed_official 181:a4cbdfbbd2f4 2347 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2348 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2349 }
mbed_official 181:a4cbdfbbd2f4 2350
mbed_official 181:a4cbdfbbd2f4 2351 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2352 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2353
mbed_official 181:a4cbdfbbd2f4 2354 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 2355 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 2356
mbed_official 181:a4cbdfbbd2f4 2357 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2358 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2359 }
mbed_official 181:a4cbdfbbd2f4 2360
mbed_official 181:a4cbdfbbd2f4 2361 /**
mbed_official 181:a4cbdfbbd2f4 2362 * @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official 181:a4cbdfbbd2f4 2363 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2364 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2365 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2366 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2367 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2368 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2369 * @param pData1: The destination Buffer address for IC1.
mbed_official 181:a4cbdfbbd2f4 2370 * @param pData2: The destination Buffer address for IC2.
mbed_official 181:a4cbdfbbd2f4 2371 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 181:a4cbdfbbd2f4 2372 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2373 */
mbed_official 181:a4cbdfbbd2f4 2374 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
mbed_official 181:a4cbdfbbd2f4 2375 {
mbed_official 181:a4cbdfbbd2f4 2376 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2377 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2378
mbed_official 181:a4cbdfbbd2f4 2379 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 2380 {
mbed_official 181:a4cbdfbbd2f4 2381 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 2382 }
mbed_official 181:a4cbdfbbd2f4 2383 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 2384 {
mbed_official 181:a4cbdfbbd2f4 2385 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
mbed_official 181:a4cbdfbbd2f4 2386 {
mbed_official 181:a4cbdfbbd2f4 2387 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 2388 }
mbed_official 181:a4cbdfbbd2f4 2389 else
mbed_official 181:a4cbdfbbd2f4 2390 {
mbed_official 181:a4cbdfbbd2f4 2391 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 2392 }
mbed_official 181:a4cbdfbbd2f4 2393 }
mbed_official 181:a4cbdfbbd2f4 2394
mbed_official 181:a4cbdfbbd2f4 2395 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2396 {
mbed_official 181:a4cbdfbbd2f4 2397 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2398 {
mbed_official 181:a4cbdfbbd2f4 2399 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 2400 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 2401
mbed_official 181:a4cbdfbbd2f4 2402 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 2403 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 2404
mbed_official 181:a4cbdfbbd2f4 2405 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 2406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official 181:a4cbdfbbd2f4 2407
mbed_official 181:a4cbdfbbd2f4 2408 /* Enable the TIM Input Capture DMA request */
mbed_official 181:a4cbdfbbd2f4 2409 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 2410
mbed_official 181:a4cbdfbbd2f4 2411 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2412 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2413
mbed_official 181:a4cbdfbbd2f4 2414 /* Enable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2416 }
mbed_official 181:a4cbdfbbd2f4 2417 break;
mbed_official 181:a4cbdfbbd2f4 2418
mbed_official 181:a4cbdfbbd2f4 2419 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2420 {
mbed_official 181:a4cbdfbbd2f4 2421 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 2422 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 2423
mbed_official 181:a4cbdfbbd2f4 2424 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 2425 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
mbed_official 181:a4cbdfbbd2f4 2426 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 2427 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 181:a4cbdfbbd2f4 2428
mbed_official 181:a4cbdfbbd2f4 2429 /* Enable the TIM Input Capture DMA request */
mbed_official 181:a4cbdfbbd2f4 2430 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 2431
mbed_official 181:a4cbdfbbd2f4 2432 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2433 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2434
mbed_official 181:a4cbdfbbd2f4 2435 /* Enable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 2436 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2437 }
mbed_official 181:a4cbdfbbd2f4 2438 break;
mbed_official 181:a4cbdfbbd2f4 2439
mbed_official 181:a4cbdfbbd2f4 2440 case TIM_CHANNEL_ALL:
mbed_official 181:a4cbdfbbd2f4 2441 {
mbed_official 181:a4cbdfbbd2f4 2442 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 2443 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 2444
mbed_official 181:a4cbdfbbd2f4 2445 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 2446 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 2447
mbed_official 181:a4cbdfbbd2f4 2448 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 2449 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official 181:a4cbdfbbd2f4 2450
mbed_official 181:a4cbdfbbd2f4 2451 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 2452 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 2453
mbed_official 181:a4cbdfbbd2f4 2454 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 2455 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 2456
mbed_official 181:a4cbdfbbd2f4 2457 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 2458 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 181:a4cbdfbbd2f4 2459
mbed_official 181:a4cbdfbbd2f4 2460 /* Enable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2461 __HAL_TIM_ENABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2462
mbed_official 181:a4cbdfbbd2f4 2463 /* Enable the Capture compare channel */
mbed_official 181:a4cbdfbbd2f4 2464 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2465 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 181:a4cbdfbbd2f4 2466
mbed_official 181:a4cbdfbbd2f4 2467 /* Enable the TIM Input Capture DMA request */
mbed_official 181:a4cbdfbbd2f4 2468 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 2469 /* Enable the TIM Input Capture DMA request */
mbed_official 181:a4cbdfbbd2f4 2470 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 2471 }
mbed_official 181:a4cbdfbbd2f4 2472 break;
mbed_official 181:a4cbdfbbd2f4 2473
mbed_official 181:a4cbdfbbd2f4 2474 default:
mbed_official 181:a4cbdfbbd2f4 2475 break;
mbed_official 181:a4cbdfbbd2f4 2476 }
mbed_official 181:a4cbdfbbd2f4 2477 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2478 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2479 }
mbed_official 181:a4cbdfbbd2f4 2480
mbed_official 181:a4cbdfbbd2f4 2481 /**
mbed_official 181:a4cbdfbbd2f4 2482 * @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official 181:a4cbdfbbd2f4 2483 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2484 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2485 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2486 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2487 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2488 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2489 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2490 */
mbed_official 181:a4cbdfbbd2f4 2491 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2492 {
mbed_official 181:a4cbdfbbd2f4 2493 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2494 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2495
mbed_official 181:a4cbdfbbd2f4 2496 /* Disable the Input Capture channels 1 and 2
mbed_official 181:a4cbdfbbd2f4 2497 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 181:a4cbdfbbd2f4 2498 if(Channel == TIM_CHANNEL_1)
mbed_official 181:a4cbdfbbd2f4 2499 {
mbed_official 181:a4cbdfbbd2f4 2500 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2501
mbed_official 181:a4cbdfbbd2f4 2502 /* Disable the capture compare DMA Request 1 */
mbed_official 181:a4cbdfbbd2f4 2503 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 2504 }
mbed_official 181:a4cbdfbbd2f4 2505 else if(Channel == TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2506 {
mbed_official 181:a4cbdfbbd2f4 2507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2508
mbed_official 181:a4cbdfbbd2f4 2509 /* Disable the capture compare DMA Request 2 */
mbed_official 181:a4cbdfbbd2f4 2510 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 2511 }
mbed_official 181:a4cbdfbbd2f4 2512 else
mbed_official 181:a4cbdfbbd2f4 2513 {
mbed_official 181:a4cbdfbbd2f4 2514 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2515 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 181:a4cbdfbbd2f4 2516
mbed_official 181:a4cbdfbbd2f4 2517 /* Disable the capture compare DMA Request 1 and 2 */
mbed_official 181:a4cbdfbbd2f4 2518 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 181:a4cbdfbbd2f4 2519 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 181:a4cbdfbbd2f4 2520 }
mbed_official 181:a4cbdfbbd2f4 2521
mbed_official 181:a4cbdfbbd2f4 2522 /* Disable the Peripheral */
mbed_official 181:a4cbdfbbd2f4 2523 __HAL_TIM_DISABLE(htim);
mbed_official 181:a4cbdfbbd2f4 2524
mbed_official 181:a4cbdfbbd2f4 2525 /* Change the htim state */
mbed_official 181:a4cbdfbbd2f4 2526 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 2527
mbed_official 181:a4cbdfbbd2f4 2528 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 2529 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2530 }
mbed_official 181:a4cbdfbbd2f4 2531
mbed_official 181:a4cbdfbbd2f4 2532 /**
mbed_official 181:a4cbdfbbd2f4 2533 * @}
mbed_official 181:a4cbdfbbd2f4 2534 */
mbed_official 181:a4cbdfbbd2f4 2535 /** @defgroup TIM_Group7 TIM IRQ handler management
mbed_official 181:a4cbdfbbd2f4 2536 * @brief IRQ handler management
mbed_official 181:a4cbdfbbd2f4 2537 *
mbed_official 181:a4cbdfbbd2f4 2538 @verbatim
mbed_official 181:a4cbdfbbd2f4 2539 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 2540 ##### IRQ handler management #####
mbed_official 181:a4cbdfbbd2f4 2541 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 2542 [..]
mbed_official 181:a4cbdfbbd2f4 2543 This section provides Timer IRQ handler function.
mbed_official 181:a4cbdfbbd2f4 2544
mbed_official 181:a4cbdfbbd2f4 2545 @endverbatim
mbed_official 181:a4cbdfbbd2f4 2546 * @{
mbed_official 181:a4cbdfbbd2f4 2547 */
mbed_official 181:a4cbdfbbd2f4 2548 /**
mbed_official 181:a4cbdfbbd2f4 2549 * @brief This function handles TIM interrupts requests.
mbed_official 181:a4cbdfbbd2f4 2550 * @param htim: TIM handle
mbed_official 181:a4cbdfbbd2f4 2551 * @retval None
mbed_official 181:a4cbdfbbd2f4 2552 */
mbed_official 181:a4cbdfbbd2f4 2553 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 2554 {
mbed_official 181:a4cbdfbbd2f4 2555 /* Capture compare 1 event */
mbed_official 181:a4cbdfbbd2f4 2556 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official 181:a4cbdfbbd2f4 2557 {
mbed_official 181:a4cbdfbbd2f4 2558 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
mbed_official 181:a4cbdfbbd2f4 2559 {
mbed_official 181:a4cbdfbbd2f4 2560 {
mbed_official 181:a4cbdfbbd2f4 2561 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official 181:a4cbdfbbd2f4 2562 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 181:a4cbdfbbd2f4 2563
mbed_official 181:a4cbdfbbd2f4 2564 /* Input capture event */
mbed_official 181:a4cbdfbbd2f4 2565 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official 181:a4cbdfbbd2f4 2566 {
mbed_official 181:a4cbdfbbd2f4 2567 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2568 }
mbed_official 181:a4cbdfbbd2f4 2569 /* Output compare event */
mbed_official 181:a4cbdfbbd2f4 2570 else
mbed_official 181:a4cbdfbbd2f4 2571 {
mbed_official 181:a4cbdfbbd2f4 2572 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2573 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2574 }
mbed_official 181:a4cbdfbbd2f4 2575 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 181:a4cbdfbbd2f4 2576 }
mbed_official 181:a4cbdfbbd2f4 2577 }
mbed_official 181:a4cbdfbbd2f4 2578 }
mbed_official 181:a4cbdfbbd2f4 2579 /* Capture compare 2 event */
mbed_official 181:a4cbdfbbd2f4 2580 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official 181:a4cbdfbbd2f4 2581 {
mbed_official 181:a4cbdfbbd2f4 2582 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
mbed_official 181:a4cbdfbbd2f4 2583 {
mbed_official 181:a4cbdfbbd2f4 2584 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official 181:a4cbdfbbd2f4 2585 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 181:a4cbdfbbd2f4 2586 /* Input capture event */
mbed_official 181:a4cbdfbbd2f4 2587 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official 181:a4cbdfbbd2f4 2588 {
mbed_official 181:a4cbdfbbd2f4 2589 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2590 }
mbed_official 181:a4cbdfbbd2f4 2591 /* Output compare event */
mbed_official 181:a4cbdfbbd2f4 2592 else
mbed_official 181:a4cbdfbbd2f4 2593 {
mbed_official 181:a4cbdfbbd2f4 2594 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2595 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2596 }
mbed_official 181:a4cbdfbbd2f4 2597 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 181:a4cbdfbbd2f4 2598 }
mbed_official 181:a4cbdfbbd2f4 2599 }
mbed_official 181:a4cbdfbbd2f4 2600 /* Capture compare 3 event */
mbed_official 181:a4cbdfbbd2f4 2601 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official 181:a4cbdfbbd2f4 2602 {
mbed_official 181:a4cbdfbbd2f4 2603 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
mbed_official 181:a4cbdfbbd2f4 2604 {
mbed_official 181:a4cbdfbbd2f4 2605 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official 181:a4cbdfbbd2f4 2606 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 181:a4cbdfbbd2f4 2607 /* Input capture event */
mbed_official 181:a4cbdfbbd2f4 2608 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
mbed_official 181:a4cbdfbbd2f4 2609 {
mbed_official 181:a4cbdfbbd2f4 2610 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2611 }
mbed_official 181:a4cbdfbbd2f4 2612 /* Output compare event */
mbed_official 181:a4cbdfbbd2f4 2613 else
mbed_official 181:a4cbdfbbd2f4 2614 {
mbed_official 181:a4cbdfbbd2f4 2615 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2616 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2617 }
mbed_official 181:a4cbdfbbd2f4 2618 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 181:a4cbdfbbd2f4 2619 }
mbed_official 181:a4cbdfbbd2f4 2620 }
mbed_official 181:a4cbdfbbd2f4 2621 /* Capture compare 4 event */
mbed_official 181:a4cbdfbbd2f4 2622 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official 181:a4cbdfbbd2f4 2623 {
mbed_official 181:a4cbdfbbd2f4 2624 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
mbed_official 181:a4cbdfbbd2f4 2625 {
mbed_official 181:a4cbdfbbd2f4 2626 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official 181:a4cbdfbbd2f4 2627 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 181:a4cbdfbbd2f4 2628 /* Input capture event */
mbed_official 181:a4cbdfbbd2f4 2629 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
mbed_official 181:a4cbdfbbd2f4 2630 {
mbed_official 181:a4cbdfbbd2f4 2631 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2632 }
mbed_official 181:a4cbdfbbd2f4 2633 /* Output compare event */
mbed_official 181:a4cbdfbbd2f4 2634 else
mbed_official 181:a4cbdfbbd2f4 2635 {
mbed_official 181:a4cbdfbbd2f4 2636 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2637 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2638 }
mbed_official 181:a4cbdfbbd2f4 2639 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 181:a4cbdfbbd2f4 2640 }
mbed_official 181:a4cbdfbbd2f4 2641 }
mbed_official 181:a4cbdfbbd2f4 2642 /* TIM Update event */
mbed_official 181:a4cbdfbbd2f4 2643 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official 181:a4cbdfbbd2f4 2644 {
mbed_official 181:a4cbdfbbd2f4 2645 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
mbed_official 181:a4cbdfbbd2f4 2646 {
mbed_official 181:a4cbdfbbd2f4 2647 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official 181:a4cbdfbbd2f4 2648 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2649 }
mbed_official 181:a4cbdfbbd2f4 2650 }
mbed_official 181:a4cbdfbbd2f4 2651 /* TIM Trigger detection event */
mbed_official 181:a4cbdfbbd2f4 2652 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official 181:a4cbdfbbd2f4 2653 {
mbed_official 181:a4cbdfbbd2f4 2654 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official 181:a4cbdfbbd2f4 2655 {
mbed_official 181:a4cbdfbbd2f4 2656 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official 181:a4cbdfbbd2f4 2657 HAL_TIM_TriggerCallback(htim);
mbed_official 181:a4cbdfbbd2f4 2658 }
mbed_official 181:a4cbdfbbd2f4 2659 }
mbed_official 181:a4cbdfbbd2f4 2660 }
mbed_official 181:a4cbdfbbd2f4 2661
mbed_official 181:a4cbdfbbd2f4 2662 /**
mbed_official 181:a4cbdfbbd2f4 2663 * @}
mbed_official 181:a4cbdfbbd2f4 2664 */
mbed_official 181:a4cbdfbbd2f4 2665 /** @defgroup TIM_Group3 Peripheral Control functions
mbed_official 181:a4cbdfbbd2f4 2666 * @brief Peripheral Control functions
mbed_official 181:a4cbdfbbd2f4 2667 *
mbed_official 181:a4cbdfbbd2f4 2668 @verbatim
mbed_official 181:a4cbdfbbd2f4 2669 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 2670 ##### Peripheral Control functions #####
mbed_official 181:a4cbdfbbd2f4 2671 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 2672 [..]
mbed_official 181:a4cbdfbbd2f4 2673 This section provides functions allowing to:
mbed_official 181:a4cbdfbbd2f4 2674 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official 181:a4cbdfbbd2f4 2675 (+) Configure External Clock source.
mbed_official 181:a4cbdfbbd2f4 2676 (+) Configure Master and the Slave synchronization.
mbed_official 181:a4cbdfbbd2f4 2677 (+) Configure the DMA Burst Mode.
mbed_official 181:a4cbdfbbd2f4 2678
mbed_official 181:a4cbdfbbd2f4 2679 @endverbatim
mbed_official 181:a4cbdfbbd2f4 2680 * @{
mbed_official 181:a4cbdfbbd2f4 2681 */
mbed_official 181:a4cbdfbbd2f4 2682 /**
mbed_official 181:a4cbdfbbd2f4 2683 * @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official 181:a4cbdfbbd2f4 2684 * parameters in the TIM_OC_InitTypeDef.
mbed_official 181:a4cbdfbbd2f4 2685 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2686 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2687 * @param sConfig: TIM Output Compare configuration structure
mbed_official 181:a4cbdfbbd2f4 2688 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2689 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2690 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2691 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2692 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 2693 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 2694 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2695 */
mbed_official 181:a4cbdfbbd2f4 2696 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2697 {
mbed_official 181:a4cbdfbbd2f4 2698 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2699 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 181:a4cbdfbbd2f4 2700 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official 181:a4cbdfbbd2f4 2701 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 181:a4cbdfbbd2f4 2702 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official 181:a4cbdfbbd2f4 2703
mbed_official 181:a4cbdfbbd2f4 2704 /* Check input state */
mbed_official 181:a4cbdfbbd2f4 2705 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2706
mbed_official 181:a4cbdfbbd2f4 2707 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 2708
mbed_official 181:a4cbdfbbd2f4 2709 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2710 {
mbed_official 181:a4cbdfbbd2f4 2711 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2712 {
mbed_official 181:a4cbdfbbd2f4 2713 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2714 /* Configure the TIM Channel 1 in Output Compare */
mbed_official 181:a4cbdfbbd2f4 2715 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2716 }
mbed_official 181:a4cbdfbbd2f4 2717 break;
mbed_official 181:a4cbdfbbd2f4 2718
mbed_official 181:a4cbdfbbd2f4 2719 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2720 {
mbed_official 181:a4cbdfbbd2f4 2721 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2722 /* Configure the TIM Channel 2 in Output Compare */
mbed_official 181:a4cbdfbbd2f4 2723 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2724 }
mbed_official 181:a4cbdfbbd2f4 2725 break;
mbed_official 181:a4cbdfbbd2f4 2726
mbed_official 181:a4cbdfbbd2f4 2727 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 2728 {
mbed_official 181:a4cbdfbbd2f4 2729 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2730 /* Configure the TIM Channel 3 in Output Compare */
mbed_official 181:a4cbdfbbd2f4 2731 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2732 }
mbed_official 181:a4cbdfbbd2f4 2733 break;
mbed_official 181:a4cbdfbbd2f4 2734
mbed_official 181:a4cbdfbbd2f4 2735 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 2736 {
mbed_official 181:a4cbdfbbd2f4 2737 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2738 /* Configure the TIM Channel 4 in Output Compare */
mbed_official 181:a4cbdfbbd2f4 2739 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2740 }
mbed_official 181:a4cbdfbbd2f4 2741 break;
mbed_official 181:a4cbdfbbd2f4 2742
mbed_official 181:a4cbdfbbd2f4 2743 default:
mbed_official 181:a4cbdfbbd2f4 2744 break;
mbed_official 181:a4cbdfbbd2f4 2745 }
mbed_official 181:a4cbdfbbd2f4 2746 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 2747
mbed_official 181:a4cbdfbbd2f4 2748 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2749
mbed_official 181:a4cbdfbbd2f4 2750 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2751 }
mbed_official 181:a4cbdfbbd2f4 2752
mbed_official 181:a4cbdfbbd2f4 2753 /**
mbed_official 181:a4cbdfbbd2f4 2754 * @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official 181:a4cbdfbbd2f4 2755 * parameters in the TIM_IC_InitTypeDef.
mbed_official 181:a4cbdfbbd2f4 2756 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2757 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2758 * @param sConfig: TIM Input Capture configuration structure
mbed_official 181:a4cbdfbbd2f4 2759 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2760 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2761 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2762 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2763 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 2764 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 2765 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2766 */
mbed_official 181:a4cbdfbbd2f4 2767 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2768 {
mbed_official 181:a4cbdfbbd2f4 2769 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2770 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2771 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official 181:a4cbdfbbd2f4 2772 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official 181:a4cbdfbbd2f4 2773 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official 181:a4cbdfbbd2f4 2774 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official 181:a4cbdfbbd2f4 2775
mbed_official 181:a4cbdfbbd2f4 2776 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2777
mbed_official 181:a4cbdfbbd2f4 2778 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 2779
mbed_official 181:a4cbdfbbd2f4 2780 if (Channel == TIM_CHANNEL_1)
mbed_official 181:a4cbdfbbd2f4 2781 {
mbed_official 181:a4cbdfbbd2f4 2782 /* TI1 Configuration */
mbed_official 181:a4cbdfbbd2f4 2783 TIM_TI1_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 2784 sConfig->ICPolarity,
mbed_official 181:a4cbdfbbd2f4 2785 sConfig->ICSelection,
mbed_official 181:a4cbdfbbd2f4 2786 sConfig->ICFilter);
mbed_official 181:a4cbdfbbd2f4 2787
mbed_official 181:a4cbdfbbd2f4 2788 /* Reset the IC1PSC Bits */
mbed_official 181:a4cbdfbbd2f4 2789 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 181:a4cbdfbbd2f4 2790
mbed_official 181:a4cbdfbbd2f4 2791 /* Set the IC1PSC value */
mbed_official 181:a4cbdfbbd2f4 2792 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
mbed_official 181:a4cbdfbbd2f4 2793 }
mbed_official 181:a4cbdfbbd2f4 2794 else if (Channel == TIM_CHANNEL_2)
mbed_official 181:a4cbdfbbd2f4 2795 {
mbed_official 181:a4cbdfbbd2f4 2796 /* TI2 Configuration */
mbed_official 181:a4cbdfbbd2f4 2797 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2798
mbed_official 181:a4cbdfbbd2f4 2799 TIM_TI2_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 2800 sConfig->ICPolarity,
mbed_official 181:a4cbdfbbd2f4 2801 sConfig->ICSelection,
mbed_official 181:a4cbdfbbd2f4 2802 sConfig->ICFilter);
mbed_official 181:a4cbdfbbd2f4 2803
mbed_official 181:a4cbdfbbd2f4 2804 /* Reset the IC2PSC Bits */
mbed_official 181:a4cbdfbbd2f4 2805 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 181:a4cbdfbbd2f4 2806
mbed_official 181:a4cbdfbbd2f4 2807 /* Set the IC2PSC value */
mbed_official 181:a4cbdfbbd2f4 2808 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
mbed_official 181:a4cbdfbbd2f4 2809 }
mbed_official 181:a4cbdfbbd2f4 2810 else if (Channel == TIM_CHANNEL_3)
mbed_official 181:a4cbdfbbd2f4 2811 {
mbed_official 181:a4cbdfbbd2f4 2812 /* TI3 Configuration */
mbed_official 181:a4cbdfbbd2f4 2813 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2814
mbed_official 181:a4cbdfbbd2f4 2815 TIM_TI3_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 2816 sConfig->ICPolarity,
mbed_official 181:a4cbdfbbd2f4 2817 sConfig->ICSelection,
mbed_official 181:a4cbdfbbd2f4 2818 sConfig->ICFilter);
mbed_official 181:a4cbdfbbd2f4 2819
mbed_official 181:a4cbdfbbd2f4 2820 /* Reset the IC3PSC Bits */
mbed_official 181:a4cbdfbbd2f4 2821 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official 181:a4cbdfbbd2f4 2822
mbed_official 181:a4cbdfbbd2f4 2823 /* Set the IC3PSC value */
mbed_official 181:a4cbdfbbd2f4 2824 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
mbed_official 181:a4cbdfbbd2f4 2825 }
mbed_official 181:a4cbdfbbd2f4 2826 else
mbed_official 181:a4cbdfbbd2f4 2827 {
mbed_official 181:a4cbdfbbd2f4 2828 /* TI4 Configuration */
mbed_official 181:a4cbdfbbd2f4 2829 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2830
mbed_official 181:a4cbdfbbd2f4 2831 TIM_TI4_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 2832 sConfig->ICPolarity,
mbed_official 181:a4cbdfbbd2f4 2833 sConfig->ICSelection,
mbed_official 181:a4cbdfbbd2f4 2834 sConfig->ICFilter);
mbed_official 181:a4cbdfbbd2f4 2835
mbed_official 181:a4cbdfbbd2f4 2836 /* Reset the IC4PSC Bits */
mbed_official 181:a4cbdfbbd2f4 2837 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official 181:a4cbdfbbd2f4 2838
mbed_official 181:a4cbdfbbd2f4 2839 /* Set the IC4PSC value */
mbed_official 181:a4cbdfbbd2f4 2840 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
mbed_official 181:a4cbdfbbd2f4 2841 }
mbed_official 181:a4cbdfbbd2f4 2842
mbed_official 181:a4cbdfbbd2f4 2843 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 2844
mbed_official 181:a4cbdfbbd2f4 2845 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2846
mbed_official 181:a4cbdfbbd2f4 2847 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2848 }
mbed_official 181:a4cbdfbbd2f4 2849
mbed_official 181:a4cbdfbbd2f4 2850 /**
mbed_official 181:a4cbdfbbd2f4 2851 * @brief Initializes the TIM PWM channels according to the specified
mbed_official 181:a4cbdfbbd2f4 2852 * parameters in the TIM_OC_InitTypeDef.
mbed_official 181:a4cbdfbbd2f4 2853 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2854 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2855 * @param sConfig: TIM PWM configuration structure
mbed_official 181:a4cbdfbbd2f4 2856 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2857 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2858 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2859 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2860 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 2861 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 2862 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2863 */
mbed_official 181:a4cbdfbbd2f4 2864 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 2865 {
mbed_official 181:a4cbdfbbd2f4 2866 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2867
mbed_official 181:a4cbdfbbd2f4 2868 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2869 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 181:a4cbdfbbd2f4 2870 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official 181:a4cbdfbbd2f4 2871 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 181:a4cbdfbbd2f4 2872
mbed_official 181:a4cbdfbbd2f4 2873 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 2874
mbed_official 181:a4cbdfbbd2f4 2875 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 2876 {
mbed_official 181:a4cbdfbbd2f4 2877 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2878 {
mbed_official 181:a4cbdfbbd2f4 2879 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2880 /* Configure the Channel 1 in PWM mode */
mbed_official 181:a4cbdfbbd2f4 2881 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2882
mbed_official 181:a4cbdfbbd2f4 2883 /* Set the Preload enable bit for channel1 */
mbed_official 181:a4cbdfbbd2f4 2884 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
mbed_official 181:a4cbdfbbd2f4 2885
mbed_official 181:a4cbdfbbd2f4 2886 /* Configure the Output Fast mode */
mbed_official 181:a4cbdfbbd2f4 2887 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official 181:a4cbdfbbd2f4 2888 htim->Instance->CCMR1 |= sConfig->OCFastMode;
mbed_official 181:a4cbdfbbd2f4 2889 }
mbed_official 181:a4cbdfbbd2f4 2890 break;
mbed_official 181:a4cbdfbbd2f4 2891
mbed_official 181:a4cbdfbbd2f4 2892 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2893 {
mbed_official 181:a4cbdfbbd2f4 2894 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2895 /* Configure the Channel 2 in PWM mode */
mbed_official 181:a4cbdfbbd2f4 2896 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2897
mbed_official 181:a4cbdfbbd2f4 2898 /* Set the Preload enable bit for channel2 */
mbed_official 181:a4cbdfbbd2f4 2899 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
mbed_official 181:a4cbdfbbd2f4 2900
mbed_official 181:a4cbdfbbd2f4 2901 /* Configure the Output Fast mode */
mbed_official 181:a4cbdfbbd2f4 2902 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official 181:a4cbdfbbd2f4 2903 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
mbed_official 181:a4cbdfbbd2f4 2904 }
mbed_official 181:a4cbdfbbd2f4 2905 break;
mbed_official 181:a4cbdfbbd2f4 2906
mbed_official 181:a4cbdfbbd2f4 2907 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 2908 {
mbed_official 181:a4cbdfbbd2f4 2909 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2910 /* Configure the Channel 3 in PWM mode */
mbed_official 181:a4cbdfbbd2f4 2911 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2912
mbed_official 181:a4cbdfbbd2f4 2913 /* Set the Preload enable bit for channel3 */
mbed_official 181:a4cbdfbbd2f4 2914 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
mbed_official 181:a4cbdfbbd2f4 2915
mbed_official 181:a4cbdfbbd2f4 2916 /* Configure the Output Fast mode */
mbed_official 181:a4cbdfbbd2f4 2917 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official 181:a4cbdfbbd2f4 2918 htim->Instance->CCMR2 |= sConfig->OCFastMode;
mbed_official 181:a4cbdfbbd2f4 2919 }
mbed_official 181:a4cbdfbbd2f4 2920 break;
mbed_official 181:a4cbdfbbd2f4 2921
mbed_official 181:a4cbdfbbd2f4 2922 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 2923 {
mbed_official 181:a4cbdfbbd2f4 2924 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2925 /* Configure the Channel 4 in PWM mode */
mbed_official 181:a4cbdfbbd2f4 2926 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 181:a4cbdfbbd2f4 2927
mbed_official 181:a4cbdfbbd2f4 2928 /* Set the Preload enable bit for channel4 */
mbed_official 181:a4cbdfbbd2f4 2929 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
mbed_official 181:a4cbdfbbd2f4 2930
mbed_official 181:a4cbdfbbd2f4 2931 /* Configure the Output Fast mode */
mbed_official 181:a4cbdfbbd2f4 2932 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official 181:a4cbdfbbd2f4 2933 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
mbed_official 181:a4cbdfbbd2f4 2934 }
mbed_official 181:a4cbdfbbd2f4 2935 break;
mbed_official 181:a4cbdfbbd2f4 2936
mbed_official 181:a4cbdfbbd2f4 2937 default:
mbed_official 181:a4cbdfbbd2f4 2938 break;
mbed_official 181:a4cbdfbbd2f4 2939 }
mbed_official 181:a4cbdfbbd2f4 2940
mbed_official 181:a4cbdfbbd2f4 2941 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 2942
mbed_official 181:a4cbdfbbd2f4 2943 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2944
mbed_official 181:a4cbdfbbd2f4 2945 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 2946 }
mbed_official 181:a4cbdfbbd2f4 2947
mbed_official 181:a4cbdfbbd2f4 2948 /**
mbed_official 181:a4cbdfbbd2f4 2949 * @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official 181:a4cbdfbbd2f4 2950 * parameters in the TIM_OnePulse_InitTypeDef.
mbed_official 181:a4cbdfbbd2f4 2951 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 2952 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 2953 * @param sConfig: TIM One Pulse configuration structure
mbed_official 181:a4cbdfbbd2f4 2954 * @param OutputChannel : TIM Channels to be enabled
mbed_official 181:a4cbdfbbd2f4 2955 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2956 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2957 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2958 * @param InputChannel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 2959 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 2960 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 2961 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 2962 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 2963 */
mbed_official 181:a4cbdfbbd2f4 2964 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official 181:a4cbdfbbd2f4 2965 {
mbed_official 181:a4cbdfbbd2f4 2966 TIM_OC_InitTypeDef temp1;
mbed_official 181:a4cbdfbbd2f4 2967
mbed_official 181:a4cbdfbbd2f4 2968 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 2969 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official 181:a4cbdfbbd2f4 2970 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official 181:a4cbdfbbd2f4 2971
mbed_official 181:a4cbdfbbd2f4 2972 if(OutputChannel != InputChannel)
mbed_official 181:a4cbdfbbd2f4 2973 {
mbed_official 181:a4cbdfbbd2f4 2974 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 2975
mbed_official 181:a4cbdfbbd2f4 2976 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 2977
mbed_official 181:a4cbdfbbd2f4 2978 /* Extract the Ouput compare configuration from sConfig structure */
mbed_official 181:a4cbdfbbd2f4 2979 temp1.OCMode = sConfig->OCMode;
mbed_official 181:a4cbdfbbd2f4 2980 temp1.Pulse = sConfig->Pulse;
mbed_official 181:a4cbdfbbd2f4 2981 temp1.OCPolarity = sConfig->OCPolarity;
mbed_official 181:a4cbdfbbd2f4 2982
mbed_official 181:a4cbdfbbd2f4 2983 switch (OutputChannel)
mbed_official 181:a4cbdfbbd2f4 2984 {
mbed_official 181:a4cbdfbbd2f4 2985 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 2986 {
mbed_official 181:a4cbdfbbd2f4 2987 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2988
mbed_official 181:a4cbdfbbd2f4 2989 TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official 181:a4cbdfbbd2f4 2990 }
mbed_official 181:a4cbdfbbd2f4 2991 break;
mbed_official 181:a4cbdfbbd2f4 2992 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 2993 {
mbed_official 181:a4cbdfbbd2f4 2994 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 2995
mbed_official 181:a4cbdfbbd2f4 2996 TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official 181:a4cbdfbbd2f4 2997 }
mbed_official 181:a4cbdfbbd2f4 2998 break;
mbed_official 181:a4cbdfbbd2f4 2999 default:
mbed_official 181:a4cbdfbbd2f4 3000 break;
mbed_official 181:a4cbdfbbd2f4 3001 }
mbed_official 181:a4cbdfbbd2f4 3002 switch (InputChannel)
mbed_official 181:a4cbdfbbd2f4 3003 {
mbed_official 181:a4cbdfbbd2f4 3004 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 3005 {
mbed_official 181:a4cbdfbbd2f4 3006 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3007
mbed_official 181:a4cbdfbbd2f4 3008 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 181:a4cbdfbbd2f4 3009 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 181:a4cbdfbbd2f4 3010
mbed_official 181:a4cbdfbbd2f4 3011 /* Reset the IC1PSC Bits */
mbed_official 181:a4cbdfbbd2f4 3012 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 181:a4cbdfbbd2f4 3013
mbed_official 181:a4cbdfbbd2f4 3014 /* Select the Trigger source */
mbed_official 181:a4cbdfbbd2f4 3015 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 181:a4cbdfbbd2f4 3016 htim->Instance->SMCR |= TIM_TS_TI1FP1;
mbed_official 181:a4cbdfbbd2f4 3017
mbed_official 181:a4cbdfbbd2f4 3018 /* Select the Slave Mode */
mbed_official 181:a4cbdfbbd2f4 3019 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 181:a4cbdfbbd2f4 3020 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 181:a4cbdfbbd2f4 3021 }
mbed_official 181:a4cbdfbbd2f4 3022 break;
mbed_official 181:a4cbdfbbd2f4 3023 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 3024 {
mbed_official 181:a4cbdfbbd2f4 3025 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3026
mbed_official 181:a4cbdfbbd2f4 3027 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 181:a4cbdfbbd2f4 3028 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 181:a4cbdfbbd2f4 3029
mbed_official 181:a4cbdfbbd2f4 3030 /* Reset the IC2PSC Bits */
mbed_official 181:a4cbdfbbd2f4 3031 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 181:a4cbdfbbd2f4 3032
mbed_official 181:a4cbdfbbd2f4 3033 /* Select the Trigger source */
mbed_official 181:a4cbdfbbd2f4 3034 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 181:a4cbdfbbd2f4 3035 htim->Instance->SMCR |= TIM_TS_TI2FP2;
mbed_official 181:a4cbdfbbd2f4 3036
mbed_official 181:a4cbdfbbd2f4 3037 /* Select the Slave Mode */
mbed_official 181:a4cbdfbbd2f4 3038 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 181:a4cbdfbbd2f4 3039 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 181:a4cbdfbbd2f4 3040 }
mbed_official 181:a4cbdfbbd2f4 3041 break;
mbed_official 181:a4cbdfbbd2f4 3042
mbed_official 181:a4cbdfbbd2f4 3043 default:
mbed_official 181:a4cbdfbbd2f4 3044 break;
mbed_official 181:a4cbdfbbd2f4 3045 }
mbed_official 181:a4cbdfbbd2f4 3046
mbed_official 181:a4cbdfbbd2f4 3047 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3048
mbed_official 181:a4cbdfbbd2f4 3049 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3050
mbed_official 181:a4cbdfbbd2f4 3051 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3052 }
mbed_official 181:a4cbdfbbd2f4 3053 else
mbed_official 181:a4cbdfbbd2f4 3054 {
mbed_official 181:a4cbdfbbd2f4 3055 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 3056 }
mbed_official 181:a4cbdfbbd2f4 3057 }
mbed_official 181:a4cbdfbbd2f4 3058
mbed_official 181:a4cbdfbbd2f4 3059 /**
mbed_official 181:a4cbdfbbd2f4 3060 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 3061 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3062 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3063 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
mbed_official 181:a4cbdfbbd2f4 3064 * This parameters can be on of the following values:
mbed_official 181:a4cbdfbbd2f4 3065 * @arg TIM_DMABase_CR1
mbed_official 181:a4cbdfbbd2f4 3066 * @arg TIM_DMABase_CR2
mbed_official 181:a4cbdfbbd2f4 3067 * @arg TIM_DMABase_SMCR
mbed_official 181:a4cbdfbbd2f4 3068 * @arg TIM_DMABase_DIER
mbed_official 181:a4cbdfbbd2f4 3069 * @arg TIM_DMABase_SR
mbed_official 181:a4cbdfbbd2f4 3070 * @arg TIM_DMABase_EGR
mbed_official 181:a4cbdfbbd2f4 3071 * @arg TIM_DMABase_CCMR1
mbed_official 181:a4cbdfbbd2f4 3072 * @arg TIM_DMABase_CCMR2
mbed_official 181:a4cbdfbbd2f4 3073 * @arg TIM_DMABase_CCER
mbed_official 181:a4cbdfbbd2f4 3074 * @arg TIM_DMABase_CNT
mbed_official 181:a4cbdfbbd2f4 3075 * @arg TIM_DMABase_PSC
mbed_official 181:a4cbdfbbd2f4 3076 * @arg TIM_DMABase_ARR
mbed_official 181:a4cbdfbbd2f4 3077 * @arg TIM_DMABase_CCR1
mbed_official 181:a4cbdfbbd2f4 3078 * @arg TIM_DMABase_CCR2
mbed_official 181:a4cbdfbbd2f4 3079 * @arg TIM_DMABase_CCR3
mbed_official 181:a4cbdfbbd2f4 3080 * @arg TIM_DMABase_CCR4
mbed_official 181:a4cbdfbbd2f4 3081 * @arg TIM_DMABase_DCR
mbed_official 181:a4cbdfbbd2f4 3082 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 181:a4cbdfbbd2f4 3083 * This parameters can be on of the following values:
mbed_official 181:a4cbdfbbd2f4 3084 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 181:a4cbdfbbd2f4 3085 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 181:a4cbdfbbd2f4 3086 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 181:a4cbdfbbd2f4 3087 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 181:a4cbdfbbd2f4 3088 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 181:a4cbdfbbd2f4 3089 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 181:a4cbdfbbd2f4 3090 * @param BurstBuffer: The Buffer address.
mbed_official 181:a4cbdfbbd2f4 3091 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 181:a4cbdfbbd2f4 3092 * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official 181:a4cbdfbbd2f4 3093 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3094 */
mbed_official 181:a4cbdfbbd2f4 3095 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 181:a4cbdfbbd2f4 3096 uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official 181:a4cbdfbbd2f4 3097 {
mbed_official 181:a4cbdfbbd2f4 3098 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3099 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3100 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 181:a4cbdfbbd2f4 3101 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 181:a4cbdfbbd2f4 3102 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 181:a4cbdfbbd2f4 3103
mbed_official 181:a4cbdfbbd2f4 3104 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 3105 {
mbed_official 181:a4cbdfbbd2f4 3106 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 3107 }
mbed_official 181:a4cbdfbbd2f4 3108 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 3109 {
mbed_official 181:a4cbdfbbd2f4 3110 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 181:a4cbdfbbd2f4 3111 {
mbed_official 181:a4cbdfbbd2f4 3112 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 3113 }
mbed_official 181:a4cbdfbbd2f4 3114 else
mbed_official 181:a4cbdfbbd2f4 3115 {
mbed_official 181:a4cbdfbbd2f4 3116 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 3117 }
mbed_official 181:a4cbdfbbd2f4 3118 }
mbed_official 181:a4cbdfbbd2f4 3119 switch(BurstRequestSrc)
mbed_official 181:a4cbdfbbd2f4 3120 {
mbed_official 181:a4cbdfbbd2f4 3121 case TIM_DMA_UPDATE:
mbed_official 181:a4cbdfbbd2f4 3122 {
mbed_official 181:a4cbdfbbd2f4 3123 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3124 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 181:a4cbdfbbd2f4 3125
mbed_official 181:a4cbdfbbd2f4 3126 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3127 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3128
mbed_official 181:a4cbdfbbd2f4 3129 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3130 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3131 }
mbed_official 181:a4cbdfbbd2f4 3132 break;
mbed_official 181:a4cbdfbbd2f4 3133 case TIM_DMA_CC1:
mbed_official 181:a4cbdfbbd2f4 3134 {
mbed_official 181:a4cbdfbbd2f4 3135 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3136 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 3137
mbed_official 181:a4cbdfbbd2f4 3138 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3139 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3140
mbed_official 181:a4cbdfbbd2f4 3141 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3142 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3143 }
mbed_official 181:a4cbdfbbd2f4 3144 break;
mbed_official 181:a4cbdfbbd2f4 3145 case TIM_DMA_CC2:
mbed_official 181:a4cbdfbbd2f4 3146 {
mbed_official 181:a4cbdfbbd2f4 3147 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3148 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 3149
mbed_official 181:a4cbdfbbd2f4 3150 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3151 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3152
mbed_official 181:a4cbdfbbd2f4 3153 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3154 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3155 }
mbed_official 181:a4cbdfbbd2f4 3156 break;
mbed_official 181:a4cbdfbbd2f4 3157 case TIM_DMA_CC3:
mbed_official 181:a4cbdfbbd2f4 3158 {
mbed_official 181:a4cbdfbbd2f4 3159 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3160 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 3161
mbed_official 181:a4cbdfbbd2f4 3162 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3163 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3164
mbed_official 181:a4cbdfbbd2f4 3165 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3166 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3167 }
mbed_official 181:a4cbdfbbd2f4 3168 break;
mbed_official 181:a4cbdfbbd2f4 3169 case TIM_DMA_CC4:
mbed_official 181:a4cbdfbbd2f4 3170 {
mbed_official 181:a4cbdfbbd2f4 3171 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3172 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 181:a4cbdfbbd2f4 3173
mbed_official 181:a4cbdfbbd2f4 3174 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3175 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3176
mbed_official 181:a4cbdfbbd2f4 3177 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3178 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3179 }
mbed_official 181:a4cbdfbbd2f4 3180 break;
mbed_official 181:a4cbdfbbd2f4 3181 case TIM_DMA_TRIGGER:
mbed_official 181:a4cbdfbbd2f4 3182 {
mbed_official 181:a4cbdfbbd2f4 3183 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3184 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 181:a4cbdfbbd2f4 3185
mbed_official 181:a4cbdfbbd2f4 3186 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3187 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3188
mbed_official 181:a4cbdfbbd2f4 3189 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3190 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3191 }
mbed_official 181:a4cbdfbbd2f4 3192 break;
mbed_official 181:a4cbdfbbd2f4 3193 default:
mbed_official 181:a4cbdfbbd2f4 3194 break;
mbed_official 181:a4cbdfbbd2f4 3195 }
mbed_official 181:a4cbdfbbd2f4 3196 /* configure the DMA Burst Mode */
mbed_official 181:a4cbdfbbd2f4 3197 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 181:a4cbdfbbd2f4 3198
mbed_official 181:a4cbdfbbd2f4 3199 /* Enable the TIM DMA Request */
mbed_official 181:a4cbdfbbd2f4 3200 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 181:a4cbdfbbd2f4 3201
mbed_official 181:a4cbdfbbd2f4 3202 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3203
mbed_official 181:a4cbdfbbd2f4 3204 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 3205 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3206 }
mbed_official 181:a4cbdfbbd2f4 3207
mbed_official 181:a4cbdfbbd2f4 3208 /**
mbed_official 181:a4cbdfbbd2f4 3209 * @brief Stops the TIM DMA Burst mode
mbed_official 181:a4cbdfbbd2f4 3210 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3211 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3212 * @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official 181:a4cbdfbbd2f4 3213 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3214 */
mbed_official 181:a4cbdfbbd2f4 3215 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 181:a4cbdfbbd2f4 3216 {
mbed_official 181:a4cbdfbbd2f4 3217 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3218 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 181:a4cbdfbbd2f4 3219
mbed_official 181:a4cbdfbbd2f4 3220 /* Disable the TIM Update DMA request */
mbed_official 181:a4cbdfbbd2f4 3221 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 181:a4cbdfbbd2f4 3222
mbed_official 181:a4cbdfbbd2f4 3223 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 3224 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3225 }
mbed_official 181:a4cbdfbbd2f4 3226
mbed_official 181:a4cbdfbbd2f4 3227 /**
mbed_official 181:a4cbdfbbd2f4 3228 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official 181:a4cbdfbbd2f4 3229 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3230 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3231 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
mbed_official 181:a4cbdfbbd2f4 3232 * This parameters can be on of the following values:
mbed_official 181:a4cbdfbbd2f4 3233 * @arg TIM_DMABase_CR1
mbed_official 181:a4cbdfbbd2f4 3234 * @arg TIM_DMABase_CR2
mbed_official 181:a4cbdfbbd2f4 3235 * @arg TIM_DMABase_SMCR
mbed_official 181:a4cbdfbbd2f4 3236 * @arg TIM_DMABase_DIER
mbed_official 181:a4cbdfbbd2f4 3237 * @arg TIM_DMABase_SR
mbed_official 181:a4cbdfbbd2f4 3238 * @arg TIM_DMABase_EGR
mbed_official 181:a4cbdfbbd2f4 3239 * @arg TIM_DMABase_CCMR1
mbed_official 181:a4cbdfbbd2f4 3240 * @arg TIM_DMABase_CCMR2
mbed_official 181:a4cbdfbbd2f4 3241 * @arg TIM_DMABase_CCER
mbed_official 181:a4cbdfbbd2f4 3242 * @arg TIM_DMABase_CNT
mbed_official 181:a4cbdfbbd2f4 3243 * @arg TIM_DMABase_PSC
mbed_official 181:a4cbdfbbd2f4 3244 * @arg TIM_DMABase_ARR
mbed_official 181:a4cbdfbbd2f4 3245 * @arg TIM_DMABase_CCR1
mbed_official 181:a4cbdfbbd2f4 3246 * @arg TIM_DMABase_CCR2
mbed_official 181:a4cbdfbbd2f4 3247 * @arg TIM_DMABase_CCR3
mbed_official 181:a4cbdfbbd2f4 3248 * @arg TIM_DMABase_CCR4
mbed_official 181:a4cbdfbbd2f4 3249 * @arg TIM_DMABase_DCR
mbed_official 181:a4cbdfbbd2f4 3250 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 181:a4cbdfbbd2f4 3251 * This parameters can be on of the following values:
mbed_official 181:a4cbdfbbd2f4 3252 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 181:a4cbdfbbd2f4 3253 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 181:a4cbdfbbd2f4 3254 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 181:a4cbdfbbd2f4 3255 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 181:a4cbdfbbd2f4 3256 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 181:a4cbdfbbd2f4 3257 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 181:a4cbdfbbd2f4 3258 * @param BurstBuffer: The Buffer address.
mbed_official 181:a4cbdfbbd2f4 3259 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 181:a4cbdfbbd2f4 3260 * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official 181:a4cbdfbbd2f4 3261 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3262 */
mbed_official 181:a4cbdfbbd2f4 3263 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 181:a4cbdfbbd2f4 3264 uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official 181:a4cbdfbbd2f4 3265 {
mbed_official 181:a4cbdfbbd2f4 3266 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3267 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3268 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 181:a4cbdfbbd2f4 3269 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 181:a4cbdfbbd2f4 3270 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 181:a4cbdfbbd2f4 3271
mbed_official 181:a4cbdfbbd2f4 3272 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 181:a4cbdfbbd2f4 3273 {
mbed_official 181:a4cbdfbbd2f4 3274 return HAL_BUSY;
mbed_official 181:a4cbdfbbd2f4 3275 }
mbed_official 181:a4cbdfbbd2f4 3276 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 181:a4cbdfbbd2f4 3277 {
mbed_official 181:a4cbdfbbd2f4 3278 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 181:a4cbdfbbd2f4 3279 {
mbed_official 181:a4cbdfbbd2f4 3280 return HAL_ERROR;
mbed_official 181:a4cbdfbbd2f4 3281 }
mbed_official 181:a4cbdfbbd2f4 3282 else
mbed_official 181:a4cbdfbbd2f4 3283 {
mbed_official 181:a4cbdfbbd2f4 3284 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 3285 }
mbed_official 181:a4cbdfbbd2f4 3286 }
mbed_official 181:a4cbdfbbd2f4 3287 switch(BurstRequestSrc)
mbed_official 181:a4cbdfbbd2f4 3288 {
mbed_official 181:a4cbdfbbd2f4 3289 case TIM_DMA_UPDATE:
mbed_official 181:a4cbdfbbd2f4 3290 {
mbed_official 181:a4cbdfbbd2f4 3291 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3292 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 181:a4cbdfbbd2f4 3293
mbed_official 181:a4cbdfbbd2f4 3294 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3295 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3296
mbed_official 181:a4cbdfbbd2f4 3297 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3298 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3299 }
mbed_official 181:a4cbdfbbd2f4 3300 break;
mbed_official 181:a4cbdfbbd2f4 3301 case TIM_DMA_CC1:
mbed_official 181:a4cbdfbbd2f4 3302 {
mbed_official 181:a4cbdfbbd2f4 3303 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3304 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 3305
mbed_official 181:a4cbdfbbd2f4 3306 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3307 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3308
mbed_official 181:a4cbdfbbd2f4 3309 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3310 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3311 }
mbed_official 181:a4cbdfbbd2f4 3312 break;
mbed_official 181:a4cbdfbbd2f4 3313 case TIM_DMA_CC2:
mbed_official 181:a4cbdfbbd2f4 3314 {
mbed_official 181:a4cbdfbbd2f4 3315 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3316 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 3317
mbed_official 181:a4cbdfbbd2f4 3318 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3319 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3320
mbed_official 181:a4cbdfbbd2f4 3321 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3322 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3323 }
mbed_official 181:a4cbdfbbd2f4 3324 break;
mbed_official 181:a4cbdfbbd2f4 3325 case TIM_DMA_CC3:
mbed_official 181:a4cbdfbbd2f4 3326 {
mbed_official 181:a4cbdfbbd2f4 3327 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3328 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 3329
mbed_official 181:a4cbdfbbd2f4 3330 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3331 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3332
mbed_official 181:a4cbdfbbd2f4 3333 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3334 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3335 }
mbed_official 181:a4cbdfbbd2f4 3336 break;
mbed_official 181:a4cbdfbbd2f4 3337 case TIM_DMA_CC4:
mbed_official 181:a4cbdfbbd2f4 3338 {
mbed_official 181:a4cbdfbbd2f4 3339 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3340 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 181:a4cbdfbbd2f4 3341
mbed_official 181:a4cbdfbbd2f4 3342 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3343 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3344
mbed_official 181:a4cbdfbbd2f4 3345 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3346 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3347 }
mbed_official 181:a4cbdfbbd2f4 3348 break;
mbed_official 181:a4cbdfbbd2f4 3349 case TIM_DMA_TRIGGER:
mbed_official 181:a4cbdfbbd2f4 3350 {
mbed_official 181:a4cbdfbbd2f4 3351 /* Set the DMA Period elapsed callback */
mbed_official 181:a4cbdfbbd2f4 3352 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 181:a4cbdfbbd2f4 3353
mbed_official 181:a4cbdfbbd2f4 3354 /* Set the DMA error callback */
mbed_official 181:a4cbdfbbd2f4 3355 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 181:a4cbdfbbd2f4 3356
mbed_official 181:a4cbdfbbd2f4 3357 /* Enable the DMA Stream */
mbed_official 181:a4cbdfbbd2f4 3358 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 181:a4cbdfbbd2f4 3359 }
mbed_official 181:a4cbdfbbd2f4 3360 break;
mbed_official 181:a4cbdfbbd2f4 3361 default:
mbed_official 181:a4cbdfbbd2f4 3362 break;
mbed_official 181:a4cbdfbbd2f4 3363 }
mbed_official 181:a4cbdfbbd2f4 3364
mbed_official 181:a4cbdfbbd2f4 3365 /* configure the DMA Burst Mode */
mbed_official 181:a4cbdfbbd2f4 3366 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 181:a4cbdfbbd2f4 3367
mbed_official 181:a4cbdfbbd2f4 3368 /* Enable the TIM DMA Request */
mbed_official 181:a4cbdfbbd2f4 3369 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 181:a4cbdfbbd2f4 3370
mbed_official 181:a4cbdfbbd2f4 3371 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3372
mbed_official 181:a4cbdfbbd2f4 3373 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 3374 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3375 }
mbed_official 181:a4cbdfbbd2f4 3376
mbed_official 181:a4cbdfbbd2f4 3377 /**
mbed_official 181:a4cbdfbbd2f4 3378 * @brief Stop the DMA burst reading
mbed_official 181:a4cbdfbbd2f4 3379 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3380 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3381 * @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official 181:a4cbdfbbd2f4 3382 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3383 */
mbed_official 181:a4cbdfbbd2f4 3384 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 181:a4cbdfbbd2f4 3385 {
mbed_official 181:a4cbdfbbd2f4 3386 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3387 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 181:a4cbdfbbd2f4 3388
mbed_official 181:a4cbdfbbd2f4 3389 /* Disable the TIM Update DMA request */
mbed_official 181:a4cbdfbbd2f4 3390 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 181:a4cbdfbbd2f4 3391
mbed_official 181:a4cbdfbbd2f4 3392 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 3393 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3394 }
mbed_official 181:a4cbdfbbd2f4 3395
mbed_official 181:a4cbdfbbd2f4 3396 /**
mbed_official 181:a4cbdfbbd2f4 3397 * @brief Generate a software event
mbed_official 181:a4cbdfbbd2f4 3398 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3399 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3400 * @param EventSource: specifies the event source.
mbed_official 181:a4cbdfbbd2f4 3401 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 3402 * @arg TIM_EventSource_Update: Timer update Event source
mbed_official 181:a4cbdfbbd2f4 3403 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official 181:a4cbdfbbd2f4 3404 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official 181:a4cbdfbbd2f4 3405 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official 181:a4cbdfbbd2f4 3406 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official 181:a4cbdfbbd2f4 3407 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official 181:a4cbdfbbd2f4 3408 * @note TIM6 can only generate an update event.
mbed_official 181:a4cbdfbbd2f4 3409 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3410 */
mbed_official 181:a4cbdfbbd2f4 3411
mbed_official 181:a4cbdfbbd2f4 3412 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official 181:a4cbdfbbd2f4 3413 {
mbed_official 181:a4cbdfbbd2f4 3414 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3415 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3416 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official 181:a4cbdfbbd2f4 3417
mbed_official 181:a4cbdfbbd2f4 3418 /* Process Locked */
mbed_official 181:a4cbdfbbd2f4 3419 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3420
mbed_official 181:a4cbdfbbd2f4 3421 /* Change the TIM state */
mbed_official 181:a4cbdfbbd2f4 3422 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 3423
mbed_official 181:a4cbdfbbd2f4 3424 /* Set the event sources */
mbed_official 181:a4cbdfbbd2f4 3425 htim->Instance->EGR = EventSource;
mbed_official 181:a4cbdfbbd2f4 3426
mbed_official 181:a4cbdfbbd2f4 3427 /* Change the TIM state */
mbed_official 181:a4cbdfbbd2f4 3428 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3429
mbed_official 181:a4cbdfbbd2f4 3430 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3431
mbed_official 181:a4cbdfbbd2f4 3432 /* Return function status */
mbed_official 181:a4cbdfbbd2f4 3433 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3434 }
mbed_official 181:a4cbdfbbd2f4 3435
mbed_official 181:a4cbdfbbd2f4 3436 /**
mbed_official 181:a4cbdfbbd2f4 3437 * @brief Configures the OCRef clear feature
mbed_official 181:a4cbdfbbd2f4 3438 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3439 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3440 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official 181:a4cbdfbbd2f4 3441 * contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official 181:a4cbdfbbd2f4 3442 * @param Channel: specifies the TIM Channel.
mbed_official 181:a4cbdfbbd2f4 3443 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 3444 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 3445 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 3446 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 3447 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 3448 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3449 */
mbed_official 181:a4cbdfbbd2f4 3450 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 3451 {
mbed_official 181:a4cbdfbbd2f4 3452 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3453 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3454 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 181:a4cbdfbbd2f4 3455 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official 181:a4cbdfbbd2f4 3456 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official 181:a4cbdfbbd2f4 3457 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official 181:a4cbdfbbd2f4 3458 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official 181:a4cbdfbbd2f4 3459
mbed_official 181:a4cbdfbbd2f4 3460 /* Process Locked */
mbed_official 181:a4cbdfbbd2f4 3461 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3462
mbed_official 181:a4cbdfbbd2f4 3463 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 3464
mbed_official 181:a4cbdfbbd2f4 3465 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
mbed_official 181:a4cbdfbbd2f4 3466 {
mbed_official 181:a4cbdfbbd2f4 3467 TIM_ETR_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3468 sClearInputConfig->ClearInputPrescaler,
mbed_official 181:a4cbdfbbd2f4 3469 sClearInputConfig->ClearInputPolarity,
mbed_official 181:a4cbdfbbd2f4 3470 sClearInputConfig->ClearInputFilter);
mbed_official 181:a4cbdfbbd2f4 3471 }
mbed_official 181:a4cbdfbbd2f4 3472
mbed_official 181:a4cbdfbbd2f4 3473 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 3474 {
mbed_official 181:a4cbdfbbd2f4 3475 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 3476 {
mbed_official 181:a4cbdfbbd2f4 3477 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 181:a4cbdfbbd2f4 3478 {
mbed_official 181:a4cbdfbbd2f4 3479 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 181:a4cbdfbbd2f4 3480 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
mbed_official 181:a4cbdfbbd2f4 3481 }
mbed_official 181:a4cbdfbbd2f4 3482 else
mbed_official 181:a4cbdfbbd2f4 3483 {
mbed_official 181:a4cbdfbbd2f4 3484 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 181:a4cbdfbbd2f4 3485 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official 181:a4cbdfbbd2f4 3486 }
mbed_official 181:a4cbdfbbd2f4 3487 }
mbed_official 181:a4cbdfbbd2f4 3488 break;
mbed_official 181:a4cbdfbbd2f4 3489 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 3490 {
mbed_official 181:a4cbdfbbd2f4 3491 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3492 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 181:a4cbdfbbd2f4 3493 {
mbed_official 181:a4cbdfbbd2f4 3494 /* Enable the Ocref clear feature for Channel 2 */
mbed_official 181:a4cbdfbbd2f4 3495 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
mbed_official 181:a4cbdfbbd2f4 3496 }
mbed_official 181:a4cbdfbbd2f4 3497 else
mbed_official 181:a4cbdfbbd2f4 3498 {
mbed_official 181:a4cbdfbbd2f4 3499 /* Disable the Ocref clear feature for Channel 2 */
mbed_official 181:a4cbdfbbd2f4 3500 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official 181:a4cbdfbbd2f4 3501 }
mbed_official 181:a4cbdfbbd2f4 3502 }
mbed_official 181:a4cbdfbbd2f4 3503 break;
mbed_official 181:a4cbdfbbd2f4 3504 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 3505 {
mbed_official 181:a4cbdfbbd2f4 3506 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3507 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 181:a4cbdfbbd2f4 3508 {
mbed_official 181:a4cbdfbbd2f4 3509 /* Enable the Ocref clear feature for Channel 3 */
mbed_official 181:a4cbdfbbd2f4 3510 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
mbed_official 181:a4cbdfbbd2f4 3511 }
mbed_official 181:a4cbdfbbd2f4 3512 else
mbed_official 181:a4cbdfbbd2f4 3513 {
mbed_official 181:a4cbdfbbd2f4 3514 /* Disable the Ocref clear feature for Channel 3 */
mbed_official 181:a4cbdfbbd2f4 3515 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official 181:a4cbdfbbd2f4 3516 }
mbed_official 181:a4cbdfbbd2f4 3517 }
mbed_official 181:a4cbdfbbd2f4 3518 break;
mbed_official 181:a4cbdfbbd2f4 3519 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 3520 {
mbed_official 181:a4cbdfbbd2f4 3521 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3522 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 181:a4cbdfbbd2f4 3523 {
mbed_official 181:a4cbdfbbd2f4 3524 /* Enable the Ocref clear feature for Channel 4 */
mbed_official 181:a4cbdfbbd2f4 3525 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
mbed_official 181:a4cbdfbbd2f4 3526 }
mbed_official 181:a4cbdfbbd2f4 3527 else
mbed_official 181:a4cbdfbbd2f4 3528 {
mbed_official 181:a4cbdfbbd2f4 3529 /* Disable the Ocref clear feature for Channel 4 */
mbed_official 181:a4cbdfbbd2f4 3530 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official 181:a4cbdfbbd2f4 3531 }
mbed_official 181:a4cbdfbbd2f4 3532 }
mbed_official 181:a4cbdfbbd2f4 3533 break;
mbed_official 181:a4cbdfbbd2f4 3534 default:
mbed_official 181:a4cbdfbbd2f4 3535 break;
mbed_official 181:a4cbdfbbd2f4 3536 }
mbed_official 181:a4cbdfbbd2f4 3537
mbed_official 181:a4cbdfbbd2f4 3538 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3539
mbed_official 181:a4cbdfbbd2f4 3540 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3541
mbed_official 181:a4cbdfbbd2f4 3542 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3543 }
mbed_official 181:a4cbdfbbd2f4 3544
mbed_official 181:a4cbdfbbd2f4 3545 /**
mbed_official 181:a4cbdfbbd2f4 3546 * @brief Configures the clock source to be used
mbed_official 181:a4cbdfbbd2f4 3547 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3548 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3549 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official 181:a4cbdfbbd2f4 3550 * contains the clock source information for the TIM peripheral.
mbed_official 181:a4cbdfbbd2f4 3551 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3552 */
mbed_official 181:a4cbdfbbd2f4 3553 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
mbed_official 181:a4cbdfbbd2f4 3554 {
mbed_official 181:a4cbdfbbd2f4 3555 uint32_t tmpsmcr = 0;
mbed_official 181:a4cbdfbbd2f4 3556
mbed_official 181:a4cbdfbbd2f4 3557 /* Process Locked */
mbed_official 181:a4cbdfbbd2f4 3558 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3559
mbed_official 181:a4cbdfbbd2f4 3560 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 3561
mbed_official 181:a4cbdfbbd2f4 3562 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3563 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official 181:a4cbdfbbd2f4 3564 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official 181:a4cbdfbbd2f4 3565 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official 181:a4cbdfbbd2f4 3566 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official 181:a4cbdfbbd2f4 3567
mbed_official 181:a4cbdfbbd2f4 3568 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official 181:a4cbdfbbd2f4 3569 tmpsmcr = htim->Instance->SMCR;
mbed_official 181:a4cbdfbbd2f4 3570 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 181:a4cbdfbbd2f4 3571 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 181:a4cbdfbbd2f4 3572 htim->Instance->SMCR = tmpsmcr;
mbed_official 181:a4cbdfbbd2f4 3573
mbed_official 181:a4cbdfbbd2f4 3574 switch (sClockSourceConfig->ClockSource)
mbed_official 181:a4cbdfbbd2f4 3575 {
mbed_official 181:a4cbdfbbd2f4 3576 case TIM_CLOCKSOURCE_INTERNAL:
mbed_official 181:a4cbdfbbd2f4 3577 {
mbed_official 181:a4cbdfbbd2f4 3578 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3579 /* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official 181:a4cbdfbbd2f4 3580 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 181:a4cbdfbbd2f4 3581 }
mbed_official 181:a4cbdfbbd2f4 3582 break;
mbed_official 181:a4cbdfbbd2f4 3583
mbed_official 181:a4cbdfbbd2f4 3584 case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official 181:a4cbdfbbd2f4 3585 {
mbed_official 181:a4cbdfbbd2f4 3586 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3587 /* Configure the ETR Clock source */
mbed_official 181:a4cbdfbbd2f4 3588 TIM_ETR_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3589 sClockSourceConfig->ClockPrescaler,
mbed_official 181:a4cbdfbbd2f4 3590 sClockSourceConfig->ClockPolarity,
mbed_official 181:a4cbdfbbd2f4 3591 sClockSourceConfig->ClockFilter);
mbed_official 181:a4cbdfbbd2f4 3592 /* Get the TIMx SMCR register value */
mbed_official 181:a4cbdfbbd2f4 3593 tmpsmcr = htim->Instance->SMCR;
mbed_official 181:a4cbdfbbd2f4 3594 /* Reset the SMS and TS Bits */
mbed_official 181:a4cbdfbbd2f4 3595 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 181:a4cbdfbbd2f4 3596 /* Select the External clock mode1 and the ETRF trigger */
mbed_official 181:a4cbdfbbd2f4 3597 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
mbed_official 181:a4cbdfbbd2f4 3598 /* Write to TIMx SMCR */
mbed_official 181:a4cbdfbbd2f4 3599 htim->Instance->SMCR = tmpsmcr;
mbed_official 181:a4cbdfbbd2f4 3600 }
mbed_official 181:a4cbdfbbd2f4 3601 break;
mbed_official 181:a4cbdfbbd2f4 3602
mbed_official 181:a4cbdfbbd2f4 3603 case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official 181:a4cbdfbbd2f4 3604 {
mbed_official 181:a4cbdfbbd2f4 3605 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3606 /* Configure the ETR Clock source */
mbed_official 181:a4cbdfbbd2f4 3607 TIM_ETR_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3608 sClockSourceConfig->ClockPrescaler,
mbed_official 181:a4cbdfbbd2f4 3609 sClockSourceConfig->ClockPolarity,
mbed_official 181:a4cbdfbbd2f4 3610 sClockSourceConfig->ClockFilter);
mbed_official 181:a4cbdfbbd2f4 3611 /* Enable the External clock mode2 */
mbed_official 181:a4cbdfbbd2f4 3612 htim->Instance->SMCR |= TIM_SMCR_ECE;
mbed_official 181:a4cbdfbbd2f4 3613 }
mbed_official 181:a4cbdfbbd2f4 3614 break;
mbed_official 181:a4cbdfbbd2f4 3615
mbed_official 181:a4cbdfbbd2f4 3616 case TIM_CLOCKSOURCE_TI1:
mbed_official 181:a4cbdfbbd2f4 3617 {
mbed_official 181:a4cbdfbbd2f4 3618 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3619 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3620 sClockSourceConfig->ClockPolarity,
mbed_official 181:a4cbdfbbd2f4 3621 sClockSourceConfig->ClockFilter);
mbed_official 181:a4cbdfbbd2f4 3622 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official 181:a4cbdfbbd2f4 3623 }
mbed_official 181:a4cbdfbbd2f4 3624 break;
mbed_official 181:a4cbdfbbd2f4 3625 case TIM_CLOCKSOURCE_TI2:
mbed_official 181:a4cbdfbbd2f4 3626 {
mbed_official 181:a4cbdfbbd2f4 3627 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3628 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3629 sClockSourceConfig->ClockPolarity,
mbed_official 181:a4cbdfbbd2f4 3630 sClockSourceConfig->ClockFilter);
mbed_official 181:a4cbdfbbd2f4 3631 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official 181:a4cbdfbbd2f4 3632 }
mbed_official 181:a4cbdfbbd2f4 3633 break;
mbed_official 181:a4cbdfbbd2f4 3634 case TIM_CLOCKSOURCE_TI1ED:
mbed_official 181:a4cbdfbbd2f4 3635 {
mbed_official 181:a4cbdfbbd2f4 3636 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3637 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3638 sClockSourceConfig->ClockPolarity,
mbed_official 181:a4cbdfbbd2f4 3639 sClockSourceConfig->ClockFilter);
mbed_official 181:a4cbdfbbd2f4 3640 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official 181:a4cbdfbbd2f4 3641 }
mbed_official 181:a4cbdfbbd2f4 3642 break;
mbed_official 181:a4cbdfbbd2f4 3643 case TIM_CLOCKSOURCE_ITR0:
mbed_official 181:a4cbdfbbd2f4 3644 {
mbed_official 181:a4cbdfbbd2f4 3645 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3646 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official 181:a4cbdfbbd2f4 3647 }
mbed_official 181:a4cbdfbbd2f4 3648 break;
mbed_official 181:a4cbdfbbd2f4 3649 case TIM_CLOCKSOURCE_ITR1:
mbed_official 181:a4cbdfbbd2f4 3650 {
mbed_official 181:a4cbdfbbd2f4 3651 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3652 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official 181:a4cbdfbbd2f4 3653 }
mbed_official 181:a4cbdfbbd2f4 3654 break;
mbed_official 181:a4cbdfbbd2f4 3655 case TIM_CLOCKSOURCE_ITR2:
mbed_official 181:a4cbdfbbd2f4 3656 {
mbed_official 181:a4cbdfbbd2f4 3657 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3658 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official 181:a4cbdfbbd2f4 3659 }
mbed_official 181:a4cbdfbbd2f4 3660 break;
mbed_official 181:a4cbdfbbd2f4 3661 case TIM_CLOCKSOURCE_ITR3:
mbed_official 181:a4cbdfbbd2f4 3662 {
mbed_official 181:a4cbdfbbd2f4 3663 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3664 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official 181:a4cbdfbbd2f4 3665 }
mbed_official 181:a4cbdfbbd2f4 3666 break;
mbed_official 181:a4cbdfbbd2f4 3667
mbed_official 181:a4cbdfbbd2f4 3668 default:
mbed_official 181:a4cbdfbbd2f4 3669 break;
mbed_official 181:a4cbdfbbd2f4 3670 }
mbed_official 181:a4cbdfbbd2f4 3671 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3672
mbed_official 181:a4cbdfbbd2f4 3673 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3674
mbed_official 181:a4cbdfbbd2f4 3675 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3676 }
mbed_official 181:a4cbdfbbd2f4 3677
mbed_official 181:a4cbdfbbd2f4 3678 /**
mbed_official 181:a4cbdfbbd2f4 3679 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official 181:a4cbdfbbd2f4 3680 * or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official 181:a4cbdfbbd2f4 3681 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3682 * the configuration information for TIM module..
mbed_official 181:a4cbdfbbd2f4 3683 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official 181:a4cbdfbbd2f4 3684 * output of a XOR gate.
mbed_official 181:a4cbdfbbd2f4 3685 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 3686 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official 181:a4cbdfbbd2f4 3687 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official 181:a4cbdfbbd2f4 3688 * pins are connected to the TI1 input (XOR combination)
mbed_official 181:a4cbdfbbd2f4 3689 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3690 */
mbed_official 181:a4cbdfbbd2f4 3691 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official 181:a4cbdfbbd2f4 3692 {
mbed_official 181:a4cbdfbbd2f4 3693 uint32_t tmpcr2 = 0;
mbed_official 181:a4cbdfbbd2f4 3694
mbed_official 181:a4cbdfbbd2f4 3695 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3696 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3697 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official 181:a4cbdfbbd2f4 3698
mbed_official 181:a4cbdfbbd2f4 3699 /* Get the TIMx CR2 register value */
mbed_official 181:a4cbdfbbd2f4 3700 tmpcr2 = htim->Instance->CR2;
mbed_official 181:a4cbdfbbd2f4 3701
mbed_official 181:a4cbdfbbd2f4 3702 /* Reset the TI1 selection */
mbed_official 181:a4cbdfbbd2f4 3703 tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official 181:a4cbdfbbd2f4 3704
mbed_official 181:a4cbdfbbd2f4 3705 /* Set the the TI1 selection */
mbed_official 181:a4cbdfbbd2f4 3706 tmpcr2 |= TI1_Selection;
mbed_official 181:a4cbdfbbd2f4 3707
mbed_official 181:a4cbdfbbd2f4 3708 /* Write to TIMxCR2 */
mbed_official 181:a4cbdfbbd2f4 3709 htim->Instance->CR2 = tmpcr2;
mbed_official 181:a4cbdfbbd2f4 3710
mbed_official 181:a4cbdfbbd2f4 3711 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3712 }
mbed_official 181:a4cbdfbbd2f4 3713
mbed_official 181:a4cbdfbbd2f4 3714 /**
mbed_official 181:a4cbdfbbd2f4 3715 * @brief Configures the TIM in Slave mode
mbed_official 181:a4cbdfbbd2f4 3716 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3717 * the configuration information for TIM module..
mbed_official 181:a4cbdfbbd2f4 3718 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 181:a4cbdfbbd2f4 3719 * contains the selected trigger (internal trigger input, filtered
mbed_official 181:a4cbdfbbd2f4 3720 * timer input or external trigger input) and the ) and the Slave
mbed_official 181:a4cbdfbbd2f4 3721 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 181:a4cbdfbbd2f4 3722 * @retval HAL status
mbed_official 181:a4cbdfbbd2f4 3723 */
mbed_official 181:a4cbdfbbd2f4 3724 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 181:a4cbdfbbd2f4 3725 {
mbed_official 181:a4cbdfbbd2f4 3726 uint32_t tmpsmcr = 0;
mbed_official 181:a4cbdfbbd2f4 3727 uint32_t tmpccmr1 = 0;
mbed_official 181:a4cbdfbbd2f4 3728 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 3729
mbed_official 181:a4cbdfbbd2f4 3730 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3731 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3732 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 181:a4cbdfbbd2f4 3733 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 181:a4cbdfbbd2f4 3734
mbed_official 181:a4cbdfbbd2f4 3735 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3736
mbed_official 181:a4cbdfbbd2f4 3737 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 181:a4cbdfbbd2f4 3738
mbed_official 181:a4cbdfbbd2f4 3739 /* Get the TIMx SMCR register value */
mbed_official 181:a4cbdfbbd2f4 3740 tmpsmcr = htim->Instance->SMCR;
mbed_official 181:a4cbdfbbd2f4 3741
mbed_official 181:a4cbdfbbd2f4 3742 /* Reset the Trigger Selection Bits */
mbed_official 181:a4cbdfbbd2f4 3743 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 181:a4cbdfbbd2f4 3744 /* Set the Input Trigger source */
mbed_official 181:a4cbdfbbd2f4 3745 tmpsmcr |= sSlaveConfig->InputTrigger;
mbed_official 181:a4cbdfbbd2f4 3746
mbed_official 181:a4cbdfbbd2f4 3747 /* Reset the slave mode Bits */
mbed_official 181:a4cbdfbbd2f4 3748 tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official 181:a4cbdfbbd2f4 3749 /* Set the slave mode */
mbed_official 181:a4cbdfbbd2f4 3750 tmpsmcr |= sSlaveConfig->SlaveMode;
mbed_official 181:a4cbdfbbd2f4 3751
mbed_official 181:a4cbdfbbd2f4 3752 /* Write to TIMx SMCR */
mbed_official 181:a4cbdfbbd2f4 3753 htim->Instance->SMCR = tmpsmcr;
mbed_official 181:a4cbdfbbd2f4 3754
mbed_official 181:a4cbdfbbd2f4 3755 /* Configure the trigger prescaler, filter, and polarity */
mbed_official 181:a4cbdfbbd2f4 3756 switch (sSlaveConfig->InputTrigger)
mbed_official 181:a4cbdfbbd2f4 3757 {
mbed_official 181:a4cbdfbbd2f4 3758 case TIM_TS_ETRF:
mbed_official 181:a4cbdfbbd2f4 3759 {
mbed_official 181:a4cbdfbbd2f4 3760 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3761 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3762 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official 181:a4cbdfbbd2f4 3763 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 181:a4cbdfbbd2f4 3764 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 181:a4cbdfbbd2f4 3765 /* Configure the ETR Trigger source */
mbed_official 181:a4cbdfbbd2f4 3766 TIM_ETR_SetConfig(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3767 sSlaveConfig->TriggerPrescaler,
mbed_official 181:a4cbdfbbd2f4 3768 sSlaveConfig->TriggerPolarity,
mbed_official 181:a4cbdfbbd2f4 3769 sSlaveConfig->TriggerFilter);
mbed_official 181:a4cbdfbbd2f4 3770 }
mbed_official 181:a4cbdfbbd2f4 3771 break;
mbed_official 181:a4cbdfbbd2f4 3772
mbed_official 181:a4cbdfbbd2f4 3773 case TIM_TS_TI1F_ED:
mbed_official 181:a4cbdfbbd2f4 3774 {
mbed_official 181:a4cbdfbbd2f4 3775 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3776 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3777 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 181:a4cbdfbbd2f4 3778
mbed_official 181:a4cbdfbbd2f4 3779 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 181:a4cbdfbbd2f4 3780 tmpccer = htim->Instance->CCER;
mbed_official 181:a4cbdfbbd2f4 3781 htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official 181:a4cbdfbbd2f4 3782 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 181:a4cbdfbbd2f4 3783
mbed_official 181:a4cbdfbbd2f4 3784 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 3785 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 181:a4cbdfbbd2f4 3786 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official 181:a4cbdfbbd2f4 3787
mbed_official 181:a4cbdfbbd2f4 3788 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 3789 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 181:a4cbdfbbd2f4 3790 htim->Instance->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 3791
mbed_official 181:a4cbdfbbd2f4 3792 }
mbed_official 181:a4cbdfbbd2f4 3793 break;
mbed_official 181:a4cbdfbbd2f4 3794
mbed_official 181:a4cbdfbbd2f4 3795 case TIM_TS_TI1FP1:
mbed_official 181:a4cbdfbbd2f4 3796 {
mbed_official 181:a4cbdfbbd2f4 3797 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3798 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3799 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 181:a4cbdfbbd2f4 3800 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 181:a4cbdfbbd2f4 3801
mbed_official 181:a4cbdfbbd2f4 3802 /* Configure TI1 Filter and Polarity */
mbed_official 181:a4cbdfbbd2f4 3803 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3804 sSlaveConfig->TriggerPolarity,
mbed_official 181:a4cbdfbbd2f4 3805 sSlaveConfig->TriggerFilter);
mbed_official 181:a4cbdfbbd2f4 3806 }
mbed_official 181:a4cbdfbbd2f4 3807 break;
mbed_official 181:a4cbdfbbd2f4 3808
mbed_official 181:a4cbdfbbd2f4 3809 case TIM_TS_TI2FP2:
mbed_official 181:a4cbdfbbd2f4 3810 {
mbed_official 181:a4cbdfbbd2f4 3811 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3812 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3813 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 181:a4cbdfbbd2f4 3814 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 181:a4cbdfbbd2f4 3815
mbed_official 181:a4cbdfbbd2f4 3816 /* Configure TI2 Filter and Polarity */
mbed_official 181:a4cbdfbbd2f4 3817 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 181:a4cbdfbbd2f4 3818 sSlaveConfig->TriggerPolarity,
mbed_official 181:a4cbdfbbd2f4 3819 sSlaveConfig->TriggerFilter);
mbed_official 181:a4cbdfbbd2f4 3820 }
mbed_official 181:a4cbdfbbd2f4 3821 break;
mbed_official 181:a4cbdfbbd2f4 3822
mbed_official 181:a4cbdfbbd2f4 3823 case TIM_TS_ITR0:
mbed_official 181:a4cbdfbbd2f4 3824 {
mbed_official 181:a4cbdfbbd2f4 3825 /* Check the parameter */
mbed_official 181:a4cbdfbbd2f4 3826 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3827 }
mbed_official 181:a4cbdfbbd2f4 3828 break;
mbed_official 181:a4cbdfbbd2f4 3829
mbed_official 181:a4cbdfbbd2f4 3830 case TIM_TS_ITR1:
mbed_official 181:a4cbdfbbd2f4 3831 {
mbed_official 181:a4cbdfbbd2f4 3832 /* Check the parameter */
mbed_official 181:a4cbdfbbd2f4 3833 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3834 }
mbed_official 181:a4cbdfbbd2f4 3835 break;
mbed_official 181:a4cbdfbbd2f4 3836
mbed_official 181:a4cbdfbbd2f4 3837 case TIM_TS_ITR2:
mbed_official 181:a4cbdfbbd2f4 3838 {
mbed_official 181:a4cbdfbbd2f4 3839 /* Check the parameter */
mbed_official 181:a4cbdfbbd2f4 3840 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3841 }
mbed_official 181:a4cbdfbbd2f4 3842 break;
mbed_official 181:a4cbdfbbd2f4 3843
mbed_official 181:a4cbdfbbd2f4 3844 case TIM_TS_ITR3:
mbed_official 181:a4cbdfbbd2f4 3845 {
mbed_official 181:a4cbdfbbd2f4 3846 /* Check the parameter */
mbed_official 181:a4cbdfbbd2f4 3847 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3848 }
mbed_official 181:a4cbdfbbd2f4 3849 break;
mbed_official 181:a4cbdfbbd2f4 3850
mbed_official 181:a4cbdfbbd2f4 3851 default:
mbed_official 181:a4cbdfbbd2f4 3852 break;
mbed_official 181:a4cbdfbbd2f4 3853 }
mbed_official 181:a4cbdfbbd2f4 3854
mbed_official 181:a4cbdfbbd2f4 3855 htim->State = HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 3856
mbed_official 181:a4cbdfbbd2f4 3857 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3858
mbed_official 181:a4cbdfbbd2f4 3859 return HAL_OK;
mbed_official 181:a4cbdfbbd2f4 3860 }
mbed_official 181:a4cbdfbbd2f4 3861
mbed_official 181:a4cbdfbbd2f4 3862 /**
mbed_official 181:a4cbdfbbd2f4 3863 * @brief Read the captured value from Capture Compare unit
mbed_official 181:a4cbdfbbd2f4 3864 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3865 * the configuration information for TIM module..
mbed_official 181:a4cbdfbbd2f4 3866 * @param Channel: TIM Channels to be enabled.
mbed_official 181:a4cbdfbbd2f4 3867 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 3868 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 181:a4cbdfbbd2f4 3869 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 181:a4cbdfbbd2f4 3870 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 181:a4cbdfbbd2f4 3871 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 181:a4cbdfbbd2f4 3872 * @retval Captured value
mbed_official 181:a4cbdfbbd2f4 3873 */
mbed_official 181:a4cbdfbbd2f4 3874 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 181:a4cbdfbbd2f4 3875 {
mbed_official 181:a4cbdfbbd2f4 3876 uint32_t tmpreg = 0;
mbed_official 181:a4cbdfbbd2f4 3877
mbed_official 181:a4cbdfbbd2f4 3878 __HAL_LOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3879
mbed_official 181:a4cbdfbbd2f4 3880 switch (Channel)
mbed_official 181:a4cbdfbbd2f4 3881 {
mbed_official 181:a4cbdfbbd2f4 3882 case TIM_CHANNEL_1:
mbed_official 181:a4cbdfbbd2f4 3883 {
mbed_official 181:a4cbdfbbd2f4 3884 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3885 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3886
mbed_official 181:a4cbdfbbd2f4 3887 /* Return the capture 1 value */
mbed_official 181:a4cbdfbbd2f4 3888 tmpreg = htim->Instance->CCR1;
mbed_official 181:a4cbdfbbd2f4 3889
mbed_official 181:a4cbdfbbd2f4 3890 break;
mbed_official 181:a4cbdfbbd2f4 3891 }
mbed_official 181:a4cbdfbbd2f4 3892 case TIM_CHANNEL_2:
mbed_official 181:a4cbdfbbd2f4 3893 {
mbed_official 181:a4cbdfbbd2f4 3894 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3895 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3896
mbed_official 181:a4cbdfbbd2f4 3897 /* Return the capture 2 value */
mbed_official 181:a4cbdfbbd2f4 3898 tmpreg = htim->Instance->CCR2;
mbed_official 181:a4cbdfbbd2f4 3899
mbed_official 181:a4cbdfbbd2f4 3900 break;
mbed_official 181:a4cbdfbbd2f4 3901 }
mbed_official 181:a4cbdfbbd2f4 3902
mbed_official 181:a4cbdfbbd2f4 3903 case TIM_CHANNEL_3:
mbed_official 181:a4cbdfbbd2f4 3904 {
mbed_official 181:a4cbdfbbd2f4 3905 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3906 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3907
mbed_official 181:a4cbdfbbd2f4 3908 /* Return the capture 3 value */
mbed_official 181:a4cbdfbbd2f4 3909 tmpreg = htim->Instance->CCR3;
mbed_official 181:a4cbdfbbd2f4 3910
mbed_official 181:a4cbdfbbd2f4 3911 break;
mbed_official 181:a4cbdfbbd2f4 3912 }
mbed_official 181:a4cbdfbbd2f4 3913
mbed_official 181:a4cbdfbbd2f4 3914 case TIM_CHANNEL_4:
mbed_official 181:a4cbdfbbd2f4 3915 {
mbed_official 181:a4cbdfbbd2f4 3916 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 3917 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 181:a4cbdfbbd2f4 3918
mbed_official 181:a4cbdfbbd2f4 3919 /* Return the capture 4 value */
mbed_official 181:a4cbdfbbd2f4 3920 tmpreg = htim->Instance->CCR4;
mbed_official 181:a4cbdfbbd2f4 3921
mbed_official 181:a4cbdfbbd2f4 3922 break;
mbed_official 181:a4cbdfbbd2f4 3923 }
mbed_official 181:a4cbdfbbd2f4 3924
mbed_official 181:a4cbdfbbd2f4 3925 default:
mbed_official 181:a4cbdfbbd2f4 3926 break;
mbed_official 181:a4cbdfbbd2f4 3927 }
mbed_official 181:a4cbdfbbd2f4 3928
mbed_official 181:a4cbdfbbd2f4 3929 __HAL_UNLOCK(htim);
mbed_official 181:a4cbdfbbd2f4 3930 return tmpreg;
mbed_official 181:a4cbdfbbd2f4 3931 }
mbed_official 181:a4cbdfbbd2f4 3932
mbed_official 181:a4cbdfbbd2f4 3933 /**
mbed_official 181:a4cbdfbbd2f4 3934 * @}
mbed_official 181:a4cbdfbbd2f4 3935 */
mbed_official 181:a4cbdfbbd2f4 3936
mbed_official 181:a4cbdfbbd2f4 3937 /** @defgroup TIM_Group4 TIM Callbacks functions
mbed_official 181:a4cbdfbbd2f4 3938 * @brief TIM Callbacks functions
mbed_official 181:a4cbdfbbd2f4 3939 *
mbed_official 181:a4cbdfbbd2f4 3940 @verbatim
mbed_official 181:a4cbdfbbd2f4 3941 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 3942 ##### TIM Callbacks functions #####
mbed_official 181:a4cbdfbbd2f4 3943 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 3944 [..]
mbed_official 181:a4cbdfbbd2f4 3945 This section provides TIM callback functions:
mbed_official 181:a4cbdfbbd2f4 3946 (+) Timer Period elapsed callback
mbed_official 181:a4cbdfbbd2f4 3947 (+) Timer Output Compare callback
mbed_official 181:a4cbdfbbd2f4 3948 (+) Timer Input capture callback
mbed_official 181:a4cbdfbbd2f4 3949 (+) Timer Trigger callback
mbed_official 181:a4cbdfbbd2f4 3950 (+) Timer Error callback
mbed_official 181:a4cbdfbbd2f4 3951
mbed_official 181:a4cbdfbbd2f4 3952 @endverbatim
mbed_official 181:a4cbdfbbd2f4 3953 * @{
mbed_official 181:a4cbdfbbd2f4 3954 */
mbed_official 181:a4cbdfbbd2f4 3955
mbed_official 181:a4cbdfbbd2f4 3956 /**
mbed_official 181:a4cbdfbbd2f4 3957 * @brief Period elapsed callback in non blocking mode
mbed_official 181:a4cbdfbbd2f4 3958 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3959 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3960 * @retval None
mbed_official 181:a4cbdfbbd2f4 3961 */
mbed_official 181:a4cbdfbbd2f4 3962 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 3963 {
mbed_official 181:a4cbdfbbd2f4 3964 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 3965 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 3966 */
mbed_official 181:a4cbdfbbd2f4 3967
mbed_official 181:a4cbdfbbd2f4 3968 }
mbed_official 181:a4cbdfbbd2f4 3969 /**
mbed_official 181:a4cbdfbbd2f4 3970 * @brief Output Compare callback in non blocking mode
mbed_official 181:a4cbdfbbd2f4 3971 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3972 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3973 * @retval None
mbed_official 181:a4cbdfbbd2f4 3974 */
mbed_official 181:a4cbdfbbd2f4 3975 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 3976 {
mbed_official 181:a4cbdfbbd2f4 3977 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 3978 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 3979 */
mbed_official 181:a4cbdfbbd2f4 3980 }
mbed_official 181:a4cbdfbbd2f4 3981 /**
mbed_official 181:a4cbdfbbd2f4 3982 * @brief Input Capture callback in non blocking mode
mbed_official 181:a4cbdfbbd2f4 3983 * @param htim : TIM IC handle
mbed_official 181:a4cbdfbbd2f4 3984 * @retval None
mbed_official 181:a4cbdfbbd2f4 3985 */
mbed_official 181:a4cbdfbbd2f4 3986 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 3987 {
mbed_official 181:a4cbdfbbd2f4 3988 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 3989 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 3990 */
mbed_official 181:a4cbdfbbd2f4 3991 }
mbed_official 181:a4cbdfbbd2f4 3992
mbed_official 181:a4cbdfbbd2f4 3993 /**
mbed_official 181:a4cbdfbbd2f4 3994 * @brief PWM Pulse finished callback in non blocking mode
mbed_official 181:a4cbdfbbd2f4 3995 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 3996 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 3997 * @retval None
mbed_official 181:a4cbdfbbd2f4 3998 */
mbed_official 181:a4cbdfbbd2f4 3999 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4000 {
mbed_official 181:a4cbdfbbd2f4 4001 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 4002 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 4003 */
mbed_official 181:a4cbdfbbd2f4 4004 }
mbed_official 181:a4cbdfbbd2f4 4005
mbed_official 181:a4cbdfbbd2f4 4006 /**
mbed_official 181:a4cbdfbbd2f4 4007 * @brief Hall Trigger detection callback in non blocking mode
mbed_official 181:a4cbdfbbd2f4 4008 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4009 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 4010 * @retval None
mbed_official 181:a4cbdfbbd2f4 4011 */
mbed_official 181:a4cbdfbbd2f4 4012 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4013 {
mbed_official 181:a4cbdfbbd2f4 4014 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 4015 the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 4016 */
mbed_official 181:a4cbdfbbd2f4 4017 }
mbed_official 181:a4cbdfbbd2f4 4018
mbed_official 181:a4cbdfbbd2f4 4019 /**
mbed_official 181:a4cbdfbbd2f4 4020 * @brief Timer error callback in non blocking mode
mbed_official 181:a4cbdfbbd2f4 4021 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4022 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 4023 * @retval None
mbed_official 181:a4cbdfbbd2f4 4024 */
mbed_official 181:a4cbdfbbd2f4 4025 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4026 {
mbed_official 181:a4cbdfbbd2f4 4027 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 181:a4cbdfbbd2f4 4028 the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official 181:a4cbdfbbd2f4 4029 */
mbed_official 181:a4cbdfbbd2f4 4030 }
mbed_official 181:a4cbdfbbd2f4 4031
mbed_official 181:a4cbdfbbd2f4 4032 /**
mbed_official 181:a4cbdfbbd2f4 4033 * @brief TIM DMA Period Elapse complete callback.
mbed_official 181:a4cbdfbbd2f4 4034 * @param hdma : pointer to DMA handle.
mbed_official 181:a4cbdfbbd2f4 4035 * @retval None
mbed_official 181:a4cbdfbbd2f4 4036 */
mbed_official 181:a4cbdfbbd2f4 4037 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official 181:a4cbdfbbd2f4 4038 {
mbed_official 181:a4cbdfbbd2f4 4039 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 181:a4cbdfbbd2f4 4040
mbed_official 181:a4cbdfbbd2f4 4041 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 4042
mbed_official 181:a4cbdfbbd2f4 4043 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 4044 }
mbed_official 181:a4cbdfbbd2f4 4045
mbed_official 181:a4cbdfbbd2f4 4046
mbed_official 181:a4cbdfbbd2f4 4047 /**
mbed_official 181:a4cbdfbbd2f4 4048 * @brief TIM DMA Trigger callback.
mbed_official 181:a4cbdfbbd2f4 4049 * @param hdma : pointer to DMA handle.
mbed_official 181:a4cbdfbbd2f4 4050 * @retval None
mbed_official 181:a4cbdfbbd2f4 4051 */
mbed_official 181:a4cbdfbbd2f4 4052 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official 181:a4cbdfbbd2f4 4053 {
mbed_official 181:a4cbdfbbd2f4 4054 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 181:a4cbdfbbd2f4 4055
mbed_official 181:a4cbdfbbd2f4 4056 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 4057
mbed_official 181:a4cbdfbbd2f4 4058 HAL_TIM_TriggerCallback(htim);
mbed_official 181:a4cbdfbbd2f4 4059 }
mbed_official 181:a4cbdfbbd2f4 4060
mbed_official 181:a4cbdfbbd2f4 4061 /**
mbed_official 181:a4cbdfbbd2f4 4062 * @}
mbed_official 181:a4cbdfbbd2f4 4063 */
mbed_official 181:a4cbdfbbd2f4 4064
mbed_official 181:a4cbdfbbd2f4 4065 /** @defgroup TIM_Group5 Peripheral State functions
mbed_official 181:a4cbdfbbd2f4 4066 * @brief Peripheral State functions
mbed_official 181:a4cbdfbbd2f4 4067 *
mbed_official 181:a4cbdfbbd2f4 4068 @verbatim
mbed_official 181:a4cbdfbbd2f4 4069 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 4070 ##### Peripheral State functions #####
mbed_official 181:a4cbdfbbd2f4 4071 ==============================================================================
mbed_official 181:a4cbdfbbd2f4 4072 [..]
mbed_official 181:a4cbdfbbd2f4 4073 This subsection permit to get in run-time the status of the peripheral
mbed_official 181:a4cbdfbbd2f4 4074 and the data flow.
mbed_official 181:a4cbdfbbd2f4 4075
mbed_official 181:a4cbdfbbd2f4 4076 @endverbatim
mbed_official 181:a4cbdfbbd2f4 4077 * @{
mbed_official 181:a4cbdfbbd2f4 4078 */
mbed_official 181:a4cbdfbbd2f4 4079
mbed_official 181:a4cbdfbbd2f4 4080 /**
mbed_official 181:a4cbdfbbd2f4 4081 * @brief Return the TIM Base state
mbed_official 181:a4cbdfbbd2f4 4082 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4083 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 4084 * @retval HAL state
mbed_official 181:a4cbdfbbd2f4 4085 */
mbed_official 181:a4cbdfbbd2f4 4086 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4087 {
mbed_official 181:a4cbdfbbd2f4 4088 return htim->State;
mbed_official 181:a4cbdfbbd2f4 4089 }
mbed_official 181:a4cbdfbbd2f4 4090
mbed_official 181:a4cbdfbbd2f4 4091 /**
mbed_official 181:a4cbdfbbd2f4 4092 * @brief Return the TIM OC state
mbed_official 181:a4cbdfbbd2f4 4093 * @param htim: TIM Ouput Compare handle
mbed_official 181:a4cbdfbbd2f4 4094 * @retval HAL state
mbed_official 181:a4cbdfbbd2f4 4095 */
mbed_official 181:a4cbdfbbd2f4 4096 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4097 {
mbed_official 181:a4cbdfbbd2f4 4098 return htim->State;
mbed_official 181:a4cbdfbbd2f4 4099 }
mbed_official 181:a4cbdfbbd2f4 4100
mbed_official 181:a4cbdfbbd2f4 4101 /**
mbed_official 181:a4cbdfbbd2f4 4102 * @brief Return the TIM PWM state
mbed_official 181:a4cbdfbbd2f4 4103 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4104 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 4105 * @retval HAL state
mbed_official 181:a4cbdfbbd2f4 4106 */
mbed_official 181:a4cbdfbbd2f4 4107 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4108 {
mbed_official 181:a4cbdfbbd2f4 4109 return htim->State;
mbed_official 181:a4cbdfbbd2f4 4110 }
mbed_official 181:a4cbdfbbd2f4 4111
mbed_official 181:a4cbdfbbd2f4 4112 /**
mbed_official 181:a4cbdfbbd2f4 4113 * @brief Return the TIM Input Capture state
mbed_official 181:a4cbdfbbd2f4 4114 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4115 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 4116 * @retval HAL state
mbed_official 181:a4cbdfbbd2f4 4117 */
mbed_official 181:a4cbdfbbd2f4 4118 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4119 {
mbed_official 181:a4cbdfbbd2f4 4120 return htim->State;
mbed_official 181:a4cbdfbbd2f4 4121 }
mbed_official 181:a4cbdfbbd2f4 4122
mbed_official 181:a4cbdfbbd2f4 4123 /**
mbed_official 181:a4cbdfbbd2f4 4124 * @brief Return the TIM One Pulse Mode state
mbed_official 181:a4cbdfbbd2f4 4125 * @param htim: TIM OPM handle
mbed_official 181:a4cbdfbbd2f4 4126 * @retval HAL state
mbed_official 181:a4cbdfbbd2f4 4127 */
mbed_official 181:a4cbdfbbd2f4 4128 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4129 {
mbed_official 181:a4cbdfbbd2f4 4130 return htim->State;
mbed_official 181:a4cbdfbbd2f4 4131 }
mbed_official 181:a4cbdfbbd2f4 4132
mbed_official 181:a4cbdfbbd2f4 4133 /**
mbed_official 181:a4cbdfbbd2f4 4134 * @brief Return the TIM Encoder Mode state
mbed_official 181:a4cbdfbbd2f4 4135 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4136 * the configuration information for TIM module.
mbed_official 181:a4cbdfbbd2f4 4137 * @retval HAL state
mbed_official 181:a4cbdfbbd2f4 4138 */
mbed_official 181:a4cbdfbbd2f4 4139 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official 181:a4cbdfbbd2f4 4140 {
mbed_official 181:a4cbdfbbd2f4 4141 return htim->State;
mbed_official 181:a4cbdfbbd2f4 4142 }
mbed_official 181:a4cbdfbbd2f4 4143
mbed_official 181:a4cbdfbbd2f4 4144 /**
mbed_official 181:a4cbdfbbd2f4 4145 * @}
mbed_official 181:a4cbdfbbd2f4 4146 */
mbed_official 181:a4cbdfbbd2f4 4147
mbed_official 181:a4cbdfbbd2f4 4148 /**
mbed_official 181:a4cbdfbbd2f4 4149 * @brief TIM DMA error callback
mbed_official 181:a4cbdfbbd2f4 4150 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4151 * the configuration information for the specified DMA module.
mbed_official 181:a4cbdfbbd2f4 4152 * @retval None
mbed_official 181:a4cbdfbbd2f4 4153 */
mbed_official 181:a4cbdfbbd2f4 4154 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 181:a4cbdfbbd2f4 4155 {
mbed_official 181:a4cbdfbbd2f4 4156 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 181:a4cbdfbbd2f4 4157
mbed_official 181:a4cbdfbbd2f4 4158 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 4159
mbed_official 181:a4cbdfbbd2f4 4160 HAL_TIM_ErrorCallback(htim);
mbed_official 181:a4cbdfbbd2f4 4161 }
mbed_official 181:a4cbdfbbd2f4 4162
mbed_official 181:a4cbdfbbd2f4 4163 /**
mbed_official 181:a4cbdfbbd2f4 4164 * @brief TIM DMA Delay Pulse complete callback.
mbed_official 181:a4cbdfbbd2f4 4165 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4166 * the configuration information for the specified DMA module.
mbed_official 181:a4cbdfbbd2f4 4167 * @retval None
mbed_official 181:a4cbdfbbd2f4 4168 */
mbed_official 181:a4cbdfbbd2f4 4169 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official 181:a4cbdfbbd2f4 4170 {
mbed_official 181:a4cbdfbbd2f4 4171 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 181:a4cbdfbbd2f4 4172
mbed_official 181:a4cbdfbbd2f4 4173 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 4174
mbed_official 181:a4cbdfbbd2f4 4175 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 181:a4cbdfbbd2f4 4176 }
mbed_official 181:a4cbdfbbd2f4 4177 /**
mbed_official 181:a4cbdfbbd2f4 4178 * @brief TIM DMA Capture complete callback.
mbed_official 181:a4cbdfbbd2f4 4179 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 181:a4cbdfbbd2f4 4180 * the configuration information for the specified DMA module.
mbed_official 181:a4cbdfbbd2f4 4181 * @retval None
mbed_official 181:a4cbdfbbd2f4 4182 */
mbed_official 181:a4cbdfbbd2f4 4183 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official 181:a4cbdfbbd2f4 4184 {
mbed_official 181:a4cbdfbbd2f4 4185 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 181:a4cbdfbbd2f4 4186
mbed_official 181:a4cbdfbbd2f4 4187 htim->State= HAL_TIM_STATE_READY;
mbed_official 181:a4cbdfbbd2f4 4188
mbed_official 181:a4cbdfbbd2f4 4189 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 181:a4cbdfbbd2f4 4190
mbed_official 181:a4cbdfbbd2f4 4191 }
mbed_official 181:a4cbdfbbd2f4 4192
mbed_official 181:a4cbdfbbd2f4 4193 /**
mbed_official 181:a4cbdfbbd2f4 4194 * @brief Time Base configuration
mbed_official 181:a4cbdfbbd2f4 4195 * @param TIMx: TIM periheral
mbed_official 181:a4cbdfbbd2f4 4196 * @retval None
mbed_official 181:a4cbdfbbd2f4 4197 */
mbed_official 181:a4cbdfbbd2f4 4198 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
mbed_official 181:a4cbdfbbd2f4 4199 {
mbed_official 181:a4cbdfbbd2f4 4200 uint32_t tmpcr1 = 0;
mbed_official 181:a4cbdfbbd2f4 4201 tmpcr1 = TIMx->CR1;
mbed_official 181:a4cbdfbbd2f4 4202
mbed_official 181:a4cbdfbbd2f4 4203 /* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official 181:a4cbdfbbd2f4 4204 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
mbed_official 181:a4cbdfbbd2f4 4205 {
mbed_official 181:a4cbdfbbd2f4 4206 /* Select the Counter Mode */
mbed_official 181:a4cbdfbbd2f4 4207 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
mbed_official 181:a4cbdfbbd2f4 4208 tmpcr1 |= Structure->CounterMode;
mbed_official 181:a4cbdfbbd2f4 4209 }
mbed_official 181:a4cbdfbbd2f4 4210
mbed_official 181:a4cbdfbbd2f4 4211 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official 181:a4cbdfbbd2f4 4212 {
mbed_official 181:a4cbdfbbd2f4 4213 /* Set the clock division */
mbed_official 181:a4cbdfbbd2f4 4214 tmpcr1 &= ~TIM_CR1_CKD;
mbed_official 181:a4cbdfbbd2f4 4215 tmpcr1 |= (uint32_t)Structure->ClockDivision;
mbed_official 181:a4cbdfbbd2f4 4216 }
mbed_official 181:a4cbdfbbd2f4 4217
mbed_official 181:a4cbdfbbd2f4 4218 TIMx->CR1 = tmpcr1;
mbed_official 181:a4cbdfbbd2f4 4219
mbed_official 181:a4cbdfbbd2f4 4220 /* Set the Autoreload value */
mbed_official 181:a4cbdfbbd2f4 4221 TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official 181:a4cbdfbbd2f4 4222
mbed_official 181:a4cbdfbbd2f4 4223 /* Set the Prescaler value */
mbed_official 181:a4cbdfbbd2f4 4224 TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official 181:a4cbdfbbd2f4 4225
mbed_official 181:a4cbdfbbd2f4 4226 /* Generate an update event to reload the Prescaler value immediatly */
mbed_official 181:a4cbdfbbd2f4 4227 TIMx->EGR = TIM_EGR_UG;
mbed_official 181:a4cbdfbbd2f4 4228 }
mbed_official 181:a4cbdfbbd2f4 4229
mbed_official 181:a4cbdfbbd2f4 4230 /**
mbed_official 181:a4cbdfbbd2f4 4231 * @brief Time Ouput Compare 1 configuration
mbed_official 181:a4cbdfbbd2f4 4232 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4233 * @param OC_Config: The ouput configuration structure
mbed_official 181:a4cbdfbbd2f4 4234 * @retval None
mbed_official 181:a4cbdfbbd2f4 4235 */
mbed_official 181:a4cbdfbbd2f4 4236 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 181:a4cbdfbbd2f4 4237 {
mbed_official 181:a4cbdfbbd2f4 4238 uint32_t tmpccmrx = 0;
mbed_official 181:a4cbdfbbd2f4 4239 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4240 uint32_t tmpcr2 = 0;
mbed_official 181:a4cbdfbbd2f4 4241
mbed_official 181:a4cbdfbbd2f4 4242 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 181:a4cbdfbbd2f4 4243 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 181:a4cbdfbbd2f4 4244
mbed_official 181:a4cbdfbbd2f4 4245 /* Get the TIMx CCER register value */
mbed_official 181:a4cbdfbbd2f4 4246 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4247 /* Get the TIMx CR2 register value */
mbed_official 181:a4cbdfbbd2f4 4248 tmpcr2 = TIMx->CR2;
mbed_official 181:a4cbdfbbd2f4 4249
mbed_official 181:a4cbdfbbd2f4 4250 /* Get the TIMx CCMR1 register value */
mbed_official 181:a4cbdfbbd2f4 4251 tmpccmrx = TIMx->CCMR1;
mbed_official 181:a4cbdfbbd2f4 4252
mbed_official 181:a4cbdfbbd2f4 4253 /* Reset the Output Compare Mode Bits */
mbed_official 181:a4cbdfbbd2f4 4254 tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official 181:a4cbdfbbd2f4 4255 tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official 181:a4cbdfbbd2f4 4256 /* Select the Output Compare Mode */
mbed_official 181:a4cbdfbbd2f4 4257 tmpccmrx |= OC_Config->OCMode;
mbed_official 181:a4cbdfbbd2f4 4258
mbed_official 181:a4cbdfbbd2f4 4259 /* Reset the Output Polarity level */
mbed_official 181:a4cbdfbbd2f4 4260 tmpccer &= ~TIM_CCER_CC1P;
mbed_official 181:a4cbdfbbd2f4 4261 /* Set the Output Compare Polarity */
mbed_official 181:a4cbdfbbd2f4 4262 tmpccer |= OC_Config->OCPolarity;
mbed_official 181:a4cbdfbbd2f4 4263
mbed_official 181:a4cbdfbbd2f4 4264 /* Write to TIMx CR2 */
mbed_official 181:a4cbdfbbd2f4 4265 TIMx->CR2 = tmpcr2;
mbed_official 181:a4cbdfbbd2f4 4266
mbed_official 181:a4cbdfbbd2f4 4267 /* Write to TIMx CCMR1 */
mbed_official 181:a4cbdfbbd2f4 4268 TIMx->CCMR1 = tmpccmrx;
mbed_official 181:a4cbdfbbd2f4 4269
mbed_official 181:a4cbdfbbd2f4 4270 /* Set the Capture Compare Register value */
mbed_official 181:a4cbdfbbd2f4 4271 TIMx->CCR1 = OC_Config->Pulse;
mbed_official 181:a4cbdfbbd2f4 4272
mbed_official 181:a4cbdfbbd2f4 4273 /* Write to TIMx CCER */
mbed_official 181:a4cbdfbbd2f4 4274 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4275 }
mbed_official 181:a4cbdfbbd2f4 4276
mbed_official 181:a4cbdfbbd2f4 4277 /**
mbed_official 181:a4cbdfbbd2f4 4278 * @brief Time Ouput Compare 2 configuration
mbed_official 181:a4cbdfbbd2f4 4279 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4280 * @param OC_Config: The ouput configuration structure
mbed_official 181:a4cbdfbbd2f4 4281 * @retval None
mbed_official 181:a4cbdfbbd2f4 4282 */
mbed_official 181:a4cbdfbbd2f4 4283 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 181:a4cbdfbbd2f4 4284 {
mbed_official 181:a4cbdfbbd2f4 4285 uint32_t tmpccmrx = 0;
mbed_official 181:a4cbdfbbd2f4 4286 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4287 uint32_t tmpcr2 = 0;
mbed_official 181:a4cbdfbbd2f4 4288
mbed_official 181:a4cbdfbbd2f4 4289 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 181:a4cbdfbbd2f4 4290 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 181:a4cbdfbbd2f4 4291
mbed_official 181:a4cbdfbbd2f4 4292 /* Get the TIMx CCER register value */
mbed_official 181:a4cbdfbbd2f4 4293 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4294 /* Get the TIMx CR2 register value */
mbed_official 181:a4cbdfbbd2f4 4295 tmpcr2 = TIMx->CR2;
mbed_official 181:a4cbdfbbd2f4 4296
mbed_official 181:a4cbdfbbd2f4 4297 /* Get the TIMx CCMR1 register value */
mbed_official 181:a4cbdfbbd2f4 4298 tmpccmrx = TIMx->CCMR1;
mbed_official 181:a4cbdfbbd2f4 4299
mbed_official 181:a4cbdfbbd2f4 4300 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 181:a4cbdfbbd2f4 4301 tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official 181:a4cbdfbbd2f4 4302 tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official 181:a4cbdfbbd2f4 4303
mbed_official 181:a4cbdfbbd2f4 4304 /* Select the Output Compare Mode */
mbed_official 181:a4cbdfbbd2f4 4305 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 181:a4cbdfbbd2f4 4306
mbed_official 181:a4cbdfbbd2f4 4307 /* Reset the Output Polarity level */
mbed_official 181:a4cbdfbbd2f4 4308 tmpccer &= ~TIM_CCER_CC2P;
mbed_official 181:a4cbdfbbd2f4 4309 /* Set the Output Compare Polarity */
mbed_official 181:a4cbdfbbd2f4 4310 tmpccer |= (OC_Config->OCPolarity << 4);
mbed_official 181:a4cbdfbbd2f4 4311
mbed_official 181:a4cbdfbbd2f4 4312 /* Write to TIMx CR2 */
mbed_official 181:a4cbdfbbd2f4 4313 TIMx->CR2 = tmpcr2;
mbed_official 181:a4cbdfbbd2f4 4314
mbed_official 181:a4cbdfbbd2f4 4315 /* Write to TIMx CCMR1 */
mbed_official 181:a4cbdfbbd2f4 4316 TIMx->CCMR1 = tmpccmrx;
mbed_official 181:a4cbdfbbd2f4 4317
mbed_official 181:a4cbdfbbd2f4 4318 /* Set the Capture Compare Register value */
mbed_official 181:a4cbdfbbd2f4 4319 TIMx->CCR2 = OC_Config->Pulse;
mbed_official 181:a4cbdfbbd2f4 4320
mbed_official 181:a4cbdfbbd2f4 4321 /* Write to TIMx CCER */
mbed_official 181:a4cbdfbbd2f4 4322 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4323 }
mbed_official 181:a4cbdfbbd2f4 4324
mbed_official 181:a4cbdfbbd2f4 4325 /**
mbed_official 181:a4cbdfbbd2f4 4326 * @brief Time Ouput Compare 3 configuration
mbed_official 181:a4cbdfbbd2f4 4327 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4328 * @param OC_Config: The ouput configuration structure
mbed_official 181:a4cbdfbbd2f4 4329 * @retval None
mbed_official 181:a4cbdfbbd2f4 4330 */
mbed_official 181:a4cbdfbbd2f4 4331 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 181:a4cbdfbbd2f4 4332 {
mbed_official 181:a4cbdfbbd2f4 4333 uint32_t tmpccmrx = 0;
mbed_official 181:a4cbdfbbd2f4 4334 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4335 uint32_t tmpcr2 = 0;
mbed_official 181:a4cbdfbbd2f4 4336
mbed_official 181:a4cbdfbbd2f4 4337 /* Disable the Channel 3: Reset the CC2E Bit */
mbed_official 181:a4cbdfbbd2f4 4338 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 181:a4cbdfbbd2f4 4339
mbed_official 181:a4cbdfbbd2f4 4340 /* Get the TIMx CCER register value */
mbed_official 181:a4cbdfbbd2f4 4341 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4342 /* Get the TIMx CR2 register value */
mbed_official 181:a4cbdfbbd2f4 4343 tmpcr2 = TIMx->CR2;
mbed_official 181:a4cbdfbbd2f4 4344
mbed_official 181:a4cbdfbbd2f4 4345 /* Get the TIMx CCMR2 register value */
mbed_official 181:a4cbdfbbd2f4 4346 tmpccmrx = TIMx->CCMR2;
mbed_official 181:a4cbdfbbd2f4 4347
mbed_official 181:a4cbdfbbd2f4 4348 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 181:a4cbdfbbd2f4 4349 tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official 181:a4cbdfbbd2f4 4350 tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official 181:a4cbdfbbd2f4 4351 /* Select the Output Compare Mode */
mbed_official 181:a4cbdfbbd2f4 4352 tmpccmrx |= OC_Config->OCMode;
mbed_official 181:a4cbdfbbd2f4 4353
mbed_official 181:a4cbdfbbd2f4 4354 /* Reset the Output Polarity level */
mbed_official 181:a4cbdfbbd2f4 4355 tmpccer &= ~TIM_CCER_CC3P;
mbed_official 181:a4cbdfbbd2f4 4356 /* Set the Output Compare Polarity */
mbed_official 181:a4cbdfbbd2f4 4357 tmpccer |= (OC_Config->OCPolarity << 8);
mbed_official 181:a4cbdfbbd2f4 4358
mbed_official 181:a4cbdfbbd2f4 4359 /* Write to TIMx CR2 */
mbed_official 181:a4cbdfbbd2f4 4360 TIMx->CR2 = tmpcr2;
mbed_official 181:a4cbdfbbd2f4 4361
mbed_official 181:a4cbdfbbd2f4 4362 /* Write to TIMx CCMR2 */
mbed_official 181:a4cbdfbbd2f4 4363 TIMx->CCMR2 = tmpccmrx;
mbed_official 181:a4cbdfbbd2f4 4364
mbed_official 181:a4cbdfbbd2f4 4365 /* Set the Capture Compare Register value */
mbed_official 181:a4cbdfbbd2f4 4366 TIMx->CCR3 = OC_Config->Pulse;
mbed_official 181:a4cbdfbbd2f4 4367
mbed_official 181:a4cbdfbbd2f4 4368 /* Write to TIMx CCER */
mbed_official 181:a4cbdfbbd2f4 4369 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4370 }
mbed_official 181:a4cbdfbbd2f4 4371
mbed_official 181:a4cbdfbbd2f4 4372 /**
mbed_official 181:a4cbdfbbd2f4 4373 * @brief Time Ouput Compare 4 configuration
mbed_official 181:a4cbdfbbd2f4 4374 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4375 * @param OC_Config: The ouput configuration structure
mbed_official 181:a4cbdfbbd2f4 4376 * @retval None
mbed_official 181:a4cbdfbbd2f4 4377 */
mbed_official 181:a4cbdfbbd2f4 4378 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 181:a4cbdfbbd2f4 4379 {
mbed_official 181:a4cbdfbbd2f4 4380 uint32_t tmpccmrx = 0;
mbed_official 181:a4cbdfbbd2f4 4381 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4382 uint32_t tmpcr2 = 0;
mbed_official 181:a4cbdfbbd2f4 4383
mbed_official 181:a4cbdfbbd2f4 4384 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 181:a4cbdfbbd2f4 4385 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 181:a4cbdfbbd2f4 4386
mbed_official 181:a4cbdfbbd2f4 4387 /* Get the TIMx CCER register value */
mbed_official 181:a4cbdfbbd2f4 4388 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4389 /* Get the TIMx CR2 register value */
mbed_official 181:a4cbdfbbd2f4 4390 tmpcr2 = TIMx->CR2;
mbed_official 181:a4cbdfbbd2f4 4391
mbed_official 181:a4cbdfbbd2f4 4392 /* Get the TIMx CCMR2 register value */
mbed_official 181:a4cbdfbbd2f4 4393 tmpccmrx = TIMx->CCMR2;
mbed_official 181:a4cbdfbbd2f4 4394
mbed_official 181:a4cbdfbbd2f4 4395 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 181:a4cbdfbbd2f4 4396 tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official 181:a4cbdfbbd2f4 4397 tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official 181:a4cbdfbbd2f4 4398
mbed_official 181:a4cbdfbbd2f4 4399 /* Select the Output Compare Mode */
mbed_official 181:a4cbdfbbd2f4 4400 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 181:a4cbdfbbd2f4 4401
mbed_official 181:a4cbdfbbd2f4 4402 /* Reset the Output Polarity level */
mbed_official 181:a4cbdfbbd2f4 4403 tmpccer &= ~TIM_CCER_CC4P;
mbed_official 181:a4cbdfbbd2f4 4404 /* Set the Output Compare Polarity */
mbed_official 181:a4cbdfbbd2f4 4405 tmpccer |= (OC_Config->OCPolarity << 12);
mbed_official 181:a4cbdfbbd2f4 4406
mbed_official 181:a4cbdfbbd2f4 4407 /* Write to TIMx CR2 */
mbed_official 181:a4cbdfbbd2f4 4408 TIMx->CR2 = tmpcr2;
mbed_official 181:a4cbdfbbd2f4 4409
mbed_official 181:a4cbdfbbd2f4 4410 /* Write to TIMx CCMR2 */
mbed_official 181:a4cbdfbbd2f4 4411 TIMx->CCMR2 = tmpccmrx;
mbed_official 181:a4cbdfbbd2f4 4412
mbed_official 181:a4cbdfbbd2f4 4413 /* Set the Capture Compare Register value */
mbed_official 181:a4cbdfbbd2f4 4414 TIMx->CCR4 = OC_Config->Pulse;
mbed_official 181:a4cbdfbbd2f4 4415
mbed_official 181:a4cbdfbbd2f4 4416 /* Write to TIMx CCER */
mbed_official 181:a4cbdfbbd2f4 4417 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4418 }
mbed_official 181:a4cbdfbbd2f4 4419
mbed_official 181:a4cbdfbbd2f4 4420 /**
mbed_official 181:a4cbdfbbd2f4 4421 * @brief Configure the TI1 as Input.
mbed_official 181:a4cbdfbbd2f4 4422 * @param TIMx to select the TIM peripheral.
mbed_official 181:a4cbdfbbd2f4 4423 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 181:a4cbdfbbd2f4 4424 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4425 * @arg TIM_ICPolarity_Rising
mbed_official 181:a4cbdfbbd2f4 4426 * @arg TIM_ICPolarity_Falling
mbed_official 181:a4cbdfbbd2f4 4427 * @arg TIM_ICPolarity_BothEdge
mbed_official 181:a4cbdfbbd2f4 4428 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 181:a4cbdfbbd2f4 4429 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4430 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official 181:a4cbdfbbd2f4 4431 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official 181:a4cbdfbbd2f4 4432 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official 181:a4cbdfbbd2f4 4433 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 181:a4cbdfbbd2f4 4434 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 181:a4cbdfbbd2f4 4435 * @retval None
mbed_official 181:a4cbdfbbd2f4 4436 */
mbed_official 181:a4cbdfbbd2f4 4437 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 4438 uint32_t TIM_ICFilter)
mbed_official 181:a4cbdfbbd2f4 4439 {
mbed_official 181:a4cbdfbbd2f4 4440 uint32_t tmpccmr1 = 0;
mbed_official 181:a4cbdfbbd2f4 4441 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4442
mbed_official 181:a4cbdfbbd2f4 4443 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 181:a4cbdfbbd2f4 4444 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 181:a4cbdfbbd2f4 4445 tmpccmr1 = TIMx->CCMR1;
mbed_official 181:a4cbdfbbd2f4 4446 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4447
mbed_official 181:a4cbdfbbd2f4 4448 /* Select the Input */
mbed_official 181:a4cbdfbbd2f4 4449 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official 181:a4cbdfbbd2f4 4450 {
mbed_official 181:a4cbdfbbd2f4 4451 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 181:a4cbdfbbd2f4 4452 tmpccmr1 |= TIM_ICSelection;
mbed_official 181:a4cbdfbbd2f4 4453 }
mbed_official 181:a4cbdfbbd2f4 4454 else
mbed_official 181:a4cbdfbbd2f4 4455 {
mbed_official 181:a4cbdfbbd2f4 4456 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 181:a4cbdfbbd2f4 4457 tmpccmr1 |= TIM_CCMR1_CC1S_0;
mbed_official 181:a4cbdfbbd2f4 4458 }
mbed_official 181:a4cbdfbbd2f4 4459
mbed_official 181:a4cbdfbbd2f4 4460 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 4461 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 181:a4cbdfbbd2f4 4462 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 181:a4cbdfbbd2f4 4463
mbed_official 181:a4cbdfbbd2f4 4464 /* Select the Polarity and set the CC1E Bit */
mbed_official 181:a4cbdfbbd2f4 4465 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 181:a4cbdfbbd2f4 4466 tmpccer |= TIM_ICPolarity;
mbed_official 181:a4cbdfbbd2f4 4467
mbed_official 181:a4cbdfbbd2f4 4468 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 4469 TIMx->CCMR1 = tmpccmr1;
mbed_official 181:a4cbdfbbd2f4 4470 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4471 }
mbed_official 181:a4cbdfbbd2f4 4472
mbed_official 181:a4cbdfbbd2f4 4473 /**
mbed_official 181:a4cbdfbbd2f4 4474 * @brief Configure the Polarity and Filter for TI1.
mbed_official 181:a4cbdfbbd2f4 4475 * @param TIMx to select the TIM peripheral.
mbed_official 181:a4cbdfbbd2f4 4476 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 181:a4cbdfbbd2f4 4477 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4478 * @arg TIM_ICPolarity_Rising
mbed_official 181:a4cbdfbbd2f4 4479 * @arg TIM_ICPolarity_Falling
mbed_official 181:a4cbdfbbd2f4 4480 * @arg TIM_ICPolarity_BothEdge
mbed_official 181:a4cbdfbbd2f4 4481 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 181:a4cbdfbbd2f4 4482 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 181:a4cbdfbbd2f4 4483 * @retval None
mbed_official 181:a4cbdfbbd2f4 4484 */
mbed_official 181:a4cbdfbbd2f4 4485 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 181:a4cbdfbbd2f4 4486 {
mbed_official 181:a4cbdfbbd2f4 4487 uint32_t tmpccmr1 = 0;
mbed_official 181:a4cbdfbbd2f4 4488 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4489
mbed_official 181:a4cbdfbbd2f4 4490 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 181:a4cbdfbbd2f4 4491 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4492 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 181:a4cbdfbbd2f4 4493 tmpccmr1 = TIMx->CCMR1;
mbed_official 181:a4cbdfbbd2f4 4494
mbed_official 181:a4cbdfbbd2f4 4495 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 4496 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 181:a4cbdfbbd2f4 4497 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 181:a4cbdfbbd2f4 4498
mbed_official 181:a4cbdfbbd2f4 4499 /* Select the Polarity and set the CC1E Bit */
mbed_official 181:a4cbdfbbd2f4 4500 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 181:a4cbdfbbd2f4 4501 tmpccer |= TIM_ICPolarity;
mbed_official 181:a4cbdfbbd2f4 4502
mbed_official 181:a4cbdfbbd2f4 4503 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 4504 TIMx->CCMR1 = tmpccmr1;
mbed_official 181:a4cbdfbbd2f4 4505 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4506 }
mbed_official 181:a4cbdfbbd2f4 4507
mbed_official 181:a4cbdfbbd2f4 4508 /**
mbed_official 181:a4cbdfbbd2f4 4509 * @brief Configure the TI2 as Input.
mbed_official 181:a4cbdfbbd2f4 4510 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4511 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 181:a4cbdfbbd2f4 4512 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4513 * @arg TIM_ICPolarity_Rising
mbed_official 181:a4cbdfbbd2f4 4514 * @arg TIM_ICPolarity_Falling
mbed_official 181:a4cbdfbbd2f4 4515 * @arg TIM_ICPolarity_BothEdge
mbed_official 181:a4cbdfbbd2f4 4516 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 181:a4cbdfbbd2f4 4517 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4518 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official 181:a4cbdfbbd2f4 4519 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official 181:a4cbdfbbd2f4 4520 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official 181:a4cbdfbbd2f4 4521 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 181:a4cbdfbbd2f4 4522 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 181:a4cbdfbbd2f4 4523 * @retval None
mbed_official 181:a4cbdfbbd2f4 4524 */
mbed_official 181:a4cbdfbbd2f4 4525 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 4526 uint32_t TIM_ICFilter)
mbed_official 181:a4cbdfbbd2f4 4527 {
mbed_official 181:a4cbdfbbd2f4 4528 uint32_t tmpccmr1 = 0;
mbed_official 181:a4cbdfbbd2f4 4529 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4530
mbed_official 181:a4cbdfbbd2f4 4531 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 181:a4cbdfbbd2f4 4532 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 181:a4cbdfbbd2f4 4533 tmpccmr1 = TIMx->CCMR1;
mbed_official 181:a4cbdfbbd2f4 4534 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4535
mbed_official 181:a4cbdfbbd2f4 4536 /* Select the Input */
mbed_official 181:a4cbdfbbd2f4 4537 tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official 181:a4cbdfbbd2f4 4538 tmpccmr1 |= (TIM_ICSelection << 8);
mbed_official 181:a4cbdfbbd2f4 4539
mbed_official 181:a4cbdfbbd2f4 4540 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 4541 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 181:a4cbdfbbd2f4 4542 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 181:a4cbdfbbd2f4 4543
mbed_official 181:a4cbdfbbd2f4 4544 /* Select the Polarity and set the CC2E Bit */
mbed_official 181:a4cbdfbbd2f4 4545 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 181:a4cbdfbbd2f4 4546 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 181:a4cbdfbbd2f4 4547
mbed_official 181:a4cbdfbbd2f4 4548 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 4549 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 181:a4cbdfbbd2f4 4550 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4551 }
mbed_official 181:a4cbdfbbd2f4 4552
mbed_official 181:a4cbdfbbd2f4 4553 /**
mbed_official 181:a4cbdfbbd2f4 4554 * @brief Configure the Polarity and Filter for TI2.
mbed_official 181:a4cbdfbbd2f4 4555 * @param TIMx to select the TIM peripheral.
mbed_official 181:a4cbdfbbd2f4 4556 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 181:a4cbdfbbd2f4 4557 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4558 * @arg TIM_ICPolarity_Rising
mbed_official 181:a4cbdfbbd2f4 4559 * @arg TIM_ICPolarity_Falling
mbed_official 181:a4cbdfbbd2f4 4560 * @arg TIM_ICPolarity_BothEdge
mbed_official 181:a4cbdfbbd2f4 4561 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 181:a4cbdfbbd2f4 4562 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 181:a4cbdfbbd2f4 4563 * @retval None
mbed_official 181:a4cbdfbbd2f4 4564 */
mbed_official 181:a4cbdfbbd2f4 4565 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 181:a4cbdfbbd2f4 4566 {
mbed_official 181:a4cbdfbbd2f4 4567 uint32_t tmpccmr1 = 0;
mbed_official 181:a4cbdfbbd2f4 4568 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4569
mbed_official 181:a4cbdfbbd2f4 4570 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 181:a4cbdfbbd2f4 4571 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 181:a4cbdfbbd2f4 4572 tmpccmr1 = TIMx->CCMR1;
mbed_official 181:a4cbdfbbd2f4 4573 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4574
mbed_official 181:a4cbdfbbd2f4 4575 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 4576 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 181:a4cbdfbbd2f4 4577 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 181:a4cbdfbbd2f4 4578
mbed_official 181:a4cbdfbbd2f4 4579 /* Select the Polarity and set the CC2E Bit */
mbed_official 181:a4cbdfbbd2f4 4580 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 181:a4cbdfbbd2f4 4581 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 181:a4cbdfbbd2f4 4582
mbed_official 181:a4cbdfbbd2f4 4583 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 4584 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 181:a4cbdfbbd2f4 4585 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4586 }
mbed_official 181:a4cbdfbbd2f4 4587
mbed_official 181:a4cbdfbbd2f4 4588 /**
mbed_official 181:a4cbdfbbd2f4 4589 * @brief Configure the TI3 as Input.
mbed_official 181:a4cbdfbbd2f4 4590 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4591 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 181:a4cbdfbbd2f4 4592 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4593 * @arg TIM_ICPolarity_Rising
mbed_official 181:a4cbdfbbd2f4 4594 * @arg TIM_ICPolarity_Falling
mbed_official 181:a4cbdfbbd2f4 4595 * @arg TIM_ICPolarity_BothEdge
mbed_official 181:a4cbdfbbd2f4 4596 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 181:a4cbdfbbd2f4 4597 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4598 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official 181:a4cbdfbbd2f4 4599 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official 181:a4cbdfbbd2f4 4600 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official 181:a4cbdfbbd2f4 4601 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 181:a4cbdfbbd2f4 4602 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 181:a4cbdfbbd2f4 4603 * @retval None
mbed_official 181:a4cbdfbbd2f4 4604 */
mbed_official 181:a4cbdfbbd2f4 4605 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 4606 uint32_t TIM_ICFilter)
mbed_official 181:a4cbdfbbd2f4 4607 {
mbed_official 181:a4cbdfbbd2f4 4608 uint32_t tmpccmr2 = 0;
mbed_official 181:a4cbdfbbd2f4 4609 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4610
mbed_official 181:a4cbdfbbd2f4 4611 /* Disable the Channel 3: Reset the CC3E Bit */
mbed_official 181:a4cbdfbbd2f4 4612 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 181:a4cbdfbbd2f4 4613 tmpccmr2 = TIMx->CCMR2;
mbed_official 181:a4cbdfbbd2f4 4614 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4615
mbed_official 181:a4cbdfbbd2f4 4616 /* Select the Input */
mbed_official 181:a4cbdfbbd2f4 4617 tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official 181:a4cbdfbbd2f4 4618 tmpccmr2 |= TIM_ICSelection;
mbed_official 181:a4cbdfbbd2f4 4619
mbed_official 181:a4cbdfbbd2f4 4620 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 4621 tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official 181:a4cbdfbbd2f4 4622 tmpccmr2 |= (TIM_ICFilter << 4);
mbed_official 181:a4cbdfbbd2f4 4623
mbed_official 181:a4cbdfbbd2f4 4624 /* Select the Polarity and set the CC3E Bit */
mbed_official 181:a4cbdfbbd2f4 4625 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
mbed_official 181:a4cbdfbbd2f4 4626 tmpccer |= (TIM_ICPolarity << 8);
mbed_official 181:a4cbdfbbd2f4 4627
mbed_official 181:a4cbdfbbd2f4 4628 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 4629 TIMx->CCMR2 = tmpccmr2;
mbed_official 181:a4cbdfbbd2f4 4630 TIMx->CCER = tmpccer;
mbed_official 181:a4cbdfbbd2f4 4631 }
mbed_official 181:a4cbdfbbd2f4 4632
mbed_official 181:a4cbdfbbd2f4 4633 /**
mbed_official 181:a4cbdfbbd2f4 4634 * @brief Configure the TI4 as Input.
mbed_official 181:a4cbdfbbd2f4 4635 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4636 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 181:a4cbdfbbd2f4 4637 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4638 * @arg TIM_ICPolarity_Rising
mbed_official 181:a4cbdfbbd2f4 4639 * @arg TIM_ICPolarity_Falling
mbed_official 181:a4cbdfbbd2f4 4640 * @arg TIM_ICPolarity_BothEdge
mbed_official 181:a4cbdfbbd2f4 4641 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 181:a4cbdfbbd2f4 4642 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4643 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official 181:a4cbdfbbd2f4 4644 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official 181:a4cbdfbbd2f4 4645 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official 181:a4cbdfbbd2f4 4646 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 181:a4cbdfbbd2f4 4647 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 181:a4cbdfbbd2f4 4648 * @retval None
mbed_official 181:a4cbdfbbd2f4 4649 */
mbed_official 181:a4cbdfbbd2f4 4650 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 181:a4cbdfbbd2f4 4651 uint32_t TIM_ICFilter)
mbed_official 181:a4cbdfbbd2f4 4652 {
mbed_official 181:a4cbdfbbd2f4 4653 uint32_t tmpccmr2 = 0;
mbed_official 181:a4cbdfbbd2f4 4654 uint32_t tmpccer = 0;
mbed_official 181:a4cbdfbbd2f4 4655
mbed_official 181:a4cbdfbbd2f4 4656 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 181:a4cbdfbbd2f4 4657 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 181:a4cbdfbbd2f4 4658 tmpccmr2 = TIMx->CCMR2;
mbed_official 181:a4cbdfbbd2f4 4659 tmpccer = TIMx->CCER;
mbed_official 181:a4cbdfbbd2f4 4660
mbed_official 181:a4cbdfbbd2f4 4661 /* Select the Input */
mbed_official 181:a4cbdfbbd2f4 4662 tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official 181:a4cbdfbbd2f4 4663 tmpccmr2 |= (TIM_ICSelection << 8);
mbed_official 181:a4cbdfbbd2f4 4664
mbed_official 181:a4cbdfbbd2f4 4665 /* Set the filter */
mbed_official 181:a4cbdfbbd2f4 4666 tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official 181:a4cbdfbbd2f4 4667 tmpccmr2 |= (TIM_ICFilter << 12);
mbed_official 181:a4cbdfbbd2f4 4668
mbed_official 181:a4cbdfbbd2f4 4669 /* Select the Polarity and set the CC4E Bit */
mbed_official 181:a4cbdfbbd2f4 4670 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
mbed_official 181:a4cbdfbbd2f4 4671 tmpccer |= (TIM_ICPolarity << 12);
mbed_official 181:a4cbdfbbd2f4 4672
mbed_official 181:a4cbdfbbd2f4 4673 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 181:a4cbdfbbd2f4 4674 TIMx->CCMR2 = tmpccmr2;
mbed_official 181:a4cbdfbbd2f4 4675 TIMx->CCER = tmpccer ;
mbed_official 181:a4cbdfbbd2f4 4676 }
mbed_official 181:a4cbdfbbd2f4 4677
mbed_official 181:a4cbdfbbd2f4 4678 /**
mbed_official 181:a4cbdfbbd2f4 4679 * @brief Selects the Input Trigger source
mbed_official 181:a4cbdfbbd2f4 4680 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4681 * @param InputTriggerSource: The Input Trigger source.
mbed_official 181:a4cbdfbbd2f4 4682 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4683 * @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official 181:a4cbdfbbd2f4 4684 * @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official 181:a4cbdfbbd2f4 4685 * @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official 181:a4cbdfbbd2f4 4686 * @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official 181:a4cbdfbbd2f4 4687 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official 181:a4cbdfbbd2f4 4688 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official 181:a4cbdfbbd2f4 4689 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official 181:a4cbdfbbd2f4 4690 * @arg TIM_TS_ETRF: External Trigger input
mbed_official 181:a4cbdfbbd2f4 4691 * @retval None
mbed_official 181:a4cbdfbbd2f4 4692 */
mbed_official 181:a4cbdfbbd2f4 4693 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
mbed_official 181:a4cbdfbbd2f4 4694 {
mbed_official 181:a4cbdfbbd2f4 4695 uint32_t tmpsmcr = 0;
mbed_official 181:a4cbdfbbd2f4 4696
mbed_official 181:a4cbdfbbd2f4 4697 /* Get the TIMx SMCR register value */
mbed_official 181:a4cbdfbbd2f4 4698 tmpsmcr = TIMx->SMCR;
mbed_official 181:a4cbdfbbd2f4 4699 /* Reset the TS Bits */
mbed_official 181:a4cbdfbbd2f4 4700 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 181:a4cbdfbbd2f4 4701 /* Set the Input Trigger source and the slave mode*/
mbed_official 181:a4cbdfbbd2f4 4702 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
mbed_official 181:a4cbdfbbd2f4 4703 /* Write to TIMx SMCR */
mbed_official 181:a4cbdfbbd2f4 4704 TIMx->SMCR = tmpsmcr;
mbed_official 181:a4cbdfbbd2f4 4705 }
mbed_official 181:a4cbdfbbd2f4 4706 /**
mbed_official 181:a4cbdfbbd2f4 4707 * @brief Configures the TIMx External Trigger (ETR).
mbed_official 181:a4cbdfbbd2f4 4708 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4709 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official 181:a4cbdfbbd2f4 4710 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4711 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official 181:a4cbdfbbd2f4 4712 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official 181:a4cbdfbbd2f4 4713 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official 181:a4cbdfbbd2f4 4714 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official 181:a4cbdfbbd2f4 4715 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official 181:a4cbdfbbd2f4 4716 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4717 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official 181:a4cbdfbbd2f4 4718 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official 181:a4cbdfbbd2f4 4719 * @param ExtTRGFilter: External Trigger Filter.
mbed_official 181:a4cbdfbbd2f4 4720 * This parameter must be a value between 0x00 and 0x0F
mbed_official 181:a4cbdfbbd2f4 4721 * @retval None
mbed_official 181:a4cbdfbbd2f4 4722 */
mbed_official 181:a4cbdfbbd2f4 4723 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 181:a4cbdfbbd2f4 4724 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official 181:a4cbdfbbd2f4 4725 {
mbed_official 181:a4cbdfbbd2f4 4726 uint32_t tmpsmcr = 0;
mbed_official 181:a4cbdfbbd2f4 4727
mbed_official 181:a4cbdfbbd2f4 4728 tmpsmcr = TIMx->SMCR;
mbed_official 181:a4cbdfbbd2f4 4729
mbed_official 181:a4cbdfbbd2f4 4730 /* Reset the ETR Bits */
mbed_official 181:a4cbdfbbd2f4 4731 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 181:a4cbdfbbd2f4 4732
mbed_official 181:a4cbdfbbd2f4 4733 /* Set the Prescaler, the Filter value and the Polarity */
mbed_official 181:a4cbdfbbd2f4 4734 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
mbed_official 181:a4cbdfbbd2f4 4735
mbed_official 181:a4cbdfbbd2f4 4736 /* Write to TIMx SMCR */
mbed_official 181:a4cbdfbbd2f4 4737 TIMx->SMCR = tmpsmcr;
mbed_official 181:a4cbdfbbd2f4 4738 }
mbed_official 181:a4cbdfbbd2f4 4739
mbed_official 181:a4cbdfbbd2f4 4740 /**
mbed_official 181:a4cbdfbbd2f4 4741 * @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official 181:a4cbdfbbd2f4 4742 * @param TIMx to select the TIM peripheral
mbed_official 181:a4cbdfbbd2f4 4743 * @param Channel: specifies the TIM Channel
mbed_official 181:a4cbdfbbd2f4 4744 * This parameter can be one of the following values:
mbed_official 181:a4cbdfbbd2f4 4745 * @arg TIM_Channel_1: TIM Channel 1
mbed_official 181:a4cbdfbbd2f4 4746 * @arg TIM_Channel_2: TIM Channel 2
mbed_official 181:a4cbdfbbd2f4 4747 * @arg TIM_Channel_3: TIM Channel 3
mbed_official 181:a4cbdfbbd2f4 4748 * @arg TIM_Channel_4: TIM Channel 4
mbed_official 181:a4cbdfbbd2f4 4749 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official 181:a4cbdfbbd2f4 4750 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official 181:a4cbdfbbd2f4 4751 * @retval None
mbed_official 181:a4cbdfbbd2f4 4752 */
mbed_official 181:a4cbdfbbd2f4 4753 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official 181:a4cbdfbbd2f4 4754 {
mbed_official 181:a4cbdfbbd2f4 4755 uint32_t tmp = 0;
mbed_official 181:a4cbdfbbd2f4 4756
mbed_official 181:a4cbdfbbd2f4 4757 /* Check the parameters */
mbed_official 181:a4cbdfbbd2f4 4758 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official 181:a4cbdfbbd2f4 4759 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 181:a4cbdfbbd2f4 4760
mbed_official 181:a4cbdfbbd2f4 4761 tmp = TIM_CCER_CC1E << Channel;
mbed_official 181:a4cbdfbbd2f4 4762
mbed_official 181:a4cbdfbbd2f4 4763 /* Reset the CCxE Bit */
mbed_official 181:a4cbdfbbd2f4 4764 TIMx->CCER &= ~tmp;
mbed_official 181:a4cbdfbbd2f4 4765
mbed_official 181:a4cbdfbbd2f4 4766 /* Set or reset the CCxE Bit */
mbed_official 181:a4cbdfbbd2f4 4767 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
mbed_official 181:a4cbdfbbd2f4 4768 }
mbed_official 181:a4cbdfbbd2f4 4769
mbed_official 181:a4cbdfbbd2f4 4770
mbed_official 181:a4cbdfbbd2f4 4771 /**
mbed_official 181:a4cbdfbbd2f4 4772 * @}
mbed_official 181:a4cbdfbbd2f4 4773 */
mbed_official 181:a4cbdfbbd2f4 4774
mbed_official 181:a4cbdfbbd2f4 4775 #endif /* HAL_TIM_MODULE_ENABLED */
mbed_official 181:a4cbdfbbd2f4 4776 /**
mbed_official 181:a4cbdfbbd2f4 4777 * @}
mbed_official 181:a4cbdfbbd2f4 4778 */
mbed_official 181:a4cbdfbbd2f4 4779
mbed_official 181:a4cbdfbbd2f4 4780 /**
mbed_official 181:a4cbdfbbd2f4 4781 * @}
mbed_official 181:a4cbdfbbd2f4 4782 */
mbed_official 181:a4cbdfbbd2f4 4783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/